TW201618241A - Improved composite carrier board structure of flip-chip chip-scale package - Google Patents
Improved composite carrier board structure of flip-chip chip-scale package Download PDFInfo
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- TW201618241A TW201618241A TW103139472A TW103139472A TW201618241A TW 201618241 A TW201618241 A TW 201618241A TW 103139472 A TW103139472 A TW 103139472A TW 103139472 A TW103139472 A TW 103139472A TW 201618241 A TW201618241 A TW 201618241A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract
Description
本發明係有關一種改良覆晶晶片級封裝之複合式載板結構，係將載板與基板之間的絕緣膜改良成異方性導電膠膜或類似結構之材料，並以異方性導電膠膜內所具有之導電粒子取代絕緣膜上加工之複數導通開口，不僅可避免各導通開口經機械加工所產生間距與大小的誤差，也可避免人工以各導通開口對位第二電極墊與第二電性接觸墊之間的誤差。The invention relates to a composite carrier structure for improving a flip chip wafer level package, which is characterized in that an insulating film between a carrier board and a substrate is modified into an anisotropic conductive film or the like, and an anisotropic conductive adhesive is used. The conductive particles in the film replace the plurality of conductive openings processed on the insulating film, thereby avoiding the error of the pitch and the size of each conductive opening through mechanical processing, and avoiding the manual alignment of the second electrode pads with the conductive openings. The error between the two electrical contact pads.
按，圖1A~圖1D所示之覆晶晶片級封裝(Flip chip-Chip scale package,FC-CSP)之複合式載板結構，係為本公司之台灣申請案號102121661(美國申請案號13/938,335)且尚未公開，乃為三次元封裝技術，朝向高功率、高密度、輕薄微小化來符合通訊產品之需求，亦可為疊接封裝件(Package on Package,POP)的主要結構，可上承或下接其他封裝結構或印刷電路板，然而，基本上可分成載板流程及封裝流程的兩個階段。According to the composite carrier structure of the Flip chip-Chip scale package (FC-CSP) shown in FIG. 1A to FIG. 1D, it is the Taiwanese application No. 102121661 (U.S. Application No. 13) /938,335), which has not yet been disclosed, is a three-dimensional packaging technology that meets the requirements of communication products for high power, high density, thin and light miniaturization, and can also be the main structure of package on package (POP). It can be divided into two stages: the carrier process and the packaging process.
如圖1A、圖1B所示之載板與基板結合前後之示意圖，其屬於載板流程: a)提供一載板20，該載板20其上表面設有複數第一電性接觸墊21及複數第二電性接觸墊22，該第二電性接觸墊22係環設於該第一電性接觸墊21周圍，又其下表面設有複數第三電性接觸墊23； b) 提供一基板40，該基板設有複數貫穿的電性導通體41，該電性導通體41上、下端裸露該基板之上、下表面，且該電性導通體41上、下端係分別電性連接一第一電極墊42之下表面與一第二電極墊43之上表面，且該基板40挖開一貫穿開口之覆晶區域44，並提供一絕緣膜30A之上表面貼合於其下表面，再者，該第二電極墊43之下表面相對於該第二電性接觸墊22的位置，而使該第二電性接觸墊22電性連接該第二電極墊43之下表面，又該第一電性接觸墊21相對於該覆晶區域44的位置，而使該第一電性接觸墊21位於該覆晶區域44內，形成該絕緣膜30A(Non-conductive Film,NCF)之下表面結合該載板20之上表面，即可完成複合式載板結構。FIG. 1A and FIG. 1B are schematic diagrams showing the carrier board before and after being combined with the substrate, which is a carrier board process: a) providing a carrier board 20 having a plurality of first electrical contact pads 21 on the upper surface thereof a plurality of second electrical contact pads 22, the second electrical contact pads 22 are disposed around the first electrical contact pads 21, and a plurality of third electrical contact pads 23 are disposed on the lower surface thereof; b) providing a The substrate 40 is provided with a plurality of electrically conductive bodies 41 penetrating therethrough. The upper and lower ends of the electrically conductive body 41 expose the upper and lower surfaces of the substrate, and the upper and lower ends of the electrically conductive body 41 are electrically connected to each other. a lower surface of the first electrode pad 42 and a top surface of a second electrode pad 43, and the substrate 40 is dug through a flip-chip region 44 extending through the opening, and an upper surface of the insulating film 30A is attached to the lower surface thereof. Furthermore, the position of the lower surface of the second electrode pad 43 relative to the second electrical contact pad 22 is such that the second electrical contact pad 22 is electrically connected to the lower surface of the second electrode pad 43. Positioning the first electrical contact pad 21 relative to the flip chip region 44 such that the first electrical contact pad 21 is located in the flip chip region 44, is formed the insulating film 30A (Non-conductive Film, NCF) below the surface 20 over the surface of the binding carrier plate, the carrier plate to complete the composite structure.
如圖1C、圖1D所示之封裝成型之示意圖，其以複合式載板結構進行覆晶晶片級封裝，以下為封裝流程: c)提供至少一晶片50，該晶片50具有相對之主動及非主動表面51、52，並於該主動表面51設有複數凸塊53，該凸塊53接合該第一電性接觸墊21，再將一封膠材料60填入於該覆晶區域44與該晶片50之間的間隙，使該晶片50能固定於該覆晶區域44內，形成該非主動表面52呈裸露狀態，並提供錫球B黏著於該第三電性接觸墊23。As shown in FIG. 1C and FIG. 1D, a schematic diagram of package molding is performed on a flip-chip wafer level package in a composite carrier structure. The following is a package process: c) providing at least one wafer 50 having a relative active and non-active The active surface 51, 52, and the active surface 51 is provided with a plurality of bumps 53, the bumps 53 are joined to the first electrical contact pads 21, and a glue material 60 is filled in the flip-chip region 44 and the The gap between the wafers 50 enables the wafer 50 to be fixed in the flip-chip region 44, forming the inactive surface 52 in a bare state, and providing the solder ball B to the third electrical contact pad 23.
承上，當該晶片50經由封裝流程的熱壓，則使該覆晶區域44內產生熱，透過該低熱膨脹係數的基板40能承受熱傳導所造成的熱應力，即可避免熱傳導集中於該載板20產生熱膨脹，且該基板40、絕緣膜30A及載板20複合結構強度也能承受熱應力，同時，該覆晶區域44上方為開放區域能加速熱對流，如此一來，該晶片50覆於該載板20時，透過良好熱傳導、熱對流，亦可使該載板20於封裝流程所產生的熱能迅速消除，即可解決熱應力造成該載板20上、下彎翹的熱應變問題。不易使薄型之載板於支撐時造成彎翹問題，進而具有薄型化、提升機械強度、強化散熱及減少彎翹之功效。Therefore, when the wafer 50 is subjected to hot pressing through the packaging process, heat is generated in the flip-chip region 44, and the substrate 40 having the low thermal expansion coefficient can withstand thermal stress caused by heat conduction, thereby preventing heat conduction from being concentrated on the carrier. The plate 20 is thermally expanded, and the composite structure of the substrate 40, the insulating film 30A and the carrier 20 can also withstand thermal stress. At the same time, the open region above the flip-chip region 44 can accelerate thermal convection, and thus the wafer 50 is covered. During the carrier 20, good thermal conduction and thermal convection can be used to quickly eliminate the thermal energy generated by the carrier 20 during the packaging process, thereby solving the thermal strain problem caused by the thermal stress causing the carrier 20 to be bent up and down. . It is not easy to cause the thin carrier plate to cause a bending problem when supporting, and further has the effects of thinning, improving mechanical strength, enhancing heat dissipation, and reducing bending.
惟查，該絕緣膜30A在該複合式載板結構的主要功能，在於使該基板40之下表面與該載板20之上表面呈絕緣不導電，但絕緣部分乃具有以下之問題: (1).由於該絕緣膜30A需以機械加工完成複數導通開口(圖未示)之間距及大小，除了提升製程成本外，也會影響該第二電性接觸墊22與該第二電極墊43之間的接觸面積，或該基板40之下表面與該載板20之上表面之間的不接觸面積，換言之，若各該導通開口之間距及大小的誤差過大，則該接觸面積與該不接觸面積的誤差過大，將造成該基板40之下表面與該載板20之上表面之間難以絕緣。 (2).由於該絕緣膜30A貼合於該基板40與該載板20之間，需透過人工以各該導通開口對位於該第二電性接觸墊22與該第二電極墊43之間，除了浪費對位時間外，也會影響該第二電性接觸墊22與該第二電極墊43之間的接觸面積，或該基板40之下表面與該載板20之上表面之間的不接觸面積，換言之，若各該導通開口之對位的誤差過大，則該接觸面積與該不接觸面積的誤差過大，將造成該基板40之下表面與該載板20之上表面之間難以絕緣。是以，前述複合式載板結構，使仍有其未盡完善之處，尚有改進空間。However, the main function of the insulating film 30A in the composite carrier structure is to make the lower surface of the substrate 40 and the upper surface of the carrier 20 insulating and non-conductive, but the insulating portion has the following problems: Because the insulating film 30A needs to be mechanically processed to complete the distance and size between the plurality of conductive openings (not shown), in addition to increasing the processing cost, the second electrical contact pads 22 and the second electrode pads 43 are also affected. The contact area between the contact areas, or the non-contact area between the lower surface of the substrate 40 and the upper surface of the carrier 20, in other words, if the error between the distance and the size of each of the conductive openings is too large, the contact area does not contact the contact area. An excessively large area error will make it difficult to insulate between the lower surface of the substrate 40 and the upper surface of the carrier 20. (2) The insulating film 30A is disposed between the substrate 40 and the carrier 20, and is disposed between the second electrical contact pad 22 and the second electrode pad 43 by manual connection. In addition to wasting the alignment time, the contact area between the second electrical contact pad 22 and the second electrode pad 43 or the surface between the lower surface of the substrate 40 and the upper surface of the carrier 20 is also affected. Without contact area, in other words, if the error of the alignment of each of the conduction openings is too large, the error between the contact area and the non-contact area is too large, which may cause difficulty between the lower surface of the substrate 40 and the upper surface of the carrier 20. insulation. Therefore, the above-mentioned composite type carrier structure has still been improved, and there is still room for improvement.
本發明之主要目的，係以異方性導電膠膜內所具有之導電粒子取代習用絕緣膜上加工之導通開口，用以解決先前技術各導通開口之間距、大小及對位的誤差之問題點，進而具有製程便捷及提升絕緣可靠性之功效增進。The main object of the present invention is to replace the conductive opening processed on the conventional insulating film with the conductive particles in the anisotropic conductive film to solve the problem of the error of the distance, the size and the alignment between the conduction openings of the prior art. In addition, it has the advantages of convenient process and improved insulation reliability.
為達上述目的，本發明之改良覆晶晶片級封裝之複合式載板結構，係包含:一載板，其上表面設有複數第一電性接觸墊及複數第二電性接觸墊，該第二電性接觸墊係環設於該第一電性接觸墊周圍；一基板，其挖開一貫穿開口之覆晶區域，該覆晶區域的位置對應於該第一電性接觸墊的位置，且設有複數貫穿該基板之電性導通體，該電性導通體上、下端裸露該基板上、下表面，且該電性導通體上、下端係分別電性連接一第一電極墊之下表面與一第二電極墊之上表面，該第二電極墊之下表面的位置對應於該第二電性接觸墊之上表面的位置；以及一異方性導電膠膜，其內具有複數導電粒子，並預壓該異方性導電膠膜至該載板上後，再壓合該基板至該載板上，令該第二電極墊之下表面可擠壓對應之導電粒子爆裂至該第二電性接觸墊之上表面，形成高密度壓合區，使該第二電極墊與該第二電性接觸墊呈導電，且使該高密度壓合區以外的導電粒子形成未擠壓爆裂之膜層，使該基板之下表面與該載板之上表面呈絕緣不導電之構造。In order to achieve the above objective, the composite flip-chip package-type composite carrier structure of the present invention comprises: a carrier board having a plurality of first electrical contact pads and a plurality of second electrical contact pads on the upper surface thereof, a second electrical contact pad ring is disposed around the first electrical contact pad; a substrate that is dug through a flip chip region of the through opening, the position of the flip chip region corresponding to the position of the first electrical contact pad And a plurality of electrical conductive bodies penetrating the substrate, wherein the upper and lower ends of the electrical conductive body expose the upper and lower surfaces of the substrate, and the upper and lower ends of the electrical conductive body are electrically connected to a first electrode pad respectively. a lower surface and a second electrode pad upper surface, a position of a lower surface of the second electrode pad corresponding to a position of the upper surface of the second electrical contact pad; and an anisotropic conductive film having a plurality of Conducting the particles, and pre-pressing the anisotropic conductive film onto the carrier, and then pressing the substrate onto the carrier, so that the lower surface of the second electrode pad can be pressed to discharge the corresponding conductive particles to the a second electrical contact pad on the upper surface to form a high density nip The second electrode pad and the second electrical contact pad are made conductive, and the conductive particles outside the high-density nip are formed into an unextrusion film layer, so that the lower surface of the substrate and the carrier are The upper surface is insulative and non-conductive.
依據前揭特徵，該異方性導電膠膜的厚度為30μm ~40μm，其內各該導電粒子為直徑5μm的鎳金粒子，各該導電粒子之間的密度為2500~5000pcs/mm2 ，並以70℃~90℃、1MPa及1秒的製程參數預壓該異方性導電膠膜至該載板上後，再以150℃~220℃、2~4MPa及1~10秒的製程參數壓合該基板至該載板上，及各該第二電極墊之間距在50μm內，令該第二電極墊之下表面與該第二電性接觸墊之上表面之間可捕抓部分導電粒子的最少接觸面積為50000μm。Based on above-mentioned technical features, the thickness of the anisotropic conductive film is 30μm ~ 40μm, within each of the conductive particle diameter 5μm nickel gold particle, a density between each of the conductive particles is 2500 ~ 5000pcs / mm 2, and The anisotropic conductive film is pre-compressed to the carrier plate at a process parameter of 70 ° C to 90 ° C, 1 MPa, and 1 second, and then subjected to a process parameter pressure of 150 ° C to 220 ° C, 2 to 4 MPa, and 1 to 10 seconds. The substrate is coupled to the carrier, and the distance between the second electrode pads is within 50 μm, so that a portion of the conductive particles can be captured between the lower surface of the second electrode pad and the upper surface of the second electrical contact pad. The minimum contact area is 50,000 μm.
依據前揭特徵，該電性導通體可為通孔形狀；該通孔形狀亦可為對稱型錐台，其上、下端較寬；該基板具有一第一及第二層組合所成型；該電性導通體具有一盲孔形狀的上導體、埋孔形狀的中導體及盲孔形狀的下導體組合所成型，該上導體與中導體位於該第一層及該下導體位於該第二層；該電性導通體具有一盲孔形狀的第一導體、半通孔形狀的第二導體組合所成型，該第一導體位於該第一層及該第二導體介於該第一及第二層。According to the foregoing feature, the electrical via may be in the shape of a through hole; the through hole may also be a symmetric frustum having a wider upper and lower ends; the substrate having a combination of the first and second layers; The electrical via has a blind conductor-shaped upper conductor, a buried via-shaped middle conductor, and a blind via-shaped lower conductor combination. The upper conductor and the middle conductor are located at the first layer and the lower conductor is located at the second layer The electrical via has a first conductor of a blind hole shape and a second conductor combination of a semi-via shape, the first conductor being located at the first layer and the second conductor being between the first and second Floor.
依據前揭特徵，更可包括至少一晶片，其具有相對之主動及非主動表面，並於該主動表面設有複數凸塊，該凸塊之下表面可擠壓部份導電粒子爆裂至該第一電性接觸墊之上表面，使該凸塊與該第一電性接觸墊呈導電，再將一封膠材料填入於該覆晶區域與該晶片之間的間隙，使該晶片能固定於該覆晶區域內，形成該非主動表面呈裸露狀態。According to the foregoing feature, the method further includes at least one wafer having opposite active and inactive surfaces, and the active surface is provided with a plurality of bumps, and the lower surface of the bump can be pressed to partially discharge the conductive particles to the first An upper surface of the electrical contact pad, the bump is electrically conductive with the first electrical contact pad, and a glue material is filled in the gap between the flip chip region and the wafer to enable the wafer to be fixed In the flip chip region, the inactive surface is formed to be in a bare state.
藉助上揭技術手段，本發明將習用絕緣膜改良成該異方性導電膠膜，以該異方性導電膠膜內所具有之導電粒子取代習用絕緣膜上加工之導通開口，不僅可降低製程成本及製程時間，也可避免各導通開口之間距、大小及對位的誤差之問題，使該第二電性接觸墊與該第二電極墊之間的接觸面積，或該基板之下表面與該載板之上表面之間的不接觸面積零誤差，以提升該基板之下表面與該載板之上表面之間的絕緣可靠性。By means of the above-mentioned technical means, the present invention improves the conventional insulating film into the anisotropic conductive film, and replaces the conductive opening processed in the conventional insulating film with the conductive particles in the anisotropic conductive film, thereby not only reducing the process The cost and process time can also avoid the problem of the error of the distance, the size and the alignment between the conduction openings, and the contact area between the second electrical contact pad and the second electrode pad, or the lower surface of the substrate There is zero error in the contact area between the upper surfaces of the carrier to improve the insulation reliability between the lower surface of the substrate and the upper surface of the carrier.
首先，請參閱圖2A~圖2D及圖3A~圖3B所示，本發明改良覆晶晶片級封裝之複合式載板結構之較佳實施例包含:一載板20，其上表面設有複數第一電性接觸墊21及複數第二電性接觸墊22，該第二電性接觸墊22係環設於該第一電性接觸墊21周圍。First, referring to FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3B, a preferred embodiment of the composite flip-chip structure of the modified flip-chip wafer level package comprises: a carrier 20 having a plurality of upper surfaces The first electrical contact pad 21 and the plurality of second electrical contact pads 22 are disposed around the first electrical contact pad 21 .
一基板40，其挖開一貫穿開口之覆晶區域44，該覆晶區域44的位置對應於該第一電性接觸墊21的位置，且設有複數貫穿該基板40之電性導通體41，該電性導通體41上、下端裸露該基板40上、下表面，且該電性導通體41上、下端係分別電性連接一第一電極墊42之下表面與一第二電極墊43之上表面，該第二電極墊43之下表面的位置對應於該第二電性接觸墊22之上表面的位置。a substrate 40 is formed with a flip-chip region 44 extending through the opening. The position of the flip-chip region 44 corresponds to the position of the first electrical contact pad 21, and a plurality of electrical vias 41 extending through the substrate 40 are disposed. The upper and lower ends of the electrically conductive body 41 expose the upper and lower surfaces of the substrate 40, and the upper and lower ends of the electrically conductive body 41 are electrically connected to a lower surface of the first electrode pad 42 and a second electrode pad 43 respectively. The upper surface, the position of the lower surface of the second electrode pad 43 corresponds to the position of the upper surface of the second electrical contact pad 22.
一異方性導電膠膜30B，其內具有複數導電粒子31B，並預壓該異方性導電膠膜30B至該載板20上後，再壓合該基板40至該載板20上，令該第二電極墊43之下表面可擠壓對應之導電粒子31B爆裂至該第二電性接觸墊22之上表面，形成高密度壓合區A，使該第二電極墊43與該第二電性接觸墊22呈導電，且使該高密度壓合區A以外的導電粒子31B形成未擠壓爆裂之膜層，使該基板40之下表面與該載板20之上表面呈絕緣不導電之構造，本實施例中，該異方性導電膠膜30B上貼合一保護膜32B，當預壓該異方性導電膠膜30B至該載板20上後，可將該保護膜32B撕開，再壓合該基板40至該載板20上，但不以此為限。An anisotropic conductive film 30B having a plurality of conductive particles 31B therein, and pre-pressing the anisotropic conductive film 30B onto the carrier 20, and then pressing the substrate 40 onto the carrier 20 The lower surface of the second electrode pad 43 is squeezing the corresponding conductive particles 31B to the upper surface of the second electrical contact pad 22 to form a high-density nip A, and the second electrode pad 43 and the second electrode The electrical contact pad 22 is electrically conductive, and the conductive particles 31B outside the high-density nip area A are formed into an unextrusion film layer, so that the lower surface of the substrate 40 and the upper surface of the carrier 20 are insulated and non-conductive. In this embodiment, a protective film 32B is attached to the anisotropic conductive film 30B. After the anisotropic conductive film 30B is pre-compressed onto the carrier 20, the protective film 32B can be torn. The substrate 40 is further pressed onto the carrier 20, but is not limited thereto.
經由上述該載板20、異方性導電膠膜30B及基板40堆疊形成複合式載板結構，在堆疊過程為了確保絕緣不導電，而設定最佳製程參數，如:該異方性導電膠膜30B的厚度為30μm ~40μm，其內各該導電粒子31B為直徑5μm的鎳金粒子，各該導電粒子31B之間的密度為2500~5000pcs/mm2 ，並以70℃~90℃、1MPa及1秒的製程參數預壓該異方性導電膠膜30B至該載板20上後，再以150℃~220℃、2~4MPa及1~10秒的製程參數壓合該基板40至該載板20上，及各該第二電極墊43之間距在50μm內，令該第二電極墊43之下表面與該第二電性接觸墊22之上表面之間可捕抓部分導電粒子31B的最少接觸面積為50000μm。The composite carrier structure is formed by stacking the carrier 20, the anisotropic conductive film 30B and the substrate 40, and an optimum process parameter is set in the stacking process to ensure insulation is not conductive, such as: the anisotropic conductive film The thickness of 30B is 30 μm to 40 μm, and each of the conductive particles 31B is nickel gold particles having a diameter of 5 μm, and the density between the conductive particles 31B is 2500 to 5000 pcs/mm 2 , and 70 ° C to 90 ° C, 1 MPa and After pre-pressing the anisotropic conductive film 30B onto the carrier 20 by a process parameter of 1 second, the substrate 40 is pressed to the carrier by process parameters of 150 ° C to 220 ° C, 2 to 4 MPa, and 1 to 10 seconds. The distance between the lower surface of the second electrode pad 43 and the upper surface of the second electrical contact pad 22 is such that the conductive particles 31B can be captured between the second electrode pad 43 and the upper surface of the second electrode pad 43. The minimum contact area is 50,000 μm.
承上，在一可行實施例中，提供複合式載板結構及配合基板40材料為低熱膨脹係數(Coefficient of thermal expansion, CTE)，亦可為碳纖維基板(Carbon Composite Substrate)或陶瓷基板(Ceramic Substrate)，使150um以下的薄型載板20經封裝流程而不易受到熱應力產生彎翹現象，該複合式載板結構之覆晶區域44植入一晶片50，其具有相對之主動及非主動表面51、52，並於該主動表面51設有複數凸塊53，該凸塊53之下表面可擠壓部份導電粒子31B爆裂至該第一電性接觸墊21之上表面，使該凸塊53與該第一電性接觸墊21呈導電，再將一封膠材料60填入於該覆晶區域44與該晶片50之間的間隙，使該晶片50能固定於該覆晶區域內44，形成該非主動表面52呈裸露狀態，並提供錫球B黏著於該第三接觸墊23。In a feasible embodiment, the composite carrier structure and the substrate 40 are provided with a coefficient of thermal expansion (CTE), or may be a carbon composite substrate or a ceramic substrate (Ceramic Substrate). The thin carrier 20 below 150 um is not susceptible to thermal stress by the packaging process. The flip-chip region 44 of the composite carrier structure is implanted into a wafer 50 having opposing active and inactive surfaces 51. And the active surface 51 is provided with a plurality of bumps 53. The lower surface of the bumps 53 squeezes a portion of the conductive particles 31B to the upper surface of the first electrical contact pad 21, so that the bumps 53 The first electrical contact pad 21 is electrically conductive, and a glue material 60 is filled in the gap between the flip chip region 44 and the wafer 50 to enable the wafer 50 to be fixed in the flip chip region 44. The inactive surface 52 is formed in a bare state, and a solder ball B is attached to the third contact pad 23.
承上，在一可行實施例中，該基板40為點矩陣板(Dot-Matrix Board)，但不僅能為單一層，更能利用不同材料呈現多層堆疊；該基板40內部經由鑽頭、雷射加工可產生通孔、盲孔、埋孔、半通孔等形狀，再以電鍍方式將該電性導通體41填入於各該孔的形狀，且該電性導通體41可為銅結構，並呈現無空泡(void free)狀態，故該電性導通體41可為通孔形狀，也可利用盲孔、埋孔及半通孔的形狀進行不同的堆疊組合，如此一來，該電性導通體41與基板40能互配合而呈現不同的結構，但不以此為限。In a possible embodiment, the substrate 40 is a Dot-Matrix Board, but not only a single layer but also a multi-layer stack using different materials; the substrate 40 is processed through a drill bit and a laser. The shape of the through hole, the blind hole, the buried hole, the half through hole, and the like may be generated, and the electrical conductive body 41 is filled in the shape of each of the holes by electroplating, and the electrical conductive body 41 may be a copper structure, and The present invention is in the form of a void free state. Therefore, the electrical conductive body 41 can be in the shape of a through hole, and different stacked combinations can be performed by using the shapes of the blind hole, the buried hole and the half through hole. Thus, the electrical property is obtained. The conductive body 41 and the substrate 40 can cooperate with each other to exhibit different structures, but are not limited thereto.
如圖4所示之又一可行實施例結構示意圖，該電性導通體41的通孔形狀亦可為對稱型錐台，其上、下端較寬。4 is a schematic structural view of another possible embodiment, the through hole shape of the electrical conduction body 41 may also be a symmetric frustum, and the upper and lower ends thereof are wider.
如圖5所示之再一可行實施例結構示意圖，該基板40具有一第一及第二層401、402組合所成型，該電性導通體41具有一盲孔形狀的上導體411、埋孔形狀的中導體412及盲孔形狀的下導體413組合所成型，該上導體411與中導體412位於該第一層401及該下導體413位於該第二層402。As shown in FIG. 5, the substrate 40 has a first and second layers 401 and 402. The electrical conductor 41 has a blind hole-shaped upper conductor 411 and a buried hole. The shape of the middle conductor 412 and the blind hole-shaped lower conductor 413 are combined, and the upper conductor 411 and the middle conductor 412 are located in the first layer 401 and the lower conductor 413 is located in the second layer 402.
如圖6所示之另一可行實施例結構示意圖，該電性導通體41具有一盲孔形狀的第一導體41a、半通孔形狀的第二導體41b組合所成型，該第一導體41a位於該第一層401及該第二導體41b介於該第一及第二層401、402，且該第一及第二層401、402總厚度大於250um，但不以此為限。FIG. 6 is a schematic structural view of another possible embodiment, wherein the electrical conductor 41 has a first conductor 41a having a blind hole shape and a second conductor 41b having a semi-via shape. The first conductor 41a is located. The first layer 401 and the second conductor 41b are interposed between the first and second layers 401 and 402, and the total thickness of the first and second layers 401 and 402 is greater than 250 um, but not limited thereto.
是以，本發明異方性導電膠膜30B取代習用絕緣膜30A後，仍保有習用複合式載板結構之薄型化、提升機械強度、強化散熱及減少彎翹等功效，同時，以該異方性導電膠膜30B內所具有之導電粒子31B 取代習用絕緣膜30A上加工之導通開口，可降低製程成本、降低製程時間及提升絕緣可靠性。Therefore, after the inertial conductive film 30B of the present invention replaces the conventional insulating film 30A, the conventional composite carrier structure is still thinned, the mechanical strength is enhanced, the heat dissipation is enhanced, and the bending is reduced. The conductive particles 31 B included in the conductive adhesive film 30B replace the conductive openings processed in the conventional insulating film 30A, thereby reducing process cost, reducing process time, and improving insulation reliability.
綜上所述，本發明所揭示之構造，為昔所無，且確能達到功效之增進，並具可供產業利用性，完全符合發明專利要件，祈請 鈞局核賜專利，以勵創新，無任德感。In summary, the structure disclosed by the present invention is unprecedented, and can indeed achieve the improvement of efficacy, and has industrial availability, fully conforms to the patent requirements of the invention, and invites the bureau to grant a patent to encourage innovation. There is no sense of morality.
惟，上述所揭露之圖式、說明，僅為本發明之較佳實施例，大凡熟悉此項技藝人士，依本案精神範疇所作之修飾或等效變化，仍應包括在本案申請專利範圍內。The drawings and the descriptions of the present invention are merely preferred embodiments of the present invention, and those skilled in the art, which are subject to the spirit of the present invention, should be included in the scope of the patent application.
20‧‧‧載板
21‧‧‧第一電性接觸墊
22‧‧‧第二電性接觸墊
23‧‧‧第三電性接觸墊
30B‧‧‧異方性導電膠膜
31B‧‧‧導電粒子
32B‧‧‧保護膜
40‧‧‧基板
401‧‧‧第一層
402‧‧‧第二層
41‧‧‧電性導通體
411‧‧‧上導體
412‧‧‧中導體
413‧‧‧下導體
41a‧‧‧第一導體
41b‧‧‧第二導體
42‧‧‧第一電極墊
43‧‧‧第二電極墊
44‧‧‧覆晶區域
50‧‧‧晶片
51‧‧‧主動表面
52‧‧‧非主動表面
53‧‧‧凸塊
60‧‧‧封膠材料
A‧‧‧高密度壓合區
B‧‧‧錫球20‧‧‧ Carrier Board
21‧‧‧First electrical contact pads
22‧‧‧Second electrical contact pads
23‧‧‧ Third electrical contact pad
30B‧‧‧ anisotropic conductive film
31B‧‧‧ conductive particles
32B‧‧‧Protective film
40‧‧‧Substrate
401‧‧‧ first floor
402‧‧‧ second floor
41‧‧‧Electrical Conductors
411‧‧‧Upper conductor
412‧‧‧Medium conductor
413‧‧‧lower conductor
41a‧‧‧First conductor
41b‧‧‧second conductor
42‧‧‧First electrode pad
43‧‧‧Second electrode pad
44‧‧‧Flip area
50‧‧‧ wafer
51‧‧‧Active surface
52‧‧‧Non-active surface
53‧‧‧Bumps
60‧‧‧sealing materials
A‧‧‧High-density nip
B‧‧‧ solder ball
圖1A係習用載板與基板結合前之示意圖。 圖1B係習用載板與基板結合後之示意圖。 圖1C係習用封裝成型之示意圖。 圖1D係習用封裝成型熱傳導、熱對流之示意圖。 圖2A係本發明載板、異方性導電膠膜及基板結合前之示意圖。 圖2B係本發明異方性導電膠膜預壓至載板上之示意圖。 圖2C本發明基板壓合至載板上之示意圖。 圖2D本發明可行實施例之結構示意圖。 圖3A本發明異方性導電膠膜未壓合之示意圖。 圖3B本發明異方性導電膠膜已壓合之示意圖。 圖4係本發明又一可行實施例之結構示意圖。 圖5係本發明再一可行實施例之結構示意圖。 圖6係本發明另一可行實施例之結構示意圖。Figure 1A is a schematic view of a conventional carrier plate before being bonded to a substrate. Fig. 1B is a schematic view showing the combination of a conventional carrier and a substrate. Figure 1C is a schematic view of a conventional package molding. FIG. 1D is a schematic view showing heat conduction and heat convection of a conventional package. 2A is a schematic view of the carrier of the present invention, the anisotropic conductive film, and the substrate before bonding. 2B is a schematic view showing the pre-pressing of the anisotropic conductive film of the present invention onto a carrier. Figure 2C is a schematic illustration of the substrate of the present invention being pressed onto a carrier. Figure 2D is a schematic view showing the structure of a possible embodiment of the present invention. Fig. 3A is a schematic view showing the non-compression of the anisotropic conductive film of the present invention. FIG. 3B is a schematic view showing that the anisotropic conductive film of the present invention has been pressed. 4 is a schematic structural view of still another possible embodiment of the present invention. Figure 5 is a schematic view showing the structure of still another possible embodiment of the present invention. Figure 6 is a schematic view showing the structure of another possible embodiment of the present invention.
20‧‧‧載板 20‧‧‧ Carrier Board
21‧‧‧第一電性接觸墊 21‧‧‧First electrical contact pads
22‧‧‧第二電性接觸墊 22‧‧‧Second electrical contact pads
23‧‧‧第三電性接觸墊 23‧‧‧ Third electrical contact pad
30B‧‧‧異方性導電膠膜 30B‧‧‧ anisotropic conductive film
31B‧‧‧導電粒子 31B‧‧‧ conductive particles
40‧‧‧基板 40‧‧‧Substrate
41‧‧‧電性導通體 41‧‧‧Electrical Conductors
42‧‧‧第一電極墊 42‧‧‧First electrode pad
43‧‧‧第二電極墊 43‧‧‧Second electrode pad
44‧‧‧覆晶區域 44‧‧‧Flip area
50‧‧‧晶片 50‧‧‧ wafer
51‧‧‧主動表面 51‧‧‧Active surface
52‧‧‧非主動表面 52‧‧‧Non-active surface
53‧‧‧凸塊 53‧‧‧Bumps
60‧‧‧封膠材料 60‧‧‧sealing materials
B‧‧‧錫球 B‧‧‧ solder ball
Claims (9)
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10249567B2 (en) | 2017-08-18 | 2019-04-02 | Industrial Technology Research Institute | Redistribution layer structure of semiconductor package |
| TWI678782B (en) * | 2017-08-18 | 2019-12-01 | 財團法人工業技術研究院 | Redistribution layer structure of semiconductor package |
| US10622326B2 (en) | 2017-08-18 | 2020-04-14 | Industrial Technology Research Institute | Chip package structure |
| CN111315109A (en) * | 2018-12-12 | 2020-06-19 | 欣兴电子股份有限公司 | Composite substrate structure and manufacturing method thereof |
| US10863618B2 (en) | 2018-12-12 | 2020-12-08 | Unimicron Technology Corp. | Composite substrate structure and manufacturing method thereof |
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| JPH07169872A (en) * | 1993-12-13 | 1995-07-04 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10249567B2 (en) | 2017-08-18 | 2019-04-02 | Industrial Technology Research Institute | Redistribution layer structure of semiconductor package |
| TWI678782B (en) * | 2017-08-18 | 2019-12-01 | 財團法人工業技術研究院 | Redistribution layer structure of semiconductor package |
| US10622326B2 (en) | 2017-08-18 | 2020-04-14 | Industrial Technology Research Institute | Chip package structure |
| CN111315109A (en) * | 2018-12-12 | 2020-06-19 | 欣兴电子股份有限公司 | Composite substrate structure and manufacturing method thereof |
| US10863618B2 (en) | 2018-12-12 | 2020-12-08 | Unimicron Technology Corp. | Composite substrate structure and manufacturing method thereof |
| TWI734945B (en) * | 2018-12-12 | 2021-08-01 | 欣興電子股份有限公司 | Composite substrate structure and manufacturing method thereof |
| CN111315109B (en) * | 2018-12-12 | 2021-12-21 | 欣兴电子股份有限公司 | Composite substrate structure and manufacturing method thereof |
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