TW201603192A - Hybrid wafer dicing approach using an ultra-short pulsed laguerre gauss beam laser scribing process and plasma etch process - Google Patents
Hybrid wafer dicing approach using an ultra-short pulsed laguerre gauss beam laser scribing process and plasma etch process Download PDFInfo
- Publication number
- TW201603192A TW201603192A TW104115628A TW104115628A TW201603192A TW 201603192 A TW201603192 A TW 201603192A TW 104115628 A TW104115628 A TW 104115628A TW 104115628 A TW104115628 A TW 104115628A TW 201603192 A TW201603192 A TW 201603192A
- Authority
- TW
- Taiwan
- Prior art keywords
- laser
- laser beam
- scribing
- polarization
- mask
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 148
- 230000008569 process Effects 0.000 title claims abstract description 100
- 230000010287 polarization Effects 0.000 claims abstract description 114
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 238000001020 plasma etching Methods 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 11
- 238000005520 cutting process Methods 0.000 claims description 34
- 238000005530 etching Methods 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims 2
- 235000012431 wafers Nutrition 0.000 abstract description 102
- 239000010410 layer Substances 0.000 description 101
- 239000000758 substrate Substances 0.000 description 60
- 239000000463 material Substances 0.000 description 50
- 238000004140 cleaning Methods 0.000 description 29
- 239000013598 vector Substances 0.000 description 20
- 229910052732 germanium Inorganic materials 0.000 description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 15
- 239000002609 medium Substances 0.000 description 14
- 238000003860 storage Methods 0.000 description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 13
- 239000013078 crystal Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 230000006378 damage Effects 0.000 description 9
- 238000002679 ablation Methods 0.000 description 8
- 238000010521 absorption reaction Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 238000000608 laser ablation Methods 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000008878 coupling Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- 229910052707 ruthenium Inorganic materials 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009833 condensation Methods 0.000 description 4
- 230000005494 condensation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- -1 polytetrafluoroethylene Polymers 0.000 description 4
- 229910000416 bismuth oxide Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- TYIXMATWDRGMPF-UHFFFAOYSA-N dibismuth;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Bi+3].[Bi+3] TYIXMATWDRGMPF-UHFFFAOYSA-N 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000013467 fragmentation Methods 0.000 description 3
- 238000006062 fragmentation reaction Methods 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 238000005286 illumination Methods 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 238000010330 laser marking Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000009736 wetting Methods 0.000 description 3
- RRHGJUQNOFWUDK-UHFFFAOYSA-N Isoprene Chemical compound CC(=C)C=C RRHGJUQNOFWUDK-UHFFFAOYSA-N 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 229910000420 cerium oxide Inorganic materials 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000000075 oxide glass Substances 0.000 description 2
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229920002307 Dextran Polymers 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229920003171 Poly (ethylene oxide) Polymers 0.000 description 1
- 229920002845 Poly(methacrylic acid) Polymers 0.000 description 1
- 229920002873 Polyethylenimine Polymers 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229920002125 Sokalan® Polymers 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 239000012736 aqueous medium Substances 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229940114081 cinnamate Drugs 0.000 description 1
- 238000005345 coagulation Methods 0.000 description 1
- 230000015271 coagulation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- URQUNWYOBNUYJQ-UHFFFAOYSA-N diazonaphthoquinone Chemical compound C1=CC=C2C(=O)C(=[N]=[N])C=CC2=C1 URQUNWYOBNUYJQ-UHFFFAOYSA-N 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005459 micromachining Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910000487 osmium oxide Inorganic materials 0.000 description 1
- JIWAALDUIFCBLV-UHFFFAOYSA-N oxoosmium Chemical compound [Os]=O JIWAALDUIFCBLV-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000004584 polyacrylic acid Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- WBYWAXJHAXSJNI-VOTSOKGWSA-M trans-cinnamate Chemical compound [O-]C(=O)\C=C\C1=CC=CC=C1 WBYWAXJHAXSJNI-VOTSOKGWSA-M 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/352—Working by laser beam, e.g. welding, cutting or boring for surface treatment
- B23K26/359—Working by laser beam, e.g. welding, cutting or boring for surface treatment by providing a line or line pattern, e.g. a dotted break initiation line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
- B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Mechanical Engineering (AREA)
- Laser Beam Processing (AREA)
- Dicing (AREA)
Abstract
Description
本申請案主張於2014年5月16日提交申請之美國臨時申請案第61/994,385號之權益,該美國臨時申請案之全部內容以引用之方式併入本文。 The present application claims the benefit of U.S. Provisional Application Serial No. 61/994,385, filed on May 16, 2014, the entire disclosure of which is hereby incorporated by reference.
本發明之實施例係關於半導體處理領域,且更特定言之,係關於切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。 Embodiments of the present invention relate to the field of semiconductor processing and, more particularly, to a method of dicing a semiconductor wafer having a plurality of integrated circuits on each wafer.
在半導體晶圓處理中,在由矽或其他半導體材料所組成的晶圓(亦稱為基板)上形成積體電路。大體而言,利用各種材料層形成積體電路,該等材料為半導體、導體或者絕緣體。使用各種熟知製程摻雜、沉積及蝕刻該等材料以形成積體電路。每一晶圓經處理以形成眾多含有積體電路的個別區域,該等區域被稱為晶粒。 In semiconductor wafer processing, an integrated circuit is formed on a wafer (also referred to as a substrate) composed of germanium or other semiconductor material. In general, integrated circuits are formed using layers of various materials, such as semiconductors, conductors or insulators. The materials are doped, deposited, and etched using various well known processes to form an integrated circuit. Each wafer is processed to form a plurality of individual regions containing integrated circuits, referred to as grains.
遵循積體電路形成製程,「切割」晶圓以使個別晶粒彼此分離以便封裝或以未封裝形式用 於較大電路內。用於晶圓切割的兩種主要技術為劃線及鋸切。在劃線情況中,沿預形成之劃割線跨越晶圓表面移動金剛石鑲頭劃線器。該等劃割線沿晶粒之間的空間延伸。該等空間通常被稱為「劃道(streets)」。金剛石劃線器沿劃道在晶圓表面中形成淺劃痕。在諸如利用滾軸施加壓力後,晶圓沿劃割線分離。晶圓的斷裂遵循晶圓基板之晶格結構。劃線可用於約10密耳(千分之一吋)或以下厚度的晶圓。對於較厚晶圓,鋸切係目前較佳之切割方法。 Follow the integrated circuit forming process to "cut" the wafer to separate individual dies from each other for packaging or in an unpackaged form In a larger circuit. The two main techniques used for wafer cutting are scribing and sawing. In the case of scribing, the diamond insert scribe is moved across the surface of the wafer along a preformed scribe line. The scribe lines extend along the space between the dies. These spaces are often referred to as "streets". The diamond scriber forms shallow scratches in the wafer surface along the scribe lane. After the pressure is applied, such as by the roller, the wafer is separated along the scribe line. The fracture of the wafer follows the lattice structure of the wafer substrate. Scribing can be used for wafers of about 10 mils (thousandths of a mile) or less. For thicker wafers, sawing is currently the preferred method of cutting.
使用鋸切時,以高的每分鐘轉數旋轉的金剛石鑲頭鋸接觸晶圓表面,並沿劃道鋸切晶圓。將晶圓安裝在支撐構件上,該支撐構件為諸如跨越薄膜框拉伸的黏合薄膜,並將鋸反復應用於垂直與水平劃道兩者。劃線或鋸切的一個問題在於可沿晶粒之切斷邊緣形成碎屑及槽。另外,可形成裂紋,且該等裂紋可自晶粒邊緣傳播至基板內,並導致積體電路無法操作。碎裂及開裂尤其是劃線所具有的問題,因為僅可對正方形或矩形晶粒之一側按結晶結構之<110>方向劃線。因此,晶粒之另一側之斷裂產生鋸齒狀分離線。由於碎裂及開裂,晶圓上的晶粒之間需要額外間距,以防止損傷積體電路,例如,使碎屑及裂紋與實際積體電路保持距離。由於間隔要求,所以在標準尺寸之晶圓上形成的晶粒不多,且浪費了本可用於電路系統之晶圓使用面積。使用鋸加重了半導體晶圓上的 使用面積浪費。鋸刃之厚度為約15微米。因此,為確保由鋸產生的切口周圍之開裂及其他損傷不損害積體電路,通常必須將每一晶粒之電路系統分離三百至五百微米。此外,在切割後,每一晶粒需要大量清潔以移除產生自鋸切製程的顆粒及其他污染物。 When sawing, a diamond insert saw rotating at a high revolutions per minute contacts the wafer surface and saws the wafer along the scribe. The wafer is mounted on a support member that is an adhesive film such as stretched across a film frame, and the saw is repeatedly applied to both vertical and horizontal scribes. One problem with scribing or sawing is that debris and grooves can be formed along the cut edges of the grains. In addition, cracks can be formed, and the cracks can propagate from the edge of the die into the substrate and cause the integrated circuit to be inoperable. Fragmentation and cracking are particularly problematic for scribing because only one of the square or rectangular grains can be scribed in the <110> direction of the crystalline structure. Therefore, the fracture on the other side of the crystal grain produces a zigzag separation line. Due to chipping and cracking, additional spacing between the dies on the wafer is required to prevent damage to the integrated circuitry, for example, to keep debris and cracks away from the actual integrated circuitry. Due to the spacing requirements, there are not many dies formed on standard sized wafers, and the wafer area available for the circuitry is wasted. Using a saw to emphasize the semiconductor wafer Use area wasted. The thickness of the saw blade is about 15 microns. Therefore, in order to ensure that cracks and other damage around the slit created by the saw do not damage the integrated circuit, it is generally necessary to separate the circuitry of each die by three hundred to five hundred microns. In addition, after dicing, each die requires extensive cleaning to remove particles and other contaminants that result from the sawing process.
亦已經使用電漿切割,但電漿切割亦可具有限制。舉例而言,妨礙電漿切割實施的一個限制可為成本。用於圖案化抗蝕劑的標準微影術操作可導致實施成本過高。可能妨礙電漿切割實施的另一限制在於在沿劃道切割常見金屬(例如,銅)時對該等常見金屬之電漿處理可產生生產問題或產量限制。 Plasma cutting has also been used, but plasma cutting can also have limitations. For example, one limitation that hinders the implementation of plasma cutting can be cost. Standard lithography operations for patterning resists can result in costly implementations. Another limitation that may hinder the implementation of plasma cutting is that plasma processing of such common metals can cause production problems or yield constraints when cutting common metals (e.g., copper) along the scribe.
本發明之實施例包括切割半導體晶圓之方法及設備。 Embodiments of the invention include methods and apparatus for dicing semiconductor wafers.
在一實施例中,切割具有複數個積體電路的半導體晶圓之方法涉及在半導體晶圓上方形成遮罩,該遮罩包括覆蓋及保護積體電路的層。該方法亦涉及利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程圖案化該遮罩,以提供具有間隙的經圖案化遮罩,從而曝露半導體晶圓的介於積體電路之間的區域。超短脈衝拉蓋爾高斯雷射光束雷射劃線製程涉及利用具有軸向對稱偏振的雷射光束進行劃線。該方法亦涉及經由經圖案化遮罩中的間隙電漿蝕刻半導體晶圓,以切單積體電路。 In one embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask over the semiconductor wafer, the mask including a layer covering and protecting the integrated circuit. The method also involves patterning the mask with an ultrashort pulse Laguerre laser beam laser scribing process to provide a patterned mask having a gap to expose the semiconductor wafer between the integrated circuits Area. The ultrashort pulse Laguerre Gaussian laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization. The method also involves plasma etching the semiconductor wafer via a gap in the patterned mask to singulate the integrated circuit.
在另一實施例中,用於切割具有複數個積體電路的半導體晶圓之系統包括工廠介面。將雷射劃線設備與工廠介面耦接且該雷射劃線設備包括雷射總成,該雷射總成經配置以提供具有軸向對稱偏振的超短脈衝拉蓋爾高斯雷射光束。亦將電漿蝕刻腔室與工廠介面耦接。 In another embodiment, a system for cutting a semiconductor wafer having a plurality of integrated circuits includes a factory interface. A laser scribing apparatus is coupled to the factory interface and the laser scribing apparatus includes a laser assembly configured to provide an ultrashort pulse Laguerre laser beam having axially symmetric polarization. The plasma etch chamber is also coupled to the factory interface.
在另一實施例中,切割具有複數個積體電路的半導體晶圓之方法涉及在半導體晶圓上方形成遮罩,該遮罩包含覆蓋及保護積體電路的層。該方法亦涉及利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程圖案化遮罩及切單積體電路。超短脈衝拉蓋爾高斯雷射光束雷射劃線製程涉及利用具有軸向對稱偏振的雷射光束進行劃線。 In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask over the semiconductor wafer, the mask including a layer covering and protecting the integrated circuit. The method also relates to the use of an ultra-short pulse Laguerre laser beam laser scribing process to pattern the mask and cut the integrated circuit. The ultrashort pulse Laguerre Gaussian laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization.
100‧‧‧流程圖 100‧‧‧ Flowchart
102‧‧‧操作 102‧‧‧ operation
104‧‧‧操作 104‧‧‧Operation
106‧‧‧操作 106‧‧‧ operation
108‧‧‧操作 108‧‧‧ operation
202‧‧‧遮罩 202‧‧‧ mask
204‧‧‧半導體晶圓/基板 204‧‧‧Semiconductor wafer/substrate
206‧‧‧積體電路 206‧‧‧ integrated circuit
207‧‧‧劃道 207‧‧‧ 划道
208‧‧‧經圖案化遮罩 208‧‧‧ patterned mask
210‧‧‧間隙 210‧‧‧ gap
212‧‧‧溝槽 212‧‧‧ trench
302‧‧‧部分 Section 302‧‧‧
304‧‧‧部分 Section 304‧‧‧
306‧‧‧部分 Section 306‧‧‧
308‧‧‧部分 Section 308‧‧‧
310‧‧‧線性或圓形偏振 310‧‧‧Linear or circular polarization
312‧‧‧徑向與方位角偏振 312‧‧‧radial and azimuthal polarization
314‧‧‧示意圖 314‧‧‧ Schematic
316‧‧‧示意圖 316‧‧‧ Schematic
318‧‧‧部分 Section 318‧‧‧
320‧‧‧部分 320‧‧‧Parts
322‧‧‧部分 Section 322‧‧‧
324‧‧‧部分 Section 324‧‧‧
326‧‧‧部分 Section 326‧‧‧
328‧‧‧光點 328‧‧‧ light spots
330‧‧‧部分 330‧‧‧Parts
332‧‧‧部分 Section 332‧‧‧
334‧‧‧部分 Section 334‧‧‧
336‧‧‧光點 336‧‧‧ light spots
338‧‧‧具有不同強度結構的雷射光束 338‧‧‧Laser beams with different intensity structures
340‧‧‧具有圓柱對稱強度結構的雷射光束 340‧‧‧Laser beam with cylindrically symmetric strength structure
342‧‧‧部分 Section 342‧‧‧
344‧‧‧部分 Section 344‧‧‧
346‧‧‧部分 Section 346‧‧‧
348‧‧‧部分 Section 348‧‧‧
350‧‧‧光點 350‧‧‧ light spots
402‧‧‧部分 Section 402‧‧‧
404‧‧‧部分 Section 404‧‧‧
500A‧‧‧通孔 500A‧‧‧through hole
500B‧‧‧通孔 500B‧‧‧through hole
500C‧‧‧通孔 500C‧‧‧through hole
600‧‧‧劃道區域 600‧‧ ‧ scribing area
602‧‧‧矽基板頂部部分 602‧‧‧矽Top part of the substrate
604‧‧‧第一二氧化矽層 604‧‧‧First bismuth oxide layer
606‧‧‧第一蝕刻終止層 606‧‧‧First etch stop layer
608‧‧‧第一低介電常數介電層 608‧‧‧First low dielectric constant dielectric layer
610‧‧‧第二蝕刻終止層 610‧‧‧second etch stop layer
612‧‧‧第二低介電常數介電層 612‧‧‧Second low dielectric constant dielectric layer
614‧‧‧第三蝕刻終止層 614‧‧‧ Third etch stop layer
616‧‧‧未摻雜二氧化矽玻璃層 616‧‧‧Undoped bismuth oxide glass layer
618‧‧‧第二二氧化矽層 618‧‧‧Second dioxide layer
620‧‧‧光阻層 620‧‧‧ photoresist layer
622‧‧‧銅金屬化材料 622‧‧‧ copper metallized materials
702‧‧‧遮罩層 702‧‧‧ mask layer
704‧‧‧裝置層 704‧‧‧Device layer
706‧‧‧矽基板 706‧‧‧矽 substrate
708‧‧‧晶粒黏著薄膜 708‧‧‧ die attach film
710‧‧‧襯帶 710‧‧‧With tape
712‧‧‧超短脈衝拉蓋爾高斯雷射光束雷射劃線製程 712‧‧‧ Ultrashort pulse Laguerre Gauss laser beam laser marking process
714‧‧‧溝槽 714‧‧‧ trench
716‧‧‧透矽深層電漿蝕刻製程 716‧‧‧Deep deep plasma etching process
800‧‧‧製程工具 800‧‧‧Processing tools
802‧‧‧工廠介面 802‧‧‧Factory interface
804‧‧‧裝載鎖 804‧‧‧Load lock
806‧‧‧群集工具 806‧‧‧Cluster Tools
808‧‧‧電漿蝕刻腔室 808‧‧‧plasma etching chamber
810‧‧‧雷射劃線設備 810‧‧‧Laser marking equipment
812‧‧‧沉積室 812‧‧‧Deposition room
814‧‧‧潤濕/乾燥站 814‧‧ Wetting/drying station
900‧‧‧電腦系統 900‧‧‧Computer system
902‧‧‧處理器 902‧‧‧ processor
904‧‧‧主記憶體 904‧‧‧ main memory
906‧‧‧靜態記憶體 906‧‧‧ Static memory
908‧‧‧網路介面裝置 908‧‧‧Network interface device
910‧‧‧視訊顯示單元 910‧‧ ‧Video display unit
912‧‧‧文數字輸入裝置 912‧‧‧Text input device
914‧‧‧游標控制裝置 914‧‧‧ cursor control device
916‧‧‧訊號產生裝置 916‧‧‧Signal generating device
918‧‧‧二級記憶體 918‧‧‧secondary memory
920‧‧‧網路 920‧‧‧Network
922‧‧‧軟體 922‧‧‧Software
926‧‧‧處理邏輯 926‧‧‧ Processing logic
930‧‧‧匯流排 930‧‧ ‧ busbar
932‧‧‧機器可存取儲存媒體 932‧‧‧ Machine accessible storage media
第1圖係表示根據本發明之實施例的切割包括複數個積體電路之半導體晶圓之方法中的操作之流程圖。 1 is a flow chart showing the operation in a method of dicing a semiconductor wafer including a plurality of integrated circuits in accordance with an embodiment of the present invention.
第2A圖圖示根據本發明之實施例的在執行切割半導體晶圓之方法期間的包括複數個積體電路之半導體晶圓之橫截面視圖,該視圖對應於第1圖之流程圖之操作102。 2A illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during a method of performing a dicing of a semiconductor wafer, the view corresponding to operation 102 of the flowchart of FIG. 1 in accordance with an embodiment of the present invention. .
第2B圖圖示根據本發明之實施例的在執行切割半導體晶圓之方法期間的包括複數個積體 電路之半導體晶圓之橫截面視圖,該視圖對應於第1圖之流程圖之操作104。 2B illustrates a plurality of integrated bodies during a method of performing a dicing of a semiconductor wafer in accordance with an embodiment of the present invention. A cross-sectional view of a semiconductor wafer of circuitry corresponding to operation 104 of the flowchart of FIG.
第2C圖圖示根據本發明之實施例的在執行切割半導體晶圓之方法期間的包括複數個積體電路之半導體晶圓之橫截面視圖,該視圖對應於第1圖之流程圖之操作108。 2C illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during a method of performing a dicing of a semiconductor wafer, the view corresponding to operation 108 of the flowchart of FIG. 1 in accordance with an embodiment of the present invention. .
第3A圖圖示作為偏振面的電元件之平面。 Fig. 3A illustrates the plane of the electrical component as a plane of polarization.
第3B圖圖示雷射光束之P偏振及S偏振之概念。 Figure 3B illustrates the concept of P-polarization and S-polarization of a laser beam.
第3C圖圖示根據本發明之實施例的如箭頭所表示之習知及向量雷射光束的不同類型偏振。 Figure 3C illustrates different types of polarization of conventional and vector laser beams as indicated by the arrows in accordance with an embodiment of the present invention.
第3D圖示意性圖示根據本發明之實施例的對耦合至材料中的雷射能之偏振效應。 Figure 3D schematically illustrates the polarization effect on the laser energy coupled into the material in accordance with an embodiment of the present invention.
第3E圖圖示根據本發明之實施例的偏振方向對比雷射劃線方向。 Figure 3E illustrates the direction of polarization versus the direction of the laser scribing in accordance with an embodiment of the present invention.
第3F圖圖示根據本發明之實施例的偏振方向對比雷射劃線方向之效應。 Figure 3F illustrates the effect of polarization direction versus laser scribe direction in accordance with an embodiment of the present invention.
第3G圖圖示具有簡單強度結構及習知偏振之雷射光束。 Figure 3G illustrates a laser beam having a simple intensity structure and a conventional polarization.
第3H圖圖示根據本發明之實施例的具有複雜強度結構及偏振之雷射光束。 Figure 3H illustrates a laser beam having a complex intensity structure and polarization in accordance with an embodiment of the present invention.
第3I圖圖示根據本發明之實施例的具有不同強度結構之雷射光束之實例及具有圓柱對稱強度結構之雷射光束之實例。 Fig. 3I illustrates an example of a laser beam having different intensity structures and an example of a laser beam having a cylindrically symmetric intensity structure according to an embodiment of the present invention.
第3J圖圖示根據本發明之實施例的具有複雜偏振與複雜強度結構兩者之雷射光束。 Figure 3J illustrates a laser beam having both complex polarization and complex intensity structures in accordance with an embodiment of the present invention.
第4圖圖示根據本發明之實施例的具有徑向及/或方位角偏振之TEM01*雷射光束之形成。 Figure 4 illustrates the formation of a TEM01* laser beam having radial and/or azimuthal polarization in accordance with an embodiment of the present invention.
第5圖圖示根據本發明之實施例的使用飛秒範圍、皮秒範圍及奈秒範圍內的雷射脈衝寬度之效應。 Figure 5 illustrates the effect of using a femtosecond range, a picosecond range, and a laser pulse width in the nanosecond range, in accordance with an embodiment of the present invention.
第6圖圖示根據本發明之實施例的可用於半導體晶圓或基板之劃道區域中的材料堆疊之橫截面視圖。 Figure 6 illustrates a cross-sectional view of a stack of materials that may be used in a scribe region of a semiconductor wafer or substrate in accordance with an embodiment of the present invention.
第7A圖至第7D圖圖示根據本發明之實施例的切割半導體晶圓之方法中的各個操作之橫截面視圖。 7A through 7D illustrate cross-sectional views of various operations in a method of dicing a semiconductor wafer in accordance with an embodiment of the present invention.
第8圖圖示根據本發明之實施例的用於雷射及電漿切割晶圓或基板的工具佈置之方塊圖。 Figure 8 illustrates a block diagram of a tool arrangement for laser and plasma dicing wafers or substrates in accordance with an embodiment of the present invention.
第9圖圖示根據本發明之實施例的示例性電腦系統之方塊圖。 Figure 9 illustrates a block diagram of an exemplary computer system in accordance with an embodiment of the present invention.
本發明描述切割半導體晶圓之方法,每一晶圓上具有複數個積體電路。在下文描述中闡述眾多特定細節,諸如超短脈衝拉蓋爾高斯雷射劃線方法 及電漿蝕刻條件及材料範圍,以便提供對本發明之實施例的透徹理解。對熟習此項技術者將顯而易見的是,可在無該等特定細節的情況下實施本發明之實施例。在其他情形中,並未詳細描述諸如積體電路製造之熟知的態樣,以免不必要地模糊本發明之實施例。此外,應理解,圖式中所示之各種實施例為說明性表示,且不一定按比例繪製。 The present invention describes a method of dicing a semiconductor wafer having a plurality of integrated circuits on each wafer. Numerous specific details are set forth in the description below, such as the ultrashort pulse Laguerre Gaussian laser scribing method And plasma etching conditions and material ranges to provide a thorough understanding of embodiments of the invention. It will be apparent to those skilled in the art that the embodiments of the invention may be practiced without the specific details. In other instances, well-known aspects such as the fabrication of integrated circuits have not been described in detail so as not to unnecessarily obscure the embodiments of the invention. In addition, the various embodiments shown in the drawings are intended to be illustrative and not necessarily to scale.
可實施涉及初始雷射劃線及後續電漿蝕刻之混合式晶圓或基板切割製程,用於晶粒切單。可使用雷射劃線製程以清潔地移除遮罩層、有機與無機介電層及裝置層。隨後,在晶圓或基板之已曝露或部分蝕刻之後,可終止雷射蝕刻製程。隨後,可採用切割製程之電漿蝕刻部分以蝕刻穿過晶圓或基板的塊體,諸如穿過塊狀單晶矽,以產生晶粒或晶片之切單或切割。更特定言之,一或更多個實施例係針對實施用於例如切割應用之超短脈衝拉蓋爾高斯雷射光束雷射劃線製程。在一特定此類實施例中,雷射光束具有軸向對稱偏振。 A hybrid wafer or substrate dicing process involving initial laser scribe and subsequent plasma etch can be performed for die singulation. A laser scribing process can be used to cleanly remove the mask layer, the organic and inorganic dielectric layers, and the device layer. The laser etch process can then be terminated after the wafer or substrate has been exposed or partially etched. Subsequently, a plasma etched portion of the dicing process can be employed to etch a block through the wafer or substrate, such as through a bulk single crystal germanium, to produce a singulation or dicing of the die or wafer. More specifically, one or more embodiments are directed to implementing an ultrashort pulsed Laguerre laser beam laser scribing process for, for example, a cutting application. In a particular such embodiment, the laser beam has an axially symmetric polarization.
為了提供情境,針對晶圓切割的飛秒雷射劃線及後續電漿蝕刻已被證明對於晶圓切單可行。取決於特定應用,雷射劃線深度可限於遮罩開口及裝置層移除,直至曝露下層矽(Si)基板,或可延伸至Si基板中。在光譜之最末端處,基本上穿過整個晶圓厚度執行雷射劃線,且電漿蝕刻用於修復已切單晶 粒側壁。覆蓋遮罩層可取決於凸塊高度及晶圓厚度為厚的或薄的。在一般範圍中,以下兩個態樣可需要改良:(1)可需要減小由雷射劃線所產生之溝槽側壁之表面粗糙度;(2)可需要增加雷射材料移除速率,以便利用給定雷射功率來改良雷射製程產量。 In order to provide context, femtosecond laser scribing and subsequent plasma etching for wafer dicing have proven to be feasible for wafer singulation. Depending on the particular application, the laser scribing depth may be limited to the mask opening and device layer removal until the underlying germanium (Si) substrate is exposed, or may extend into the Si substrate. At the very end of the spectrum, laser scribing is performed substantially across the entire wafer thickness, and plasma etching is used to repair the cut single crystal Granular sidewalls. The cover mask layer may be thick or thin depending on the bump height and the wafer thickness. In the general scope, the following two aspects may need to be improved: (1) the surface roughness of the trench sidewalls generated by the laser scribing may be required to be reduced; (2) the laser material removal rate may need to be increased, In order to use a given laser power to improve laser process throughput.
習知地,實施圓形偏振高斯模式TEM00雷射光束以在雷射微機械加工中執行雷射劃線或切割,以避免當雷射劃線方向改變時與線性偏振雷射光束另外關聯的溝槽寬度變化。然而,可能以降低雷射吸收係數為代價實現圓形偏振光束之採用,此可影響製程產量。另外,儘管在應用適當雷射光點重疊下可實現雷射劃線溝槽之相對較低側壁粗糙度,例如藉由降低劃線速度或增加雷射脈衝頻率,但是可能以較低劃線速度或較昂貴的雷射總成為代價實現該相對較低側壁粗糙度。由於在較高脈衝頻率下仍必須實現最小雷射脈衝能量,因而可導致成本增加。以及,可改良雷射劃線溝槽之側壁表面粗糙度,以便減少基於電漿蝕刻的切割後側壁平坦化處理工作之費用。 Conventionally, a circularly polarized Gaussian mode TEM00 laser beam is implemented to perform laser scribing or cutting in laser micromachining to avoid a trench associated with the linearly polarized laser beam when the direction of the laser scribing changes. The groove width changes. However, the use of circularly polarized beams may be achieved at the expense of reducing the laser absorption coefficient, which may affect process throughput. In addition, although relatively low sidewall roughness of the laser scribe trenches may be achieved with the application of appropriate laser spot overlap, for example by reducing the scribe speed or increasing the laser pulse frequency, it may be at a lower scribe speed or More expensive lasers always come at a cost to achieve this relatively low sidewall roughness. Since the minimum laser pulse energy must still be achieved at higher pulse frequencies, this can result in increased costs. Moreover, the sidewall surface roughness of the laser scribing trench can be improved to reduce the cost of the plasma etching-based post-cut sidewall flattening process.
根據本文描述之一或更多個實施例,實施超短脈衝拉蓋爾高斯雷射光束(諸如具有軸向對稱偏振的TEM01*模式)以便進行雷射劃線。隨後可執行後續電漿蝕刻操作以便晶圓切割。在一個實施例中,軸向對稱偏振包括徑向偏振及方位角偏振中的一 者或兩者。具有TEM01*模式的軸向偏振雷射光束可提供與圓形偏振高斯光束(例如,TEM00模式)所提供的相比多達兩倍之高雷射吸收係數。此外,由軸向偏振雷射光束所產生之溝槽上的側壁表面粗糙度可比由圓形偏振雷射光束所實現的更低。軸向偏振雷射光束與方位角偏振雷射光束兩者皆可提供較深穿透深度,且方位角偏振光束可產生具有較陡峭錐度的側壁。在一個實施例中,具有軸向對稱偏振模式(例如,徑向偏振或方位角偏振或兩者)的環形圈形狀雷射光束(例如,TEM01*模式)可由初始線性偏振高斯光束(TEM00模式)轉換而成。在本文描述之一或更多個實施例中,具有軸向對稱偏振的雷射光束經實施以改良雷射開口溝槽之光滑度,該雷射開口溝槽可轉變為更光滑的電漿蝕刻溝槽輪廓。在本文描述之一或更多個實施例中,與軸向偏振關聯的較高能量耦合效率改良了雷射劃線產量及/或賦能厚遮罩開口、厚裝置層移除或較寬切口形成,上述之任一者本可能在利用相同雷射功率位準的圓形偏振光束下難以完成。 In accordance with one or more embodiments described herein, an ultrashort pulse Laguerre laser beam (such as a TEM01* mode with axially symmetric polarization) is implemented for laser scribing. Subsequent plasma etching operations can then be performed for wafer dicing. In one embodiment, the axially symmetric polarization comprises one of radial polarization and azimuthal polarization. Or both. An axially polarized laser beam with a TEM01* mode provides up to twice the high laser absorption coefficient compared to that provided by a circularly polarized Gaussian beam (eg, TEM00 mode). Furthermore, the sidewall surface roughness on the trench created by the axially polarized laser beam can be lower than that achieved by a circularly polarized laser beam. Both the axially polarized laser beam and the azimuthal polarized laser beam provide a deeper penetration depth, and the azimuthal polarized beam can produce a sidewall with a steeper taper. In one embodiment, an annular ring shaped laser beam (eg, TEM01* mode) having an axially symmetric polarization mode (eg, radial or azimuthal polarization or both) may be an initial linearly polarized Gaussian beam (TEM00 mode) Converted. In one or more embodiments described herein, a laser beam having axially symmetric polarization is implemented to improve the smoothness of the laser opening trench, which can be converted to a smoother plasma etch. Groove profile. In one or more embodiments described herein, higher energy coupling efficiencies associated with axial polarization improve laser scribing yield and/or energizing thick mask openings, thick device layer removal, or wider slits Forming, any of the above may have been difficult to accomplish under a circularly polarized beam of the same laser power level.
因此,在本發明之一態樣中,可使用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程與電漿蝕刻製程之組合將半導體晶圓切割成切單積體電路。第1圖係表示根據本發明之實施例的切割包括複數個積體電路之半導體晶圓之方法中的操作之流程圖 100。第2A圖至第2C圖圖示根據本發明之實施例的在執行切割半導體晶圓之方法期間的包括複數個積體電路之半導體晶圓之橫截面視圖,該等視圖對應於流程圖100之操作。 Thus, in one aspect of the invention, the semiconductor wafer can be diced into a singulated-integral circuit using a combination of an ultrashort pulse Laguerre laser beam laser scribe process and a plasma etch process. 1 is a flow chart showing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits in accordance with an embodiment of the present invention. 100. 2A through 2C illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during a method of performing a dicing of a semiconductor wafer, the views corresponding to the flowchart 100, in accordance with an embodiment of the present invention. operating.
參看流程圖100之操作102,及對應的第2A圖,在半導體晶圓或基板204上形成遮罩202。遮罩202由半導體晶圓204之表面上所形成之覆蓋及保護積體電路206的層組成。遮罩202亦覆蓋積體電路206之各者之間所形成的介入劃道207。 Referring to operation 102 of flowchart 100 and corresponding FIG. 2A, a mask 202 is formed over the semiconductor wafer or substrate 204. The mask 202 is composed of a layer formed on the surface of the semiconductor wafer 204 that covers and protects the integrated circuit 206. The mask 202 also covers the interventional tract 207 formed between each of the integrated circuits 206.
根據本發明之一實施例,形成遮罩202涉及形成一層,該層諸如但不限於光阻層或I形線圖案化層。舉例而言,諸如光阻層之聚合物層可由在其他情況下適用於微影製程的材料組成。在一個實施例中,光阻層由正向光阻材料組成,該正向光阻材料諸如但不限於248奈米(nm)抗蝕劑、193nm抗蝕劑、157nm抗蝕劑、超紫外線(extreme ultra-violet;EUV)抗蝕劑或具有重氮萘醌敏化劑的酚醛樹脂基質。在另一實施例中,光阻層由負向光阻材料組成,該負向光阻材料諸如但不限於聚順異戊二烯及聚乙烯基肉桂酸酯。 In accordance with an embodiment of the invention, forming the mask 202 involves forming a layer such as, but not limited to, a photoresist layer or an I-line patterned layer. For example, a polymer layer such as a photoresist layer can be composed of materials that are otherwise suitable for use in lithography processes. In one embodiment, the photoresist layer is comprised of a forward photoresist material such as, but not limited to, 248 nanometer (nm) resist, 193 nm resist, 157 nm resist, ultra-ultraviolet ( Extreme ultra-violet; EUV) resist or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photoresist layer is comprised of a negative photoresist material such as, but not limited to, polycis isoprene and polyvinyl cinnamate.
在另一實施例中,形成遮罩202涉及形成電漿沉積製程中沉積的層。舉例而言,在一個此類實施例中,遮罩202由電漿沉積聚四氟乙烯或類似聚四氟乙烯(聚合CF2)層組成。在一特定實施例中, 在涉及氣體C4F8的電漿沉積製程中沉積聚合CF2層。 In another embodiment, forming the mask 202 involves forming a layer deposited in a plasma deposition process. For example, in one such embodiment, the mask 202 (2 polymerizable CF) layer is deposited by a plasma Teflon polytetrafluoroethylene or the like. In a particular embodiment, it relates to a gas in a plasma deposition process C 4 F 8 in CF 2 layer deposition polymerization.
在另一實施例中,形成遮罩202涉及形成水溶性遮罩層。在一實施例中,水溶性遮罩層在水介質中可輕易溶解。舉例而言,在一個實施例中,水溶性遮罩層由可溶於鹼性溶液、酸性溶液或去離子水中的一或更多者的材料組成。在一實施例中,水溶性遮罩層在曝露於加熱製程(諸如大約處於50-160攝氏度範圍內加熱)後保持該遮罩層之水溶性。舉例而言,在一個實施例中,在曝露於雷射及電漿蝕刻切單製程中所使用的腔室條件下後,水溶性遮罩層可溶於水性溶液。在一個實施例中,水溶性遮罩層由一材料組成,該材料諸如而不限於聚乙烯醇、聚丙烯酸、葡聚糖、聚甲基丙烯酸、聚乙烯亞胺或聚氧化乙烯。在一特定實施例中,水溶性遮罩層在水性溶液中具有大約處於1-15微米/分鐘範圍內的蝕刻速率,且更特定言之具有大約1.3微米/分鐘的蝕刻速率。 In another embodiment, forming the mask 202 involves forming a water soluble mask layer. In one embodiment, the water soluble mask layer is readily soluble in an aqueous medium. For example, in one embodiment, the water soluble mask layer is comprised of a material that is soluble in one or more of an alkaline solution, an acidic solution, or deionized water. In one embodiment, the water soluble mask layer maintains the water solubility of the mask layer after exposure to a heating process, such as heating in the range of about 50-160 degrees Celsius. For example, in one embodiment, the water soluble mask layer is soluble in the aqueous solution after exposure to the chamber conditions used in the laser and plasma etch dicing process. In one embodiment, the water soluble mask layer is comprised of a material such as, but not limited to, polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethyleneimine, or polyethylene oxide. In a particular embodiment, the water soluble mask layer has an etch rate in the aqueous solution of about 1-15 microns per minute, and more specifically an etch rate of about 1.3 microns per minute.
在另一實施例中,形成遮罩202涉及形成紫外線可固化遮罩層。在一實施例中,遮罩層具有對紫外光的易感性,該易感性使紫外線可固化層之黏合度減小了至少約80%。在一個此類實施例中,紫外線層由聚氯乙烯或丙烯酸基材料組成。在一實施例中,紫外線可固化層由具有黏合特性的材料或材料堆疊組成,該黏合特性在曝露於紫外光後減弱。在一實 施例中,紫外線可固化黏合薄膜對大約365nm紫外光敏感。在一個此類實施例中,此敏感性賦能使用LED光來執行固化。 In another embodiment, forming the mask 202 involves forming an ultraviolet curable mask layer. In one embodiment, the mask layer has a susceptibility to ultraviolet light that reduces the adhesion of the ultraviolet curable layer by at least about 80%. In one such embodiment, the ultraviolet layer is comprised of a polyvinyl chloride or acrylic based material. In one embodiment, the ultraviolet curable layer is comprised of a stack of materials or materials having adhesive properties that are attenuated upon exposure to ultraviolet light. In a real In the examples, the UV curable adhesive film is sensitive to about 365 nm ultraviolet light. In one such embodiment, this sensitivity enables the use of LED light to perform curing.
在一實施例中,半導體晶圓或基板204由一材料組成,該材料適合於經受製造製程,且半導體處理層可適宜地安置在該材料之上。舉例而言,在一個實施例中,半導體晶圓或基板204由基於IV族之材料組成,該材料諸如但不限於結晶矽、鍺或矽/鍺。在一特定實施例中,提供半導體晶圓204包括提供單晶矽基板。在一特定實施例中,單晶矽基板摻雜有雜質原子。在另一實施例中,半導體晶圓或基板204由III-V族材料組成,諸如例如在發光二極體(light emitting diode;LED)之製造中使用的III-V族材料基板。 In one embodiment, the semiconductor wafer or substrate 204 is comprised of a material that is suitable for undergoing a fabrication process, and a semiconductor processing layer can be suitably disposed over the material. For example, in one embodiment, the semiconductor wafer or substrate 204 is comprised of a Group IV based material such as, but not limited to, crystalline germanium, ruthenium or iridium/ruthenium. In a particular embodiment, providing semiconductor wafer 204 includes providing a single crystal germanium substrate. In a particular embodiment, the single crystal germanium substrate is doped with impurity atoms. In another embodiment, the semiconductor wafer or substrate 204 is comprised of a III-V material such as, for example, a III-V material substrate used in the fabrication of light emitting diodes (LEDs).
在一實施例中,在半導體晶圓或基板204上或中安置有作為積體電路206之一部分的半導體裝置之陣列。此類半導體裝置之實例包括但不限於製造在矽基板中且封裝在介電層中的記憶體裝置或互補金屬氧化物半導體(complimentary metal-oxide-semiconductor;CMOS)電晶體。複數個金屬互連可在該等裝置或電晶體上方及在周圍的介電層中形成,並可用於電性耦接該等裝置或電晶體以形成積體電路206。構成劃道207之材料可與用於形成積體電路206之彼等材料類似或相同。舉 例而言,劃道207可由介電材料層、半導體材料層及金屬化材料組成。在一個實施例中,劃道207中的一或更多者包括類似於積體電路206之實際裝置之測試裝置。 In one embodiment, an array of semiconductor devices as part of integrated circuit 206 is disposed on or in semiconductor wafer or substrate 204. Examples of such semiconductor devices include, but are not limited to, memory devices or complementary metal-oxide-semiconductor (CMOS) transistors fabricated in a germanium substrate and encapsulated in a dielectric layer. A plurality of metal interconnects can be formed over the devices or transistors and in surrounding dielectric layers and can be used to electrically couple the devices or transistors to form integrated circuits 206. The materials comprising the scribe lines 207 may be similar or identical to the materials used to form the integrated circuit 206. Lift For example, the scribe line 207 can be composed of a dielectric material layer, a semiconductor material layer, and a metallized material. In one embodiment, one or more of the lanes 207 include a test device similar to the actual device of the integrated circuit 206.
參看流程圖100之操作104及對應的第2B圖,利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程圖案化遮罩202以提供具有間隙210的經圖案化遮罩208,從而曝露半導體晶圓或基板204的介於積體電路206之間的區域。因此,使用雷射劃線製程移除最初形成於積體電路206之間的劃道207之材料。根據本發明之一實施例,利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程圖案化遮罩202包括使溝槽212部分地形成於半導體晶圓204的介於積體電路206之間的區域內,如第2B圖中所描繪。 Referring to operation 104 of flowchart 100 and corresponding FIG. 2B, the ultra-short pulse LaGail's laser beam laser scribing process patterning mask 202 is utilized to provide a patterned mask 208 having a gap 210 for exposure. A region of the semiconductor wafer or substrate 204 that is between the integrated circuits 206. Therefore, the material of the scribe line 207 originally formed between the integrated circuits 206 is removed using a laser scribing process. In accordance with an embodiment of the present invention, the ultra-short pulsed Laguerre laser beam laser scribing process patterning mask 202 includes a portion of the semiconductor wafer 204 that is partially formed on the semiconductor wafer 204. In the area between, as depicted in Figure 2B.
根據本發明之一實施例,超短脈衝拉蓋爾高斯雷射光束雷射劃線製程涉及利用具有軸向對稱偏振的雷射光束進行劃線。在一個實施例中,雷射光束具有徑向偏振元件。在另一實施例中,雷射光束具有方位角偏振元件。在另一實施例中,雷射光束具有徑向偏振元件與方位角偏振元件兩者。在另一實施例中,雷射光束具有TEM01*模式。在另一實施例中,雷射光束具有環形圈形狀。 In accordance with an embodiment of the present invention, an ultrashort pulse Laguerre laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization. In one embodiment, the laser beam has a radial polarization element. In another embodiment, the laser beam has an azimuthal polarization element. In another embodiment, the laser beam has both a radial polarization element and an azimuthal polarization element. In another embodiment, the laser beam has a TEM01* mode. In another embodiment, the laser beam has an annular ring shape.
為了提供進一步情境,雷射輻射之偏振係所有雷射光束中所固有之基本光學特性。雷射光係 含有電分量與磁分量兩者之橫向電磁波,且電場與磁場向量指向垂直於波行進方向。電磁波之偏振方向已經傳統界定以沿電場向量之振盪方向。當光以非垂直角度撞擊光學表面(諸如光束分光器)時,反射及透射特徵取決於偏振。位於含有入射及反射光束的平面內有偏振向量的光被稱為經P偏振,且垂直於含有入射及反射光束的平面偏振的光被稱為經S偏振。可將入射偏振之任何任意狀態表示為S及P分量之向量和。 In order to provide further context, the polarization of the laser radiation is the fundamental optical property inherent in all laser beams. Laser light system A transverse electromagnetic wave containing both electrical and magnetic components, and the electric field and magnetic field vector are directed perpendicular to the direction of travel of the wave. The polarization direction of the electromagnetic wave has been conventionally defined to oscillate along the direction of the electric field vector. When light strikes an optical surface (such as a beam splitter) at a non-perpendicular angle, the reflection and transmission characteristics depend on the polarization. Light having a polarization vector in a plane containing incident and reflected beams is referred to as P-polarized, and light perpendicular to the plane containing the incident and reflected beams is referred to as S-polarized. Any arbitrary state of the incident polarization can be expressed as a vector sum of the S and P components.
第3A圖圖示作為偏振面的電分量之平面。參看第3A圖之部分302,圖示相對於光束行進方向的電場與磁場向量之定向。參看第3A圖之部分304,圖示在z方向(或k方向)上傳播的線性偏振光以及電場振幅Y及磁場振幅X。參看第3A圖之部分306,圖示傳播方向及偏振面以及磁場與電場向量。第3B圖圖示雷射光束之P偏振及S偏振之概念。參看第3B圖,部分308圖示自光束分光器相對於雷射光束傳播方向的反射光束與透射光束之S偏振及P偏振。 Fig. 3A illustrates the plane of the electrical component as a plane of polarization. Referring to portion 302 of Figure 3A, the orientation of the electric and magnetic field vectors relative to the direction of travel of the beam is illustrated. Referring to portion 304 of Figure 3A, the linearly polarized light propagating in the z-direction (or k-direction) and the electric field amplitude Y and the magnetic field amplitude X are illustrated. Referring to portion 306 of Figure 3A, the direction of propagation and the plane of polarization and the magnetic field and electric field vector are illustrated. Figure 3B illustrates the concept of P-polarization and S-polarization of a laser beam. Referring to Figure 3B, portion 308 illustrates the S-polarization and P-polarization of the reflected and transmitted beams from the beam splitter relative to the direction of propagation of the laser beam.
應瞭解,存在不同類型偏振。習知偏振狀態包括線性偏振與圓形偏振。在兩種情況中,電向量之方向並不取決於光束截面中的空間位置。線性偏振雷射具有在固定方向上延伸的固定電向量。具有圓形偏振的雷射使得自身電向量以圓形圖案均勻旋轉。非習知偏振狀態包括徑向偏振,其中光束截面之平面內的電向量方向平行於徑向方向。非習知偏振狀 態亦包括方位角偏振,其中光束截面之平面內的電向量方向垂直於徑向方向。在雷射光束內,電向量(而非磁向量)含有處理功率。因此,電向量定向(亦即,偏振狀態/方向)影響雷射材料相互作用,且因此影響材料處理能力。詳言之,根據本發明之一實施例,偏振方向可對雷射劃線/切割製程之品質及產量/效率具有明顯影響。 It should be understood that there are different types of polarization. Conventional polarization states include linear polarization and circular polarization. In both cases, the direction of the electrical vector does not depend on the spatial position in the beam section. Linearly polarized lasers have a fixed electrical vector that extends in a fixed direction. A laser with circular polarization causes its own electrical vector to rotate uniformly in a circular pattern. Non-conventional polarization states include radial polarization in which the direction of the electrical vector in the plane of the beam section is parallel to the radial direction. Non-known polarization The state also includes azimuthal polarization, wherein the direction of the electrical vector in the plane of the beam section is perpendicular to the radial direction. Within a laser beam, an electrical vector (rather than a magnetic vector) contains processing power. Thus, the electrical vector orientation (ie, polarization state/direction) affects the laser material interaction and thus the material handling capabilities. In particular, in accordance with an embodiment of the present invention, the polarization direction can have a significant impact on the quality and yield/efficiency of the laser scribing/cutting process.
第3C圖圖示根據本發明之實施例的如箭頭所表示之習知及向量雷射光束的不同類型偏振。參看第3C圖,對於習知偏振狀態,諸如線性或圓形偏振310,電向量之方向並不取決於光束截面中的空間位置。在向量光束中,偏振狀態為諸如徑向與方位角偏振312之空間變體。 Figure 3C illustrates different types of polarization of conventional and vector laser beams as indicated by the arrows in accordance with an embodiment of the present invention. Referring to Figure 3C, for conventional polarization states, such as linear or circular polarization 310, the direction of the electrical vector does not depend on the spatial position in the beam section. In a vector beam, the polarization state is a spatial variant such as radial and azimuthal polarization 312.
第3D圖示意性圖示根據本發明之實施例的對耦合至材料中的雷射能之偏振效應。參看第3D圖,示意圖314表明,可將作為入射的雷射輻射之總能量(表示為1或100%)分成透射率(T)、反射率(R)及吸收率(A),其中A+R+T=1,或A=1-R-T。由A表示之能量耦合效率受R及T影響。偏振對雷射輻射之一個已知效應為,偏振可影響材料表面上的雷射光束之反射率。 Figure 3D schematically illustrates the polarization effect on the laser energy coupled into the material in accordance with an embodiment of the present invention. Referring to Figure 3D, diagram 314 shows that the total energy (expressed as 1 or 100%) of the incident laser radiation can be divided into transmittance (T), reflectance (R), and absorption (A), where A+ R+T=1, or A=1-RT. The energy coupling efficiency represented by A is affected by R and T. One known effect of polarization on laser radiation is that polarization can affect the reflectivity of a laser beam on the surface of a material.
根據本發明之一實施例,對耦合至材料中的雷射能之偏振效應可歸於以下觀察:偏振方向藉由影響材料表面上的雷射反射性來影響耦合至給定 材料中的雷射能。例如,第3E圖圖示根據本發明之實施例的偏振方向對比雷射劃線方向。參看第3E圖,示意圖316圖示偏振方向可改變,且因此可取決於偏振方向與切割/劃線(雷射運動)方向之間的關聯影響雷射劃線/切割製程之品質及產量/效率。在第3E圖中描繪所使用坐標系中的相關樣本及雷射光束位置。 In accordance with an embodiment of the present invention, the polarization effect of the laser energy coupled into the material can be attributed to the observation that the polarization direction affects coupling to a given by affecting the laser reflectivity on the surface of the material. The laser energy in the material. For example, Figure 3E illustrates a polarization direction versus a laser scribe line direction in accordance with an embodiment of the present invention. Referring to FIG. 3E, schematic 316 illustrates that the polarization direction can be varied, and thus the quality and yield/efficiency of the laser scribing/cutting process can be affected depending on the relationship between the polarization direction and the cutting/scoping (laser motion) direction. . The correlation samples and laser beam positions in the coordinate system used are depicted in Figure 3E.
第3F圖圖示根據本發明之實施例的偏振方向對比雷射劃線方向之效應。參看第3F圖之部分318,在線性偏振的情況中,光束與物質相互作用之參數取決於偏振方向。參看第3F圖之部分320,當改變雷射劃線方向時,可發生切口寬度變化。該變化之原因可為當偏振成直線及垂直於雷射光束行進方向時吸收之雷射功率不同。 Figure 3F illustrates the effect of polarization direction versus laser scribe direction in accordance with an embodiment of the present invention. Referring to section 318 of Figure 3F, in the case of linear polarization, the parameters of the beam interacting with matter depend on the direction of polarization. Referring to portion 320 of Figure 3F, a change in the width of the slit can occur when the direction of the laser scribing is changed. The reason for this change may be that the laser power absorbed is different when the polarization is linear and perpendicular to the direction of travel of the laser beam.
更概括而言,根據本發明之一實施例,在線性偏振情況中,光束與物質相互作用之參數取決於偏振方向。此外,當改變雷射劃線方向時可發生劃線深度變化,因為當偏振成直線及垂直於雷射光束行進方向時吸收之雷射功率不同。在某些情況中,能量效率被定義為切割深度乘以切割速度之乘積。在圓形或隨機偏振光束的情況中,電向量隨時間推移快速變化。亦即,電向量在所有切割方向上被均勻定向,使得偏振對切割品質之效應經時間平均,且可看到對切口寬度或切割深度無影響。然而,根據本發明之一實施例,從雷射能量耦合效率或切割及關聯切割產量觀 點來看,圓形偏振對於最小損失或最大吸收並非最佳。 More generally, in accordance with an embodiment of the present invention, in the case of linear polarization, the parameters of the beam interacting with matter depend on the direction of polarization. In addition, a change in the depth of the scribe line may occur when the direction of the laser scribe line is changed because the absorbed laser power is different when the polarization is linear and perpendicular to the direction of travel of the laser beam. In some cases, energy efficiency is defined as the product of the depth of cut multiplied by the cutting speed. In the case of a circular or randomly polarized beam, the electrical vector changes rapidly over time. That is, the electric vector is uniformly oriented in all cutting directions such that the effect of polarization on the cutting quality is time averaged and it can be seen that there is no effect on the slit width or depth of cut. However, according to an embodiment of the present invention, the efficiency of coupling from laser energy or the relationship between cutting and associated cutting yield From a point of view, circular polarization is not optimal for minimum loss or maximum absorption.
第3G圖圖示具有簡單強度結構及習知偏振之雷射光束。參看第3G圖,部分322圖示對於習知高斯光束之圓形及線性偏振模式。部分324圖示TEM00光束之高斯強度結構。部分326係隨光束輪廓函數變化之功率曲線圖,具有對應光點328。 Figure 3G illustrates a laser beam having a simple intensity structure and a conventional polarization. Referring to Figure 3G, section 322 illustrates the circular and linear polarization modes for a conventional Gaussian beam. Portion 324 illustrates the Gaussian intensity structure of the TEM00 beam. Portion 326 is a power plot that varies with beam profile function and has a corresponding spot 328.
第3H圖圖示根據本發明之實施例的具有複雜強度結構及偏振之雷射光束。參看第3H圖,部分330圖示繪製為隨時間函數變化之線性偏振拉蓋爾高斯光束偏振模式。部分332圖示TEM01*光束之環形圈形狀強度結構。部分334係隨光束輪廓函數變化之功率曲線圖,具有對應光點336。為了提供情境,第3I圖圖示根據本發明之實施例的具有不同強度結構的雷射光束(338)之實例及具有圓柱對稱強度結構的雷射光束(340)之實例。 Figure 3H illustrates a laser beam having a complex intensity structure and polarization in accordance with an embodiment of the present invention. Referring to Figure 3H, section 330 illustrates a linearly polarized Laguerre Gaussian beam polarization mode that is plotted as a function of time. Portion 332 illustrates the annular ring shape strength structure of the TEM01* beam. Portion 334 is a power plot that varies with beam profile function and has a corresponding spot 336. To provide a context, FIG. 3I illustrates an example of a laser beam (338) having different intensity structures and a laser beam (340) having a cylindrically symmetric intensity structure in accordance with an embodiment of the present invention.
第3J圖圖示根據本發明之實施例的具有複雜偏振與複雜強度結構兩者之雷射光束。參看第3J圖之部分342,(a)圖示徑向偏振光束,及(b)圖示方位角偏振光束。部分344圖示繪製為隨時間函數變化之徑向偏振拉蓋爾高斯光束偏振模式。部分346圖示環形圈形狀強度結構。部分348係隨光束輪廓函數變化之功率曲線圖,具有對應光點350。在一實施 例中,非習知偏振與獨特強度輪廓之組合提供了雷射剝蝕方面的改良效率及精確度。 Figure 3J illustrates a laser beam having both complex polarization and complex intensity structures in accordance with an embodiment of the present invention. Referring to portion 342 of Figure 3J, (a) illustrates a radially polarized beam, and (b) illustrates an azimuthally polarized beam. Portion 344 is illustrated as a radially polarized Laguerre Gaussian beam polarization mode as a function of time. Portion 346 illustrates an annular ring shape strength structure. Portion 348 is a power plot that varies with beam profile function and has a corresponding spot 350. In one implementation In the example, the combination of non-conventional polarization and unique intensity profile provides improved efficiency and precision in laser ablation.
在一實施例中,隨後,使用具有複雜偏振與複雜強度結構兩者的雷射光束執行雷射剝蝕。在一個實施例中,使用徑向偏振光束。為了比較,徑向偏振光束對比圓形偏振光束,在徑向偏振情況中的有效吸收係數為圓形偏振之有效吸收係數的兩倍。因此,對於徑向偏振光束,切割深度乘以切割速度之乘積比圓形偏振光束之乘積高出約1.5-2.0倍。在一個實施例中,就雷射機械加工之粗糙度而言,實現改良的劃線/切割品質。在一特定實施例中,徑向偏振光束與圓形偏振光束相比產生更光滑的側壁。在一特定實例中,徑向偏振光束TEM01*與圓形偏振高斯光束TEM00相比展示出高出約兩倍之雷射吸收,及穿過切割厚度(例如,上部分及下部分)的下側壁表面粗糙度(Rz)。 In an embodiment, laser ablation is then performed using a laser beam having both complex polarization and complex intensity structures. In one embodiment, a radially polarized beam is used. For comparison, a radially polarized beam contrasts with a circularly polarized beam, and the effective absorption coefficient in the case of radial polarization is twice the effective absorption coefficient of circular polarization. Thus, for a radially polarized beam, the product of the depth of cut multiplied by the cutting speed is about 1.5-2.0 times higher than the product of the circularly polarized beam. In one embodiment, improved scribing/cutting quality is achieved with respect to the roughness of laser machining. In a particular embodiment, the radially polarized beam produces a smoother sidewall than the circularly polarized beam. In a particular example, the radially polarized beam TEM01* exhibits approximately twice the absorption of the laser compared to the circularly polarized Gaussian beam TEM00, and the lower sidewall passing through the cut thickness (eg, the upper and lower portions) Surface roughness (Rz).
第4圖圖示根據本發明之實施例的具有徑向及/或方位角偏振之TEM01*雷射光束之形成。參看第4圖,部分402圖示路徑(a),其中實現徑向偏振以提供TME01*。部分404圖示路徑(b),其中實現方位角偏振以提供TME01*。在一個實施例中,將偏振形成為兩個平面偏振模式TEM01之重疊。在一實施例中,此類線性至徑向/方位角偏振轉換(radial/azimuthal polarization conversion;LRAC)係基於分段半波片。在比較徑向偏振光束TEM01*與方位角偏振光束TEM01*時,相對於切割效率,方位角偏振光束可實現與徑向偏振光束相比兩倍深度的穿透。相對於切口輪廓,方位角偏振光束比徑向偏振光束產生具有較大錐度的較窄切割。 Figure 4 illustrates the formation of a TEM01* laser beam having radial and/or azimuthal polarization in accordance with an embodiment of the present invention. Referring to Figure 4, portion 402 illustrates path (a) in which radial polarization is achieved to provide TME01*. Portion 404 illustrates path (b) in which azimuthal polarization is achieved to provide TME01*. In one embodiment, the polarization is formed as an overlap of two plane polarization modes TEM01. In an embodiment, such linear to radial/azimuth polarization conversion (radial/azimuthal polarization) Conversion; LRAC) is based on segmented half-wave plates. When comparing the radially polarized beam TEM01* with the azimuthal polarized beam TEM01*, the azimuthal polarized beam can achieve twice the depth of penetration compared to the radially polarized beam with respect to the cutting efficiency. The azimuthal polarized beam produces a narrower cut with a larger taper than the radially polarized beam relative to the slit profile.
在一實施例中,將基於飛秒之雷射用作超短脈衝拉蓋爾高斯雷射光束雷射劃線製程的來源。舉例而言,在一實施例中,使用波長處於可見光譜加紫外線(ultra-violet;UV)及紅外線(infra-red;IR)範圍(總稱為寬頻帶光譜)內的雷射來提供基於飛秒之雷射,亦即脈衝寬度在飛秒(10-15秒)數量級之雷射。在一個實施例中,剝蝕並非或基本上並非依波長而定,且因此,剝蝕適合於複雜薄膜,該等薄膜諸如遮罩202之薄膜、劃道207之薄膜,及在可能情況下的半導體晶圓或基板204的一部分之薄膜。 In one embodiment, a femtosecond-based laser is used as a source of ultrashort pulse Laguerre's laser beam laser scribing process. For example, in one embodiment, a laser with a wavelength in the visible spectrum plus ultraviolet (infra-red; IR) and infrared (infra-red; IR) ranges (collectively referred to as a broadband spectrum) is used to provide femtosecond-based femtoseconds. The laser, that is, a laser with a pulse width on the order of femtoseconds (10 -15 seconds). In one embodiment, the ablation is not or substantially independent of wavelength, and thus, the ablation is suitable for complex films such as a film of mask 202, a film of scribe 207, and, where possible, a semiconductor crystal. A film of a portion of a circle or substrate 204.
第5圖圖示根據本發明之實施例的使用飛秒範圍、皮秒範圍及奈秒範圍內的雷射脈衝寬度之效應。參看第5圖,與使用較長脈衝寬度(例如,通孔500A經奈秒處理後得到顯著損傷502A)相比,藉由使用具有來自飛秒範圍內之貢獻的雷射光束輪廓使熱損傷問題得以減緩或消除(例如,通孔500C經飛秒處理後損傷最小化至無損傷502C)。在通孔 500C之形成期間,損傷之消除或減緩可歸因於缺乏低能回耦(如500B/502B之基於皮秒之雷射剝蝕所見)或熱平衡(如基於奈秒之雷射剝蝕所見),如第5圖中所描繪。 Figure 5 illustrates the effect of using a femtosecond range, a picosecond range, and a laser pulse width in the nanosecond range, in accordance with an embodiment of the present invention. Referring to Fig. 5, the thermal damage problem is achieved by using a laser beam profile having a contribution from the femtosecond range compared to using a longer pulse width (e.g., through hole 500A yielding significant damage 502A after nanosecond processing). It can be slowed or eliminated (for example, the damage of the through hole 500C after femtosecond treatment is minimized to no damage 502C). Through hole During the formation of 500C, the elimination or slowing of damage can be attributed to the lack of low-energy back-coupling (as seen in picosecond-based laser ablation of 500B/502B) or thermal equilibrium (as seen in nanosecond-based laser ablation), such as section 5. It is depicted in the figure.
諸如光束輪廓之雷射參數選擇對開發成功的雷射劃線及切割製程而言可能至關重要,該製程使碎裂、微裂紋及分層最小化,以便實現清潔的雷射劃線切痕。雷射劃線切痕愈清潔,可在最終晶粒切單時執行的蝕刻製程便愈平滑。在半導體裝置晶圓中,通常在晶圓上安置不同材料類型(例如,導體、絕緣體、半導體)及厚度之眾多功能層。此類材料可包括但不限於諸如聚合物之有機材料、金屬或諸如二氧化矽及氮化矽之無機介電質。 Laser parameter selection such as beam profile may be critical to the development of successful laser scribing and cutting processes that minimize fragmentation, microcracking and delamination for clean laser scribing . The cleaner the laser markings, the smoother the etching process that can be performed when the final die is singulated. In a semiconductor device wafer, a plurality of functional layers of different material types (eg, conductors, insulators, semiconductors) and thicknesses are typically placed on the wafer. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as cerium oxide and tantalum nitride.
安置在晶圓或基板上的個別積體電路之間的劃道可包括與積體電路自身類似或相同的層。舉例而言,第6圖圖示根據本發明之實施例的可用於半導體晶圓或基板之劃道區域中的材料堆疊之橫截面視圖。 The scribes between the individual integrated circuits disposed on the wafer or substrate may include layers similar or identical to the integrated circuits themselves. For example, Figure 6 illustrates a cross-sectional view of a stack of materials that can be used in a scribe region of a semiconductor wafer or substrate in accordance with an embodiment of the present invention.
參看第6圖,劃道區域600包括矽基板之頂部部分602、第一二氧化矽層604、第一蝕刻終止層606、第一低介電常數介電層608(例如,具有一介電常數,該介電常數低於二氧化矽之介電常數4.0)、第二蝕刻終止層610、第二低介電常數介電層612、第三蝕刻終止層614、未摻雜二氧化矽玻璃 (undoped silica glass;USG)層616、第二二氧化矽層618及光阻層620,該等層以相對厚度加以描繪。在第一蝕刻終止層606與第三蝕刻終止層614之間且穿過第二蝕刻終止層610安置銅金屬化材料622。在一特定實施例中,第一蝕刻終止層606、第二蝕刻終止層610及第三蝕刻終止層614由氮化矽組成,而低介電常數介電層608及612由摻雜碳的氧化矽材料組成。 Referring to FIG. 6, the scribe region 600 includes a top portion 602 of the germanium substrate, a first ruthenium dioxide layer 604, a first etch stop layer 606, and a first low-k dielectric layer 608 (eg, having a dielectric constant) The dielectric constant is lower than the dielectric constant of the germanium dioxide 4.0), the second etch stop layer 610, the second low-k dielectric layer 612, the third etch stop layer 614, and the undoped bismuth oxide glass. An undoped silica glass (USG) layer 616, a second hafnium oxide layer 618, and a photoresist layer 620 are depicted in relative thicknesses. A copper metallization material 622 is disposed between the first etch stop layer 606 and the third etch stop layer 614 and through the second etch stop layer 610. In a particular embodiment, the first etch stop layer 606, the second etch stop layer 610, and the third etch stop layer 614 are composed of tantalum nitride, and the low-k dielectric layers 608 and 612 are doped with carbon.矽 material composition.
在習知雷射照射(諸如基於奈秒之照射)下,劃道600之材料在光學吸收及剝蝕機制方面表現差異巨大。舉例而言,諸如二氧化矽之介電層在正常條件下對於所有市售雷射波長而言基本上為透明。相比而言,金屬、有機物(例如,低介電常數材料)及矽可非常容易地耦合光子,尤其是回應於基於奈秒之照射。在一實施例中,藉由剝蝕二氧化矽層,隨後剝蝕低介電常數材料層及銅層,將超短脈衝拉蓋爾高斯雷射光束雷射劃線製程用於圖案化二氧化矽層、低介電常數材料層及銅層。 Under conventional laser illumination (such as nanosecond-based illumination), the material of the scribe 600 varies greatly in optical absorption and erosion mechanisms. For example, a dielectric layer such as hafnium oxide is substantially transparent under normal conditions for all commercially available laser wavelengths. In contrast, metals, organics (eg, low dielectric constant materials), and germanium can couple photons very easily, especially in response to nanosecond-based illumination. In one embodiment, an ultrashort pulse Laguerre laser beam laser scribing process is used to pattern the ceria layer by ablation of the hafnium oxide layer followed by ablation of the low dielectric constant material layer and the copper layer. , low dielectric constant material layer and copper layer.
可以單道次執行或以多道次執行劃線製程,但在一實施例中,較佳為執行1至2道次。在一個實施例中,工件中的劃線深度大約處於5微米至50微米深的範圍內,較佳地大約處於10微米至20微米深的範圍內。在一實施例中,所產生之雷射光束切口寬度大約處於2微米至15微米範圍內,但在矽晶圓劃線 /切割中較佳的切口寬度大約處於6微米至10微米範圍內,該等切口寬度在裝置/矽介面處測得。 The scribing process can be performed in a single pass or in multiple passes, but in one embodiment, it is preferred to perform 1 to 2 passes. In one embodiment, the scribe depth in the workpiece is in the range of from about 5 microns to about 50 microns deep, preferably from about 10 microns to about 20 microns deep. In one embodiment, the resulting laser beam kerf width is in the range of approximately 2 microns to 15 microns, but is scribed on the wafer The preferred slit width in the cut is approximately in the range of 6 microns to 10 microns, and the width of the slits is measured at the device/tank interface.
可選擇具有益處及優勢之雷射參數,諸如提供足夠高的雷射強度以實現無機介電質(例如,二氧化矽)之游離化及在直接剝蝕無機介電質之前將由下層損傷導致的分層及碎裂最小化。此外,可選擇參數以提供具有精確控制剝蝕寬度(例如,切口寬度)及深度之有意義的工業應用製程產量。在一實施例中,超短脈衝拉蓋爾高斯雷射光束雷射劃線製程適合於提供此等優勢。 Laser parameters with benefits and advantages can be selected, such as providing a sufficiently high laser intensity to effect the dissociation of the inorganic dielectric (eg, cerium oxide) and the damage caused by the underlying damage prior to direct ablation of the inorganic dielectric Layers and fragmentation are minimized. In addition, parameters can be selected to provide meaningful industrial application process throughput with precise control of the ablation width (eg, slit width) and depth. In one embodiment, an ultrashort pulse Laguerre's laser beam laser scribing process is suitable to provide these advantages.
應瞭解,在使用雷射劃線圖案化遮罩以及劃線完全穿過晶圓或基板以便切單晶粒的情況中,在上文所描述之雷射劃線後,可停止切割或切單製程。因此,在此情況中將不需要進一步切單處理。然而,在並未針對總體切單實施雷射劃線的情況中,可考慮以下實施例。 It should be understood that in the case of patterning a mask using a laser scribing line and scribing through the wafer or substrate completely to cut a single crystal grain, the cutting or singulation may be stopped after the laser scribing described above. Process. Therefore, no further singulation processing will be required in this case. However, in the case where the laser scribing is not performed for the overall singulation, the following embodiments can be considered.
現參看流程圖100之可選操作106,執行中間的遮罩開口後清潔操作。在一實施例中,遮罩開口後清潔操作係基於電漿之清潔製程。在第一實例中,如下文所述,基於電漿之清潔製程對基板204的由間隙210所曝露之區域具有反應性。在基於反應性電漿之清潔製程情況中,清潔製程自身可在基板204中形成或延伸溝槽212,因為基於反應性電漿之清潔操作至少在某種程度上對於基板204係蝕刻劑。在第 二不同實例中,亦如下文所述,基於電漿之清潔製程對基板204的由間隙210所曝露之區域無反應性。 Referring now to optional operation 106 of flowchart 100, an intermediate mask opening post-cleaning operation is performed. In one embodiment, the cleaning operation of the mask opening is based on a plasma cleaning process. In the first example, the plasma-based cleaning process is reactive to the area of the substrate 204 exposed by the gap 210, as described below. In the case of a reactive plasma based cleaning process, the cleaning process itself may form or extend the trenches 212 in the substrate 204 because the reactive plasma based cleaning operation at least to some extent is an etchant for the substrate 204. In the first In two different examples, as described below, the plasma based cleaning process is non-reactive with respect to the area of substrate 204 that is exposed by gap 210.
根據第一實施例,基於電漿之清潔製程對基板204之已曝露區域具有反應性,因為在清潔製程期間部分地蝕刻了已曝露區域。在一個此類實施例中,Ar或另一非反應性氣體(或混合物)與SF6組合用於高偏壓電漿處理以便清潔已劃割開口。使用混合氣體Ar+SF6在高偏壓功率下執行電漿處理,以便轟擊遮罩開口區域來實現遮罩開口區域之清潔。在反應性穿透製程中,來自Ar及SF6的物理轟擊與因SF6及F離子的化學蝕刻兩者皆有助於清潔遮罩開口區域。該方法可適合於光阻或電漿沉積聚四氟乙烯遮罩202,其中穿透處理導致相當均勻的遮罩厚度減小及溫和的Si蝕刻。然而,此類穿透蝕刻製程可並非最適合於水溶性遮罩材料。 According to a first embodiment, the plasma based cleaning process is reactive to the exposed areas of the substrate 204 because the exposed areas are partially etched during the cleaning process. In one such embodiment, Ar or another non-reactive gas (or mixture) is used in combination with SF 6 for high bias plasma processing to clean the cut openings. Using a mixed gas of Ar + SF 6 plasma processing performed under a high bias power, in order to mask the opening area is achieved bombardment cleaning opening area mask. In the reaction of the penetration process, the physical bombardment from Ar and SF 6 and SF 6 due to etch both the chemical and the F ions are masked help clean the opening region. The method can be adapted to photoresist or plasma deposited polytetrafluoroethylene mask 202, wherein the penetration treatment results in a fairly uniform mask thickness reduction and a mild Si etch. However, such through etching processes may not be most suitable for water soluble mask materials.
根據第二實施例,基於電漿之清潔製程對基板204之已曝露區域無反應性,因為在清潔製程期間並未蝕刻或僅可忽略地蝕刻已曝露區域。在一個此類實施例中,僅使用非反應性氣體電漿清潔。舉例而言,使用Ar或另一非反應性氣體(或混合物)執行高偏壓電漿處理,兩者皆用於遮罩凝結(mask condensation)及清潔已劃割開口。該方法可適合於水溶性遮罩或更薄的電漿沉積聚四氟乙烯202。在另一此類實施例中,使用單獨遮罩凝結及已 劃割溝槽清潔操作,例如,先執行Ar或非反應性氣體(或混合物)高偏壓電漿處理以便遮罩凝結,並隨後執行雷射已劃割溝槽之Ar+SF6電漿清潔。此實施例可適合於以下情況:由於遮罩材料過厚,Ar清潔不足以用於溝槽清潔。提高清潔效率用於更薄遮罩,但遮罩蝕刻速率更低得多,在後續深層矽蝕刻製程中幾乎無消耗。在又一此類實施例中,執行三個操作清潔:(a)Ar或非反應性氣體(或混合物)高偏壓電漿處理以便遮罩凝結,(b)雷射已劃割溝槽之Ar+SF6高偏壓電漿清潔,及(c)Ar或非反應性氣體(或混合物)高偏壓電漿處理以便遮罩凝結。根據本發明之另一實施例,電漿清潔操作涉及先使用反應性電漿清潔處理,諸如上文在操作106之第一態樣中所描述的清潔處理。反應性電漿清潔處理隨後繼之以非反應性電漿清潔處理,諸如與操作106之第二態樣關聯所描述的清潔處理。 According to a second embodiment, the plasma based cleaning process is non-reactive with respect to the exposed areas of the substrate 204 because the exposed areas are not etched or negligibly etched during the cleaning process. In one such embodiment, only non-reactive gas plasma cleaning is used. For example, high bias plasma processing is performed using Ar or another non-reactive gas (or mixture), both for mask condensation and cleaning of the cut openings. The method can be adapted to a water soluble mask or a thinner plasma deposited polytetrafluoroethylene 202. In another such embodiment, separate mask coagulation and diced trench cleaning operations are used, for example, Ar or non-reactive gas (or mixture) high bias plasma treatment is performed first to mask condensation, and then Perform Ar+SF 6 plasma cleaning of the laser that has been cut into the groove. This embodiment may be suitable for the case where Ar cleaning is insufficient for trench cleaning because the mask material is too thick. Improved cleaning efficiency for thinner masks, but the mask etch rate is much lower and there is almost no consumption in subsequent deep etch processes. In yet another such embodiment, three operational cleanings are performed: (a) Ar or a non-reactive gas (or mixture) high bias plasma treatment to mask condensation, and (b) the laser has been scribed. Ar+SF 6 high bias plasma cleaning, and (c) Ar or non-reactive gas (or mixture) high bias plasma treatment to mask condensation. In accordance with another embodiment of the present invention, the plasma cleaning operation involves first using a reactive plasma cleaning process, such as the cleaning process described above in the first aspect of operation 106. The reactive plasma cleaning process is then followed by a non-reactive plasma cleaning process, such as the cleaning process described in association with the second aspect of operation 106.
參看流程圖100之操作108,及對應的第2C圖,經由經圖案化遮罩208中的間隙210來蝕刻半導體晶圓204,以切單積體電路206。根據本發明之一實施例,蝕刻半導體晶圓204包括:藉由蝕刻利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程最初形成之溝槽212,最終蝕刻完全貫穿半導體晶圓204,如第2C圖中所描繪。 Referring to operation 108 of flowchart 100, and corresponding FIG. 2C, semiconductor wafer 204 is etched via gap 210 in patterned mask 208 to singulate integrated circuit 206. In accordance with an embodiment of the present invention, etching the semiconductor wafer 204 includes: etching the trench 212 initially formed by an ultrashort pulse Raggahl's laser beam laser scribing process, and finally etching completely through the semiconductor wafer 204, As depicted in Figure 2C.
根據本發明之一實施例,自雷射劃線所得之遮罩開口粗糙度可因電漿蝕刻溝槽之後續形成而影響晶粒側壁品質。微影開口遮罩常常具有光滑輪廓,從而導致電漿蝕刻溝槽光滑的對應側壁。相比之下,若選擇不適當的雷射製程參數,則習知雷射開口遮罩可沿劃線方向具有非常粗糙的輪廓(諸如點重疊,導致電漿蝕刻溝槽於水平方向中之側壁粗糙)。儘管可藉由額外電漿製程使表面粗糙度光滑,但在補救此類問題上存在成本與產量打擊。因此,本文所描述之實施例在自切單製程之雷射劃線部分提供更光滑的劃線製程方面可為有利的。 According to an embodiment of the present invention, the roughness of the mask opening obtained from the laser scribing may affect the quality of the sidewall of the die due to subsequent formation of the plasma etched trench. The lithographic opening masks often have a smooth profile, resulting in a corresponding sidewall of the plasma etched trench that is smooth. In contrast, if an inappropriate laser process parameter is selected, the conventional laser opening mask can have a very rough profile along the scribe line direction (such as dot overlap, resulting in plasma etching the trench in the horizontal direction of the sidewall Rough). Although surface roughness can be smoothed by an additional plasma process, there are cost and yield blows in remedying such problems. Thus, the embodiments described herein may be advantageous in providing a smoother scribing process for the laser scribing portion of the self-cutting process.
在一實施例中,蝕刻半導體晶圓204包括使用電漿蝕刻製程。在一個實施例中,使用透矽通孔型蝕刻製程。舉例而言,在一特定實施例中,對半導體晶圓204之材料的蝕刻速率大於25微米/分鐘。可在晶粒切單製程之電漿蝕刻部分中使用超高密度電漿源。適合於執行此種電漿蝕刻製程之製程腔室之實例為Applied Centura® SilviaTM蝕刻系統,該系統可購自美國加利福尼亞州森尼維耳市的應用材料公司。Applied Centura® SilviaTM蝕刻系統結合電容式及電感式射頻耦合,從而提供可能比僅使用電容式耦合,甚至比利用由磁性增強所提供之改良更為獨立的離子密度及離子能控制。此組合賦能離子密度與離子能之有效解耦,以便實現相對較高密度 的電漿,且該電漿即使在極低壓力下亦不具有潛在損傷性的高直流偏壓位準。此特徵導致製程窗口格外寬。然而,可使用任何能夠蝕刻矽之電漿蝕刻腔室。在一示例性實施例中,使用深層矽蝕刻以蝕刻單晶矽基板或晶圓204,所用蝕刻速率比習知矽蝕刻速率大約40%,同時保持基本上精確的輪廓控制及幾乎無扇形之側壁。在一特定實施例中,使用透矽通孔型蝕刻製程。蝕刻製程基於由反應性氣體所產生之電漿,該反應氣體一般為基於氟的氣體,例如SF6、C4F8、CHF3、XeF2,或任何其他能夠以相對較快之蝕刻速率蝕刻矽的反應物氣體。在一實施例中,在切單製程後移除遮罩層208,如第2C圖中所描繪。在另一實施例中,與第2C圖關聯所描述之電漿蝕刻操作採用習知Bosch型沉積/蝕刻/沉積製程以蝕刻穿過基板204。大體而言,Bosch型製程由三個子操作組成:沉積、定向轟擊蝕刻及等向性化學蝕刻,該製程被執行許多迭代(循環)直至蝕刻穿過矽為止。 In an embodiment, etching the semiconductor wafer 204 includes using a plasma etch process. In one embodiment, a through-via via etch process is used. For example, in a particular embodiment, the etch rate of the material of semiconductor wafer 204 is greater than 25 microns/minute. Ultra-high density plasma sources can be used in the plasma etched portion of the die singulation process. Examples of suitable execution chamber of the plasma etching process such as the process of the system of Applied Centura ® Silvia TM etching system available from Sunnyvale, California, United States Applied Materials. The Applied Centura ® Silvia TM etch system combines capacitive and inductive RF coupling to provide ion density and ion energy control that is more independent than using only capacitive coupling, even with the improvements provided by magnetic enhancement. This combination energizes the effective decoupling of ion density from ion energy to achieve a relatively high density plasma that does not have potentially damaging high DC bias levels even at very low pressures. This feature causes the process window to be extra wide. However, any plasma etch chamber capable of etching ruthenium can be used. In an exemplary embodiment, a deep germanium etch is used to etch a single crystal germanium substrate or wafer 204 using an etch rate that is about 40% faster than conventional etch rates while maintaining substantially accurate contour control and virtually fan-free sidewalls. . In a particular embodiment, a through-via via etch process is used. The etching process is based on a plasma generated by a reactive gas, typically a fluorine-based gas, such as SF 6 , C 4 F 8 , CHF 3 , XeF 2 , or any other that can be etched at a relatively faster etch rate. The reactant reactant gas. In one embodiment, the mask layer 208 is removed after the singulation process, as depicted in Figure 2C. In another embodiment, the plasma etch operation described in association with FIG. 2C is etched through substrate 204 using a conventional Bosch type deposition/etch/deposition process. In general, Bosch-type processes consist of three sub-operations: deposition, directed bombardment etching, and isotropic chemical etching, which are performed many iterations (cycles) until etching passes through the crucible.
因此,再次參看流程圖100及第2A圖至第2C圖,可藉由使用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程進行初始剝蝕以剝蝕穿過遮罩層、穿過晶圓劃道(包括金屬化材料)及部分進入矽基板中來執行晶圓切割。可隨後藉由後續透矽深層電漿蝕刻完成晶粒切單。根據本發明之一實施例,下文將與第7A 圖至第7D圖關聯描述用於切割之材料堆疊之特定實例。 Therefore, referring again to flowchart 100 and FIGS. 2A-2C, initial ablation can be performed by using an ultrashort pulse Laguerre laser beam laser scribing process to ablate through the mask layer and through the wafer. Wafer cutting is performed by scribe (including metallized material) and partially into the ruthenium substrate. The die singulation can then be completed by subsequent deep plasma etching. According to an embodiment of the present invention, the following will be with the 7A Figures to 7D relate to a specific example of a stack of materials for cutting.
參看第7A圖,用於混合式雷射剝蝕及電漿蝕刻切割的材料堆疊包括遮罩層702、裝置層704及基板706。在黏附於襯帶710的晶粒黏著薄膜708上安置遮罩層、裝置層及基板。在一實施例中,遮罩層702為水溶性層,諸如上文與遮罩202關聯所描述之水溶性層。裝置層704包括安置於一或更多個金屬層(諸如銅層)及一或更多個低介電常數介電層(諸如摻雜碳的氧化物層)上的無機介電層(諸如二氧化矽)。裝置層704亦包括積體電路之間排列的劃道,該等劃道包括與積體電路相同或相似的層。基板706係塊狀單晶矽基板。 Referring to FIG. 7A, the material stack for hybrid laser ablation and plasma etch cutting includes a mask layer 702, a device layer 704, and a substrate 706. A mask layer, a device layer, and a substrate are disposed on the die attach film 708 adhered to the tape 710. In an embodiment, the mask layer 702 is a water soluble layer, such as the water soluble layer described above in association with the mask 202. Device layer 704 includes an inorganic dielectric layer (such as two) disposed on one or more metal layers (such as a copper layer) and one or more low-k dielectric layers (such as a carbon-doped oxide layer) Osmium oxide). The device layer 704 also includes scribes arranged between the integrated circuits, the scribes including the same or similar layers as the integrated circuits. The substrate 706 is a bulk single crystal germanium substrate.
在一實施例中,在將塊狀單晶矽基板706黏附至晶粒黏著薄膜708前,自背側使該矽基板薄化。可藉由背側研磨製程執行此薄化操作。在一個實施例中,塊狀單晶矽基板706經薄化至大約處於50-100微米範圍內之厚度。應注意,在一實施例中,在雷射剝蝕及電漿蝕刻切割製程之前執行此薄化操作很重要。在一實施例中,光阻層702具有約5微米之厚度且裝置層704具有大約處於2-3微米範圍內之厚度。在一實施例中,晶粒黏著薄膜708(或能夠將經薄化或薄的晶圓或基板黏接至襯帶710之任何適宜替代物)具有約20微米之厚度。 In one embodiment, the tantalum substrate is thinned from the back side before the bulk single crystal germanium substrate 706 is adhered to the die attach film 708. This thinning operation can be performed by a back side grinding process. In one embodiment, the bulk single crystal germanium substrate 706 is thinned to a thickness in the range of approximately 50-100 microns. It should be noted that in one embodiment, it is important to perform this thinning operation prior to the laser ablation and plasma etch cutting processes. In one embodiment, the photoresist layer 702 has a thickness of about 5 microns and the device layer 704 has a thickness in the range of about 2-3 microns. In one embodiment, the die attach film 708 (or any suitable alternative capable of bonding a thinned or thin wafer or substrate to the backing tape 710) has a thickness of about 20 microns.
參看第7B圖,利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程712圖案化遮罩702、裝置層704及基板706的一部分,以在基板706中形成溝槽714。參看第7C圖,使用透矽深層電漿蝕刻製程716使溝槽714向下延伸至晶粒黏著薄膜708,從而曝露晶粒黏著薄膜708之頂部部分並切單矽基板706。在透矽深層電漿蝕刻製程716期間,由遮罩層702保護裝置層704。 Referring to FIG. 7B, a portion of mask 702, device layer 704, and substrate 706 is patterned with ultrashort pulsed LaGalger laser beam laser scribing process 712 to form trenches 714 in substrate 706. Referring to FIG. 7C, trench 714 is extended down to die attach film 708 using a deep plasma etch process 716 to expose the top portion of die attach film 708 and singulate substrate 706. Device layer 704 is protected by mask layer 702 during the deep plasma etch process 716.
參看第7D圖,切單製程可進一步包括圖案化晶粒黏著薄膜708,從而曝露襯帶710之頂部部分並切單晶粒黏著薄膜708。在一實施例中,藉由雷射製程或藉由蝕刻製程來切單晶粒黏著薄膜。另外的實施例可包括隨後自襯帶710移除基板706之已切單部分(例如,作為個別積體電路)。在一個實施例中,已切單晶粒黏著薄膜708保留在基板706之已切單部分的背側上。其他實施例可包括自裝置層704移除遮罩層702。在一替代實施例中,在基板706厚度小於約50微米的情況中,使用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程712完全切單基板706,而無需使用額外電漿製程。 Referring to FIG. 7D, the dicing process can further include patterning the die attach film 708 to expose the top portion of the liner 710 and dicing the single die attach film 708. In one embodiment, the single die attach film is diced by a laser process or by an etch process. Further embodiments may include subsequently removing the singulated portion of the substrate 706 from the backing strip 710 (eg, as an individual integrated circuit). In one embodiment, the diced die attach film 708 remains on the back side of the singulated portion of the substrate 706. Other embodiments may include removing the mask layer 702 from the device layer 704. In an alternate embodiment, where the thickness of the substrate 706 is less than about 50 microns, the ultra-short pulse Laguergain laser beam laser scribing process 712 is used to completely sing the single substrate 706 without the need for an additional plasma process.
單個製程工具可經配置以執行利用超短脈衝拉蓋爾高斯雷射光束剝蝕及電漿蝕刻切單製程之混合式雷射系列中的許多或全部操作。舉例而言, 第8圖圖示根據本發明之實施例的用於雷射及電漿切割晶圓或基板的工具佈置之方塊圖。 A single process tool can be configured to perform many or all of the hybrid laser series using ultrashort pulse Laguerre laser beam ablation and plasma etch singulation processes. For example, Figure 8 illustrates a block diagram of a tool arrangement for laser and plasma dicing wafers or substrates in accordance with an embodiment of the present invention.
參看第8圖,製程工具800包括工廠介面802(factory interface;FI),該介面耦接有複數個裝載鎖804。群集工具806與工廠介面802耦接。群集工具806包括一或更多個電漿蝕刻腔室,諸如電漿蝕刻腔室808。雷射劃線設備810亦耦接至工廠介面802。在一個實施例中,該製程工具800之總佔地面積可為約3500毫米(3.5公尺)乘以約3800毫米(3.8公尺),如第8圖所描繪。 Referring to FIG. 8, the process tool 800 includes a factory interface (FI) coupled to a plurality of load locks 804. Cluster tool 806 is coupled to factory interface 802. Cluster tool 806 includes one or more plasma etch chambers, such as plasma etch chamber 808. Laser scribing device 810 is also coupled to factory interface 802. In one embodiment, the total footprint of the process tool 800 can be about 3500 millimeters (3.5 meters) by about 3800 millimeters (3.8 meters), as depicted in FIG.
在一實施例中,雷射劃線設備810容納雷射總成,該雷射總成經配置以提供超短脈衝拉蓋爾高斯雷射光束。在一個此類實施例中,雷射光束具有軸向對稱偏振。在一特定實施例中,雷射總成經配置以提供具有徑向偏振元件的雷射光束。在另一特定實施例中,雷射總成經配置以提供具有方位角偏振分量的雷射光束。在另一特定實施例中,雷射總成經配置以提供具有徑向偏振分量及方位角偏振分量兩者的雷射光束。在另一特定實施例中,雷射總成經配置以提供具有TEM01*模式的雷射光束。在另一特定實施例中,雷射總成經配置以提供具有環形圈形狀的雷射光束。在一實施例中,雷射劃線設備經配置以基於分段半波片提供線性至徑向轉換,或線性至方位角轉換,或線性至徑向與方位角兩者的轉換。 In an embodiment, the laser scribing device 810 houses a laser assembly that is configured to provide an ultrashort pulse Laguerre laser beam. In one such embodiment, the laser beam has an axially symmetric polarization. In a particular embodiment, the laser assembly is configured to provide a laser beam having a radial polarization element. In another particular embodiment, the laser assembly is configured to provide a laser beam having an azimuthal polarization component. In another particular embodiment, the laser assembly is configured to provide a laser beam having both a radial polarization component and an azimuthal polarization component. In another particular embodiment, the laser assembly is configured to provide a laser beam having a TEM01* mode. In another particular embodiment, the laser assembly is configured to provide a laser beam having an annular ring shape. In an embodiment, the laser scribing apparatus is configured to provide linear to radial conversion, or linear to azimuthal conversion, or linear to both radial and azimuth conversion based on the segmented half wave plate.
在一實施例中,雷射適合於執行混合式雷射及蝕刻切單製程中的雷射剝蝕部分,諸如上文所描述之雷射剝蝕製程。在一個實施例中,雷射劃線設備810中亦包括可移動平臺,該可移動平臺經配置用於相對於雷射移動晶圓或基板(或晶圓或基板之載體)。在一特定實施例中,雷射亦為可移動的。在一個實施例中,雷射劃線設備810之總佔地面積可為約2240毫米乘以約1270毫米,如第8圖中所描繪。 In one embodiment, the laser is adapted to perform a laser ablation portion in a hybrid laser and etch singulation process, such as the laser ablation process described above. In one embodiment, the laser scribing apparatus 810 also includes a movable platform configured to move the wafer or substrate (or the carrier of the wafer or substrate) relative to the laser. In a particular embodiment, the laser is also movable. In one embodiment, the total footprint of the laser scribing device 810 can be about 2240 millimeters by about 1270 millimeters, as depicted in FIG.
在一實施例中,一或更多個電漿蝕刻腔室808經配置用於經由經圖案化遮罩中的間隙蝕刻晶圓或基板,以切單複數個積體電路。在一個此類實施例中,一或更多個電漿蝕刻腔室808經配置以執行深層矽蝕刻製程。在一特定實施例中,一或更多個電漿蝕刻腔室808係Applied Centura® SilviaTM蝕刻系統,該系統可購自美國加利福尼亞州森尼維耳市的應用材料公司。蝕刻腔室可經特定設計以用於深層矽蝕刻,該蝕刻用於產生切單積體電路,該等積體電路被容納在單晶矽基板或晶圓之上或之中。在一實施例中,在電漿蝕刻腔室808中包括高密度電漿源以促進高矽蝕刻速率。在一實施例中,在製程工具800之群集工具806部分中包括一個以上蝕刻腔室,以賦能切單或切割製程的高製造產量。 In an embodiment, one or more plasma etch chambers 808 are configured to etch a wafer or substrate via a gap in the patterned mask to singulate a plurality of integrated circuits. In one such embodiment, one or more plasma etch chambers 808 are configured to perform a deep ruthenium etch process. In a particular embodiment, the one or more plasma etch chambers 808 based Applied Centura ® Silvia TM etching system available from Applied Materials, Inc., California Sunnyvale. The etch chamber can be specifically designed for deep ruthenium etching, which is used to create tangential integrated circuits that are housed on or in a single crystal germanium substrate or wafer. In one embodiment, a high density plasma source is included in the plasma etch chamber 808 to promote a high erbium etch rate. In one embodiment, more than one etch chamber is included in the cluster tool 806 portion of the process tool 800 to enable high manufacturing throughput for the singulation or cutting process.
工廠介面802可為適宜大氣埠,該埠在具有雷射劃線設備810之外部製造設施與群集工具 806之間建立介面。工廠介面802可包括具有手臂或刀刃之機器人以用於將晶圓(或晶圓之載體)自儲存單元(諸如前開口式晶圓盒)移送至群集工具806或雷射劃線設備810或兩者內。 The factory interface 802 can be a suitable atmosphere that is externally fabricated and clustered with the laser scribing device 810 An interface is established between 806. The factory interface 802 can include a robot with an arm or a blade for transferring a wafer (or carrier of a wafer) from a storage unit (such as a front open wafer cassette) to a cluster tool 806 or a laser scribing device 810 or two Inside.
群集工具806可包括適合於執行切單方法中的各功能之其他腔室。舉例而言,在一個實施例中,包括沉積室812,以代替額外蝕刻腔室。沉積室812可經配置用於在晶圓或基板之雷射劃線前在晶圓或基板之裝置層上或上方進行遮罩沉積。在一個此類實施例中,沉積室812適合於沉積光阻層。在另一實施例中,包括潤濕/乾燥站814,以代替額外蝕刻腔室。潤濕/乾燥站可適合於在基板或晶圓之雷射劃線及電漿蝕刻切單製程之後清潔殘餘物及碎片,或移除遮罩。在一實施例中,亦包括計量站作為製程工具800中的元件。 Cluster tool 806 can include other chambers suitable for performing various functions in the singulation method. For example, in one embodiment, a deposition chamber 812 is included in place of the additional etch chamber. The deposition chamber 812 can be configured to perform mask deposition on or over the wafer or substrate device layer prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber 812 is adapted to deposit a photoresist layer. In another embodiment, a wetting/drying station 814 is included in place of the additional etching chamber. The wetting/drying station can be adapted to clean residues and debris, or remove the mask after laser scribe and plasma etch dicing processes on the substrate or wafer. In an embodiment, a metering station is also included as an element in the process tool 800.
本發明之實施例可作為電腦程式產品或軟體而提供,該電腦程式產品或軟體可包括機器可讀取媒體,在該媒體上儲存有指令,該電腦程式產品或軟體可用於程式化電腦系統(或其他電子裝置)以執行根據本發明之實施例之製程。在一個實施例中,電腦系統與第8圖關聯所描述之製程工具800耦接。機器可讀取媒體包括任何以機器(例如,電腦)可讀取的形式儲存或傳輸資訊之機構。舉例而言,機器可讀取(例如,電腦可讀取)媒體包括機器(例如,電腦) 可讀取儲存媒體(例如,唯讀記憶體(read only memory;「ROM」)、隨機存取記憶體(random access memory;「RAM」)、磁碟儲存媒體、光儲存媒體、快閃記憶體裝置等)、機器(例如,電腦)可讀取傳輸媒體(電訊號、光訊號、聲訊號或其他形式之傳播訊號(例如,紅外線訊號、數位訊號等))等。 Embodiments of the invention may be provided as a computer program product or software, which may include a machine readable medium having instructions stored thereon, the computer program product or software being usable for use in a programmed computer system ( Or other electronic device) to perform a process in accordance with an embodiment of the present invention. In one embodiment, the computer system is coupled to the process tool 800 described in association with FIG. Machine readable media includes any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). For example, a machine readable (eg, computer readable) medium includes a machine (eg, a computer) Readable storage medium (for example, read only memory ("ROM"), random access memory (RAM), disk storage media, optical storage media, flash memory A device (eg, a computer) can read a transmission medium (a telecommunication number, an optical signal, an audio signal, or other forms of propagation signals (eg, an infrared signal, a digital signal, etc.)).
第9圖圖示電腦系統900之示例性形式之機器的圖解表示,可在該電腦系統中執行指令集以用於引發該機器執行本文所描述之方法中的任何一或更多者。在替代實施例中,可在區域網路(Local Area Network;LAN)、內部網路、外部網路或網際網路中將機器連接(例如,網路連接)至其他機器。該機器可作為主從式網路環境中的伺服器或客戶端機器操作,或作為同級間(或分散式)網路環境中的同級機器操作。該機器可為個人電腦(personal computer;PC)、平板PC、機上盒(set-top box;STB)、個人數位助理(Personal Digital Assistant;PDA)、蜂巢式電話、網路設備、伺服器、網路路由器、交換機或橋接器,或任何能夠執行指令集(按順序或以其他方式)之機器,該指令集指定將由彼機器所採取的動作。進一步地,儘管僅圖示單個機器,但術語「機器」應亦被視為包括機器(例如,電腦)之任何集合,該等機器個別或共同執行一 個指令集(或多個指令集)以執行本文所描述之方法中的任何一或更多者。 9 illustrates a graphical representation of an exemplary form of computer system 900 in which a set of instructions can be executed for causing the machine to perform any one or more of the methods described herein. In an alternate embodiment, the machine can be connected (e.g., networked) to other machines in a local area network (LAN), an internal network, an external network, or the Internet. The machine can operate as a server or client machine in a master-slave network environment or as a peer machine in a peer-to-peer (or decentralized) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, A network router, switch, or bridge, or any machine capable of executing a set of instructions (in order or otherwise) that specifies the actions to be taken by the machine. Further, although only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (eg, computers) that individually or collectively perform one An instruction set (or sets of instructions) to perform any one or more of the methods described herein.
示例性電腦系統900包括處理器902、主記憶體904(例如,唯讀記憶體(ROM)、快閃記憶體、諸如同步DRAM(SDRAM)或Rambus DRAM(RDRAM)之動態隨機存取記憶體(dynamic random access memory;DRAM)等)、靜態記憶體906(例如,快閃記憶體、靜態隨機存取記憶體(static random access memory;SRAM)等)及二級記憶體918(例如,資料儲存裝置),上述各者經由匯流排930與彼此通訊。 The exemplary computer system 900 includes a processor 902, main memory 904 (eg, read only memory (ROM), flash memory, dynamic random access memory such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM) ( Dynamic random access memory; DRAM), static memory 906 (eg, flash memory, static random access memory (SRAM), etc.) and secondary memory 918 (eg, data storage device) Each of the above communicates with each other via the bus 930.
處理器902表示一或更多個通用處理裝置,諸如微處理器、中央處理單元或類似者。更特定言之,處理器902可為複雜指令集計算(complex instruction set computing;CISC)微處理器、精簡指令集計算(reduced instruction set computing;RISC)微處理器、超長指令字(very long instruction word;VLIW)微處理器、實施其他指令集的處理器或實施指令集組合的處理器。處理器902亦可為一或更多個專用處理裝置,諸如特殊應用積體電路(application specific integrated circuit;ASIC)、現場可程式化閘陣列(field programmable gate array; FPGA)、數位訊號處理器(digital signal processor;DSP)、網路處理器或類似者。處理器902經配置以執行處理邏輯926,該處理邏輯用於執行本文所描述之操作。 Processor 902 represents one or more general purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processor 902 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, or a very long instruction word (very long instruction). Word; VLIW) A microprocessor, a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processor 902 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (field programmable gate array; FPGA), digital signal processor (DSP), network processor or the like. Processor 902 is configured to execute processing logic 926 for performing the operations described herein.
電腦系統900可進一步包括網路介面裝置908。電腦系統900亦可包括視訊顯示單元910(例如,液晶顯示器(liquid crystal display;LCD)、發光二極體顯示器(light emitting diode display;LED)或陰極射線管(cathode ray tube;CRT))、文數字輸入裝置912(例如,鍵盤)、游標控制裝置914(例如,滑鼠)及訊號產生裝置916(例如,揚聲器)。 Computer system 900 can further include a network interface device 908. The computer system 900 can also include a video display unit 910 (eg, a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), A digital input device 912 (eg, a keyboard), a cursor control device 914 (eg, a mouse), and a signal generating device 916 (eg, a speaker).
二級記憶體918可包括機器可存取儲存媒體(或更特定言之,電腦可讀取儲存媒體)932,在該媒體上儲存有一或更多個指令集(例如,軟體922),該等指令集具體實現本文所描述之方法或功能中的任何一或更多者。軟體922亦可完全或至少部分位於主記憶體904內及/或在由電腦系統900執行該軟體期間位於處理器902內,主記憶體904及處理器902亦組成機器可讀取儲存媒體。可經由網路介面裝置908在網路920上進一步傳輸或接收軟體922。 The secondary memory 918 can include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 932 on which one or more sets of instructions (eg, software 922) are stored, such The set of instructions specifically implements any one or more of the methods or functions described herein. The software 922 may also be located entirely or at least partially within the main memory 904 and/or within the processor 902 during execution of the software by the computer system 900. The main memory 904 and the processor 902 also form a machine readable storage medium. Software 922 can be further transmitted or received over network 920 via network interface device 908.
儘管機器可存取儲存媒體932在一示例性實施例中展示為單個媒體,但術語「機器可讀取儲存媒體」應被視為包括儲存一或更多個指令集之單個 媒體或多個媒體(例如,集中式或分散式資料庫,及/或關聯的快取記憶體及伺服器)。術語「機器可讀取儲存媒體」亦應被視為包括任何能夠儲存或編碼一指令集之媒體,該指令集由該機器執行,並引發該機器執行本發明之方法中的任何一或更多者。因此,術語「機器可讀取儲存媒體」應被視為包括但不限定於固態記憶體及光學媒體與磁性媒體。 Although the machine-accessible storage medium 932 is shown as a single medium in an exemplary embodiment, the term "machine-readable storage medium" shall be taken to include a single storage of one or more instruction sets. Media or multiple media (eg, centralized or decentralized repositories, and/or associated caches and servers). The term "machine readable storage medium" shall also be taken to include any medium capable of storing or encoding a set of instructions executed by the machine and causing the machine to perform any one or more of the methods of the present invention. By. Therefore, the term "machine readable storage medium" shall be taken to include, but is not limited to, solid state memory and optical media and magnetic media.
根據本發明之一實施例,機器可存取儲存媒體上儲存有指令,該等指令引發資料處理系統執行切割具有複數個積體電路的半導體晶圓之方法。該方法包括在半導體晶圓上方形成遮罩,該遮罩包括覆蓋及保護積體電路的層。隨後利用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程圖案化該遮罩,以提供具有間隙的經圖案化遮罩,從而曝露半導體晶圓的介於積體電路之間的區域。超短脈衝拉蓋爾高斯雷射光束雷射劃線製程涉及利用具有軸向對稱偏振的雷射光束進行劃線。隨後經由經圖案化遮罩中的間隙電漿蝕刻半導體晶圓,以切單積體電路。 In accordance with an embodiment of the present invention, a machine-accessible storage medium stores instructions that cause a data processing system to perform a method of cutting a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask over a semiconductor wafer, the mask including a layer covering and protecting the integrated circuit. The mask is then patterned using an ultrashort pulse Laguerre's laser beam laser scribing process to provide a patterned mask with a gap to expose the area of the semiconductor wafer between the integrated circuits. The ultrashort pulse Laguerre Gaussian laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuit.
因此,已揭示使用超短脈衝拉蓋爾高斯雷射光束雷射劃線製程及電漿蝕刻的混合式晶圓切割方法。 Thus, a hybrid wafer dicing method using an ultrashort pulse Laguerre laser beam laser scribing process and plasma etching has been disclosed.
100‧‧‧流程圖 100‧‧‧ Flowchart
102‧‧‧操作 102‧‧‧ operation
104‧‧‧操作 104‧‧‧Operation
106‧‧‧操作 106‧‧‧ operation
108‧‧‧操作 108‧‧‧ operation
Claims (20)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461994385P | 2014-05-16 | 2014-05-16 | |
US61/994,385 | 2014-05-16 | ||
US201414297274A | 2014-06-05 | 2014-06-05 | |
US14/297,274 | 2014-06-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201603192A true TW201603192A (en) | 2016-01-16 |
TWI666729B TWI666729B (en) | 2019-07-21 |
Family
ID=54480452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW104115628A TWI666729B (en) | 2014-05-16 | 2015-05-15 | Hybrid wafer dicing approach using an ultra-short pulsed laguerre gauss beam laser scribing process and plasma etch process |
Country Status (2)
Country | Link |
---|---|
TW (1) | TWI666729B (en) |
WO (1) | WO2015175268A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI612621B (en) * | 2017-01-25 | 2018-01-21 | 矽品精密工業股份有限公司 | Electronic element and the manufacture thereof |
TWI618166B (en) * | 2016-12-01 | 2018-03-11 | 塔工程有限公司 | Scribing apparatus |
TWI705486B (en) * | 2016-01-19 | 2020-09-21 | 日商迪思科股份有限公司 | Wafer processing method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10510550B2 (en) | 2017-09-26 | 2019-12-17 | The Board Of Trustees Of The University Of Illinois | Polarization-dependent laser-assisted plasma etching |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8624157B2 (en) * | 2006-05-25 | 2014-01-07 | Electro Scientific Industries, Inc. | Ultrashort laser pulse wafer scribing |
KR100976035B1 (en) * | 2008-07-15 | 2010-08-17 | 나노전광 주식회사 | Laser Cutting Method |
US8642448B2 (en) * | 2010-06-22 | 2014-02-04 | Applied Materials, Inc. | Wafer dicing using femtosecond-based laser and plasma etch |
TWI513670B (en) * | 2010-08-31 | 2015-12-21 | Corning Inc | Methods of separating strengthened glass substrates |
JP5596750B2 (en) * | 2012-07-06 | 2014-09-24 | 東芝機械株式会社 | Laser dicing method |
-
2015
- 2015-05-05 WO PCT/US2015/029260 patent/WO2015175268A1/en active Application Filing
- 2015-05-15 TW TW104115628A patent/TWI666729B/en active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI705486B (en) * | 2016-01-19 | 2020-09-21 | 日商迪思科股份有限公司 | Wafer processing method |
TWI618166B (en) * | 2016-12-01 | 2018-03-11 | 塔工程有限公司 | Scribing apparatus |
TWI612621B (en) * | 2017-01-25 | 2018-01-21 | 矽品精密工業股份有限公司 | Electronic element and the manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
WO2015175268A1 (en) | 2015-11-19 |
TWI666729B (en) | 2019-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11217536B2 (en) | Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process | |
TWI557789B (en) | Hybrid laser and plasma etch wafer dicing using substrate carrier | |
KR102122940B1 (en) | Wafer dicing using femtosecond-based laser and plasma etch | |
CN111801788B (en) | Hybrid wafer dicing method using multi-pass laser scribing process and plasma etching process | |
US9349648B2 (en) | Hybrid wafer dicing approach using a rectangular shaped two-dimensional top hat laser beam profile or a linear shaped one-dimensional top hat laser beam profile laser scribing process and plasma etch process | |
KR102377901B1 (en) | A hybrid wafer dicing approach using a rotating beam laser scribing process and a plasma etching process | |
US9355907B1 (en) | Hybrid wafer dicing approach using a line shaped laser beam profile laser scribing process and plasma etch process | |
US9245803B1 (en) | Hybrid wafer dicing approach using a bessel beam shaper laser scribing process and plasma etch process | |
US20150243559A1 (en) | Hybrid wafer dicing approach using temporally-controlled laser scribing process and plasma etch | |
TWI666729B (en) | Hybrid wafer dicing approach using an ultra-short pulsed laguerre gauss beam laser scribing process and plasma etch process | |
TWI826798B (en) | Laser scribing trench opening control in wafer dicing using hybrid laser scribing and plasma etch approach | |
US20210233816A1 (en) | Hybrid wafer dicing approach using a spatially multi-focused laser beam laser scribing process and plasma etch process | |
US9196536B1 (en) | Hybrid wafer dicing approach using a phase modulated laser beam profile laser scribing process and plasma etch process | |
US9281244B1 (en) | Hybrid wafer dicing approach using an adaptive optics-controlled laser scribing process and plasma etch process | |
US10903121B1 (en) | Hybrid wafer dicing approach using a uniform rotating beam laser scribing process and plasma etch process | |
US9177861B1 (en) | Hybrid wafer dicing approach using laser scribing process based on an elliptical laser beam profile or a spatio-temporal controlled laser beam profile | |
US20160197015A1 (en) | Hybrid wafer dicing approach using a polygon scanning-based laser scribing process and plasma etch process | |
US20220246476A1 (en) | Hybrid wafer dicing approach using an actively-focused laser beam laser scribing process and plasma etch process | |
US9330977B1 (en) | Hybrid wafer dicing approach using a galvo scanner and linear stage hybrid motion laser scribing process and plasma etch process |