TW201546780A - Display device and method of switching display mode - Google Patents
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本發明係關於一種顯示裝置及切換顯示模式的方法，特別是關於一種避免閘極驅動模組洩漏大電流之顯示裝置及切換顯示模式的方法。 The present invention relates to a display device and a method for switching display modes, and more particularly to a display device that avoids leakage of a large current by a gate drive module and a method of switching display modes.
目前許多的顯示裝置已具備二維以及三維畫面切換的功能，使得使用者可更便利的使用各種應用裝置。然而，當時序控制模組(Tcon)以及電壓位準移位模組(level shifter)接收到從二維顯示轉換成三維顯示(即2D轉3D)時，因各家廠牌的設計不同，時序控制模組以及電壓位準移位模組可能不是同步收到2D轉3D的指令。舉例來說，於一個例子中，當時序控制模組先收到2D轉3D的指令，並已經改變起始脈衝訊號的脈寬時，若是電壓位準移位模組尚未改變驅動訊號的輸出方式，電壓位準移位模組即會輸出錯誤的驅動訊號，導致閘極驅動模組產生洩漏電流的情況，進一步造成積體電路端電源崩潰的現象。 At present, many display devices have the functions of two-dimensional and three-dimensional picture switching, so that users can more conveniently use various application devices. However, when the timing control module (Tcon) and the voltage level shifter (level shifter) receive the conversion from the two-dimensional display to the three-dimensional display (ie, 2D to 3D), the timing is different due to the design of each brand. The control module and the voltage level shifting module may not be instructions for synchronously receiving 2D to 3D. For example, in an example, when the timing control module first receives the 2D to 3D instruction and has changed the pulse width of the start pulse signal, if the voltage level shift module has not changed the output mode of the driving signal, The voltage level shifting module outputs an incorrect driving signal, which causes the gate driving module to generate a leakage current, which further causes the power supply of the integrated circuit to collapse.
有鑑於此，如何提供一種顯示裝置及切換顯示模式的方法以解決上述問題已成為目前業界極需克服的問題。 In view of this, how to provide a display device and a method for switching display modes to solve the above problems has become a problem that the industry is in urgent need of overcoming.
本發明提出一種顯示裝置以及切換顯示模式的方法，用來解決先前技術中，閘極驅動模組產生洩漏電流而進一步造成積體電路端電源崩潰的問題。 The invention provides a display device and a method for switching display modes, which are used to solve the problem that the gate drive module generates leakage current in the prior art and further causes the power supply of the integrated circuit end to collapse.
本發明提供一種切換顯示模式的方法，適用於顯示裝置，所述方法包含：提供至少一高頻訊號，並依據模式切換訊號，選擇性地以二維模式或三維模式提供起始脈衝訊號；將高頻訊號解碼成多個驅動訊號；依據模式切換訊號，間隔一段預設時間後，選擇性地以二維驅動模式或三維驅動模式提供所述多個驅動訊號；以及依據具有二維驅動模式或三維驅動模式的所述多個驅動訊號，以輸出畫面。 The present invention provides a method for switching a display mode, which is applicable to a display device. The method includes: providing at least one high frequency signal, and selectively providing a start pulse signal in a two-dimensional mode or a three-dimensional mode according to a mode switching signal; The high frequency signal is decoded into a plurality of driving signals; the plurality of driving signals are selectively provided in a two-dimensional driving mode or a three-dimensional driving mode after a predetermined time interval according to the mode switching signal; and according to the two-dimensional driving mode or The plurality of driving signals of the three-dimensional driving mode to output a picture.
本發明更揭露一種利用切換顯示模式方法的顯示裝置。顯示裝置包含面板、時序控制模組、電壓位準移位模組以及閘極驅動模組。時序控制模組用以提供至少一高頻訊號，並受控於模式切換訊號，選擇性地以二維模式或三維模式提供起始脈衝訊號。電壓位準移位模組耦接時序控制模組，用以將高頻訊號解碼成多個驅動訊號，並受控於模式切換訊號，間隔一段預設時間後，選擇性地以二維驅動模式或三維驅動模式輸出所述多個驅動訊號。閘極驅動模組耦接面板與電壓位準移位模組，受控於電壓位準移位模組輸出的所述多個驅動訊號，以驅動面板輸出畫面。 The present invention further discloses a display device using a method of switching display modes. The display device comprises a panel, a timing control module, a voltage level shifting module and a gate driving module. The timing control module is configured to provide at least one high frequency signal and controlled by the mode switching signal to selectively provide the starting pulse signal in a two-dimensional mode or a three-dimensional mode. The voltage level shifting module is coupled to the timing control module for decoding the high frequency signal into a plurality of driving signals and controlled by the mode switching signal, and selectively driving in a two-dimensional driving mode after a preset time interval Or the three-dimensional driving mode outputs the plurality of driving signals. The gate driving module is coupled to the panel and the voltage level shifting module, and is controlled by the plurality of driving signals output by the voltage level shifting module to drive the panel output screen.
承上所述，本發明顯示裝置以及切換顯示模式的方法，藉由間隔一段預設時間，使得時序控制模組在接收三維模式以及起始脈衝訊號之後，提早切換起始脈衝訊號為低電壓準位， 亦即改變起始脈衝訊號的長度，避免閘極驅動模組上的電晶體於輸入驅動訊號時被提早開啟，因而導致閘極驅動模組洩漏大電流的情況，而產生積體電路端電源崩潰的現象。 As described above, the display device of the present invention and the method for switching the display mode enable the timing control module to switch the start pulse signal to a low voltage level after receiving the three-dimensional mode and the start pulse signal by a predetermined period of time. Bit, That is, the length of the starting pulse signal is changed to prevent the transistor on the gate driving module from being turned on earlier when the driving signal is input, thereby causing the gate driving module to leak a large current, and the integrated circuit power supply collapses. The phenomenon.
S02~S08‧‧‧步驟 S02~S08‧‧‧Steps
HC 1~8‧‧‧驅動訊號 HC 1~8‧‧‧ drive signal
HC‧‧‧高頻訊號 HC‧‧‧High frequency signal
LC1~2‧‧‧低頻訊號 LC1~2‧‧‧Low frequency signal
ST‧‧‧起始脈衝訊號 ST‧‧‧start pulse signal
mode_sw‧‧‧模式切換訊號 Mode_sw‧‧‧ mode switching signal
end‧‧‧畫框終止訊號 End‧‧‧picture frame termination signal
T11、T12、T31、T41‧‧‧電晶體 T11, T12, T31, T41‧‧‧ transistors
Q‧‧‧閘極電壓 Q‧‧‧ gate voltage
G‧‧‧汲極電壓 G‧‧‧汲polar voltage
VGH‧‧‧汲極端 VGH‧‧汲 extreme
VSS‧‧‧負電壓端 VSS‧‧‧negative voltage terminal
21‧‧‧時序控制模組 21‧‧‧Sequence Control Module
22‧‧‧電壓位準移位模組 22‧‧‧Voltage level shift module
23‧‧‧閘極驅動模組 23‧‧‧Gate drive module
221‧‧‧解碼單元 221‧‧‧Decoding unit
222‧‧‧畫框偵測單元 222‧‧‧Frame detection unit
223‧‧‧輸出單元 223‧‧‧Output unit
第1圖係為本發明一實施例之切換顯示模式的方法流程圖；第2圖係為本發明一實施例之顯示裝置的功能方塊圖；第3圖係為本發明一實施例之切換顯示模式的訊號時序圖；第4圖係為本發明一實施例之第一級閘極驅動模組；第5圖係為放大第3圖起始脈衝訊號第二週期的訊號時序圖；以及第6圖係為電壓位準移位模組的示意圖。 1 is a flow chart of a method for switching display modes according to an embodiment of the present invention; FIG. 2 is a functional block diagram of a display device according to an embodiment of the present invention; and FIG. 3 is a switch display according to an embodiment of the present invention; The signal timing diagram of the mode; FIG. 4 is a first-stage gate driving module according to an embodiment of the present invention; FIG. 5 is a signal timing diagram for amplifying the second period of the initial pulse signal of FIG. 3; and the sixth The figure is a schematic diagram of a voltage level shifting module.
請一併參閱第1圖與第2圖，第1圖係為本發明一實施例之切換顯示模式的方法流程圖，第2圖係為本發明一實施例之顯示裝置的功能方塊圖。如圖所示，本實施例之顯示裝置具有時序控制模組21、電壓位準移位模組22以及閘極驅動模組23。於步驟S02時，時序控制模組21除了提供高頻訊號HC與低頻訊號LC之外，也依據模式切換訊號mode_sw，選擇性地以二維模式或三維模式提供起始脈衝訊號ST。於實務上，當外部輸入的模式切換訊號mode_sw係指示時序控制模組21從二維模式轉成三維模式時，時序控制模組21會提供較短脈寬的起始脈衝訊號ST。 Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a flowchart of a method for switching display modes according to an embodiment of the present invention, and FIG. 2 is a functional block diagram of a display device according to an embodiment of the present invention. As shown in the figure, the display device of this embodiment has a timing control module 21, a voltage level shifting module 22, and a gate driving module 23. In step S02, the timing control module 21 selectively supplies the start pulse signal ST in a two-dimensional mode or a three-dimensional mode according to the mode switching signal mode_sw in addition to the high-frequency signal HC and the low-frequency signal LC. In practice, when the externally input mode switching signal mode_sw indicates that the timing control module 21 is switched from the two-dimensional mode to the three-dimensional mode, the timing control module 21 provides a short pulse width start pulse signal ST.
於步驟S04中，電壓位準移位模組22接收到來自時序控制模組21的高頻訊號HC後，會先將高頻訊號HC解碼成多個驅動訊號HC1~8，用以驅動閘極驅動模組23。此外，除了高頻訊號HC以外，時序控制模組21亦提供低頻訊號LC驅動閘極驅動模組23。於一個例子中，低頻訊號LC係與高頻訊號HC獨立分開，亦即低頻訊號LC並不需要透過解碼，而是直接輸入至閘極驅動模組23，其中，時序控制模組21可提供至少二個低頻訊號，輸入至驅動閘極驅動模組23。對應於第4圖的電路圖，低頻訊號係為LC1及LC2。 In step S04, after receiving the high frequency signal HC from the timing control module 21, the voltage level shifting module 22 first decodes the high frequency signal HC into a plurality of driving signals HC1~8 for driving the gate. Drive module 23. In addition to the high frequency signal HC, the timing control module 21 also provides a low frequency signal LC driving gate drive module 23. In an example, the low frequency signal LC is separated from the high frequency signal HC independently, that is, the low frequency signal LC does not need to be decoded, but is directly input to the gate driving module 23, wherein the timing control module 21 can provide at least Two low frequency signals are input to the driving gate driving module 23. Corresponding to the circuit diagram of Figure 4, the low frequency signals are LC1 and LC2.
於步驟S06中，依據模式切換訊號mode_sw，間隔一段預設時間後，選擇性地以二維驅動模式或三維驅動模式提供多個驅動訊號。舉例來說，當外部輸入的模式切換訊號mode_sw係指示電壓位準移位模組22以二維驅動模式驅動閘極驅動模組23時，電壓位準移位模組22將以循序方式逐一輸出驅動訊號HC1~8。若模式切換訊號mode_sw係指示電壓位準移位模組22以三維驅動模式驅動閘極驅動模組23時，電壓位準移位模組22將以兩兩組合的方式輸出驅動訊號HC1~8。 In step S06, according to the mode switching signal mode_sw, after a predetermined period of time, a plurality of driving signals are selectively provided in the two-dimensional driving mode or the three-dimensional driving mode. For example, when the externally input mode switching signal mode_sw indicates that the voltage level shifting module 22 drives the gate driving module 23 in the two-dimensional driving mode, the voltage level shifting module 22 outputs one by one in a sequential manner. Drive signal HC1~8. When the mode switching signal mode_sw indicates that the voltage level shifting module 22 drives the gate driving module 23 in the three-dimensional driving mode, the voltage level shifting module 22 outputs the driving signals HC1 to 8 in a combination of two and two.
為了解決習知技術中，當顯示裝置由二維畫面轉換為三維畫面時，模式切換訊號mode_sw可能無法同時傳輸給時序控制模組21以及電壓位準移位模組22的問題，請參閱第3圖，其係為本發明一實施例之切換顯示模式的訊號時序圖。本發明藉由間隔一預設時間的方式，能確保於這段預設時間後，時序控制 模組21會以三維模式訊號提供起始脈衝訊號ST，並且電壓位準移位模組22也會以三維驅動模式輸出驅動訊號HC1~8。換句話說，暫停一段預設時間是為了避免顯示裝置由二維畫面轉換為三維畫面的瞬間，縱使時序控制模組21以及電壓位準移位模組22未能同步收到模式切換訊號mode_sw，也能夠在預設時間後穩定地提供正確的起始脈衝訊號ST與驅動訊號HC1~8。所謂的間隔一段預設時間可以根據模式切換訊號mode_sw操作於三維模式(高電壓準位)時，開始起算所述預設時間，使得起始脈衝訊號ST保持為低電壓準位而無法開啟閘極驅動模組23，避免閘極驅動模組23洩漏大電流的情況。換句話說，本實施例的顯示裝置在二維畫面轉換為三維畫面時，不會立刻顯示所述三維畫面，而是等待一段預設時間，藉此可讓時序控制模組21穩定地輸出正確脈寬的起始脈衝訊號ST。 In order to solve the problem in the prior art, when the display device is converted from a two-dimensional picture to a three-dimensional picture, the mode switching signal mode_sw may not be simultaneously transmitted to the timing control module 21 and the voltage level shifting module 22, please refer to the third. The figure is a signal timing diagram of a switching display mode according to an embodiment of the present invention. The invention can ensure the timing control after the preset time by means of a preset time interval The module 21 provides a start pulse signal ST in a three-dimensional mode signal, and the voltage level shift module 22 also outputs drive signals HC1~8 in a three-dimensional drive mode. In other words, the preset time is paused to avoid the moment when the display device is converted from the two-dimensional picture to the three-dimensional picture. Even if the timing control module 21 and the voltage level shifting module 22 fail to synchronously receive the mode switching signal mode_sw, It is also possible to stably supply the correct start pulse signal ST and drive signals HC1~8 after a preset time. The preset interval can be started according to the mode switching signal mode_sw in the three-dimensional mode (high voltage level), and the preset time is started, so that the start pulse signal ST is kept at a low voltage level and the gate cannot be turned on. The driving module 23 prevents the gate driving module 23 from leaking a large current. In other words, when the two-dimensional screen is converted into a three-dimensional image, the display device of the present embodiment does not immediately display the three-dimensional image, but waits for a preset time, thereby allowing the timing control module 21 to stably output correctly. The starting pulse signal ST of the pulse width.
請繼續參考第1圖，於步驟S08中，於一步驟的預設時間之後，閘極驅動模組23才會依據接收到的驅動訊號HC1~8輸出閘極訊號，此時驅動訊號HC1~8可以是由電壓位準移位模組22以二維驅動模式(依序提供)或三維驅動模式(成對提供)傳輸給閘極驅動模組23。顯示裝置係包括多級的閘極驅動模組23，而每一級閘極驅動模組23係具有相同的電路，於本發明的實施例中係以八級的閘極驅動模組23為例。如第4圖所示，其係為顯示裝置中其中一級閘極驅動模組23的電路圖。起始脈衝訊號ST(start pulse)係由每一級閘極驅動模組23的電晶體T11的閘極輸入， 電壓位準移位模組22將高頻訊號HC解碼之後的驅動訊號分別由每一級閘極驅動模組之電晶體T12、T21的汲極輸入。於下列實施例中，括號中的數字係表示該級的符號意義。 Please continue to refer to FIG. 1. In step S08, after a preset time of one step, the gate driving module 23 outputs the gate signal according to the received driving signals HC1~8, and the driving signals HC1~8 at this time. It may be transmitted to the gate driving module 23 by the voltage level shifting module 22 in a two-dimensional driving mode (sequentially provided) or a three-dimensional driving mode (provided in pairs). The display device includes a plurality of gate drive modules 23, and each of the gate drive modules 23 has the same circuit. In the embodiment of the present invention, the eight-stage gate drive module 23 is taken as an example. As shown in FIG. 4, it is a circuit diagram of one of the gate driving modules 23 in the display device. The start pulse signal is input from the gate of the transistor T11 of each stage of the gate driving module 23. The driving signal after the high-frequency signal HC is decoded by the voltage level shifting module 22 is input by the drains of the transistors T12 and T21 of each level of the gate driving module. In the following embodiments, the numbers in parentheses indicate the symbolic meaning of the level.
如第3圖及第4圖所示，當第一級閘極驅動模組接收到驅動訊號HC1/HC2以及起始脈衝訊號ST之後，將使得電晶體T11導通，電晶體T12的閘極電壓Q(1)因此處於高準位的狀態，電晶體T12、T21隨之導通，使得電晶體T21的汲極電壓G(1)亦處於高準位的狀態。此外，在顯示裝置的架構中，可由第一級閘極驅動模組之電晶體T21的汲極傳送驅動電壓G(1)至第五級閘極驅動模組的電晶體T12的閘極Q(5)上，以驅動第五級閘極驅動模組，而第一級閘極驅動模組之電晶體T12的閘極電壓Q(1)則透過第五級閘極驅動模組傳送驅動電壓G(5)將第一級閘極驅動模組的電晶體T31、T41打開，以降低電晶體T12的閘極電壓Q(1)準位以及電晶體T21的汲極電壓G(1)準位。 As shown in FIG. 3 and FIG. 4, when the first-stage gate driving module receives the driving signals HC1/HC2 and the start pulse signal ST, the transistor T11 is turned on, and the gate voltage Q of the transistor T12 is turned on. (1) Therefore, in a state of high level, the transistors T12 and T21 are turned on, so that the gate voltage G(1) of the transistor T21 is also at a high level. In addition, in the architecture of the display device, the driving voltage G(1) of the transistor T21 of the first-stage gate driving module can be transmitted to the gate Q of the transistor T12 of the fifth-level gate driving module ( 5) driving the fifth-level gate driving module, and the gate voltage Q(1) of the transistor T12 of the first-stage gate driving module transmits the driving voltage G through the fifth-level gate driving module (5) The transistors T31 and T41 of the first-stage gate driving module are turned on to lower the gate voltage Q(1) of the transistor T12 and the gate voltage G(1) of the transistor T21.
請參閱第5圖，其係用以對照本發明一實施例之切換顯示模式的訊號時序圖。由第5圖的訊號時序圖示範了時序控制模組21與電壓位準移位模組22未能同步收到模式切換訊號mode_sw的情況，即當電壓位準移位模組22已經切換成兩兩輸出(三維驅動模式)驅動訊號HC1~8，但時序控制模組21尚未將起始脈衝訊號ST的脈寬從第一寬度d1縮短至第二寬度d2。此時，當驅動訊號HC5/HC6傳送至第5級、第6級閘極驅動模組電晶體T12、T21的汲極時，由於起始脈衝訊號ST仍持續維持在高電壓 準位，因此第一級閘極驅動模組電晶體T12的閘極電壓Q(1)亦維持於高電壓的準位，如實線Q1/Q2所示。換句話說，此時，第一級閘極驅動模組電晶體T12、T21仍處於開啟導通的狀態。 Please refer to FIG. 5, which is a signal timing diagram for switching display modes according to an embodiment of the present invention. The signal timing diagram of FIG. 5 demonstrates that the timing control module 21 and the voltage level shifting module 22 fail to synchronously receive the mode switching signal mode_sw, that is, when the voltage level shifting module 22 has switched to two. The two outputs (three-dimensional driving mode) drive signals HC1~8, but the timing control module 21 has not shortened the pulse width of the start pulse signal ST from the first width d1 to the second width d2. At this time, when the driving signal HC5/HC6 is transmitted to the drains of the transistors T12 and T21 of the fifth-stage and sixth-stage gate driving module, the initial pulse signal ST is continuously maintained at a high voltage. Therefore, the gate voltage Q(1) of the first-stage gate driving module transistor T12 is also maintained at a high voltage level, as indicated by the solid line Q1/Q2. In other words, at this time, the first-stage gate driving module transistors T12 and T21 are still in an on-state.
承上所述，由於第一級閘極驅動模組的電晶體T31、T41的閘極電壓係藉由第5級閘極驅動模組電晶體T21的汲極電壓G(5)開啟，因此，在第一級閘極驅動模組電晶體T12、T21仍處於開啟導通的狀態時，當第5級閘極驅動模組電晶體T21的源極電壓G(5)傳送至第一級閘極驅動模組的電晶體T31、T41的閘極，電晶體T31、T41因而導通，將進一步使得第一級閘極驅動模組的電晶體T11、T12、T21經由電晶體T41、T31形成一導通迴路，亦即，其將導致由第一級閘極驅動模組電晶體T11的汲極端VGH(正電壓端)抽取大電流至負電壓端VSS。由此可知，本實施例藉由等待一段預設時間，避免過早輸出驅動訊號HC1~8而造成整個積體電路端電源崩潰的現象。 As described above, since the gate voltages of the transistors T31 and T41 of the first-stage gate driving module are turned on by the gate voltage G(5) of the transistor T21 of the fifth-level gate driving module, When the first stage gate driving module transistors T12 and T21 are still in the on state, when the source voltage G(5) of the fifth stage gate driving module transistor T21 is transmitted to the first stage gate driving The gates of the transistors T31 and T41 of the module, and the transistors T31 and T41 are thus turned on, which further causes the transistors T11, T12 and T21 of the first-stage gate driving module to form a conduction loop via the transistors T41 and T31. That is, it will cause a large current to be drawn from the 汲 terminal VGH (positive voltage terminal) of the first stage gate driving module transistor T11 to the negative voltage terminal VSS. Therefore, in this embodiment, by waiting for a preset time, the phenomenon that the power supply of the entire integrated circuit is collapsed is avoided by prematurely outputting the driving signals HC1~8.
據此，為克服先前技術中閘極驅動模組洩漏電流的問題，本發明切換顯示模式的方法係依據模式切換訊號mode_sw產生禁能訊號disable，並依據禁能訊號disable，於一段預設時間內不輸出多個驅動訊號至閘極驅動模組23。此處的禁能訊號disable係針對致能三維模式之後，亦即三維模式轉換為高電壓準位的狀態之一段預設時間後，禁止輸出多個驅動訊號至閘極驅動模組23的訊號。因此，在經過一段預設時間不輸出多個驅動訊號至閘極驅動模組23的情況下，將可在時序控制模組21接收到三 維模式之後，改變起始脈衝訊號ST的長度。 Accordingly, in order to overcome the problem of the leakage current of the gate driving module in the prior art, the method for switching the display mode according to the present invention generates the disable signal disable according to the mode switching signal mode_sw, and according to the disable signal disable, for a preset time. A plurality of driving signals are not output to the gate driving module 23. The disable signal disable here disables the output of the plurality of drive signals to the gate drive module 23 after the preset time is enabled after the three-dimensional mode is enabled, that is, the state in which the three-dimensional mode is converted to the high voltage level. Therefore, in the case that a plurality of driving signals are not output to the gate driving module 23 after a predetermined period of time, the timing control module 21 can receive three After the dimension mode, the length of the start pulse signal ST is changed.
如第5圖所示，當起始脈衝訊號ST的長度在致能三維模式之後改變，可使得第一級閘極驅動模組的電晶體T12的閘極電壓Q(1)轉換為低電壓準位時，進一步提早關閉電晶體T12、T21，其如虛線所示。據此，在改變起始脈衝訊號ST的長度而提早關閉閘第一級閘極驅動模組的電晶體T12、T21之後，可防止電晶體T11的汲極端VGH(正電壓端)抽取大電流至負電壓端VSS，避免整個積體電路端電源崩潰的現象。據此，藉由下列本發明切換顯示模式的方法可改善起始脈衝訊號與與高頻訊號不同步的問題。 As shown in FIG. 5, when the length of the start pulse signal ST is changed after the three-dimensional mode is enabled, the gate voltage Q(1) of the transistor T12 of the first-stage gate driving module can be converted to a low voltage level. In the case of the bit, the transistors T12, T21 are further turned off early, as indicated by the dotted line. Accordingly, after the transistor T12 and T21 of the first-stage gate driving module of the gate are turned off early by changing the length of the start pulse signal ST, the 汲 extreme VGH (positive voltage terminal) of the transistor T11 can be prevented from extracting a large current to The negative voltage terminal VSS prevents the power supply of the entire integrated circuit from collapsing. Accordingly, the following problem of switching the display mode of the present invention can improve the problem that the start pulse signal is out of sync with the high frequency signal.
承上所述，當電壓位準移位模組22收到三維模式指令時或當模式切換訊號mode_sw為高位準時，電壓位準移位模組22開始計數第一時脈clk數量達到第一門檻值時，結束預設時間Tp，並停止禁能訊號disable，即禁能訊號disable為低位準，以輸出起始脈衝訊號ST及多個驅動訊號(HC1~8)至閘極驅動模組23，請參考第3圖。換句話說，當禁能訊號disable為低位準時，電壓位準移位模組22才可以輸出驅動訊號至閘極驅動模組23。於本發明之實施例中，當第一時脈clk數量達到16個時，結束預設時間Tp，並停止禁能訊號disable以輸出多個驅動訊號。 As described above, when the voltage level shifting module 22 receives the three-dimensional mode command or when the mode switching signal mode_sw is at the high level, the voltage level shifting module 22 starts counting the number of the first clock clk to reach the first threshold. When the value is set, the preset time Tp is ended, and the disable signal disable is disabled, that is, the disable signal disable is low, and the start pulse signal ST and the plurality of drive signals (HC1~8) are output to the gate drive module 23, Please refer to Figure 3. In other words, when the disable signal disable is low, the voltage level shift module 22 can output the drive signal to the gate drive module 23. In the embodiment of the present invention, when the number of first clock clk reaches 16, the preset time Tp is ended, and the disable signal disable is stopped to output a plurality of driving signals.
進一步而言，顯示裝置的每一個輸出畫面必須在輸入起始脈衝訊號之後才能輸出，亦即，不論是二維的畫面或是三維的畫面，在沒有接收到起始脈衝訊號之前閘極驅動模組23並無 法輸出閘極訊號。因此，切換顯示模式的方法亦可根據何時輸出三維的畫面來計數起始脈衝訊號的數量。於另一實施例中，當電壓位準移位模組22收到三維模式指令時或當模式切換訊號mode_sw為高位準時，電壓位準移位模組22亦可計數起始脈衝訊號ST的數量，並於當起始脈衝訊號ST的數量達第二門檻值時，結束預設時間，停止禁能訊號disable以輸出多個驅動訊號。於本發明之實施例中，於當起始脈衝訊號ST的數量達到2時，停止禁能訊號disable以輸出多個驅動訊號。 Further, each output screen of the display device must be output after the start pulse signal is input, that is, the gate drive mode is not received before the start pulse signal is received, whether it is a two-dimensional picture or a three-dimensional picture. Group 23 does not have The method outputs a gate signal. Therefore, the method of switching the display mode can also count the number of start pulse signals depending on when the three-dimensional picture is output. In another embodiment, when the voltage level shifting module 22 receives the three-dimensional mode command or when the mode switching signal mode_sw is at a high level, the voltage level shifting module 22 can also count the number of the starting pulse signals ST. And when the number of the start pulse signal ST reaches the second threshold, the preset time is ended, and the disable signal disable is stopped to output a plurality of driving signals. In the embodiment of the present invention, when the number of the start pulse signals ST reaches 2, the disable signal disable is stopped to output a plurality of drive signals.
於另一實施例中，當電壓位準移位模組22收到三維模式指令時或當模式切換訊號mode_sw為高位準時，電壓位準移位模組22依據畫框終止訊號end開始計數第一時脈clk的數量或脈衝訊號ST的數量達第一門檻值或第二門檻值，而停止禁能訊號disable以輸出多個驅動訊號。如第3圖所示，畫框終止訊號end係於所有驅動訊號(例如為HC1~8)之第一週期輸入完畢之後產生，畫框終止訊號end可由時序控制模組21提供或由電壓位準移位模組22產生。 In another embodiment, when the voltage level shifting module 22 receives the three-dimensional mode command or when the mode switching signal mode_sw is at the high level, the voltage level shifting module 22 starts counting according to the frame end signal end. The number of clock clks or the number of pulse signals ST reaches a first threshold or a second threshold, and the disable signal disable is stopped to output a plurality of driving signals. As shown in FIG. 3, the frame end signal end is generated after the first cycle of all the driving signals (for example, HC1~8) is input, and the frame end signal end can be provided by the timing control module 21 or by the voltage level. The shift module 22 is generated.
據此，藉由上述方式，可縮短時序控制模組在接收三維模式之後的起始脈衝訊號ST週期，使得起始脈衝訊號提早轉換為低電壓準位，進一步使得第一級閘極驅動模組的電晶體T12的閘極電壓Q(1)轉換為低電壓準位，因此即使在第五級閘極驅動模組傳送驅動電壓G(5)至第一級閘極驅動模組的電晶體T31、T41時亦無法開啟電晶體T12，因而可避免第一級閘極驅動 模組電晶體T11的汲極端VGH洩漏大電流至負電壓端VSS，造成整個積體電路端電源崩潰的現象。 Accordingly, in the above manner, the start pulse signal ST period after the timing control module receives the three-dimensional mode can be shortened, so that the initial pulse signal is converted to a low voltage level early, and the first-stage gate driving module is further enabled. The gate voltage Q(1) of the transistor T12 is converted to a low voltage level, so even if the fifth stage gate driving module transmits the driving voltage G(5) to the transistor T31 of the first stage gate driving module , T41 can not open the transistor T12, thus avoiding the first stage gate drive The 汲 extreme VGH of the module transistor T11 leaks a large current to the negative voltage terminal VSS, causing the power supply of the entire integrated circuit to collapse.
於第2圖中，本發明之顯示裝置包含面板(未圖式)、時序控制模組21、電壓位準移位模組22以及閘極驅動模組23。時序控制模組21提供至少一高頻訊號，並由控制轉換二維或三維畫面的模式切換訊號控制，以選擇根據二維模式或三維模式提供輸出畫面的起始脈衝訊號ST。 In the second embodiment, the display device of the present invention comprises a panel (not shown), a timing control module 21, a voltage level shifting module 22, and a gate driving module 23. The timing control module 21 provides at least one high frequency signal and is controlled by a mode switching signal for controlling the conversion of the two-dimensional or three-dimensional picture to select a starting pulse signal ST for providing an output picture according to the two-dimensional mode or the three-dimensional mode.
電壓位準移位模組22耦接時序控制模組21，用以將高頻訊號解碼成多個驅動訊號，並由模式切換訊號控制。相較於先前技術，本發明的顯示裝置係於間隔一段預設時間後，選擇以二維驅動模式或三維驅動模式輸出多個驅動訊號。閘極驅動模組23耦接於面板及電壓位準移位模組22，由電壓位準移位模組22輸出的多個驅動訊號控制，以驅動面板輸出畫面。 The voltage level shifting module 22 is coupled to the timing control module 21 for decoding the high frequency signal into a plurality of driving signals and controlled by the mode switching signal. Compared with the prior art, the display device of the present invention selects to output a plurality of driving signals in a two-dimensional driving mode or a three-dimensional driving mode after a predetermined period of time. The gate driving module 23 is coupled to the panel and the voltage level shifting module 22, and is controlled by a plurality of driving signals output by the voltage level shifting module 22 to drive the panel output screen.
請參閱第6圖，其係為第2圖電壓位準移位模組22的示意圖。電壓位準移位模組22包含解碼單元221、畫框偵測單元222以及輸出單元223。解碼單元221耦接時序控制模組21，用以將高頻訊號解碼成多個驅動訊號，以輸出至閘極驅動模組23。畫框偵測單元222耦接解碼單元221與時序控制模組21，依據模式切換訊號產生一禁能訊號disable，並依據模式切換訊號，以二維驅動模式或三維驅動模式輸出多個驅動訊號。輸出單元223耦接畫框偵測單元222與閘極驅動模組23，接收多個驅動訊號並由禁能訊號disable控制，於上述的預設時間內不輸出多個驅 動訊號。 Please refer to FIG. 6 , which is a schematic diagram of the voltage level shifting module 22 of FIG. 2 . The voltage level shifting module 22 includes a decoding unit 221, a picture frame detecting unit 222, and an output unit 223. The decoding unit 221 is coupled to the timing control module 21 for decoding the high frequency signal into a plurality of driving signals for output to the gate driving module 23. The frame detection unit 222 is coupled to the decoding unit 221 and the timing control module 21, generates a disable signal disable according to the mode switching signal, and outputs a plurality of driving signals in the two-dimensional driving mode or the three-dimensional driving mode according to the mode switching signal. The output unit 223 is coupled to the picture frame detecting unit 222 and the gate driving module 23, and receives a plurality of driving signals and is controlled by the disable signal disable, and does not output multiple drives within the preset time period. Motion signal.
畫框偵測單元222可用於計數第一時脈clk的數量以及起始脈衝訊號ST的數量。當畫框偵測單元222收到三維模式指令時或模式切換訊號mode_sw為高位準時，計數第一時脈clk的數量達第一門檻值，預設時間結束，畫框偵測單元222停止傳送禁能訊號disable至輸出單元223，並藉由輸出單元223輸出多個驅動訊號；或者，當畫框偵測單元222收到模式切換訊號與畫框終止訊號end後，開始計數第一時脈clk的數量，當計數第一時脈clk的數量達第三門檻值，畫框偵測單元222停止傳送禁能訊號disable至輸出單元223。 The frame detection unit 222 can be used to count the number of the first clock clk and the number of the start pulse signals ST. When the picture frame detecting unit 222 receives the three-dimensional mode command or the mode switching signal mode_sw is high, the number of the first clock clk is counted to reach the first threshold, and the preset time is over, and the frame detecting unit 222 stops transmitting the message. The signal can be disabled to the output unit 223, and the plurality of driving signals are outputted by the output unit 223; or, when the frame detecting unit 222 receives the mode switching signal and the frame end signal end, the counting of the first clock clk is started. The number, when the number of the first clock clk is counted to reach the third threshold, the frame detection unit 222 stops transmitting the disable signal disable to the output unit 223.
當畫框偵測單元222收到模式切換訊號，計數起始脈衝訊號ST的數量達第二門檻值，畫框偵測單元222停止傳送禁能訊號disable至輸出單元223，並藉由輸出單元223輸出多個驅動訊號；或者，當畫框偵測單元222收到模式切換訊號與畫框終止訊號end後，開始計數起始脈衝訊號ST的數量達第二門檻值，畫框偵測單元222停止傳送禁能訊號disable至輸出單元223。 When the frame detection unit 222 receives the mode switching signal, the number of the start pulse signal ST reaches the second threshold, and the frame detection unit 222 stops transmitting the disable signal to the output unit 223, and the output unit 223 And outputting a plurality of driving signals; or, when the frame detecting unit 222 receives the mode switching signal and the frame termination signal end, the number of starting pulse signals ST is counted to a second threshold, and the frame detecting unit 222 stops. The disable signal is transmitted to the output unit 223.
據此，顯示裝置藉由利用上述切換顯示模式的方法同步起始脈衝訊號以及高頻訊號，可避免閘極驅動模組電晶體T11的汲極端VGH洩漏大電流至負電壓端VSS，造成整個積體電路端電源崩潰的現象。 Accordingly, the display device synchronizes the start pulse signal and the high frequency signal by using the method for switching the display mode, thereby preventing the 汲 extreme VGH of the gate driving module transistor T11 from leaking a large current to the negative voltage terminal VSS, resulting in the entire product. The power failure of the body circuit.
綜上所述，本發明顯示裝置以及切換顯示模式的方法，藉由間隔一段預設時間，使得時序控制模組在接收三維模式 以及起始脈衝訊號之後，提早切換起始脈衝訊號為低電壓準位，亦即改變起始脈衝訊號之第二週期的長度，避免閘極驅動模組上的電晶體於輸入高頻訊號時被提早開啟，因而導致閘極驅動模組洩漏大電流的情況，而產生積體電路端電源崩潰的現象。 In summary, the display device of the present invention and the method for switching the display mode enable the timing control module to receive the three-dimensional mode by being separated by a preset time. After the start pulse signal, the start pulse signal is switched to a low voltage level early, that is, the length of the second period of the start pulse signal is changed, so that the transistor on the gate drive module is prevented from being input when the high frequency signal is input. Opening early, thus causing the gate drive module to leak a large current, and the power supply of the integrated circuit is collapsed.
S02~S08‧‧‧步驟 S02~S08‧‧‧Steps
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103119540A TWI514349B (en) | 2014-06-05 | 2014-06-05 | Display device and method of switching display mode |
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| Country | Link |
|---|---|
| CN (1) | CN104123907B (en) |
| TW (1) | TWI514349B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI553623B (en) * | 2015-05-11 | 2016-10-11 | 友達光電股份有限公司 | Driver circuit and control method thereof |
| TWI587280B (en) * | 2016-10-18 | 2017-06-11 | 友達光電股份有限公司 | Signal controlling method and display panel utilizing the same |
| CN108154859B (en) * | 2018-01-16 | 2020-09-08 | 深圳市华星光电技术有限公司 | Array substrate and display device |
| WO2023220858A1 (en) * | 2022-05-16 | 2023-11-23 | 京东方科技集团股份有限公司 | Driving method for display panel, and display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4845281B2 (en) * | 2001-04-11 | 2011-12-28 | 三洋電機株式会社 | Display device |
| US8836621B2 (en) * | 2004-12-15 | 2014-09-16 | Nlt Technologies, Ltd. | Liquid crystal display apparatus, driving method for same, and driving circuit for same |
| TWI346316B (en) * | 2006-09-25 | 2011-08-01 | Novatek Microelectronics Corp | Display apparatus and transmission method of the control signals |
| KR101326075B1 (en) * | 2007-01-12 | 2013-11-07 | 삼성디스플레이 주식회사 | Liquid crystal display divice and driving method thereof |
| JP5336285B2 (en) * | 2009-07-21 | 2013-11-06 | 富士フイルム株式会社 | Stereoscopic image display apparatus, method and program, and imaging apparatus |
| TWI483229B (en) * | 2012-12-22 | 2015-05-01 | Chunghwa Picture Tubes Ltd | Display apparatus and method for processing frame thereof |
| CN103617785B (en) * | 2013-11-29 | 2016-08-03 | 青岛海信电器股份有限公司 | A kind of three-dimensional liquid crystal display device and display control method |
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2014
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104123907A (en) | 2014-10-29 |
| TWI514349B (en) | 2015-12-21 |
| CN104123907B (en) | 2016-09-07 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |