TW201537882A - Method of controlling synchronous rectifier for power converter, control circuit, and power converter thereof - Google Patents

Method of controlling synchronous rectifier for power converter, control circuit, and power converter thereof Download PDF

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TW201537882A
TW201537882A TW103110132A TW103110132A TW201537882A TW 201537882 A TW201537882 A TW 201537882A TW 103110132 A TW103110132 A TW 103110132A TW 103110132 A TW103110132 A TW 103110132A TW 201537882 A TW201537882 A TW 201537882A
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signal
period
switching
rectifier
transistor
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TW103110132A
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TWI516009B (en
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Chou-Sheng Wang
Tse-Jen Tseng
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System General Corp
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Abstract

A method for controlling a synchronous rectifier for a power converter, a control circuit, and a power converter thereof are provided. The method comprises the following steps: turning on a transistor by a rectifier; generating a switching-period signal in accordance with a period of a voltage-sensing signal; generating a turn-on-period signal in accordance with a turned-on period of the rectifier; generating a first disabling signal responding to the switching-period signal; and generating a second disabling signal in response to the turn-on-period signal. The transistor is turned off in response to the first disabling signal and the second disabling signal, and the voltage-sensing signal is related to the switching waveform of a transformer.

Description

控制同步整流器的方法、控制電路及其功率轉換器 Method, control circuit and power converter for controlling synchronous rectifier

本發明是有關於一種控制功率轉換器的技術，且特別是有關於一種用於控制返馳(flyback)功率轉換器的同步整流器(synchronous rectifier，SR)的控制電路和方法，所述返馳功率轉換器可以操作於不連續電流模式(discontinuous current mode，DCM)以及連續電流模式(continuous current mode，CCM)，其中週期鎖定功能提供可靠的並且穩固的方法以防止同步整流(SR)功率電晶體發生反向導通(backward conduction)。 The present invention relates to a technique for controlling a power converter, and more particularly to a control circuit and method for controlling a synchronous rectifier (SR) of a flyback power converter, the flyback power The converter can operate in discontinuous current mode (DCM) and continuous current mode (CCM), where the period locking function provides a reliable and robust method to prevent synchronous rectification (SR) power transistors from occurring. Backward conduction.

功率轉換器已被頻繁地用於將未經調節的電源轉化為恒定的電壓輸出。在各種功率轉換器中，返馳(flyback)功率轉換器是最常見的一種。具有一次繞組和次級繞組的變壓器是返馳功率轉換器的主要部分，並且返馳功率轉換器進一步包括輸出電容器。一次繞組連接到未經調節的電源，並且切換裝置連接到一次 繞組以導通和截止未經調節的電源與一次繞組之間的連接。整流二極體通常連接到次級繞組，用於將從一次繞組傳送的能量整流成直流電壓。 Power converters have been frequently used to convert unregulated power to a constant voltage output. Among various power converters, a flyback power converter is the most common one. A transformer having a primary winding and a secondary winding is a major part of the flyback power converter, and the flyback power converter further includes an output capacitor. The primary winding is connected to an unregulated power supply and the switching device is connected to the primary The windings electrically connect and disconnect the unregulated power supply to the primary winding. The rectifying diode is typically connected to the secondary winding for rectifying the energy delivered from the primary winding to a DC voltage.

返馳功率轉換器通常具有兩種操作模式，即，不連續導通模式(discontinuous conduction mode，DCM)和連續導通模式(continuous conduction mode，CCM)。在不連續導通模式中，儲存在變壓器中的所有能量在下一迴圈開始之前被完全傳送。因此，將不會有感應電壓保留在變壓器中來抵抗輸出電容器放電回到變壓器。然而，當在切換裝置截止的瞬間，一旦儲存在變壓器中的能量完全釋放，那麼電流將以反向的方向從輸出電容器中排放出來。相比之下，在連續操作模式中，一些能量保留在返馳功率轉換器的變壓器中。也就是說，在從次級繞組釋放的電流下降到零之前，下一切換迴圈將開始。在連續模式操作下，變壓器在下一切換迴圈開始時持續對能量進行續流(freewheeling)。如果在下一切換迴圈開始之前返馳功率轉換器的同步整流器沒有截止，那麼輸出電容器將以反向的方向充電。上述情況被稱為功率轉換器的“反向導通(backward conduction)”。 The flyback power converter typically has two modes of operation, namely, a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM). In the discontinuous conduction mode, all of the energy stored in the transformer is fully transmitted before the next cycle begins. Therefore, there will be no induced voltage remaining in the transformer to resist discharge of the output capacitor back to the transformer. However, when the switching device is turned off, once the energy stored in the transformer is completely released, the current will be discharged from the output capacitor in the reverse direction. In contrast, in the continuous mode of operation, some of the energy remains in the transformer of the flyback power converter. That is, the next switching loop will begin before the current released from the secondary winding drops to zero. In continuous mode operation, the transformer continues to freewheeling energy at the beginning of the next switching loop. If the synchronous rectifier of the flyback power converter is not turned off before the start of the next switching loop, the output capacitor will be charged in the reverse direction. This situation is referred to as "backward conduction" of the power converter.

在上述揭示內容中，輸出電容器仍然是經由MOSFET同步整流器(synchronous rectifier，SR)以連續模式和不連續模式在切換的瞬間突然地充電和放電的。因此，將降低效率並且升高噪音。另外，在上述方法中，變壓器需要額外的輔助繞組來產生驅動信號以獲得同步整流，並且因此增加了製造變壓器的複雜度。 In the above disclosure, the output capacitor is still suddenly charged and discharged at the instant of switching in a continuous mode and a discontinuous mode via a MOSFET synchronous rectifier (SR). Therefore, efficiency will be lowered and noise will be increased. Additionally, in the above method, the transformer requires an additional auxiliary winding to generate a drive signal to achieve synchronous rectification, and thus increases the complexity of manufacturing the transformer.

本發明揭示了一種用於控制功率轉換器的同步整流器的方法。所述方法包括以下步驟：回應於整流器的導通週期以導通電晶體；根據電壓感測信號的週期產生切換週期信號；根據整流器的導通週期以產生導通週期信號；回應於所述切換週期信號產生第一停用信號；回應於所述導通週期信號產生第二停用信號；回應於所述第一停用信號和所述第二停用信號以截止電晶體。在本發明的一個實施例中，電壓感測信號與變壓器的切換波形有關，並且電晶體耦接到變壓器並且作為同步整流器操作。第一停用信號的導通週期比切換週期信號的導通週期為短。在本申請案的一個實施例中，第二停用信號的導通週期比導通週期信號的導通週期為短。 A method for controlling a synchronous rectifier of a power converter is disclosed. The method includes the steps of: generating a switching period signal according to a period of the voltage sensing signal in response to a turn-on period of the rectifier; generating a turn-on period signal according to a turn-on period of the rectifier; generating a signal in response to the switching period signal a disable signal; generating a second disable signal in response to the turn-on period signal; responding to the first disable signal and the second disable signal to turn off the transistor. In one embodiment of the invention, the voltage sensing signal is related to the switching waveform of the transformer, and the transistor is coupled to the transformer and operates as a synchronous rectifier. The on period of the first disable signal is shorter than the on period of the switching period signal. In one embodiment of the present application, the on period of the second disable signal is shorter than the on period of the on period signal.

從另一觀點來看，本發明揭示了一種用於功率轉換器的同步整流器的控制方法。所述控制方法包括以下步驟：回應於整流器的導通週期以導通電晶體；回應於變壓器的切換波形的導通週期截止電晶體；回應於整流器的導通週期截止電晶體。所述電晶體耦接到變壓器並且並聯連接到整流器，並且操作以進行同步整流。電晶體的導通週期比變壓器的切換波形的導通週期為短，並且也比整流器的導通週期為短。 From another point of view, the present invention discloses a control method for a synchronous rectifier of a power converter. The control method includes the steps of: turning on a crystal in response to a turn-on period of the rectifier; turning off the transistor in response to a turn-on period of the switching waveform of the transformer; and turning off the transistor in response to a turn-on period of the rectifier. The transistor is coupled to a transformer and connected in parallel to the rectifier and is operative to perform synchronous rectification. The on period of the transistor is shorter than the on period of the switching waveform of the transformer, and is also shorter than the on period of the rectifier.

從另一觀點來看，本發明揭示了一種功率轉換器。所述功率轉換器包括變壓器、整流器、電晶體、以及控制電路。所述電晶體耦接到所述整流器，並且操作以進行同步整流。所述控制 電路耦接到所述電晶體，並且經配置以回應於所述整流器的導通而導通所述電晶體。所述控制電路包括第一比較器、同步整流重置電路、觸發器和及閘。第一比較器用於根據電壓感測信號產生啟用信號。同步整流重置電路用於根據電壓感測信號產生切換週期信號，根據所述整流器的導通週期產生導通週期信號，回應於所述切換週期信號產生第一停用信號，回應於所述導通週期信號產生第二停用信號，並且根據所述第一停用信號和所述第二停用信號產生停用信號。所述停用信號耦接到所述觸發器的復位端，所述觸發器是通過所述啟用信號設置的，所述觸發器的輸出和所述啟用信號連接到所述及閘以產生用於控制所述電晶體的控制信號。所述電壓感測信號與所述變壓器的切換波形有關；所述第一停用信號的導通週期比所述切換週期信號的導通週期為短；所述第二停用信號的導通週期比所述導通週期信號的導通週期為短；所述導通週期信號的所述導通週期不與所述第一停用信號的所述導通週期和所述第二停用信號的所述導通週期重疊。從另一觀點來看，本發明揭示了一種功率轉換器，所述功率轉換器包括變壓器、整流器、電晶體，以及控制電路。電晶體耦接到整流器，並且整流器並聯連接到電晶體。控制電路耦接到電晶體，並且控制電路回應於整流器的導通以導通電晶體；回應於變壓器的切換波形的導通週期截止電晶體；並且回應於整流器的導通週期截止電晶體。電晶體的導通週期比變壓器的切換波形的導通週期為短，並且電晶體的導通週期比整流器的導通週期為短。 From another point of view, the present invention discloses a power converter. The power converter includes a transformer, a rectifier, a transistor, and a control circuit. The transistor is coupled to the rectifier and operates to perform synchronous rectification. The control A circuit is coupled to the transistor and configured to turn on the transistor in response to conduction of the rectifier. The control circuit includes a first comparator, a synchronous rectification reset circuit, a flip flop, and a gate. The first comparator is operative to generate an enable signal based on the voltage sense signal. The synchronous rectification reset circuit is configured to generate a switching period signal according to the voltage sensing signal, generate an on period signal according to the on period of the rectifier, generate a first deactivation signal in response to the switching period signal, and respond to the on period signal A second disable signal is generated, and a disable signal is generated based on the first disable signal and the second disable signal. The disable signal is coupled to a reset terminal of the flip flop, the flip flop is set by the enable signal, an output of the flip flop and the enable signal are coupled to the NAND gate to generate Controlling the control signal of the transistor. The voltage sensing signal is related to a switching waveform of the transformer; an on period of the first deactivation signal is shorter than an on period of the switching period signal; and an on period of the second deactivation signal is greater than The on period of the on period signal is short; the on period of the on period signal does not overlap with the on period of the first disable signal and the on period of the second disable signal. From another point of view, the present invention discloses a power converter that includes a transformer, a rectifier, a transistor, and a control circuit. The transistor is coupled to the rectifier and the rectifier is connected in parallel to the transistor. The control circuit is coupled to the transistor, and the control circuit is responsive to the conduction of the rectifier to conduct the crystal; the conduction period in response to the switching waveform of the transformer is turned off the transistor; and the transistor is turned off in response to the on-period of the rectifier. The on period of the transistor is shorter than the on period of the switching waveform of the transformer, and the on period of the transistor is shorter than the on period of the rectifier.

從另一觀點來看，本發明揭示了一種功率轉換器的控制電路，用於控制所述功率轉換器的同步整流。所述控制電路包括第一比較器、同步整流重置電路、觸發器和及閘。第一比較器用於根據電壓感測信號產生啟用信號。同步整流重置電路用於根據電壓感測信號產生切換週期信號，根據所述整流器的導通週期產生導通週期信號，回應於所述切換週期信號產生第一停用信號，回應於所述導通週期信號產生第二停用信號，並且根據所述第一停用信號和所述第二停用信號產生停用信號。所述停用信號耦接到所述觸發器的復位端，所述觸發器是通過所述啟用信號設置的，所述觸發器的輸出和所述啟用信號連接到所述及閘以產生用於控制所述電晶體的控制信號。所述電壓感測信號與所述變壓器的切換波形有關；所述第一停用信號的導通週期比所述切換週期信號的導通週期為短；所述第二停用信號的導通週期比所述導通週期信號的導通週期為短；所述導通週期信號的所述導通週期不與所述第一停用信號的所述導通週期和所述第二停用信號的所述導通週期重疊。 From another point of view, the present invention discloses a control circuit for a power converter for controlling synchronous rectification of the power converter. The control circuit includes a first comparator, a synchronous rectification reset circuit, a flip flop, and a gate. The first comparator is operative to generate an enable signal based on the voltage sense signal. The synchronous rectification reset circuit is configured to generate a switching period signal according to the voltage sensing signal, generate an on period signal according to the on period of the rectifier, generate a first deactivation signal in response to the switching period signal, and respond to the on period signal A second disable signal is generated, and a disable signal is generated based on the first disable signal and the second disable signal. The disable signal is coupled to a reset terminal of the flip flop, the flip flop is set by the enable signal, an output of the flip flop and the enable signal are coupled to the NAND gate to generate Controlling the control signal of the transistor. The voltage sensing signal is related to a switching waveform of the transformer; an on period of the first deactivation signal is shorter than an on period of the switching period signal; and an on period of the second deactivation signal is greater than The on period of the on period signal is short; the on period of the on period signal does not overlap with the on period of the first disable signal and the on period of the second disable signal.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧變壓器 10‧‧‧Transformers

20‧‧‧脈寬調製(PWM)控制器 20‧‧‧ Pulse Width Modulation (PWM) Controller

25‧‧‧電晶體 25‧‧‧Optoelectronics

30‧‧‧電晶體 30‧‧‧Optoelectronics

40‧‧‧整流器 40‧‧‧Rectifier

45‧‧‧輸出電容器 45‧‧‧ output capacitor

51、52‧‧‧電阻器 51, 52‧‧‧ resistors

100‧‧‧控制電路 100‧‧‧Control circuit

110、160、260‧‧‧比較器 110, 160, 260‧‧‧ comparator

120‧‧‧觸發器 120‧‧‧ Trigger

121、211‧‧‧反相器 121, 211‧‧ ‧ inverter

125‧‧‧及閘(AND gate) 125‧‧‧AND gate

150‧‧‧同步整流重置(SR-reset)電路 150‧‧‧Synchronous rectification reset (SR-reset) circuit

170‧‧‧或閘(OR gate) 170‧‧‧ or gate (OR gate)

200‧‧‧切換週期鎖定電路 200‧‧‧Switching cycle lockout circuit

210、215、265‧‧‧脈衝發生器 210, 215, 265‧ ‧ pulse generator

220‧‧‧功率電晶體 220‧‧‧Power transistor

230‧‧‧電流源 230‧‧‧current source

235、245‧‧‧電容器 235, 245‧‧ ‧ capacitor

240‧‧‧開關 240‧‧‧ switch

250‧‧‧緩衝放大器 250‧‧‧Buffer amplifier

251、252‧‧‧電阻器 251, 252‧‧‧ resistors

300‧‧‧導通週期鎖定電路 300‧‧‧ On-cycle lockout circuit

310、315、365、380‧‧‧脈衝發生器 310, 315, 365, 380‧‧ ‧ pulse generator

311、371、372‧‧‧反相器 311, 371, 372‧‧ ‧ inverter

320‧‧‧功率電晶體 320‧‧‧Power transistor

335、345‧‧‧電容器 335, 345‧‧ ‧ capacitor

340‧‧‧開關 340‧‧‧ switch

350‧‧‧緩衝放大器 350‧‧‧Buffer amplifier

351352‧‧‧電阻器 351352‧‧‧Resistors

360‧‧‧比較器 360‧‧‧ comparator

370‧‧‧觸發器 370‧‧‧ Trigger

410‧‧‧電流源 410‧‧‧current source

411、420‧‧‧比較器 411, 420‧‧‧ comparator

412‧‧‧電晶體 412‧‧‧Optoelectronics

415‧‧‧電容器 415‧‧‧ capacitor

425‧‧‧及閘 425‧‧‧ and gate

VIN‧‧‧輸入 V IN ‧‧‧ input

VDS‧‧‧信號 V DS ‧‧‧ signal

SW‧‧‧切換信號 S W ‧‧‧Switching signal

SSR‧‧‧控制信號 S SR ‧‧‧ control signal

VS‧‧‧電壓感測信號 V S ‧‧‧ voltage sensing signal

VO‧‧‧輸出 V O ‧‧‧ output

VTL‧‧‧低電平閾值 V TL ‧‧‧ low threshold

SE‧‧‧啟用信號 S E ‧‧‧Enable signal

ENB‧‧‧信號 ENB‧‧‧ signal

SD‧‧‧停用信號 S D ‧‧‧Deactivation signal

VTH‧‧‧高電平閾值 V TH ‧‧‧ high threshold

SD1‧‧‧第一停用信號 S D1 ‧‧‧First stop signal

SD2‧‧‧第二停用信號 S D2 ‧‧‧second stop signal

T‧‧‧週期 T‧‧ cycle

TON‧‧‧導通時間/導通週期 T ON ‧‧‧ On-time/on-period

ST‧‧‧切換週期信號 S T ‧‧‧Switching cycle signal

VF1‧‧‧衰減信號 V F1 ‧‧‧Attenuation signal

SON‧‧‧導通週期信號 S ON ‧‧‧ conduction cycle signal

X‧‧‧輸入信號 X‧‧‧ input signal

Y‧‧‧輸出信號 Y‧‧‧ output signal

S1010~S1130‧‧‧步驟 S1010~S1130‧‧‧Steps

圖1繪示以說明根據本發明的一個實施例的具有同步整流器 (SR)的返馳功率轉換器的示意圖。 1 is a diagram illustrating a synchronous rectifier according to an embodiment of the present invention. Schematic of the flyback power converter of (SR).

圖2繪示以說明根據本發明的一個實施例的控制電路的方塊圖。 2 is a block diagram illustrating a control circuit in accordance with one embodiment of the present invention.

圖3繪示以說明根據本發明的一個實施例的同步整流重置電路的方塊圖。 3 is a block diagram illustrating a synchronous rectification reset circuit in accordance with one embodiment of the present invention.

圖4繪示以根據本發明的一個實施例在DCM中操作的返馳功率轉換器的波形。 4 depicts waveforms of a flyback power converter operating in a DCM in accordance with an embodiment of the present invention.

圖5繪示以根據本發明的一個實施例在CCM中操作的返馳功率轉換器的波形。 Figure 5 depicts waveforms of a flyback power converter operating in a CCM in accordance with one embodiment of the present invention.

圖6繪示以說明根據本發明的一個實施例的切換週期鎖定電路的電路圖。 6 is a circuit diagram illustrating a switching period locking circuit in accordance with one embodiment of the present invention.

圖7繪示以說明根據本發明的一個實施例的導通週期鎖定電路的電路圖。 FIG. 7 is a circuit diagram illustrating an on-period locking circuit in accordance with an embodiment of the present invention.

圖8繪示以說明根據本發明的一個實施例的圖6和圖7中的脈衝發生器中的一個的參考電路圖。 Figure 8 is a diagram showing a reference circuit diagram illustrating one of the pulse generators of Figures 6 and 7 in accordance with one embodiment of the present invention.

圖9繪示以根據本發明的一個實施例的脈衝發生器的波形。 Figure 9 depicts waveforms of a pulse generator in accordance with one embodiment of the present invention.

圖10繪示以說明根據本發明的一個實施例的控制功率轉換器的同步整流器的方法的流程圖。 10 is a flow chart illustrating a method of controlling a synchronous rectifier of a power converter, in accordance with one embodiment of the present invention.

圖11繪示以說明根據本發明的一個實施例的用於功率轉換器的同步整流器的控制方法的流程圖。 11 is a flow chart illustrating a method of controlling a synchronous rectifier for a power converter in accordance with one embodiment of the present invention.

本發明提供了用於可以在DCM(不連續電流模式)和CCM(連續電流模式)中操作的返馳功率轉換器的具有週期鎖定功能的同步整流器(SR)的控制電路和方法。返馳功率轉換器的週期鎖定功能提供可靠的並且穩固的方法以防止同步整流電晶體發生反向導通。 The present invention provides a control circuit and method for a synchronous rectifier (SR) having a period locking function for a flyback power converter that can operate in DCM (discontinuous current mode) and CCM (continuous current mode). The cycle lock function of the flyback power converter provides a reliable and robust way to prevent reverse commutation of the synchronous rectifying transistor.

DCM操作意味著功率轉換器的變壓器在變壓器重新磁化(下一切換迴圈的開始)之前是完全去磁的。CCM操作意味著功率轉換器的變壓器在下一切換迴圈開始時不是完全去磁的。 DCM operation means that the transformer of the power converter is completely demagnetized before the transformer is re-magnetized (the beginning of the next switching loop). CCM operation means that the transformer of the power converter is not fully demagnetized at the beginning of the next switching loop.

圖1繪示以說明根據本發明的一個實施例的具有同步整流器(SR)的返馳功率轉換器的示意圖。所述返馳功率轉換器包括變壓器10、脈寬調製(PWM)控制器20、電晶體25和30、整流器40、輸出電容器45、電阻器51和52，以及控制電路100。整流器25操作以進行功率轉換器的同步整流。電晶體25經配置以切換變壓器10的一次繞組(primary-winding)，用於將能量從輸入VIN轉移到返馳功率轉換器的輸出VO。在電晶體25與變壓器10的一次繞組之間產生信號VDS。PWM控制器20經配置以檢測輸出VO，用於產生切換信號SW以控制電晶體25並且調節輸出VO。當整流器40(或電晶體30的體二極體)導通以用於將功率從變壓器10傳送到輸出電容器45時，電晶體30將被導通以減少整流器40的導通損失(整流器40的正向壓降)。控制電路100產生控制信號SSR以驅動電晶體30來用於進行同步整流操作。電阻 器51和52耦接到變壓器10的次級繞組(secondary-winding)以用於根據變壓器10的波形產生電壓感測信號VS。電壓感測信號VS耦接到控制電路100以用於產生控制信號SSR。 1 is a schematic diagram illustrating a flyback power converter having a synchronous rectifier (SR) in accordance with one embodiment of the present invention. The flyback power converter includes a transformer 10, a pulse width modulation (PWM) controller 20, transistors 25 and 30, a rectifier 40, an output capacitor 45, resistors 51 and 52, and a control circuit 100. The rectifier 25 operates to perform synchronous rectification of the power converter. The transistor 25 is configured to switch the primary-winding of the transformer 10 for transferring energy from the input V IN to the output V O of the flyback power converter. A signal V DS is generated between the transistor 25 and the primary winding of the transformer 10. The PWM controller 20 is configured to detect an output V O for generating a switching signal S W to control the transistor 25 and to adjust the output V O . When the rectifier 40 (or the body diode of the transistor 30) is turned on for transferring power from the transformer 10 to the output capacitor 45, the transistor 30 will be turned on to reduce the conduction loss of the rectifier 40 (the forward voltage of the rectifier 40) drop). Control circuit 100 generates control signal SSR to drive transistor 30 for performing a synchronous rectification operation. Resistors 51 and 52 are coupled to a secondary winding (secondary-winding) transformer 10 for generating a voltage sense signal V S of the waveform of the transformer 10. The voltage sense signal V S is coupled to the control circuit 100 for generating a control signal S SR .

圖2繪示以說明根據本發明的一個實施例的控制電路100的方塊圖。控制電路100包括比較器110、觸發器120、反相器121、及閘(AND gate)125以及同步整流重置(SR-reset)電路150。當電壓感測信號VS低於低電平閾值VTL時，比較器110產生啟用信號SE。啟用信號SE的上升緣(rising edge)經配置以設置(啟用(enable))觸發器120。觸發器120的輸出以及啟用信號SE連接到及閘125以產生控制信號SSR。同步整流重置電路150經配置以接收啟用信號SE、電壓感測信號VS以及控制信號SSR，用於產生停用信號(disabling signal)SD。通過反相器121，停用信號SD經配置以重置(reset)觸發器120並且停用控制信號SSR。觸發器120的信號ENB是常態性為高的。 2 is a block diagram illustrating a control circuit 100 in accordance with one embodiment of the present invention. The control circuit 100 includes a comparator 110, a flip flop 120, an inverter 121, an AND gate 125, and a synchronous rectification reset (SR-reset) circuit 150. When the voltage sense signal V S is below the low level threshold V TL , the comparator 110 generates an enable signal S E . The rising edge of the enable signal S E is configured to set (enable) the flip flop 120. The output of flip flop 120 and enable signal S E are coupled to AND gate 125 to generate control signal S SR . The synchronous rectification reset circuit 150 is configured to receive the enable signal S E , the voltage sense signal V S , and the control signal S SR for generating a disabling signal S D . Through the inverter 121, the disable signal S D is configured to reset the flip flop 120 and deactivate the control signal S SR . The signal ENB of the flip-flop 120 is normally high.

當整流器40被導通時，電壓感測信號VS將低於低電平閾值VTL。因此，控制信號SSR將被啟用以在整流器40被導通的同時導通電晶體30。控制信號SSR將回應於電壓感測信號VS、控制信號SSR以及啟用信號SE而被停用。電壓感測信號VS與變壓器10的波形有關。 When the rectifier 40 is turned on, the voltage sense signal V S will be below the low level threshold V TL . Therefore, the control signal SSR will be enabled to conduct the crystal 30 while the rectifier 40 is turned on. The control signal S SR will be deactivated in response to the voltage sense signal V S , the control signal S SR , and the enable signal S E . The voltage sensing signal V S is related to the waveform of the transformer 10.

圖3繪示以說明根據本發明的一個實施例的同步整流重置電路150的方塊圖。同步整流重置電路150包括比較器160、或閘(OR gate)170、切換週期鎖定電路200，以及導通週期鎖定電 路300。當電壓感測信號VS高於高電平閾值VTH時，比較器160產生切換週期信號ST。切換週期信號ST通過切換週期鎖定電路200以產生第一停用信號SD1。控制信號SSR和啟用信號SE通過導通週期鎖定電路300以產生第二停用信號SD2。第一停用信號SD1和第二停用信號SD2都耦接到或閘170以產生停用信號SD。 3 is a block diagram illustrating a synchronous rectification reset circuit 150 in accordance with one embodiment of the present invention. The synchronous rectification reset circuit 150 includes a comparator 160, an OR gate 170, a switching period locking circuit 200, and an on period locking circuit 300. When the voltage sensing signal V S is higher than the high level threshold V TH , the comparator 160 generates the switching period signal S T . The switching period signal S T is generated by switching the period locking circuit 200 to generate a first disable signal S D1 . The control signal S SR and the enable signal S E pass through the period locking circuit 300 to generate a second disable signal S D2 . Both the first disable signal S D1 and the second disable signal S D2 are coupled to the OR gate 170 to generate a disable signal S D .

圖4繪示以根據本發明的一個實施例在DCM中操作的返馳功率轉換器的波形。信號VDS是在圖1中的電晶體25與變壓器10的一次繞組之間產生的。週期T是切換信號SW的切換週期。導通時間TON表示整流器40的導通週期(turned-on period)(連接週期(conduction period))，並且整流器40的導通週期與變壓器10的去磁時間相關。第二停用信號SD2是被產生以在整流器40的導通週期結束之前停用控制信號SSR。 4 depicts waveforms of a flyback power converter operating in a DCM in accordance with an embodiment of the present invention. Signal V DS is generated between transistor 25 in FIG. 1 and the primary winding of transformer 10. The period T is a switching period of the switching signal S W . The on-time T ON represents a turned-on period (conduction period) of the rectifier 40, and the on-period of the rectifier 40 is related to the demagnetization time of the transformer 10. The second disable signal S D2 is generated to disable the control signal S SR before the end of the on period of the rectifier 40.

圖5繪示以根據本發明的一個實施例在CCM中操作的返馳功率轉換器的波形。導通時間TON表示整流器40的導通週期(連接週期)，並且導通時間TON是回應於切換信號SW的開始(下一切換迴圈的開始)結束的。產生第一停用信號SD1是被產生以在下一切換迴圈開始之前停用控制信號SSR。 Figure 5 depicts waveforms of a flyback power converter operating in a CCM in accordance with one embodiment of the present invention. The on-time T ON represents the on period (connection period) of the rectifier 40, and the on-time T ON is ended in response to the start of the switching signal S W (the start of the next switching loop). Generating a first disable signal S D1 is generated to deactivate the control signal S SR before the next switching loop begins.

圖6繪示以說明根據本發明的一個實施例的切換週期鎖定電路200的電路圖。切換週期鎖定電路200包括第一脈衝發生器210、第二脈衝發生器215、第三脈衝發生器265、反相器211、功率電晶體220、電流源230、電容器235和245、開關240、緩衝放大器250以及電阻器251、252。電流源230耦接到功率電晶 體220、電容器235以及開關240，並且應用電流源230給電容器235充電。第二脈衝發生器215通過反相器211接收第一脈衝發生器210的輸出。第二脈衝發生器215的輸出耦接到功率電晶體220的控制節點，功率電晶體220的第一節點耦接到電流源230，並且功率電晶體220的第二節點耦接到地面。開關240經配置以將電容器235的電壓取樣給由脈衝發生器210的輸出控制的電容器245。切換週期信號ST通過脈衝發生器210產生脈衝信號。脈衝發生器210的輸出經配置以導通開關240用於回應於切換週期信號ST的上升緣進行取樣。脈衝發生器210的輸出進一步經配置以在取樣之後通過反相器211、脈衝發生器215和功率電晶體220使電容器235放電。電容器245的電壓電平V245與切換信號SW的週期T(即，切換週期信號ST)有關，並且可以根據電流源230的電流I230以及電容器235的電容C235通過公式(1)計算電壓電平V245。 FIG. 6 is a circuit diagram illustrating a switching cycle lockout circuit 200 in accordance with one embodiment of the present invention. The switching period locking circuit 200 includes a first pulse generator 210, a second pulse generator 215, a third pulse generator 265, an inverter 211, a power transistor 220, a current source 230, capacitors 235 and 245, a switch 240, and a buffer. Amplifier 250 and resistors 251, 252. Current source 230 is coupled to power transistor 220, capacitor 235, and switch 240, and current source 230 is applied to charge capacitor 235. The second pulse generator 215 receives the output of the first pulse generator 210 through the inverter 211. The output of the second pulse generator 215 is coupled to a control node of the power transistor 220, the first node of the power transistor 220 is coupled to the current source 230, and the second node of the power transistor 220 is coupled to the ground. Switch 240 is configured to sample the voltage of capacitor 235 to capacitor 245 controlled by the output of pulse generator 210. The switching period signal S T generates a pulse signal through the pulse generator 210. The output of pulse generator 210 is configured to turn on switch 240 for sampling in response to the rising edge of switching period signal S T . The output of pulse generator 210 is further configured to discharge capacitor 235 through inverter 211, pulse generator 215, and power transistor 220 after sampling. The voltage level V 245 of the capacitor 245 is related to the period T of the switching signal S W (ie, the switching period signal S T ), and can be calculated by the formula (1) according to the current I 230 of the current source 230 and the capacitance C 235 of the capacitor 235. Voltage level V 245 .

電容器245經配置以通過緩衝放大器250以及電阻器251和252產生衰減信號VF1。比較器260經配置以在電容器235的電壓電平高於衰減信號VF1時通過脈衝發生器265產生第一停用信號SD1。因此，第一停用信號SD1將在切換信號SW啟用之前(在下一切換迴圈開始之前)被產生。 Capacitor 245 is configured to generate an attenuation signal V F1 through buffer amplifier 250 and resistors 251 and 252. Comparator 260 is configured to generate a first disable signal S D1 by pulse generator 265 when the voltage level of capacitor 235 is higher than attenuation signal V F1 . Therefore, the first disable signal S D1 will be generated before the switching signal S W is enabled (before the start of the next switching loop).

圖7繪示以說明根據本發明的一個實施例的導通週期鎖 定電路300的電路圖。導通週期鎖定電路300包括脈衝發生器310、315、365和380、觸發器370、反相器311、371和372、電流源330、電容器335和345、功率電晶體320、開關340、緩衝放大器350以及電阻器351和352。控制信號SSR的上升緣在觸發器370中產生導通週期信號SON。啟用信號SE用以重置觸發器370並且在啟用信號SE停用(低邏輯；整流器40未導通)時通過反相器371、372以及脈衝發生器380將導通週期信號SON停用(disable)。 FIG. 7 is a circuit diagram illustrating an on-period locking circuit 300 in accordance with an embodiment of the present invention. The on-cycle locking circuit 300 includes pulse generators 310, 315, 365, and 380, a flip-flop 370, inverters 311, 371, and 372, a current source 330, capacitors 335 and 345, a power transistor 320, a switch 340, and a buffer amplifier 350. And resistors 351 and 352. The rising edge of the control signal S SR generates an on-period signal S ON in the flip-flop 370. The enable signal S E is used to reset the flip-flop 370 and disables the on-period signal S ON through the inverters 371, 372 and the pulse generator 380 when the enable signal S E is deactivated (low logic; rectifier 40 is not conducting) Disable).

電流源330耦接到功率電晶體320、電容器335以及開關340，並且電流源330是用以為電容器335充電。開關340經配置以將電容器335的電壓取樣給由脈衝發生器310的輸出所控制的電容器345。導通週期信號SON經由脈衝發生器310產生脈衝信號。脈衝發生器310的輸出用以導通開關340以用於回應於導通週期信號SON的上升緣而進行取樣。脈衝發生器310的輸出進一步用以在取樣之後通過反相器311、脈衝發生器315和功率電晶體320使電容器335放電。第二脈衝發生器315的輸出耦接到功率電晶體320的控制節點。電容器345的電壓電平將與整流器40的導通時間TON(導通週期)相關，並且可以根據電流源330的電流I330以及電容器335的電容C335通過公式(2)計算電壓電平V345。 Current source 330 is coupled to power transistor 320, capacitor 335, and switch 340, and current source 330 is used to charge capacitor 335. Switch 340 is configured to sample the voltage of capacitor 335 to capacitor 345 controlled by the output of pulse generator 310. The on period signal S ON generates a pulse signal via the pulse generator 310. The output of pulse generator 310 is used to turn on switch 340 for sampling in response to the rising edge of turn-on periodic signal S ON . The output of pulse generator 310 is further used to discharge capacitor 335 through inverter 311, pulse generator 315, and power transistor 320 after sampling. The output of the second pulse generator 315 is coupled to a control node of the power transistor 320. The voltage level of the capacitor 345 will be related to the on-time T ON (on-period) of the rectifier 40, and the voltage level V 345 can be calculated by equation (2) from the current I 330 of the current source 330 and the capacitance C 335 of the capacitor 335.

電容器345用以通過緩衝放大器350以及電阻器351和 352而產生衰減信號VF2。比較器360用以在電容器335的電壓電平高於衰減信號VF2時通過脈衝發生器365而產生第二停用信號SD2。因此，第二停用信號SD2將在整流器40的導通時間結束之前產生，也就是說，在導通時間TON結束時產生。 Capacitor 345 is used to generate attenuation signal V F2 through buffer amplifier 350 and resistors 351 and 352. The comparator 360 is operative to generate a second disable signal S D2 by the pulse generator 365 when the voltage level of the capacitor 335 is higher than the attenuation signal V F2 . Therefore, the second deactivation signal S D2 will be generated before the end of the on-time of the rectifier 40, that is, at the end of the on-time T ON .

圖8繪示以說明根據本發明的一個實施例的圖6和圖7中的脈衝發生器中的一個的參考電路圖。圖8中所示的脈衝發生器包括電流源410、反相器411和420、電晶體412、及閘425，以及電容器415。輸入信號X是通過電晶體412經由反相器411接收的。電流源410經配置以給電容器415充電。電容器415的電壓電平通過反相器420反相。電晶體412經配置以使由輸入信號X控制的電容器415放電。輸入信號X和電容器415的反相電壓電平由及閘425接收以產生輸出信號Y。 Figure 8 is a diagram showing a reference circuit diagram illustrating one of the pulse generators of Figures 6 and 7 in accordance with one embodiment of the present invention. The pulse generator shown in FIG. 8 includes a current source 410, inverters 411 and 420, a transistor 412, and a gate 425, and a capacitor 415. The input signal X is received via the transistor 412 via the inverter 411. Current source 410 is configured to charge capacitor 415. The voltage level of capacitor 415 is inverted by inverter 420. The transistor 412 is configured to discharge the capacitor 415 controlled by the input signal X. The inverted signal levels of input signal X and capacitor 415 are received by AND gate 425 to produce an output signal Y.

圖9繪示以根據本發明的一個實施例的脈衝發生器的波形。回應於脈衝發生器的輸入信號X的上升緣，脈衝發生器的輸出信號Y將產生脈衝。輸出信號Y的脈寬是通過圖8中所示的電流源410的電流以及電容器415的電容確定的。 Figure 9 depicts waveforms of a pulse generator in accordance with one embodiment of the present invention. In response to the rising edge of the pulse generator's input signal X, the pulse generator's output signal Y will produce a pulse. The pulse width of the output signal Y is determined by the current of the current source 410 shown in Fig. 8 and the capacitance of the capacitor 415.

因此，回應於整流器40的導通，圖1中所示的電晶體30是導通的。切換週期信號ST是根據電壓感測信號VS的週期產生的。導通週期信號SON是根據整流器40的導通週期產生的。第一停用信號SD1是回應於切換週期信號ST產生的。第二停用信號SD2是回應於導通週期信號SON產生的。電晶體30回應於第一停用信號和第二停用信號而截止。第一停用信號SD1的週期比切換週期信 號ST的週期為短。第二停用信號SD2的週期比導通週期信號SON的週期為短。 Therefore, in response to the conduction of the rectifier 40, the transistor 30 shown in Fig. 1 is turned on. The switching period signal S T is generated according to the period of the voltage sensing signal V S . The on period signal S ON is generated in accordance with the on period of the rectifier 40. The first disable signal S D1 is generated in response to the switching period signal S T . The second disable signal S D2 is generated in response to the on period signal S ON . The transistor 30 is turned off in response to the first disable signal and the second disable signal. The period of the first disable signal S D1 is shorter than the period of the switching period signal S T . The period of the second disable signal S D2 is shorter than the period of the on period signal S ON .

圖10繪示以說明根據本發明的一個實施例的控制用於功率轉換器的同步整流器的方法的流程圖。在本實施例中，控制功率轉換器的同步整流器的方法適用於圖1到圖3的功率轉換器。本文中描述了所述方法的每個步驟。參考圖1至圖3以及圖10，在步驟S1010中，回應於整流器40的導通週期，控制電路100導通電晶體30(電晶體30的體二極體)。在步驟S1020中，控制電路100根據電壓感測信號VS的週期產生切換週期信號ST(即切換信號SW)。在步驟S1030中，控制電路100根據整流器40的導通週期(即，導通週期)TON產生導通週期信號SON。在步驟S1040中，回應於切換週期信號ST(即，切換信號SW)，控制電路100產生第一停用信號SD1。在步驟S1050中，回應於導通週期信號SON，控制電路100產生第二停用信號SD2。在步驟S1060中，回應於第一停用信號SD1和第二停用信號SD2，控制電路100截止電晶體30。電壓感測信號VS與變壓器10的切換波形有關。電晶體30耦接到變壓器10並且作為同步整流器操作。整流器40並聯連接到電晶體30。第一停用信號SD1的導通週期比切換週期信號ST(即，切換信號SW)的導通週期為短。第二停用信號SD2的導通週期比導通週期信號SON的導通週期為短。在本發明的上述實施例中描述了與控制功率轉換器的同步整流器的方法相結合的技術以及這種方法的具體實施。 10 is a flow chart illustrating a method of controlling a synchronous rectifier for a power converter, in accordance with one embodiment of the present invention. In the present embodiment, the method of controlling the synchronous rectifier of the power converter is applied to the power converter of FIGS. 1 to 3. Each step of the method is described herein. Referring to FIGS. 1 through 3 and FIG. 10, in step S1010, in response to the on period of the rectifier 40, the control circuit 100 conducts the transistor 30 (the body diode of the transistor 30). In step S1020, the control circuit 100 generates a switching period signal S T (i.e., switching signal S W ) according to the period of the voltage sensing signal V S . In step S1030, the control circuit 100 generates the on-period signal S ON according to the on-period (i.e., on-period) T ON of the rectifier 40. In step S1040, in response to the switching period signal S T (ie, the switching signal S W ), the control circuit 100 generates a first disable signal S D1 . In step S1050, in response to the on period signal S ON , the control circuit 100 generates a second disable signal S D2 . In step S1060, in response to the first disable signal S D1 and the second disable signal S D2 , the control circuit 100 turns off the transistor 30. The voltage sensing signal V S is related to the switching waveform of the transformer 10. The transistor 30 is coupled to the transformer 10 and operates as a synchronous rectifier. The rectifier 40 is connected in parallel to the transistor 30. The on period of the first disable signal S D1 is shorter than the on period of the switching period signal S T (ie, the switching signal S W ). The on period of the second disable signal S D2 is shorter than the on period of the on period signal S ON . Techniques in combination with methods of controlling a synchronous rectifier of a power converter and implementations of such a method are described in the above-described embodiments of the present invention.

從另一觀點來看，圖11繪示以說明根據本發明的一個實施例的功率轉換器的同步整流器的控制方法的流程圖。在本實施例中，用於功率轉換器的同步整流器的控制方法適用於圖1到圖3的功率轉換器。本文中描述了所述方法的每個步驟。在步驟S1110中，，控制電路100回應於整流器40的導通週期以導通電晶體30(電晶體30的體二極體)。在步驟S1120中，回應於變壓器10的切換波形的週期，控制電路100截止電晶體30。在步驟S1130中，回應於整流器40的導通週期，控制電路100截止電晶體30。電晶體30耦接到變壓器10並且作為同步整流器操作。整流器40並聯連接到電晶體30。電晶體30的導通週期比變壓器10的切換波形的週期為短，並且電晶體30的導通週期比整流器40的導通週期為短。 From another point of view, FIG. 11 is a flow chart illustrating a method of controlling a synchronous rectifier of a power converter in accordance with an embodiment of the present invention. In the present embodiment, the control method for the synchronous rectifier of the power converter is applied to the power converter of FIGS. 1 to 3. Each step of the method is described herein. In step S1110, the control circuit 100 is responsive to the on period of the rectifier 40 to conduct the transistor 30 (the body diode of the transistor 30). In step S1120, the control circuit 100 turns off the transistor 30 in response to the period of the switching waveform of the transformer 10. In step S1130, in response to the on period of the rectifier 40, the control circuit 100 turns off the transistor 30. The transistor 30 is coupled to the transformer 10 and operates as a synchronous rectifier. The rectifier 40 is connected in parallel to the transistor 30. The on period of the transistor 30 is shorter than the period of the switching waveform of the transformer 10, and the on period of the transistor 30 is shorter than the on period of the rectifier 40.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧變壓器 10‧‧‧Transformers

20‧‧‧脈寬調製(PWM)控制器 20‧‧‧ Pulse Width Modulation (PWM) Controller

25‧‧‧電晶體 25‧‧‧Optoelectronics

30‧‧‧電晶體 30‧‧‧Optoelectronics

40‧‧‧整流器 40‧‧‧Rectifier

45‧‧‧輸出電容器 45‧‧‧ output capacitor

51、52‧‧‧電阻器 51, 52‧‧‧ resistors

100‧‧‧控制電路 100‧‧‧Control circuit

VIN‧‧‧輸入 V IN ‧‧‧ input

VDS‧‧‧信號 V DS ‧‧‧ signal

SW‧‧‧切換信號 S W ‧‧‧Switching signal

SSR‧‧‧控制信號 S SR ‧‧‧ control signal

VS‧‧‧電壓感測信號 V S ‧‧‧ voltage sensing signal

VO‧‧‧輸出 V O ‧‧‧ output

Claims (21)

一種用於控制功率轉換器的同步整流器的方法，包括：回應於整流器的導通週期以導通電晶體；根據電壓感測信號的週期產生切換週期信號；根據所述整流器的導通週期產生導通週期信號；回應於所述切換週期信號產生第一停用信號；回應於所述導通週期信號產生第二停用信號；並且回應於所述第一停用信號和所述第二停用信號以截止所述電晶體，其中所述電壓感測信號與變壓器的切換波形有關；所述電晶體耦接到所述變壓器並且作為同步整流器操作；所述第一停用信號的週期比所述切換週期信號的週期為短；所述第二停用信號的週期比所述導通週期信號的週期為短。 A method for controlling a synchronous rectifier of a power converter, comprising: responsive to a conduction period of a rectifier to conduct a current crystal; generating a switching period signal according to a period of the voltage sensing signal; generating an on period signal according to an on period of the rectifier; Generating a first disable signal in response to the switching cycle signal; generating a second disable signal in response to the turn-on periodic signal; and responding to the first disable signal and the second disable signal to disable a transistor, wherein the voltage sensing signal is related to a switching waveform of a transformer; the transistor is coupled to the transformer and operates as a synchronous rectifier; a period of the first deactivation signal is longer than a period of the switching period signal Short; the period of the second disable signal is shorter than the period of the on period signal. 如申請專利範圍第1項所述的方法，其中切換信號經配置以切換所述變壓器用於調節所述功率轉換器的輸出；所述切換波形與所述切換信號相關；所述導通週期信號的所述導通週期不與所述切換信號的導通週期重疊；所述第一停用信號的所述導通週期以及所述第二停用信號的所述導通週期設置在所述導通週期信號的所述導通週期與所述切換信號的所述導通週期之間。 The method of claim 1, wherein the switching signal is configured to switch the transformer for adjusting an output of the power converter; the switching waveform is related to the switching signal; The on period does not overlap with an on period of the switching signal; the on period of the first disable signal and the on period of the second disable signal are set in the said on period signal The on period is between the on period of the switching signal. 如申請專利範圍第1項所述的方法，其中控制信號經配置以控制所述電晶體；所述控制信號回應於所述整流器的所述導通週期而啟用；所述控制信號回應於所述第一停用信號和所述第 二停用信號而停用。 The method of claim 1, wherein the control signal is configured to control the transistor; the control signal is enabled in response to the conduction period of the rectifier; the control signal is responsive to the a disable signal and the first Second, the signal is deactivated and disabled. 如申請專利範圍第1項所述的方法，其中所述電壓感測信號是通過檢測所述變壓器的波形來檢測的。 The method of claim 1, wherein the voltage sensing signal is detected by detecting a waveform of the transformer. 如申請專利範圍第1項所述的方法，其中所述整流器是所述電晶體的體二極體。 The method of claim 1, wherein the rectifier is a body diode of the transistor. 如申請專利範圍第1項所述的方法，其中所述第一停用信號是通過切換週期鎖定電路產生的；所述切換週期鎖定電路經配置以通過電阻器檢測所述變壓器的波形。 The method of claim 1, wherein the first disable signal is generated by a switching period lock circuit; the switching period lock circuit is configured to detect a waveform of the transformer through a resistor. 如申請專利範圍第1項所述的方法，其中所述第二停用信號是通過導通週期鎖定電路產生的；所述導通週期鎖定電路經配置以通過電阻器檢測所述整流器的波形。 The method of claim 1, wherein the second disable signal is generated by a turn-on period lock circuit; the turn-on period lock circuit is configured to detect a waveform of the rectifier through a resistor. 一種用於功率轉換器的同步整流器的控制方法，包括：回應於整流器的導通週期以導通電晶體；回應於變壓器的切換波形的週期截止所述電晶體；並且回應於所述整流器的導通週期截止所述電晶體，其中所述電晶體耦接到所述變壓器並且並聯連接到所述整流器，並且操作以進行同步整流；所述電晶體的導通週期比所述變壓器的所述切換波形的週期為短，並且也比所述整流器的所述導通週期為短。 A control method for a synchronous rectifier of a power converter, comprising: a conducting current crystal in response to a turn-on period of the rectifier; a period of the switching transistor in response to a switching waveform of the transformer; and a turn-on period in response to the rectifier The transistor, wherein the transistor is coupled to the transformer and connected in parallel to the rectifier, and is operative to perform synchronous rectification; an on period of the transistor is longer than a period of the switching waveform of the transformer It is short and also shorter than the conduction period of the rectifier. 如申請專利範圍第8項所述的控制方法，其中切換信號經配置以切換所述變壓器用於調節所述功率轉換器的輸出；所述切換波形與所述切換信號相關；所述導通週期信號的所述導通週 期不與所述切換信號的導通週期重疊；所述第一停用信號的所述導通週期以及所述第二停用信號的所述導通週期設置在所述導通週期信號的所述導通週期與所述切換信號的所述導通週期之間。 The control method of claim 8, wherein the switching signal is configured to switch the transformer for adjusting an output of the power converter; the switching waveform is related to the switching signal; the conduction period signal Said week The period does not overlap with the on period of the switching signal; the on period of the first disable signal and the on period of the second disable signal are set in the on period of the on period signal Between the conduction periods of the switching signal. 如申請專利範圍第8項所述的控制方法，其中控制信號經配置以控制所述電晶體；所述控制信號是回應於所述整流器的所述導通週期；所述控制信號是回應於所述變壓器的所述切換波形的所述週期而停用的。 The control method of claim 8, wherein the control signal is configured to control the transistor; the control signal is responsive to the conduction period of the rectifier; the control signal is responsive to the The cycle of the switching waveform of the transformer is deactivated. 如申請專利範圍第8項所述的控制方法，其中控制信號經配置以控制所述電晶體；所述控制信號是回應於所述整流器的所述導通啟用的；所述控制信號是回應於所述整流器的所述導通週期而停用的。 The control method of claim 8, wherein the control signal is configured to control the transistor; the control signal is responsive to the conduction of the rectifier; the control signal is responsive to The conduction period of the rectifier is disabled. 如申請專利範圍第8項所述的控制方法，其中所述整流器是所述電晶體的體二極體。 The control method of claim 8, wherein the rectifier is a body diode of the transistor. 如申請專利範圍第8項所述的控制方法，其中所述變壓器的所述切換波形的所述週期是通過切換週期鎖定電路而確定的；所述切換週期鎖定電路經配置以通過電阻器檢測所述變壓器的波形。 The control method of claim 8, wherein the period of the switching waveform of the transformer is determined by switching a period locking circuit; the switching period locking circuit is configured to detect through a resistor The waveform of the transformer. 如申請專利範圍第8項所述的控制方法，其中所述整流器的導通週期是通過導通週期鎖定電路而確定的；所述導通週期鎖定電路經配置以通過電阻器檢測所述整流器的波形。 The control method of claim 8, wherein the on period of the rectifier is determined by turning on a period locking circuit; the on period locking circuit is configured to detect a waveform of the rectifier through a resistor. 一種功率轉換器，包括：變壓器； 整流器；電晶體，所述電晶體耦接到所述整流器，並且操作以進行同步整流；以及控制電路，所述控制電路耦接到所述電晶體，並且經配置以回應於所述整流器的導通而導通所述電晶體，所述控制電路包括：第一比較器，用於根據電壓感測信號產生啟用信號；同步整流重置電路，用於根據電壓感測信號產生切換週期信號，根據所述整流器的導通週期產生導通週期信號，回應於所述切換週期信號產生第一停用信號，回應於所述導通週期信號產生第二停用信號，並且根據所述第一停用信號和所述第二停用信號產生停用信號；以及觸發器和及閘，其中所述停用信號耦接到所述觸發器的復位端，所述觸發器是通過所述啟用信號設置的，所述觸發器的輸出和所述啟用信號連接到所述及閘以產生用於控制所述電晶體的控制信號，其中所述電壓感測信號與所述變壓器的切換波形有關；所述第一停用信號的導通週期比所述切換週期信號的導通週期為短；所述第二停用信號的導通週期比所述導通週期信號的導通週期為短；所述導通週期信號的所述導通週期不與所述第一停用信號的所述導通週期和所述第二停用信號的所述導通週期重疊。 A power converter comprising: a transformer; a rectifier; a transistor coupled to the rectifier and operative to perform synchronous rectification; and a control circuit coupled to the transistor and configured to be responsive to conduction of the rectifier And turning on the transistor, the control circuit includes: a first comparator for generating an enable signal according to the voltage sensing signal; and a synchronous rectification reset circuit for generating a switching period signal according to the voltage sensing signal, according to the An on period of the rectifier generates an on period signal, generates a first disable signal in response to the switching period signal, generates a second disable signal in response to the on period signal, and according to the first disable signal and the a second disable signal generating a disable signal; and a flip-flop and a gate, wherein the disable signal is coupled to a reset terminal of the flip-flop, the flip-flop being set by the enable signal, the flip-flop And an enable signal coupled to the AND gate to generate a control signal for controlling the transistor, wherein the voltage sensing signal and the change The switching waveform of the first deactivation signal is shorter than the on period of the switching period signal; the on period of the second deactivation signal is shorter than the on period of the on period signal; The on period of the on period signal does not overlap with the on period of the first disable signal and the on period of the second disable signal. 如申請專利範圍第15項所述的功率轉換器，其中所述同步整流重置電路包括： 第二比較器，用於根據所述電壓感測信號的週期和高電平閾值產生所述切換週期信號；導通週期鎖定電路，用於根據所述整流器的所述導通週期和所述控制信號產生所述導通週期信號，並且回應於所述導通週期信號產生第二停用信號；切換週期鎖定電路，用於回應於所述切換週期信號產生第一停用信號；以及或閘，用於產生所述啟用信號以回應於所述第一停用信號和所述第二停用信號而截止所述電晶體。 The power converter of claim 15, wherein the synchronous rectification reset circuit comprises: a second comparator, configured to generate the switching period signal according to a period of the voltage sensing signal and a high level threshold; and an on period locking circuit configured to generate according to the on period of the rectifier and the control signal Transducing a periodic signal, and generating a second disable signal in response to the turn-on period signal; switching a period lock circuit for generating a first disable signal in response to the switching period signal; and or a gate for generating The enable signal turns off the transistor in response to the first disable signal and the second disable signal. 一種功率轉換器，包括：變壓器；整流器；電晶體，所述電晶體耦接到所述整流器，並且所述整流器操作以進行同步整流；以及控制電路，所述控制電路耦接到所述電晶體，所述控制電路回應於所述整流器的導通而導通所述電晶體；回應於變壓器的切換波形的導通週期截止所述電晶體；並且回應於所述整流器的導通週期截止所述電晶體，其中所述電晶體的導通週期比所述變壓器的所述切換波形的所述導通週期為短；所述電晶體的所述導通週期比所述整流器的所述導通週期為短。 A power converter comprising: a transformer; a rectifier; a transistor coupled to the rectifier, and the rectifier is operative to perform synchronous rectification; and a control circuit coupled to the transistor And the control circuit turns on the transistor in response to conduction of the rectifier; turns off the transistor in response to an on period of a switching waveform of the transformer; and turns off the transistor in response to an on period of the rectifier, wherein The on period of the transistor is shorter than the on period of the switching waveform of the transformer; the on period of the transistor is shorter than the on period of the rectifier. 一種功率轉換器的控制電路，用於控制所述功率轉換器 的同步整流，所述控制電路包括：第一比較器，用於根據電壓感測信號產生啟用信號；同步整流重置電路，用於根據電壓感測信號產生切換週期信號，根據所述整流器的導通週期產生導通週期信號，回應於所述切換週期信號產生第一停用信號，回應於所述導通週期信號產生第二停用信號，並且根據所述第一停用信號和所述第二停用信號產生停用信號；以及觸發器和及閘，其中所述停用信號耦接到所述觸發器的復位端，所述觸發器是通過所述啟用信號設置的，所述觸發器的輸出和所述啟用信號連接到所述及閘以產生用於控制所述電晶體的控制信號，其中所述電壓感測信號與所述變壓器的切換波形有關；所述第一停用信號的導通週期比所述切換週期信號的導通週期為短；所述第二停用信號的導通週期比所述導通週期信號的導通週期為短；所述導通週期信號的所述導通週期不與所述第一停用信號的所述導通週期和所述第二停用信號的所述導通週期重疊。 A control circuit of a power converter for controlling the power converter Synchronous rectification, the control circuit includes: a first comparator for generating an enable signal according to the voltage sensing signal; and a synchronous rectification reset circuit for generating a switching period signal according to the voltage sensing signal, according to the conducting of the rectifier Generating a turn-on period signal, generating a first disable signal in response to the switching period signal, generating a second disable signal in response to the turn-on period signal, and according to the first disable signal and the second disable signal a signal generating a disable signal; and a flip-flop and a gate, wherein the disable signal is coupled to a reset terminal of the flip-flop, the flip-flop being set by the enable signal, an output of the flip-flop The enable signal is coupled to the AND gate to generate a control signal for controlling the transistor, wherein the voltage sense signal is related to a switching waveform of the transformer; a turn-on period ratio of the first disable signal The on period of the switching period signal is short; the on period of the second deactivation signal is shorter than the on period of the on period signal; the on period The number of on-period does not overlap with the conduction period of the first turn-on period of the disable signal and the second signal is deactivated. 如申請專利範圍第18項所述的控制電路，其中所述同步整流重置電路包括：第二比較器，用於根據所述電壓感測信號的週期和高電平閾值產生所述切換週期信號；導通週期鎖定電路，用於根據所述整流器的所述導通週期和所述控制信號產生所述導通週期信號，並且回應於所述導通週期 信號產生第二停用信號；切換週期鎖定電路，用於回應於所述切換週期信號產生第一停用信號；以及或閘，用於產生所述啟用信號以回應於所述第一停用信號和所述第二停用信號以截止所述功率轉換器的電晶體。 The control circuit of claim 18, wherein the synchronous rectification reset circuit comprises: a second comparator, configured to generate the switching period signal according to a period of the voltage sensing signal and a high level threshold a turn-on period locking circuit for generating the turn-on period signal according to the turn-on period of the rectifier and the control signal, and responsive to the turn-on period The signal generates a second disable signal; a switching period lock circuit for generating a first disable signal in response to the switching period signal; and an OR gate for generating the enable signal in response to the first disable signal And the second disable signal to turn off the transistor of the power converter. 如申請專利範圍第19項所述的控制電路，其中所述切換週期鎖定電路包括：第一脈衝發生器、第二脈衝發生器、第三脈衝發生器、功率電晶體、開關、電流源、電容器，以及比較器，其中所述電流源耦接到所述功率電晶體、電容器和所述開關，所述電流源被應用於給所述電容器充電；所述第二脈衝發生器經配置以通過反相器接收所述第一脈衝發生器的輸出，並且所述第二脈衝發生器的輸出耦接到所述功率電晶體的控制節點，其中所述功率電晶體的第一節點耦接到所述電流源；所述開關經配置以對由所述第一脈衝發生器的輸出控制的所述電容器的電壓進行取樣；其中所述第一脈衝發生器接收所述切換週期信號以產生脈衝信號，所述第一脈衝發生器的輸出經配置以導通所述開關用於回應於所述切換週期信號的上升緣進行取樣；並且所述比較器經配置以在所述電容器的電壓電平高於衰減信號時通過所述第三脈衝發生器產生所述第一停用信號。 The control circuit of claim 19, wherein the switching period locking circuit comprises: a first pulse generator, a second pulse generator, a third pulse generator, a power transistor, a switch, a current source, and a capacitor And a comparator, wherein the current source is coupled to the power transistor, a capacitor, and the switch, the current source being applied to charge the capacitor; the second pulse generator configured to pass an inverse a phaser receives an output of the first pulse generator, and an output of the second pulse generator is coupled to a control node of the power transistor, wherein a first node of the power transistor is coupled to the a current source; the switch configured to sample a voltage of the capacitor controlled by an output of the first pulse generator; wherein the first pulse generator receives the switching period signal to generate a pulse signal, An output of the first pulse generator is configured to turn on the switch for sampling in response to a rising edge of the switching period signal; and the comparator is configured to Voltage level of the capacitor, said first deactivation signal generated by the pulse generator is higher than said third attenuated signal. 如申請專利範圍第19項所述的控制電路，其中所述導通週期鎖定電路包括：觸發器，用於根據所述控制信號的上升緣產生導通週期信號；功率電晶體、第一電容器和第二電容器、開關；電流源，所述電流源耦接到所述功率電晶體的第一節點、第一電容器和所述開關，其中所述開關經配置以將所述第一電容器的電壓取樣給由所述第一脈衝發生器的輸出控制的所述第二電容器；所述第一脈衝發生器的輸出經配置以導通所述開關用於回應於所述導通週期信號的上升緣進行取樣；並且在取樣之後通過所述第二脈衝發生器和所述功率電晶體使所述第一電容器放電；所述第二脈衝發生器的輸出耦接到所述功率電晶體的控制節點；以及比較器，用於通過所述第三脈衝發生器產生所述第二停用信號。 The control circuit of claim 19, wherein the on-period locking circuit comprises: a flip-flop for generating an on-period signal according to a rising edge of the control signal; a power transistor, a first capacitor, and a second a capacitor, a switch, a current source coupled to the first node of the power transistor, the first capacitor, and the switch, wherein the switch is configured to sample a voltage of the first capacitor The second capacitor of the first pulse generator is controlled; the output of the first pulse generator is configured to turn on the switch for sampling in response to a rising edge of the on-period signal; Discharging the first capacitor by the second pulse generator and the power transistor after sampling; the output of the second pulse generator is coupled to a control node of the power transistor; and a comparator The second disable signal is generated by the third pulse generator.
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