TW201535649A - Semiconductor package and semiconductor structure thereof - Google Patents
Semiconductor package and semiconductor structure thereof Download PDFInfo
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- TW201535649A TW201535649A TW103107387A TW103107387A TW201535649A TW 201535649 A TW201535649 A TW 201535649A TW 103107387 A TW103107387 A TW 103107387A TW 103107387 A TW103107387 A TW 103107387A TW 201535649 A TW201535649 A TW 201535649A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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Abstract
Description
本發明係有關一種三維(3D)晶片堆疊技術，尤指一種堆疊元件式半導體封裝件及其半導體結構。 The present invention relates to a three-dimensional (3D) wafer stacking technique, and more particularly to a stacked component semiconductor package and a semiconductor structure thereof.
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態。覆晶技術由於具有縮小晶片封裝面積及縮短訊號傳輸路徑等優點，目前已經廣泛應用於晶片封裝領域，例如晶片尺寸構裝(Chip Scale Package,CSP)、晶片直接貼附封裝(Direct Chip Attached,DCA)以及多晶片模組封裝(Multi-Chip Module,MCM)等型態的封裝模組，均可以利用覆晶技術而達到封裝之目的。 With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types. Flip chip technology has been widely used in chip packaging fields due to its advantages of shrinking chip package area and shortening signal transmission path, such as Chip Scale Package (CSP) and Direct Chip Attached (DCA). ), as well as multi-chip module (MCM) and other types of package modules, can use the flip chip technology to achieve the purpose of packaging.
由於電子產品之微小化以及高運作速度需求的增加，而為提高單一半導體封裝結構之性能與容量以符合電子產品小型化之需求，半導體封裝件採用多晶片模組化(Multichip Module)之技術乃成一趨勢，俾藉此將兩個或兩個以上之半導體晶片組合在單一封裝結構中，以縮減電子產品整體電路結構體積，並提昇電性功能。亦即，多晶片 封裝結構可藉由將兩個或兩個以上之晶片組合在單一封裝結構中，來使系統運作速度之限制最小化。此外，多晶片封裝結構可減少晶片間連接線路之長度而降低訊號延遲以及存取時間。 Due to the miniaturization of electronic products and the increasing demand for high operating speeds, in order to improve the performance and capacity of a single semiconductor package structure to meet the needs of miniaturization of electronic products, the technology of multi-chip modules in semiconductor packages is In this way, two or more semiconductor wafers are combined in a single package structure to reduce the overall circuit structure volume of the electronic product and improve the electrical function. That is, multi-chip The package structure minimizes the operating speed of the system by combining two or more wafers in a single package. In addition, the multi-chip package structure reduces the length of the connection line between the chips and reduces signal delay and access time.
常見的多晶片封裝結構係為採用並排式(side-by-side)多晶片封裝結構，其係將兩個以上之晶片彼此並排地安裝於一共同基板之主要安裝面。 A common multi-chip package structure is a side-by-side multi-chip package structure in which two or more wafers are mounted side by side on a main mounting surface of a common substrate.
如第1圖所示，一半導體基板10具有相對之第一表面10a與第二表面10b、及複數連通該第一表面10a及第二表面10b之導電穿孔100，於該第一表面10a與該導電穿孔100上形成至少一線路重佈層(Redistribution layer,RDL)104，且該線路重佈層104電性連接該導電穿孔100，而最外層之線路重佈層104具有複數第一電性連接墊101與複數第二電性連接墊102。再者，一第一半導體元件11藉由複數第一導電元件110以覆晶方式設於該些第一電性連接墊101上，且一第二半導體元件12藉由複數第二導電元件120以覆晶方式設於該些第二電性連接墊102上，使該第一半導體元件11與該第二半導體元件12間隔地並排。又，形成底膠14於該半導體基板10之第一表面10a上，以包覆該第一及第二導電元件110,120。 As shown in FIG. 1 , a semiconductor substrate 10 has a first surface 10a and a second surface 10b opposite to each other, and a plurality of conductive vias 100 communicating with the first surface 10a and the second surface 10b, the first surface 10a and the first surface 10a At least one redistribution layer (RDL) 104 is formed on the conductive via 100, and the circuit redistribution layer 104 is electrically connected to the conductive via 100, and the outermost circuit redistribution layer 104 has a plurality of first electrical connections. Pad 101 and a plurality of second electrical connection pads 102. Furthermore, a first semiconductor element 11 is flip-chip mounted on the first electrical connection pads 101 by a plurality of first conductive elements 110, and a second semiconductor element 12 is provided by a plurality of second conductive elements 120. The flip chip is disposed on the second electrical connection pads 102 such that the first semiconductor element 11 and the second semiconductor element 12 are spaced apart from each other. Further, a primer 14 is formed on the first surface 10a of the semiconductor substrate 10 to cover the first and second conductive members 110, 120.
惟，習知半導體封裝件1中，若欲達成現今終端產品的需求，需並排更多半導體元件，該半導體基板10之面積將隨之增加，致使封裝成本過高，且該半導體封裝件1之尺寸過大，因而無法符合輕、薄、短、小之需求。 However, in the conventional semiconductor package 1, if the demand for the current end product is to be achieved, more semiconductor components need to be arranged side by side, the area of the semiconductor substrate 10 will increase, resulting in an excessively high package cost, and the semiconductor package 1 The size is too large to meet the requirements of light, thin, short, and small.
因此，如何克服習知技術中之問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems in the prior art has become a problem that is currently being solved.
鑑於上述習知技術之缺失，本發明提供一種半導體結構，係包括：半導體基板，係具有複數第一電性連接墊與複數第二電性連接墊；複數第一導電元件，係分別設於該些第一電性連接墊上；以及複數第二導電元件，係分別設於該些第二電性連接墊上，且該第二導電元件之高度大於該第一導電元件之高度。 In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor structure comprising: a semiconductor substrate having a plurality of first electrical connection pads and a plurality of second electrical connection pads; and a plurality of first conductive elements respectively disposed on the The plurality of second conductive elements are respectively disposed on the second electrical connection pads, and the height of the second conductive elements is greater than the height of the first conductive elements.
本發明復提供一種半導體封裝件，係包括：半導體基板，係具有複數第一電性連接墊與複數第二電性連接墊；第一半導體元件，係設於該些第一電性連接墊上，且電性連接該些第一電性連接墊；以及第二半導體元件，係設於該些第二電性連接墊上，且電性連接該些第二電性連接墊，該第二半導體元件並間隔地位於該第一半導體元件之上。 The present invention further provides a semiconductor package, comprising: a semiconductor substrate having a plurality of first electrical connection pads and a plurality of second electrical connection pads; the first semiconductor component being disposed on the first electrical connection pads, And electrically connecting the first electrical connection pads; and the second semiconductor component is disposed on the second electrical connection pads, and electrically connected to the second electrical connection pads, the second semiconductor components Located above the first semiconductor component at intervals.
前述之半導體封裝件中，該第一半導體元件係藉由複數導電元件設於該些第一電性連接墊上。 In the above semiconductor package, the first semiconductor component is provided on the first electrical connection pads by a plurality of conductive components.
前述之半導體封裝件中，該第二半導體元件係藉由複數導電元件設於該些第二電性連接墊上。 In the above semiconductor package, the second semiconductor component is disposed on the second electrical connection pads by a plurality of conductive components.
前述之半導體封裝件中，該第一半導體元件係藉由複數第一導電元件設於該些第一電性連接墊上，且該第二半導體元件係藉由複數第二導電元件設於該些第二電性連接墊上，該第二導電元件之高度大於該第一導電元件之高度。 In the above semiconductor package, the first semiconductor component is disposed on the first electrical connection pads by a plurality of first conductive components, and the second semiconductor component is disposed on the first conductive component by the plurality of second conductive components. The height of the second conductive element is greater than the height of the first conductive element.
前述之半導體封裝件中，該第二半導體元件之垂直投影面積大於該第一半導體元件之垂直投影面積。 In the above semiconductor package, the vertical projected area of the second semiconductor element is larger than the vertical projected area of the first semiconductor element.
前述之半導體封裝件中，復包括封裝材，係設於該半導體基板上，以包覆該第一及第二半導體元件。 In the above semiconductor package, a package material is included on the semiconductor substrate to cover the first and second semiconductor elements.
前述之半導體封裝件及其半導體結構中，該些第二電性連接墊係圍繞於該些第一電性連接墊之外圍。 In the foregoing semiconductor package and the semiconductor structure thereof, the second electrical connection pads surround the periphery of the first electrical connection pads.
前述之半導體封裝件及其半導體結構中，該第二導電元件之寬度大於該第一導電元件之寬度。 In the foregoing semiconductor package and semiconductor structure thereof, the width of the second conductive element is greater than the width of the first conductive element.
另外，前述之半導體封裝件及其半導體結構中，該半導體基板上復具有複數第三電性連接墊，且復包括複數第三導電元件，係設於該些第三電性連接墊上，例如，該第三導電元件之高度係大於第二導電元件之高度。因此，至少一第三半導體元件設於該些第三電性連接墊上並電性連接該些第三電性連接墊，且該第三半導體元件間隔地位於該第二半導體元件之上，又當該第三半導體元件係為複數時，該些第三半導體元件係相互間隔地堆疊於彼此之上。 In addition, in the foregoing semiconductor package and the semiconductor structure thereof, the semiconductor substrate has a plurality of third electrical connection pads, and the plurality of third conductive elements are disposed on the third electrical connection pads, for example, The height of the third conductive element is greater than the height of the second conductive element. Therefore, at least one third semiconductor component is disposed on the third electrical connection pads and electrically connected to the third electrical connection pads, and the third semiconductor component is spaced above the second semiconductor component, and When the third semiconductor element is plural, the third semiconductor elements are stacked on each other at intervals.
由上可知，本發明半導體封裝件及其半導體結構，係藉由垂直式之堆疊方法以增加半導體元件之數量，以堆疊不同大小、不同功能之半導體元件於另一半導體元件上，使該半導體基板之面積無需增加，故相較於習知技術之並排式，本發明不僅能降低封裝成本，且能縮小該半導體封裝件之尺寸，以符合輕、薄、短、小之需求。 As can be seen from the above, the semiconductor package of the present invention and the semiconductor structure thereof are stacked by a vertical stacking method to increase the number of semiconductor components to stack semiconductor components of different sizes and functions on another semiconductor component. The area does not need to be increased, so the invention can not only reduce the packaging cost, but also reduce the size of the semiconductor package to meet the requirements of light, thin, short, and small, compared with the side-by-side type of the prior art.
1、3、3’、3”‧‧‧半導體封裝件 1, 3, 3', 3" ‧ ‧ semiconductor packages
10、20‧‧‧半導體基板 10, 20‧‧‧ semiconductor substrate
10a、20a‧‧‧第一表面 10a, 20a‧‧‧ first surface
10b、20b‧‧‧第二表面 10b, 20b‧‧‧ second surface
100、200‧‧‧導電穿孔 100,200‧‧‧Electrical perforation
101、201‧‧‧第一電性連接墊 101, 201‧‧‧ first electrical connection pad
102、202‧‧‧第二電性連接墊 102, 202‧‧‧Second electrical connection pads
104、204‧‧‧線路重佈層 104, 204‧‧‧Line redistribution
11、21‧‧‧第一半導體元件 11, 21‧‧‧ first semiconductor components
110、210、205a‧‧‧第一導電元件 110, 210, 205a‧‧‧ first conductive element
12、22‧‧‧第二半導體元件 12, 22‧‧‧ second semiconductor component
120、220、205b‧‧‧第二導電元件 120, 220, 205b‧‧‧ second conductive element
14‧‧‧底膠 14‧‧‧Bottom glue
2、2’、2”‧‧‧半導體結構 2, 2', 2" ‧ ‧ semiconductor structure
203‧‧‧第三電性連接墊 203‧‧‧The third electrical connection pad
23、23’‧‧‧第三半導體元件 23, 23'‧‧‧ Third semiconductor component
230、205c‧‧‧第三導電元件 230, 205c‧‧‧ third conductive element
24‧‧‧封裝材 24‧‧‧Package
305‧‧‧銅柱 305‧‧‧Bronze Column
A、B、C‧‧‧垂直投影面積 A, B, C‧‧‧ vertical projection area
D、W、T‧‧‧寬度 D, W, T‧‧‧ width
H、h、L、R、r、t‧‧‧高度 H, h, L, R, r, t‧‧‧ height
第1圖係為習知半導體結構之剖視示意圖； 第2A至2C圖係為本發明半導體封裝件之製法之第一實施例的剖視示意圖；以及第3A至3C圖係為本發明半導體封裝件之製法之第二實施例的剖視示意圖；其中，第3B’圖係為第3B圖之另一態樣，第3C’圖係為第3C圖之另一態樣。 Figure 1 is a schematic cross-sectional view of a conventional semiconductor structure; 2A to 2C are schematic cross-sectional views showing a first embodiment of a method of fabricating a semiconductor package of the present invention; and FIGS. 3A to 3C are cross-sectional views showing a second embodiment of a method of fabricating a semiconductor package of the present invention; The 3B' diagram is another aspect of the 3B diagram, and the 3C' diagram is another aspect of the 3C diagram.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、“第三”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second", "third" and "one" are used in the description for convenience of description, and are not intended to limit the present invention. The scope of the invention, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.
第2A至2C圖係為本發明半導體封裝件3之製法之第一實施例之剖視示意圖。 2A to 2C are schematic cross-sectional views showing a first embodiment of the method of fabricating the semiconductor package 3 of the present invention.
如第2A圖所示，提供一半導體結構2，其具有一相對之第一表面20a及第二表面20b之半導體基板20，該半導 體基板20之第一表面20a上具有複數第一電性連接墊201與複數第二電性連接墊202，且形成預銲錫材之第一導電元件205a與第二導電元件205b於該些第一電性連接墊201與第二電性連接墊202上。 As shown in FIG. 2A, a semiconductor structure 2 having a semiconductor substrate 20 opposite to the first surface 20a and the second surface 20b is provided. The first surface 20a of the body substrate 20 has a plurality of first electrical connection pads 201 and a plurality of second electrical connection pads 202, and a first conductive element 205a and a second conductive element 205b of the pre-solder material are formed on the first surface The electrical connection pad 201 is connected to the second electrical connection pad 202.
於本實施例中，該半導體基板20係具有複數連通該第一表面20a及第二表面20b之導電穿孔200。例如，該半導體基板20係為矽基板時，該導電穿孔200係為導電矽穿孔(Through-silicon via,TSV)。 In this embodiment, the semiconductor substrate 20 has a plurality of conductive vias 200 that communicate with the first surface 20a and the second surface 20b. For example, when the semiconductor substrate 20 is a germanium substrate, the conductive via 200 is a through-silicon via (TSV).
再者，於該第一表面20a與該導電穿孔200上形成至少一線路重佈層(Redistribution layer,RDL)204，且該線路重佈層204電性連接該導電穿孔200，而最外層之線路重佈層204具有該些第一電性連接墊201與第二電性連接墊202。 Furthermore, at least one redistribution layer (RDL) 204 is formed on the first surface 20a and the conductive via 200, and the circuit redistribution layer 204 is electrically connected to the conductive via 200, and the outermost layer is connected. The redistribution layer 204 has the first electrical connection pads 201 and the second electrical connection pads 202.
又，該些第二電性連接墊202係圍繞於該些第一電性連接墊201之外圍。 Moreover, the second electrical connection pads 202 surround the periphery of the first electrical connection pads 201.
另外，該第二導電元件205b之高度h大於該第一導電元件205a之高度t。 In addition, the height h of the second conductive element 205b is greater than the height t of the first conductive element 205a.
如第2B圖所示，分別設置一第一半導體元件21與一第二半導體元件22於該些第一電性連接墊201與第二電性連接墊202上，且該第一半導體元件21電性連接該些第一電性連接墊201，該第二半導體元件22電性連接該些第二電性連接墊202。 As shown in FIG. 2B, a first semiconductor component 21 and a second semiconductor component 22 are respectively disposed on the first electrical connection pads 201 and the second electrical connection pads 202, and the first semiconductor component 21 is electrically The first electrical connection pads 201 are electrically connected to the second electrical connection pads 202.
於本實施例中，該第一半導體元件21係藉由複數另一第一導電元件210(包含該第一導電元件205a)以覆晶方 式設於該些第一電性連接墊201上，且該第二半導體元件22係藉由複數另一第二導電元件220(包含該第二導電元件205b)以覆晶方式設於該些第二電性連接墊202上。 In this embodiment, the first semiconductor component 21 is covered by a plurality of other first conductive components 210 (including the first conductive component 205a). The second semiconductor component 22 is provided on the first electrical connection pads 201, and the second semiconductor component 22 is provided in the flip chip by the plurality of other second conductive components 220 (including the second conductive component 205b). Two electrical connection pads 202.
再者，該第二導電元件220之高度H大於該第一導電元件210之高度L，使該第二半導體元件22間隔地堆疊於該第一半導體元件21之上。 Moreover, the height H of the second conductive element 220 is greater than the height L of the first conductive element 210, so that the second semiconductor element 22 is stacked on the first semiconductor element 21 at intervals.
又，該第二導電元件220之寬度D大於該第一導電元件210之寬度W。 Moreover, the width D of the second conductive element 220 is greater than the width W of the first conductive element 210.
另外，該第二半導體元件22之垂直投影面積B大於該第一半導體元件21之垂直投影面積A。 In addition, the vertical projected area B of the second semiconductor element 22 is larger than the vertical projected area A of the first semiconductor element 21.
如第2C圖所示，形成封裝材24於該半導體基板20之第一表面20a上，以包覆該第一及第二半導體元件21,22。 As shown in FIG. 2C, a package member 24 is formed on the first surface 20a of the semiconductor substrate 20 to cover the first and second semiconductor elements 21, 22.
第3A至3C圖係為本發明半導體封裝件3’之製法之第二實施例之剖視示意圖。本實施例與第一實施例之差異在於增設至少一第三半導體元件23。 3A to 3C are schematic cross-sectional views showing a second embodiment of the method of fabricating the semiconductor package 3' of the present invention. The difference between this embodiment and the first embodiment is that at least one third semiconductor element 23 is added.
如第3A圖所示，提供一半導體結構2’，其半導體基板20之第一表面20a上復具有複數第三電性連接墊203。 As shown in Fig. 3A, a semiconductor structure 2' is provided having a plurality of third electrical connection pads 203 on the first surface 20a of the semiconductor substrate 20.
於本實施例中，該些第三電性連接墊203係圍繞於該些第二電性連接墊202之外圍。 In the embodiment, the third electrical connection pads 203 surround the periphery of the second electrical connection pads 202.
再者，亦形成如預銲錫材之第三導電元件205c於該些第三電性連接墊203上，且該第三導電元件205c之高度r係大於該第二導電元件205b之高度h。 Moreover, a third conductive element 205c such as a pre-solder material is formed on the third electrical connection pads 203, and a height r of the third conductive element 205c is greater than a height h of the second conductive element 205b.
如第3B圖所示，分別設置一第一半導體元件21、一第二半導體元件22與一第三半導體元件23於該些第一電 性連接墊201、第二電性連接墊202與第三電性連接墊203上，且該第一半導體元件21電性連接該些第一電性連接墊201，該第二半導體元件22電性連接該些第二電性連接墊202，該第三半導體元件23電性連接該些第三電性連接墊203。 As shown in FIG. 3B, a first semiconductor element 21, a second semiconductor element 22 and a third semiconductor element 23 are respectively disposed on the first electrodes. The first connecting device 201 is electrically connected to the first electrical connecting pads 201, and the second semiconductor device 22 is electrically connected to the first electrical connecting pads 201. The second electrical connection pads 202 are connected to the third electrical connection pads 203.
於本實施例中，該第三半導體元件23係藉由複數另一第三導電元件230(包含該第三導電元件205c)以覆晶方式設於該些第三電性連接墊203上。 In this embodiment, the third semiconductor component 23 is provided on the third electrical connection pads 203 in a flip chip manner by a plurality of other third conductive components 230 (including the third conductive component 205c).
再者，該第三導電元件230之高度R大於該第二導電元件220之高度H，使該第三半導體元件23間隔地位於該第二半導體元件22之上。 Moreover, the height R of the third conductive element 230 is greater than the height H of the second conductive element 220 such that the third semiconductor element 23 is spaced above the second semiconductor element 22.
又，該第三導電元件230之寬度T大於該第二導電元件220之寬度D，且該第三半導體元件23之垂直投影面積C大於該第二半導體元件22之垂直投影面積B。 Moreover, the width T of the third conductive element 230 is greater than the width D of the second conductive element 220, and the vertical projected area C of the third semiconductor element 23 is greater than the vertical projected area B of the second semiconductor element 22.
如第3C圖所示，形成封裝材24於該半導體基板20之第一表面20a上，以包覆該第一、第二及第三半導體元件21,22,23。 As shown in FIG. 3C, a package member 24 is formed on the first surface 20a of the semiconductor substrate 20 to cover the first, second, and third semiconductor elements 21, 22, 23.
再者，如第3B’圖所示，若該半導體封件3”具有複數第三半導體元件23,23’時(圖中之點狀表示省略之第三半導體元件)，該些第三半導體元件23,23’係相互間隔地堆疊於彼此之上，且該些第三半導體元件23,23’之垂直投影面積係由下往上遞增，如上層之第三半導體元件23’之垂直投影面積大於下層之第三半導體元件23之垂直投影面積C。 Further, as shown in FIG. 3B', when the semiconductor package 3" has a plurality of third semiconductor elements 23, 23' (the dotted dots in the figure indicate the omitted third semiconductor elements), the third semiconductor elements 23, 23' are stacked on each other at intervals, and the vertical projection areas of the third semiconductor elements 23, 23' are increased from bottom to top, and the vertical projection area of the third semiconductor element 23' of the upper layer is greater than The vertical projected area C of the lower third semiconductor element 23.
本發明之半導體封裝件3,3’,3”及其半導體結構2,2’，係藉由垂直式之堆疊方法以增加半導體元件之數量，且其堆疊的方式係依半導體元件之垂直投影面積由下至上依序遞增，以堆疊不同大小、不同功能之半導體元件於另一半導體元件上，使該半導體基板20之面積無需增加，故本發明不僅能降低封裝成本，且能縮小該半導體封裝件3,3’,3”之尺寸，以符合輕、薄、短、小之需求。 The semiconductor package 3, 3', 3" and its semiconductor structure 2, 2' of the present invention are stacked by a vertical method to increase the number of semiconductor elements, and the manner of stacking depends on the vertical projected area of the semiconductor element. The semiconductor element of different sizes and different functions is stacked on another semiconductor element in order to increase the area of the semiconductor substrate 20 without increasing the area of the semiconductor substrate 20, so that the invention can not only reduce the packaging cost, but also reduce the semiconductor package. 3, 3', 3" size to meet the needs of light, thin, short and small.
本發明提供一種半導體封裝件3,3’,3”，係包括：一半導體基板20、一第一半導體元件21、以及一第二半導體元件22。 The present invention provides a semiconductor package 3, 3', 3" comprising a semiconductor substrate 20, a first semiconductor component 21, and a second semiconductor component 22.
所述之半導體基板20係具有複數第一電性連接墊201與複數第二電性連接墊202，且該些第二電性連接墊202係圍繞於該些第一電性連接墊201之外圍。 The semiconductor substrate 20 has a plurality of first electrical connection pads 201 and a plurality of second electrical connection pads 202, and the second electrical connection pads 202 surround the periphery of the first electrical connection pads 201. .
所述之第一半導體元件21係設於該些第一電性連接墊201上，且電性連接該些第一電性連接墊201。例如，該第一半導體元件21係藉由複數第一導電元件210設於該些第一電性連接墊201上。 The first semiconductor component 21 is disposed on the first electrical connection pads 201 and electrically connected to the first electrical connection pads 201. For example, the first semiconductor element 21 is disposed on the first electrical connection pads 201 by a plurality of first conductive elements 210.
所述之第二半導體元件22係設於該些第二電性連接墊202上，且電性連接該些第二電性連接墊202，該第二半導體元件22並間隔地位於該第一半導體元件21之上。例如，該第二半導體元件22係藉由複數第二導電元件220設於該些第二電性連接墊202上，且該第二導電元件220之高度H大於該第一導電元件210之高度L。 The second semiconductor component 22 is disposed on the second electrical connection pads 202 and electrically connected to the second electrical connection pads 202. The second semiconductor component 22 is spaced apart from the first semiconductor. Above element 21. For example, the second semiconductor component 22 is disposed on the second electrical connection pads 202 by the plurality of second conductive components 220, and the height H of the second conductive component 220 is greater than the height L of the first conductive component 210. .
於一實施例中，該第二導電元件220之寬度D大於該 第一導電元件210之寬度W。 In an embodiment, the width D of the second conductive element 220 is greater than the The width W of the first conductive element 210.
於一實施例中，該第二半導體元件22之垂直投影面積B大於該第一半導體元件21之垂直投影面積A。 In one embodiment, the vertical projected area B of the second semiconductor component 22 is greater than the vertical projected area A of the first semiconductor component 21.
於一實施例中，該半導體基板20復具有複數第三電性連接墊203，且一第三半導體元件23設於該些第三電性連接墊203上並電性連接該些第三電性連接墊203，又該第三半導體元件23間隔地位於該第二半導體元件22之上。例如，該至少一第三半導體元件23係藉由複數第三導電元件230設於該些第三電性連接墊上。 In one embodiment, the semiconductor substrate 20 has a plurality of third electrical connection pads 203, and a third semiconductor component 23 is disposed on the third electrical connection pads 203 and electrically connected to the third electrical interfaces. The connection pad 203 is further disposed on the second semiconductor element 22 at intervals. For example, the at least one third semiconductor component 23 is disposed on the third electrical connection pads by the plurality of third conductive components 230.
於一實施例中，該半導體結構2”具有複數該第三半導體元件23,23’，且該些第三半導體元件23,23’係相互間隔地堆疊於彼此之上。 In one embodiment, the semiconductor structure 2" has a plurality of the third semiconductor elements 23, 23', and the third semiconductor elements 23, 23' are stacked on top of one another.
於一實施例中，所述之半導體封裝件3,3’,3”復包括封裝材24，係設於該半導體基板20上，以包覆該第一及第二半導體元件21,22。又於一實施例中，該封裝材24復包覆該第三半導體元件23,23’。 In one embodiment, the semiconductor package 3, 3', 3" includes a package 24, which is disposed on the semiconductor substrate 20 to cover the first and second semiconductor elements 21, 22. In one embodiment, the package 24 overlies the third semiconductor component 23, 23'.
於上述各實施例中，所述之半導體元件(如第一至第三半導體元件21,22,23,23’)係為晶片，例如，功能性晶片(如邏輯、記憶體、中央處理器等)、或無功能性晶片(如具有TSV晶片，其僅供電性傳輸用)，但不限於該些種類。 In the above embodiments, the semiconductor components (such as the first to third semiconductor components 21, 22, 23, 23') are wafers, for example, functional wafers (such as logic, memory, central processing unit, etc.). ), or a non-functional wafer (such as a TSV chip, which is only for power transmission), but is not limited to these types.
再者，所述之電性連接墊(如第一至第三電性連接墊201,202,203)之尺寸亦可設計為不同大小，且可依需求令該導電元件之高低不同或直徑不同。 Furthermore, the size of the electrical connection pads (such as the first to third electrical connection pads 201, 202, 203) can also be designed to different sizes, and the height or the diameter of the conductive elements can be different according to requirements.
又，所述之導電元件(如第一至第三導電元件 205a,205b,205c,210,220,230)可為銲錫球(solder ball)。或者，該導電元件可為具銅柱(Cu pillar)之銲錫凸塊(solder bump)，以利於後續之堆疊製程，如第3A及3B圖所示之第三導電元件205c,230；具體地，先於該第三電性連接墊203上形成銅柱305，再於該銅柱305上形成預銲錫材205，以構成該第三導電元件205c。 Also, the conductive element (such as the first to third conductive elements) 205a, 205b, 205c, 210, 220, 230) may be solder balls. Alternatively, the conductive element may be a solder bump with a copper pillar to facilitate a subsequent stacking process, such as the third conductive elements 205c, 230 shown in FIGS. 3A and 3B; specifically, A copper pillar 305 is formed on the third electrical connection pad 203, and a pre-solder material 205 is formed on the copper pillar 305 to form the third conductive component 205c.
另外，該半導體基板20之第二表面20b上可依需求作設計，例如，形成RDL、於導電通孔200上植設導電凸塊等。 In addition, the second surface 20b of the semiconductor substrate 20 can be designed according to requirements, for example, RDL is formed, conductive bumps are implanted on the conductive vias 200, and the like.
綜上所述，本發明半導體封裝件及其半導體結構，係藉由垂直式之堆疊方法以增加半導體元件之數量，使該半導體基板之面積無需增加，不僅能降低封裝成本，且能縮小該半導體封裝件之尺寸，以符合輕、薄、短、小之需求。 In summary, the semiconductor package of the present invention and the semiconductor structure thereof are stacked by a vertical method to increase the number of semiconductor components, so that the area of the semiconductor substrate does not need to be increased, thereby not only reducing the package cost, but also reducing the semiconductor. The size of the package is to meet the requirements of light, thin, short and small.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧半導體結構 2‧‧‧Semiconductor structure
20‧‧‧半導體基板 20‧‧‧Semiconductor substrate
20a‧‧‧第一表面 20a‧‧‧ first surface
20b‧‧‧第二表面 20b‧‧‧second surface
200‧‧‧導電穿孔 200‧‧‧Electrical perforation
201‧‧‧第一電性連接墊 201‧‧‧First electrical connection pad
202‧‧‧第二電性連接墊 202‧‧‧Second electrical connection pad
204‧‧‧線路重佈層 204‧‧‧Line redistribution
205a‧‧‧第一導電元件 205a‧‧‧First conductive element
205b‧‧‧第二導電元件 205b‧‧‧Second conductive element
h、t‧‧‧高度 h, t‧‧‧ height
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