TW201532209A - Package apparatus and manufacturing method thereof - Google Patents
Package apparatus and manufacturing method thereof Download PDFInfo
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- TW201532209A TW201532209A TW103104900A TW103104900A TW201532209A TW 201532209 A TW201532209 A TW 201532209A TW 103104900 A TW103104900 A TW 103104900A TW 103104900 A TW103104900 A TW 103104900A TW 201532209 A TW201532209 A TW 201532209A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
本發明是有關於一種封裝裝置及其製作方法，特別是有關於一種半導體封裝裝置及其製作方法。 The present invention relates to a package device and a method of fabricating the same, and more particularly to a semiconductor package device and a method of fabricating the same.
在新一代的電子產品中，不斷追求更輕薄短小，更要求產品具有多功能與高性能，因此，積體電路(Integrated Circuit,IC)必須在有限的區域中容納更多電子元件以達到高密度與微型化之要求，為此電子產業開發新型構裝技術，將電子元件埋入基板中，大幅縮小構裝體積，也縮短電子元件與基板的連接路徑，另外還可利用增層技術(Build-Up)增加佈線面積，以符合輕薄短小及多功能的潮流趨勢。 In the new generation of electronic products, the pursuit of thinner and lighter, more demanding products with versatility and high performance, therefore, integrated circuits (IC) must accommodate more electronic components in a limited area to achieve high density With the miniaturization requirements, the electronics industry has developed a new type of packaging technology to embed electronic components in the substrate, greatly reducing the size of the package, shortening the connection path between the electronic components and the substrate, and also using the build-up technology (Build- Up) Increase the wiring area to meet the trend of light, short, and versatile.
圖1為傳統之玻璃纖維基板封裝結構。玻璃纖維基板封裝結構10包括有玻璃纖維基板100，例如可為玻纖環氧樹脂銅箔基板FR-4型號或FR-5型號，其中玻璃纖維基板100係經由雷射開孔(Laser Via)而形成凹槽110與複數個導通孔120，電子元件130固定在凹槽110中，金屬導電柱140設置在部份之導通孔120中，第一金屬導電層142、144分別設置在玻璃纖維基板100上且與金屬導電柱140電性導通，絕緣層150覆蓋凹槽110、電子元件130及複數個導通孔120，第二金屬導電層146、148設置在絕緣層150之上且與電子元件130及第一金屬導電層142、144電性導通。 Figure 1 shows a conventional glass fiber substrate package structure. The glass fiber substrate package structure 10 includes a glass fiber substrate 100, which may be, for example, a glass fiber epoxy copper foil substrate FR-4 model or an FR-5 model, wherein the glass fiber substrate 100 is via a laser via (Laser Via). The recess 110 and the plurality of vias 120 are formed, the electronic component 130 is fixed in the recess 110, and the metal conductive pillars 140 are disposed in the partial vias 120. The first metal conductive layers 142 and 144 are respectively disposed on the glass fiber substrate 100. The second conductive layer 150 is disposed on the insulating layer 150 and is connected to the electronic component 130 and The first metal conductive layers 142, 144 are electrically conductive.
然而，上述傳統之玻璃纖維基板封裝結構，其係使用玻璃纖維材質作為基板之成本過於昂貴，並且再反覆利用雷射開孔技術來形成四層金屬層雷射盲埋孔之疊層結構，其中，複數次雷射開孔加工時間較長且製程複雜，四層金屬層之成本亦較高，都會造 成傳統之玻璃纖維基板封裝結構不具產業優勢。 However, the above-mentioned conventional glass fiber substrate packaging structure, which is made of a glass fiber material as a substrate, is too expensive, and a laser opening technique is used to form a laminated structure of four layers of metal layer laser blind buried holes, wherein The processing time of the plurality of laser openings is long and the process is complicated, and the cost of the four metal layers is also high. The traditional glass fiber substrate packaging structure has no industrial advantage.
本發明提出一種封裝裝置，其係可使用封膠層(Mold Compound Layer)為無核心基板(Coreless Substrate)之主體材料，並利用電鍍導柱層形成導通孔與預封包互連系統(Mold Interconnect System,MIS)封裝方式於基板製作中順勢將被動元件埋入於基板之內，形成簡單之三層金屬層內埋被動元件之疊層結構。 The invention provides a packaging device which can use a Mold Compound Layer as a core material of a Coreless Substrate and forms a via hole and a pre-package interconnection system by using a plating pillar layer (Mold Interconnect System) The MIS) package method embeds the passive component in the substrate in the fabrication of the substrate, forming a simple three-layer metal layer with a stacked structure of buried passive components.
本發明提出一種封裝裝置之製作方法，其係可使用較低成本的封膠(Mold Compound)取代昂貴的玻璃纖維基板，並以較低成本的三層金屬層電鍍導柱層流程取代昂貴的四層金屬層雷射盲埋孔流程，所以加工時間較短且流程簡單。 The invention provides a manufacturing method of a packaging device, which can replace an expensive glass fiber substrate with a lower cost Mold Compound, and replace the expensive four with a lower cost three-layer metal layer plating pillar layer process. The layer metal layer laser blind buried hole process, so the processing time is short and the process is simple.
在第一實施例中，本發明提出一種封裝裝置，其包括一第一導線層、一金屬層、一第一介電層、一第二導線層、一導柱層、一被動元件、一第一封膠層、一第三導線層以及一防焊層。第一導線層具有相對之一第一表面與一第二表面。金屬層設置於第一導線層之第一表面上。第一介電層設置於第一導線層上與第一導線層之部分區域內，其中第一介電層不露出於第一導線層之第一表面。第二導線層設置於第一導線層與第一介電層上。導柱層設置於第二導線層上，並且與第二導線層形成一凹型結構。被動元件設置並電性連結於凹型結構內之第二導線層上。第一封膠層設置於第二導線層與導柱層之部分區域內，並且包覆被動元件，其中第一封膠層不露出於導柱層之一端。第三導線層設置於第一封膠層與導柱層之一端上。防焊層設置於第一封膠層與第三導線層上。 In a first embodiment, the present invention provides a package device including a first wire layer, a metal layer, a first dielectric layer, a second wire layer, a pillar layer, a passive component, and a first A glue layer, a third wire layer and a solder mask. The first wire layer has a first surface and a second surface. The metal layer is disposed on the first surface of the first wire layer. The first dielectric layer is disposed on the first wire layer and a portion of the first wire layer, wherein the first dielectric layer is not exposed on the first surface of the first wire layer. The second wire layer is disposed on the first wire layer and the first dielectric layer. The pillar layer is disposed on the second wire layer and forms a concave structure with the second wire layer. The passive component is disposed and electrically coupled to the second wire layer within the concave structure. The first adhesive layer is disposed in a portion of the second wire layer and the pillar layer, and covers the passive component, wherein the first sealant layer is not exposed at one end of the pillar layer. The third wire layer is disposed on one end of the first sealant layer and the pillar layer. The solder resist layer is disposed on the first sealant layer and the third wire layer.
在第一實施例中，本發明提出一種封裝裝置之製作方法，其步驟包括：提供一金屬載板，其具有相對之一第一側面與一第二側面；形成一第一導線層於金屬載板之第二側面上；形成一第一介電層於金屬載板之第二側面與第一導線層上；形成一第二導線層於第一導線層與第一介電層上；形成一導柱層於第二導線層 上，其中導柱層與第二導線層形成一凹型結構；提供一被動元件設置並電性連結於凹型結構內之第二導線層上；形成一第一封膠層包覆第一介電層、第二導線層、被動元件、導柱層與金屬載板之第二側面；露出導柱層之一端；形成一第三導線層於第一封膠層與露出之導柱層之一端上；形成一防焊層於第一封膠層與第三導線層上；移除金屬載板之部分區域以形成一窗口，其中第一導線層與第一介電層從窗口露出。 In a first embodiment, the present invention provides a method of fabricating a package device, the method comprising: providing a metal carrier having a first side and a second side; forming a first wire layer on the metal Forming a first dielectric layer on the second side of the metal carrier and the first wire layer; forming a second wire layer on the first wire layer and the first dielectric layer; forming a The pillar layer is on the second wire layer The guiding pillar layer and the second wire layer form a concave structure; providing a passive component and electrically connecting to the second wire layer in the concave structure; forming a first sealing layer covering the first dielectric layer a second wire layer, a passive component, a pillar layer and a second side of the metal carrier; exposing one end of the pillar layer; forming a third conductor layer on one end of the first sealant layer and the exposed pillar layer; Forming a solder resist layer on the first sealant layer and the third wire layer; removing a portion of the metal carrier plate to form a window, wherein the first wire layer and the first dielectric layer are exposed from the window.
在第二實施例中，本發明提出一種封裝裝置，其包括一第一導線層、一金屬層、一第一介電層、一第二介電層、一第二導線層、一導柱層、一被動元件、一第一封膠層、一第三導線層以及一防焊層。第一導線層具有相對之一第一表面與一第二表面。金屬層設置於第一導線層之第一表面上。第一介電層設置於第一導線層之部分區域內，其中第一介電層不露出於第一導線層之第一表面，第一介電層不低於第一導線層之第二表面。第二介電層設置於第一導線層與第一介電層上。第二導線層設置於第一導線層與第二介電層上。導柱層設置於第二導線層上，並且與第二導線層形成一凹型結構。被動元件設置並電性連結於凹型結構內之第一導線層上。第一封膠層設置於第一介電層、第二介電層、第二導線層與導柱層之部分區域內，並且包覆被動元件，其中第一封膠層不露出於導柱層之一端。第三導線層設置於第一封膠層與導柱層之一端上。防焊層設置於第一封膠層與第三導線層上。 In a second embodiment, the present invention provides a package device including a first wire layer, a metal layer, a first dielectric layer, a second dielectric layer, a second wire layer, and a pillar layer. a passive component, a first sealant layer, a third wire layer, and a solder resist layer. The first wire layer has a first surface and a second surface. The metal layer is disposed on the first surface of the first wire layer. The first dielectric layer is disposed in a portion of the first conductive layer, wherein the first dielectric layer is not exposed on the first surface of the first conductive layer, and the first dielectric layer is not lower than the second surface of the first conductive layer . The second dielectric layer is disposed on the first wire layer and the first dielectric layer. The second wire layer is disposed on the first wire layer and the second dielectric layer. The pillar layer is disposed on the second wire layer and forms a concave structure with the second wire layer. The passive component is disposed and electrically coupled to the first wire layer within the concave structure. The first adhesive layer is disposed in a portion of the first dielectric layer, the second dielectric layer, the second conductive layer and the pillar layer, and covers the passive component, wherein the first sealant layer is not exposed to the pillar layer One end. The third wire layer is disposed on one end of the first sealant layer and the pillar layer. The solder resist layer is disposed on the first sealant layer and the third wire layer.
在第二實施例中，本發明提出一種封裝裝置之製作方法，其步驟包括：提供一金屬載板，其具有相對之一第一側面與一第二側面；形成一第一介電層於金屬載板之第二側面上；形成一第一導線層於金屬載板之第二側面上，其中第一介電層設置於第一導線層之部分區域內，第一介電層不低於第一導線層；形成一第二介電層於第一導線層與第一介電層上；形成一第二導線層於第一導線層與第二介電層上；形成一導柱層於第二導線層上，其中導柱層與第二導線層形成一凹型結構；提供一被動元件設置並電性連結於凹型結構內之第一導線層上；形成一第一封膠層包覆第 一介電層、第一導線層、第二介電層、第二導線層、導柱層、被動元件與金屬載板之第二側面；露出導柱層之一端；形成一第三導線層於第一封膠層與露出之導柱層之一端上；形成一防焊層於第一封膠層與第三導線層上；移除金屬載板之部分區域以形成一窗口，其中第一導線層與第一介電層從窗口露出。 In a second embodiment, the present invention provides a method of fabricating a package device, the method comprising: providing a metal carrier having a first side and a second side; forming a first dielectric layer on the metal Forming a first wire layer on the second side of the metal carrier, wherein the first dielectric layer is disposed in a portion of the first wire layer, and the first dielectric layer is not lower than the first layer a wire layer; forming a second dielectric layer on the first wire layer and the first dielectric layer; forming a second wire layer on the first wire layer and the second dielectric layer; forming a pillar layer On the two wire layers, wherein the pillar layer and the second wire layer form a concave structure; a passive component is provided and electrically connected to the first wire layer in the concave structure; forming a first sealant layer a dielectric layer, a first wiring layer, a second dielectric layer, a second wiring layer, a pillar layer, a passive component and a second side of the metal carrier; exposing one end of the pillar layer; forming a third conductor layer a first adhesive layer and one end of the exposed pillar layer; forming a solder resist layer on the first sealant layer and the third wire layer; removing a portion of the metal carrier plate to form a window, wherein the first wire The layer and the first dielectric layer are exposed from the window.
10‧‧‧玻璃纖維基板封裝結構 10‧‧‧glass fiber substrate package structure
100‧‧‧玻璃纖維基板 100‧‧‧glass fiber substrate
110‧‧‧凹槽 110‧‧‧ Groove
120‧‧‧導通孔 120‧‧‧vias
130‧‧‧電子元件 130‧‧‧Electronic components
140‧‧‧金屬導電柱 140‧‧‧Metal conductive column
142、144‧‧‧第一金屬導電層 142, 144‧‧‧ first metal conductive layer
146、148‧‧‧第二金屬導電層 146, 148‧‧‧Second metal conductive layer
150‧‧‧絕緣層 150‧‧‧Insulation
20、40‧‧‧封裝裝置 20, 40‧‧‧Package
200‧‧‧第一導線層 200‧‧‧First wire layer
202‧‧‧第一表面 202‧‧‧ first surface
204‧‧‧第二表面 204‧‧‧Second surface
210‧‧‧金屬層 210‧‧‧metal layer
220‧‧‧第一介電層 220‧‧‧First dielectric layer
222‧‧‧第二介電層 222‧‧‧Second dielectric layer
230‧‧‧第二導線層 230‧‧‧Second wire layer
240‧‧‧導柱層 240‧‧‧ Guide column
242‧‧‧凹型結構 242‧‧‧ concave structure
244‧‧‧部分區域 244‧‧‧Partial areas
246‧‧‧導柱層之一端 246‧‧ ‧ one end of the guide column
250‧‧‧被動元件 250‧‧‧ Passive components
260‧‧‧第一封膠層 260‧‧‧First adhesive layer
270‧‧‧第三導線層 270‧‧‧ third wire layer
280‧‧‧防焊層 280‧‧‧ solder mask
290‧‧‧外接元件 290‧‧‧External components
292‧‧‧第二封膠層 292‧‧‧Second sealant
294‧‧‧金屬球 294‧‧‧metal ball
30、50‧‧‧製作方法 30, 50‧‧‧How to make
步驟S302-步驟S336 Step S302 - step S336
步驟S502-步驟S540 Step S502 - step S540
300‧‧‧金屬載板 300‧‧‧Metal carrier board
302‧‧‧第一側面 302‧‧‧ first side
304‧‧‧第二側面 304‧‧‧ second side
306‧‧‧窗口 306‧‧‧ window
310‧‧‧第一光阻層 310‧‧‧First photoresist layer
320‧‧‧第二光阻層 320‧‧‧Second photoresist layer
330‧‧‧第三光阻層 330‧‧‧ Third photoresist layer
340‧‧‧第四光阻層 340‧‧‧fourth photoresist layer
350‧‧‧第五光阻層 350‧‧‧ Fifth photoresist layer
C‧‧‧切割製程 C‧‧‧ cutting process
圖1為傳統之玻璃纖維基板封裝結構。 Figure 1 shows a conventional glass fiber substrate package structure.
圖2為本發明第一實施例之封裝裝置示意圖。 2 is a schematic view of a packaging device according to a first embodiment of the present invention.
圖3為本發明第一實施例之封裝裝置製作方法流程圖。 3 is a flow chart of a method of fabricating a packaging device according to a first embodiment of the present invention.
圖4A至圖4R為本發明第一實施例之封裝裝置製作示意圖。 4A to 4R are schematic views showing the fabrication of a packaging device according to a first embodiment of the present invention.
圖5為本發明第二實施例之封裝裝置示意圖。 FIG. 5 is a schematic diagram of a packaging device according to a second embodiment of the present invention.
圖6為本發明第二實施例之封裝裝置製作方法流程圖。 FIG. 6 is a flow chart of a method for fabricating a packaging device according to a second embodiment of the present invention.
圖7A至圖7T為本發明第二實施例之封裝裝置製作示意圖。 7A to 7T are schematic views showing the fabrication of a packaging device according to a second embodiment of the present invention.
圖2為本發明第一實施例之封裝裝置示意圖。封裝裝置20，其包括一第一導線層200、一金屬層210、一第一介電層220、一第二導線層230、一導柱層240、一被動元件250、一第一封膠層260、一第三導線層270以及一防焊層280。第一導線層200具有相對之一第一表面202與一第二表面204。金屬層210設置於第一導線層200之第一表面202上。第一介電層220設置於第一導線層200上與第一導線層200之部分區域內，其中第一介電層220不露出於第一導線層200之第一表面202。第二導線層230設置於第一導線層200與第一介電層220上。導柱層240設置於第二導線層230上，並且與第二導線層230形成一凹型結構242。被動元件250設置並電性連結於凹型結構242內之第二導線層230上。第一封膠層260設置於第二導線層230與導柱層240之部分區域244內，並且包覆被動元件250，其中第一封膠層260不露出於導柱層240之一端246。在本實施例中，第一封膠層260設置於第二導線層230與導柱層240之全部區域內，但並不以此為限。此外，第一封膠層260係具有酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之包覆劑，但並不以此為限。第三導線層270設置於第一封膠層260與導柱層240之一端246上。防焊層280設置於第一封膠層260與第三導線層270上。 2 is a schematic view of a packaging device according to a first embodiment of the present invention. The package device 20 includes a first wire layer 200, a metal layer 210, a first dielectric layer 220, a second wire layer 230, a pillar layer 240, a passive component 250, and a first sealant layer. 260, a third wire layer 270 and a solder resist layer 280. The first wire layer 200 has a first surface 202 and a second surface 204 opposite to each other. The metal layer 210 is disposed on the first surface 202 of the first wire layer 200. The first dielectric layer 220 is disposed on the first wire layer 200 and a portion of the first wire layer 200 , wherein the first dielectric layer 220 is not exposed on the first surface 202 of the first wire layer 200 . The second wire layer 230 is disposed on the first wire layer 200 and the first dielectric layer 220. The pillar layer 240 is disposed on the second wire layer 230 and forms a concave structure 242 with the second wire layer 230. The passive component 250 is disposed and electrically coupled to the second wire layer 230 within the female structure 242. The first adhesive layer 260 is disposed in the partial region 244 of the second wire layer 230 and the pillar layer 240 and covers the passive component 250, wherein the first sealant layer 260 is not exposed to one end 246 of the pillar layer 240. In this embodiment, the first sealant layer 260 is disposed in the entire area of the second wire layer 230 and the pillar layer 240, but is not limited thereto. In addition, the first sealant layer 260 has a phenolic resin (Novolac-Based) Resin), Epoxy-Based Resin, Silicone-Based Resin or other suitable coating agents, but not limited thereto. The third wire layer 270 is disposed on one end 246 of the first sealant layer 260 and the pillar layer 240. The solder resist layer 280 is disposed on the first sealant layer 260 and the third wire layer 270.
其中，封裝裝置20更可包括一外接元件290、一第二封膠層292及複數個金屬球294。外接元件290設置並電性連結於第一導線層200之第一表面202上。第二封膠層292設置於外接元件290與第一導線層200之第一表面202上。複數個金屬球294設置於第三導線層270上。在一實施例中，外接元件290係為一主動元件、一被動元件、一半導體晶片或一軟性電路板，但並不以此為限。 The packaging device 20 further includes an external component 290, a second sealing layer 292, and a plurality of metal balls 294. The external component 290 is disposed and electrically coupled to the first surface 202 of the first wire layer 200. The second sealant layer 292 is disposed on the first surface 202 of the external component 290 and the first wire layer 200. A plurality of metal balls 294 are disposed on the third wire layer 270. In an embodiment, the external component 290 is an active component, a passive component, a semiconductor chip, or a flexible circuit board, but is not limited thereto.
圖3為本發明第一實施例之封裝裝置製作方法流程圖，圖4A至圖4R為本發明第一實施例之封裝裝置製作示意圖。封裝裝置20之製作方法30，其步驟包括： 3 is a flow chart of a method for fabricating a package device according to a first embodiment of the present invention, and FIGS. 4A to 4R are schematic views showing the manufacture of a package device according to a first embodiment of the present invention. The manufacturing method 30 of the packaging device 20 includes the following steps:
步驟S302，如圖4A所示，提供一金屬載板300，其具有相對之一第一側面302與一第二側面304。 Step S302, as shown in FIG. 4A, provides a metal carrier 300 having a first side 302 and a second side 304.
步驟S304，如圖4B所示，形成一第一導線層200於金屬載板300之第二側面304上。在本實施例中，第一導線層200係可應用無電鍍(Electroless Plating)技術、濺鍍(Sputtering Coating)技術或蒸鍍(Thermal Coating)技術，再經過微影製程(Photolithography)與蝕刻製程(Etch Process)所形成，但並不以此為限。其中第一導線層200可以為圖案化導線層，其包括至少一走線與至少一晶片座，第一導線層200之材質可以為金屬，例如是銅。 Step S304, as shown in FIG. 4B, a first wire layer 200 is formed on the second side 304 of the metal carrier 300. In this embodiment, the first wire layer 200 can be applied by electroless plating technology, sputtering or thermal coating technology, and then subjected to photolithography and etching processes ( Etch Process) is formed, but not limited to this. The first wire layer 200 may be a patterned wire layer including at least one trace and at least one wafer holder. The material of the first wire layer 200 may be metal, such as copper.
步驟S306，如圖4C所示，形成一第一介電層220於金屬載板300之第二側面304與第一導線層200上，以及形成一第一光阻層310於金屬載板300之第一側面302上。在本實施例中，第一介電層220係應用塗佈製程，再經過微影製程(Photolithography)與蝕刻製程(Etch Process)所形成，第一光阻層310係應用壓合乾膜光阻製程所形成，但並不以此為限。 Step S306, as shown in FIG. 4C, a first dielectric layer 220 is formed on the second side surface 304 of the metal carrier 300 and the first wiring layer 200, and a first photoresist layer 310 is formed on the metal carrier 300. On the first side 302. In this embodiment, the first dielectric layer 220 is formed by a coating process, and then formed by a photolithography process and an etching process (Etch Process), and the first photoresist layer 310 is applied with a dry film photoresist. The process is formed, but not limited to this.
步驟S308，如圖4D所示，形成一第二導線層230於第一導線層200與第一介電層220上。在本實施例中，第二導線層230係可應用無電鍍(Electroless Plating)技術、濺鍍(Sputtering Coating)技術或蒸鍍(Thermal Coating)技術，再經過微影製程(Photolithography)與蝕刻製程(Etch Process)所形成，但並不以此為限。其中第二導線層230可以為圖案化導線層，其包括至少一走線，並形成對應於露出之第一導線層200上。 Step S308, as shown in FIG. 4D, a second wire layer 230 is formed on the first wire layer 200 and the first dielectric layer 220. In this embodiment, the second wire layer 230 can be applied by Electroless Plating technology, Sputtering Coating technology or Thermal Coating technology, and then subjected to Photolithography and etching processes ( Etch Process) is formed, but not limited to this. The second wire layer 230 may be a patterned wire layer including at least one trace and formed corresponding to the exposed first wire layer 200.
步驟S310，如圖4E所示，形成一第二阻層320於第一介電層220與第二導線層230上。在本實施例中，第二光阻層320係應用壓合乾膜光阻製程所形成，但並不以此為限。 Step S310, as shown in FIG. 4E, a second resist layer 320 is formed on the first dielectric layer 220 and the second conductive layer 230. In this embodiment, the second photoresist layer 320 is formed by using a dry film photoresist process, but is not limited thereto.
步驟S312，如圖4F所示，移除第二光阻層320之部分區域以露出第二導線層230。在本實施例中，移除第二光阻層320之部分區域係應用微影製程(Photolithography)技術所達成，但並不以此為限。 Step S312, as shown in FIG. 4F, a portion of the second photoresist layer 320 is removed to expose the second wire layer 230. In this embodiment, the removal of a portion of the second photoresist layer 320 is achieved by using a photolithography technique, but is not limited thereto.
步驟S314，如圖4G所示，形成一導柱層240於第二導線層230上。在本實施例中，導柱層240係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中，導柱層240包括至少一導電柱，其形成對應於第二導線層230之走線上，導柱層240之材質可以為金屬，例如是銅。 Step S314, as shown in FIG. 4G, a pillar layer 240 is formed on the second wiring layer 230. In the present embodiment, the pillar layer 240 is formed by electroplating (Electrolytic Plating) technology, but is not limited thereto. The pillar layer 240 includes at least one conductive pillar formed on a trace corresponding to the second wire layer 230. The material of the pillar layer 240 may be metal, such as copper.
步驟S316，如圖4H所示，移除第一光阻層310、第二光阻層320而形成第一導線層200於金屬載板300之第二側面304上，形成第一介電層220於金屬載板300之第二側面304與第一導線層200上，形成第二導線層230於第一導線層200與第一介電層220上，以及形成導柱層240於第二導線層230上，其中導柱層240與第二導線層230形成一凹型結構242。 Step S316, as shown in FIG. 4H, removing the first photoresist layer 310 and the second photoresist layer 320 to form the first wiring layer 200 on the second side 304 of the metal carrier 300 to form the first dielectric layer 220. On the second side 304 of the metal carrier 300 and the first conductive layer 200, a second conductive layer 230 is formed on the first conductive layer 200 and the first dielectric layer 220, and a pillar layer 240 is formed on the second conductive layer. 230, wherein the pillar layer 240 and the second wire layer 230 form a concave structure 242.
步驟S318，如圖4I所示，提供一被動元件250設置並電性連結於凹型結構242內之第二導線層230上。 Step S318, as shown in FIG. 4I, a passive component 250 is provided and electrically connected to the second wire layer 230 in the concave structure 242.
步驟S320，如圖4J所示，形成一第一封膠層260包覆第一介電層220、第二導線層230、導柱層240、被動元件250與金屬載板300之第二側面304。在本實施例中，第一封膠層260係應 用轉注成型(Transfer Molding)之封裝技術所形成，第一封膠層260之材質可包括酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之包覆劑，在高溫和高壓下，以液體狀態包覆第一介電層220、第二導線層230、導柱層240與被動元件250，其固化後形成第一封膠層260。第一封膠層260亦可包括適當之填充劑，例如是粉狀之二氧化矽。 Step S320, as shown in FIG. 4J, forming a first sealant layer 260 covering the first dielectric layer 220, the second wire layer 230, the pillar layer 240, the passive component 250, and the second side 304 of the metal carrier 300 . In this embodiment, the first sealant layer 260 is Formed by a transfer molding technique, the material of the first sealant layer 260 may include Novolac-Based Resin, Epoxy-Based Resin, and Silicone-based resin (Silicone- The first dielectric layer 220, the second wire layer 230, the pillar layer 240 and the passive component 250 are coated in a liquid state under high temperature and high pressure, and are cured to form a first Sealing layer 260. The first adhesive layer 260 may also include a suitable filler such as powdered cerium oxide.
在另一實施例中，亦可應用注射成型(Injection Molding)或壓縮成型(Compression Molding)之封裝技術形成第一封膠層260。 In another embodiment, the first encapsulation layer 260 may also be formed using an injection molding or compression molding technique.
其中，形成第一封膠層260之步驟可包括：提供一包覆劑，其中包覆劑具有樹脂及粉狀之二氧化矽。加熱包覆劑至液體狀態。注入呈液態之包覆劑於金屬載板300之第二側面304上，包覆劑在高溫和高壓下包覆第一介電層220、第二導線層230、導柱層240與被動元件250。固化包覆劑，使包覆劑形成第一封膠層260，但形成第一封膠層260之步驟並不以此為限。 The step of forming the first sealant layer 260 may include: providing a coating agent, wherein the coating agent has a resin and powdered cerium oxide. The coating agent is heated to a liquid state. Injecting a liquid coating agent onto the second side 304 of the metal carrier 300, the coating agent coating the first dielectric layer 220, the second wiring layer 230, the pillar layer 240 and the passive component 250 under high temperature and high pressure . The coating agent is cured to form the first sealing layer 260, but the step of forming the first sealing layer 260 is not limited thereto.
步驟S322，如圖4K所示，露出導柱層240之一端246。在本實施例中，露出導柱層240係應用磨削(Grinding)方式移除第一封膠層260之一部分，以露出導柱層240之一端246。較佳但非限定地，導柱層240之一端246與第一封膠層260實質上對齊，例如是共面。在另一實施例中，可在形成第一封膠層260的同時，露出導柱層240之一端246，而無需移除第一封膠層260的任何部分。 Step S322, as shown in FIG. 4K, exposes one end 246 of the pillar layer 240. In the present embodiment, the exposed pillar layer 240 is subjected to a Grinding method to remove a portion of the first sealant layer 260 to expose one end 246 of the pillar layer 240. Preferably, but not limited to, one end 246 of the pillar layer 240 is substantially aligned with the first sealant layer 260, such as coplanar. In another embodiment, one end 246 of the pillar layer 240 may be exposed while forming the first sealant layer 260 without removing any portion of the first sealant layer 260.
步驟S324，如圖4L所示，形成一第三導線層270於第一封膠層260與露出之導柱層240之一端246上。在一實施例中，第三導線層270係可應用無電鍍(Electroless Plating)技術、濺鍍(Sputtering Coating)技術或蒸鍍(Thermal Coating)技術所形成，但並不以此為限。其中第三導線層270可以為圖案化導線層，其包括至少一走線，並形成對應於露出之導柱層240之一端246上，第三導線層270之材質可以為金屬，例如是銅。 Step S324, as shown in FIG. 4L, a third wire layer 270 is formed on one end 246 of the first sealant layer 260 and the exposed pillar layer 240. In one embodiment, the third wire layer 270 can be formed by using an electroless plating technique, a sputtering technique, or a thermal coating technique, but is not limited thereto. The third wire layer 270 may be a patterned wire layer including at least one trace and formed on one end 246 corresponding to the exposed pillar layer 240. The material of the third wire layer 270 may be metal, such as copper.
步驟S326，如圖4M所示，形成一防焊層280於第一封膠層 260與第三導線層270上，並露出部份之第三導線層270。其中，防焊層280具有絕緣第三導線層270之各走線電性的功效。 Step S326, as shown in FIG. 4M, forming a solder resist layer 280 on the first sealant layer. 260 and the third wire layer 270, and a portion of the third wire layer 270 is exposed. The solder resist layer 280 has the effect of insulating the electrical properties of the traces of the third wire layer 270.
步驟S328，如圖4N所示，移除金屬載板300之部分區域以形成一窗口306，其中第一導線層200與第一介電層220從窗口306露出。在本實施例中，移除金屬載板300之部分區域係應用微影製程(Photolithography)與蝕刻製程(Etch Process)所達成，第一導線層200之走線與晶片座亦可從窗口306露出，此外，金屬載板300所留下之部分區域即形成一金屬層210。 Step S328, as shown in FIG. 4N, a portion of the metal carrier 300 is removed to form a window 306, wherein the first conductive layer 200 and the first dielectric layer 220 are exposed from the window 306. In this embodiment, part of the removal of the metal carrier 300 is achieved by applying a photolithography process and an etching process. The traces of the first wire layer 200 and the wafer holder may also be exposed from the window 306. In addition, a portion of the area left by the metal carrier 300 forms a metal layer 210.
步驟S330，如圖4O所示，提供一外接元件290設置並電性連結於第一導線層200之第一表面202上。在一實施例中，外接元件290係為一主動元件、一被動元件、一半導體晶片或一軟性電路板，但並不以此為限。 In step S330, as shown in FIG. 4O, an external component 290 is disposed and electrically connected to the first surface 202 of the first wire layer 200. In an embodiment, the external component 290 is an active component, a passive component, a semiconductor chip, or a flexible circuit board, but is not limited thereto.
步驟S332，如圖4P所示，形成一第二封膠層292包覆於外接元件290與第一導線層200之第一表面202上。在本實施例中，第二封膠層292係應用轉注成型(Transfer Molding)之封裝技術所形成，第二封膠層292之材質可包括酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之包覆劑，在高溫和高壓下，以液體狀態包覆外接元件292與第一導線層200之第一表面202上，其固化後形成第二封膠層292。第二封膠層292亦可包括適當之填充劑，例如是粉狀之二氧化矽。 Step S332, as shown in FIG. 4P, a second sealant layer 292 is formed on the first surface 202 of the external component 290 and the first wire layer 200. In this embodiment, the second sealant layer 292 is formed by a transfer molding technique, and the second sealant layer 292 may include a phenolic resin (Novolac-Based Resin) and an epoxy resin. (Epoxy-Based Resin), Silicone-Based Resin or other suitable coating agent for coating the external component 292 and the first surface 202 of the first wire layer 200 in a liquid state under high temperature and high pressure. After curing, a second sealant layer 292 is formed. The second sealant layer 292 may also include a suitable filler such as powdered cerium oxide.
在另一實施例中，亦可應用注射成型(Injection Molding)或壓縮成型(Compression Molding)之封裝技術形成第二封膠層292。 In another embodiment, the second encapsulation layer 292 can also be formed using an injection molding or compression molding (Packaging Molding) packaging technique.
步驟S334，如圖4Q所示，形成複數個金屬球294於第三導線層270上。每一金屬球294之材質可以為金屬，例如是銅。 Step S334, as shown in FIG. 4Q, a plurality of metal balls 294 are formed on the third wire layer 270. The material of each of the metal balls 294 may be a metal such as copper.
步驟S336，如圖4R所示，最後再進行切割製程C於第一導線層200、金屬層210、第一介電層220、第二導線層230、第一封膠層260、第三導線層270或防焊層280等至少其中一層而形成如圖2所示之封裝裝置20。 Step S336, as shown in FIG. 4R, finally performing the cutting process C on the first wire layer 200, the metal layer 210, the first dielectric layer 220, the second wire layer 230, the first sealant layer 260, and the third wire layer. At least one of 270 or solder resist layer 280 or the like forms a package device 20 as shown in FIG.
在此要特別說明，本發明第一實施例之封裝裝置20，其係利 用第一封膠層為無核心基板之主體材料來取代昂貴的傳統之玻璃纖維基板，並以較低成本的三層金屬層電鍍導柱層流程來取代昂貴的傳統之四層金屬層雷射盲埋孔流程，所以加工時間較短且流程簡單，故可大幅降低製作成本。 Herein, the packaging device 20 of the first embodiment of the present invention is specifically described. Replace the expensive traditional glass fiber substrate with the first sealing layer as the core material of the coreless substrate, and replace the expensive traditional four-layer metal layer laser with the lower cost three-layer metal layer plating pillar layer process. The blind buried hole process, so the processing time is short and the process is simple, so the production cost can be greatly reduced.
圖5為本發明第二實施例之封裝裝置示意圖。封裝裝置40基本上類似於本發明第一實施例之封裝裝置20的結構，其包括一第一導線層200、一金屬層210、一第一介電層220、一第二介電層222、一第二導線層230、一導柱層240、一被動元件250、一第一封膠層260、一第三導線層270以及一防焊層280。第一導線層200具有相對之一第一表面202與一第二表面204。金屬層210設置於第一導線層200之第一表面202上。第一介電層220設置於第一導線層200之部分區域內，其中第一介電層220不露出於第一導線層200之第一表面202，第一介電層220不低於第一導線層200之第二表面204。第二介電層222設置於第一導線層200與第一介電層220上。第二導線層230設置於第一導線層200與第二介電層222上。導柱層240設置於第二導線層230上，並且與第二導線層230形成一凹型結構242。被動元件250設置並電性連結於凹型結構242內之第一導線層200上。第一封膠層260設置於第一介電層220、第二介電層222、第二導線層230與導柱層240之部分區域244內，並且包覆被動元件250，其中第一封膠層260不露出於導柱層240之一端246。在本實施例中，第一封膠層260設置於第一介電層220、第二介電層222、第二導線層230與導柱層240之全部區域內，但並不以此為限。此外，第一封膠層260係具有酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之包覆劑，但並不以此為限。第三導線層270設置於第一封膠層260與導柱層240之一端246上。防焊層280設置於第一封膠層260與第三導線層270上。 FIG. 5 is a schematic diagram of a packaging device according to a second embodiment of the present invention. The package device 40 is substantially similar to the structure of the package device 20 of the first embodiment of the present invention, and includes a first wire layer 200, a metal layer 210, a first dielectric layer 220, and a second dielectric layer 222. A second wire layer 230, a pillar layer 240, a passive component 250, a first sealant layer 260, a third wire layer 270, and a solder resist layer 280. The first wire layer 200 has a first surface 202 and a second surface 204 opposite to each other. The metal layer 210 is disposed on the first surface 202 of the first wire layer 200. The first dielectric layer 220 is disposed in a portion of the first conductive layer 200, wherein the first dielectric layer 220 is not exposed on the first surface 202 of the first conductive layer 200, and the first dielectric layer 220 is not lower than the first The second surface 204 of the wire layer 200. The second dielectric layer 222 is disposed on the first wiring layer 200 and the first dielectric layer 220. The second wire layer 230 is disposed on the first wire layer 200 and the second dielectric layer 222. The pillar layer 240 is disposed on the second wire layer 230 and forms a concave structure 242 with the second wire layer 230. The passive component 250 is disposed and electrically coupled to the first wire layer 200 within the female structure 242. The first adhesive layer 260 is disposed in the partial region 244 of the first dielectric layer 220, the second dielectric layer 222, the second conductive layer 230, and the pillar layer 240, and covers the passive component 250, wherein the first sealant Layer 260 is not exposed to one end 246 of pillar layer 240. In this embodiment, the first sealant layer 260 is disposed in the entire area of the first dielectric layer 220, the second dielectric layer 222, the second conductive layer 230, and the pillar layer 240, but is not limited thereto. . In addition, the first sealant layer 260 has a phenolic resin (Novolac-Based Resin), an epoxy resin (Epoxy-Based Resin), a Silicone-Based Resin or other suitable coating agent, but Not limited to this. The third wire layer 270 is disposed on one end 246 of the first sealant layer 260 and the pillar layer 240. The solder resist layer 280 is disposed on the first sealant layer 260 and the third wire layer 270.
其中，封裝裝置40更可包括一外接元件290、一第二封膠層292及複數個金屬球294。外接元件290設置並電性連結於第一 導線層200之第一表面202上。第二封膠層292設置於外接元件290與第一導線層200之第一表面202上。複數個金屬球294設置於第三導線層270上。在一實施例中，外接元件290係為一主動元件、一被動元件、一半導體晶片或一軟性電路板，但並不以此為限。 The packaging device 40 further includes an external component 290, a second sealing layer 292, and a plurality of metal balls 294. The external component 290 is disposed and electrically connected to the first On the first surface 202 of the wire layer 200. The second sealant layer 292 is disposed on the first surface 202 of the external component 290 and the first wire layer 200. A plurality of metal balls 294 are disposed on the third wire layer 270. In an embodiment, the external component 290 is an active component, a passive component, a semiconductor chip, or a flexible circuit board, but is not limited thereto.
圖6為本發明第二實施例之封裝裝置製作方法流程圖，圖7A至圖7T為本發明第二實施例之封裝裝置製作示意圖。封裝裝置40之製作方法50，其步驟包括： 6 is a flow chart of a method for fabricating a package device according to a second embodiment of the present invention, and FIGS. 7A to 7T are schematic views showing the manufacture of a package device according to a second embodiment of the present invention. The manufacturing method 50 of the packaging device 40 includes the following steps:
步驟S502，如圖7A所示，提供一金屬載板300，其具有相對之一第一側面302與一第二側面304。 Step S502, as shown in FIG. 7A, provides a metal carrier 300 having a first side 302 and a second side 304 opposite to each other.
步驟S504，如圖7B所示，形成一第一介電層220於金屬載板300之第二側面304上與一第三光阻層330於金屬載板之第一側面302上。在本實施例中，第一介電層220係應用塗佈製程所形成，第三光阻層330係應用壓合乾膜光阻製程所形成，但並不以此為限。 Step S504, as shown in FIG. 7B, a first dielectric layer 220 is formed on the second side 304 of the metal carrier 300 and a third photoresist layer 330 on the first side 302 of the metal carrier. In this embodiment, the first dielectric layer 220 is formed by a coating process, and the third photoresist layer 330 is formed by using a dry film photoresist process, but is not limited thereto.
步驟S506，如圖7C所示，形成一第一導線層200於金屬載板300之第二側面304上，其中第一介電層220設置於第一導線層200之部分區域內，第一介電層220不低於第一導線層200。在本實施例中，第一導線層200係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中第一導線層200可以為圖案化導線層，其包括至少一走線與至少一晶片座，第一導線層200之材質可以為金屬，例如是銅。 Step S506, as shown in FIG. 7C, a first conductive layer 200 is formed on the second side 304 of the metal carrier 300, wherein the first dielectric layer 220 is disposed in a portion of the first conductive layer 200. The electrical layer 220 is not lower than the first wiring layer 200. In the present embodiment, the first wire layer 200 is formed by electroplating (Electrolytic Plating) technology, but is not limited thereto. The first wire layer 200 may be a patterned wire layer including at least one trace and at least one wafer holder. The material of the first wire layer 200 may be metal, such as copper.
步驟S508，如圖7D所示，形成一第二介電層222於第一導線層200與第一介電層220上。在本實施例中，第二介電層222係應用塗佈製程所形成，但並不以此為限。 Step S508, as shown in FIG. 7D, a second dielectric layer 222 is formed on the first wiring layer 200 and the first dielectric layer 220. In the present embodiment, the second dielectric layer 222 is formed by applying a coating process, but is not limited thereto.
步驟S510，如圖7E所示，形成一第四光阻層340於第一導線層200、第一介電層220與第二介電層222上。在本實施例中，第四光阻層340係應用壓合乾膜光阻製程，再經過微影製程(Photolithography)所形成，但並不以此為限。 Step S510, as shown in FIG. 7E, a fourth photoresist layer 340 is formed on the first wiring layer 200, the first dielectric layer 220, and the second dielectric layer 222. In this embodiment, the fourth photoresist layer 340 is formed by a dry film photoresist process and then formed by photolithography, but is not limited thereto.
步驟S512，如圖7F所示，形成一第二導線層230於第一導 線層200與第二介電層222上。在本實施例中，第二導線層230係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中，第二導線層230包括至少一走線，其形成對應於第一導線層200之走線上，第二導線層230之材質可以為金屬，例如是銅。 Step S512, as shown in FIG. 7F, forming a second wire layer 230 on the first guide The line layer 200 and the second dielectric layer 222 are on. In this embodiment, the second wire layer 230 is formed by using an electroplating technique, but is not limited thereto. The second wire layer 230 includes at least one trace forming a trace corresponding to the first wire layer 200. The material of the second wire layer 230 may be a metal such as copper.
步驟S514，如圖7G所示，形成一第五光阻層350於第四光阻層340與第二導線層230上。在本實施例中，第五光阻層350係應用壓合乾膜光阻製程所形成，但並不以此為限。 Step S514, as shown in FIG. 7G, a fifth photoresist layer 350 is formed on the fourth photoresist layer 340 and the second wiring layer 230. In the embodiment, the fifth photoresist layer 350 is formed by using a dry film photoresist process, but is not limited thereto.
步驟S516，如圖7H所示，移除第五光阻層350之部分區域以露出第二導線層230。在本實施例中，移除第五光阻層350之部分區域係應用微影製程(Photolithography)技術所達成，但並不以此為限。 Step S516, as shown in FIG. 7H, a portion of the fifth photoresist layer 350 is removed to expose the second wire layer 230. In this embodiment, the removal of a portion of the fifth photoresist layer 350 is achieved by using a photolithography technique, but is not limited thereto.
步驟S518，如圖7I所示，形成一導柱層240於第二導線層230上。在本實施例中，導柱層240係應用電鍍(Electrolytic Plating)技術所形成，但並不以此為限。其中，導柱層240包括至少一導電柱，其形成對應於第二導線層230之走線上，第二導線層230之材質可以為金屬，例如是銅。 Step S518, as shown in FIG. 7I, a pillar layer 240 is formed on the second wiring layer 230. In the present embodiment, the pillar layer 240 is formed by electroplating (Electrolytic Plating) technology, but is not limited thereto. The pillar layer 240 includes at least one conductive pillar formed on a trace corresponding to the second wire layer 230. The material of the second wire layer 230 may be a metal such as copper.
步驟S520，如圖7J所示，移除第四光阻層340與第五光阻層350而形成第一介電層220於金屬載板300之第二側面304上，形成第一導線層200於金屬載板300之第二側面302上，其中第一介電層220設置於第一導線層200之部分區域內，第一介電層220不低於第一導線層200，形成第二介電層222於第一導線層200與第一介電層220上，形成第二導線層230於第一導線層220與第二介電層222上，以及形成導柱層240於第一導線層200上，其中導柱層240與第二導線層230形成一凹型結構242。 Step S520, as shown in FIG. 7J, the fourth photoresist layer 340 and the fifth photoresist layer 350 are removed to form the first dielectric layer 220 on the second side 304 of the metal carrier 300 to form the first wiring layer 200. On the second side 302 of the metal carrier 300, the first dielectric layer 220 is disposed in a portion of the first conductive layer 200, and the first dielectric layer 220 is not lower than the first conductive layer 200 to form a second dielectric layer. The electric layer 222 is formed on the first wire layer 200 and the first dielectric layer 220, the second wire layer 230 is formed on the first wire layer 220 and the second dielectric layer 222, and the pillar layer 240 is formed on the first wire layer. 200, wherein the pillar layer 240 and the second wire layer 230 form a concave structure 242.
步驟S522，如圖7K所示，提供一被動元件250設置並電性連結於凹型結構222內之第一導線層200上。 Step S522, as shown in FIG. 7K, a passive component 250 is provided and electrically connected to the first wire layer 200 in the concave structure 222.
步驟S524，如圖7L所示，形成一第一封膠層260包覆第一介電層220、第一導線層200、第二介電層222、第二導線層230、導柱層240、被動元件250與金屬載板300之第二側面304。在本實施例中，第一封膠層260係應用轉注成型(Transfer Molding) 之封裝技術所形成，第一封膠層260之材質可包括酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之包覆劑，在高溫和高壓下，以液體狀態包覆第一介電層220、第一導線層200、第二介電層222、第二導線層230、導柱層240與被動元件250，其固化後形成第一封膠層260。第一封膠層260亦可包括適當之填充劑，例如是粉狀之二氧化矽。 Step S524, as shown in FIG. 7L, a first encapsulation layer 260 is formed to cover the first dielectric layer 220, the first wiring layer 200, the second dielectric layer 222, the second wiring layer 230, and the pillar layer 240. Passive element 250 and second side 304 of metal carrier 300. In this embodiment, the first sealant layer 260 is subjected to transfer molding (Transfer Molding). Formed by the packaging technology, the material of the first sealant layer 260 may include Novolac-Based Resin, Epoxy-Based Resin, Silicone-Based Resin or other suitable materials. a coating agent that coats the first dielectric layer 220, the first wiring layer 200, the second dielectric layer 222, the second wiring layer 230, the pillar layer 240, and the passive component 250 in a liquid state under high temperature and high pressure. After curing, a first sealant layer 260 is formed. The first adhesive layer 260 may also include a suitable filler such as powdered cerium oxide.
在另一實施例中，亦可應用注射成型(Injection Molding)或壓縮成型(Compression Molding)之封裝技術形成第一封膠層260。 In another embodiment, the first encapsulation layer 260 may also be formed using an injection molding or compression molding technique.
其中，形成第一封膠層260之步驟可包括：提供一包覆劑，其中包覆劑具有樹脂及粉狀之二氧化矽。加熱包覆劑至液體狀態。注入呈液態之包覆劑於金屬載板300之第二側面304上，包覆劑在高溫和高壓下包覆第一介電層220、第一導線層200、第二介電層222、第二導線層230、導柱層240與被動元件250。固化包覆劑，使包覆劑形成第一封膠層260，但形成第一封膠層260之步驟並不以此為限。 The step of forming the first sealant layer 260 may include: providing a coating agent, wherein the coating agent has a resin and powdered cerium oxide. The coating agent is heated to a liquid state. Injecting a coating agent in a liquid state on the second side surface 304 of the metal carrier 300, the coating agent coating the first dielectric layer 220, the first wiring layer 200, the second dielectric layer 222, and the first layer under high temperature and high pressure The two wire layers 230, the pillar layer 240 and the passive component 250. The coating agent is cured to form the first sealing layer 260, but the step of forming the first sealing layer 260 is not limited thereto.
步驟S526，如圖7M所示，露出導柱層240之一端246。在本實施例中，露出導柱層240係應用磨削(Grinding)方式移除第一封膠層260之一部分，以露出導柱層240之一端246。較佳但非限定地，導柱層240之一端246與第一封膠層260實質上對齊，例如是共面。在另一實施例中，可在形成第一封膠層260的同時，露出導柱層240之一端246，而無需移除第一封膠層260的任何部分。 Step S526, as shown in FIG. 7M, exposes one end 246 of the pillar layer 240. In the present embodiment, the exposed pillar layer 240 is subjected to a Grinding method to remove a portion of the first sealant layer 260 to expose one end 246 of the pillar layer 240. Preferably, but not limited to, one end 246 of the pillar layer 240 is substantially aligned with the first sealant layer 260, such as coplanar. In another embodiment, one end 246 of the pillar layer 240 may be exposed while forming the first sealant layer 260 without removing any portion of the first sealant layer 260.
步驟S528，如圖7N所示，形成一第三導線層270於第一封膠層260與露出之導柱層240之一端246上。在一實施例中，第三導線層270係可應用無電鍍(Electroless Plating)技術、濺鍍(Sputtering Coating)技術或蒸鍍(Thermal Coating)技術所形成，但並不以此為限。其中第三導線層270可以為圖案化導線層，其包括至少一走線，並形成對應於露出之導柱層240之一端246上，第三導線層270之材質可以為金屬，例如是銅。 Step S528, as shown in FIG. 7N, a third wire layer 270 is formed on one end 246 of the first sealant layer 260 and the exposed pillar layer 240. In one embodiment, the third wire layer 270 can be formed by using an electroless plating technique, a sputtering technique, or a thermal coating technique, but is not limited thereto. The third wire layer 270 may be a patterned wire layer including at least one trace and formed on one end 246 corresponding to the exposed pillar layer 240. The material of the third wire layer 270 may be metal, such as copper.
步驟S530，如圖7O所示，形成一防焊層280於第一封膠層260與第三導線層270上，並露出部份之第三導線層270。其中，防焊層280具有絕緣第三導線層270之各走線電性的功效。 Step S530, as shown in FIG. 7O, a solder resist layer 280 is formed on the first sealant layer 260 and the third wire layer 270, and a portion of the third wire layer 270 is exposed. The solder resist layer 280 has the effect of insulating the electrical properties of the traces of the third wire layer 270.
步驟S532，如圖7P所示，移除金屬載板300之部分區域以形成一窗口306，其中第一導線層200與第一介電層220從窗口306露出。在本實施例中，移除金屬載板300之部分區域係應用微影製程(Photolithography)與蝕刻製程(Etch Process)所達成，第一導線層200之走線與晶片座亦可從窗口306露出，此外，金屬載板300所留下之部分區域即形成一金屬層210。 Step S532, as shown in FIG. 7P, a portion of the metal carrier 300 is removed to form a window 306, wherein the first conductive layer 200 and the first dielectric layer 220 are exposed from the window 306. In this embodiment, part of the removal of the metal carrier 300 is achieved by applying a photolithography process and an etching process. The traces of the first wire layer 200 and the wafer holder may also be exposed from the window 306. In addition, a portion of the area left by the metal carrier 300 forms a metal layer 210.
步驟S534，如圖7Q所示，提供一外接元件290設置並電性連結於第一導線層200之第一表面202上。在一實施例中，外接元件290係為一主動元件、一被動元件、一半導體晶片或一軟性電路板，但並不以此為限。 Step S534, as shown in FIG. 7Q, an external component 290 is disposed and electrically connected to the first surface 202 of the first wire layer 200. In an embodiment, the external component 290 is an active component, a passive component, a semiconductor chip, or a flexible circuit board, but is not limited thereto.
步驟S536，如圖7R所示，形成一第二封膠層292包覆於外接元件290與第一導線層200之第一表面202上。在本實施例中，第二封膠層292係應用轉注成型(Transfer Molding)之封裝技術所形成，第二封膠層292之材質可包括酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)、矽基樹脂(Silicone-Based Resin)或其他適當之包覆劑，在高溫和高壓下，以液體狀態包覆外接元件290與第一導線層200之第一表面202上，其固化後形成第二封膠層292。第二封膠層292亦可包括適當之填充劑，例如是粉狀之二氧化矽。 Step S536, as shown in FIG. 7R, a second encapsulation layer 292 is formed on the first surface 202 of the external component 290 and the first wiring layer 200. In this embodiment, the second sealant layer 292 is formed by a transfer molding technique, and the second sealant layer 292 may include a phenolic resin (Novolac-Based Resin) and an epoxy resin. (Epoxy-Based Resin), Silicone-Based Resin or other suitable coating agent for coating the external component 290 and the first surface 202 of the first wire layer 200 in a liquid state under high temperature and high pressure. After curing, a second sealant layer 292 is formed. The second sealant layer 292 may also include a suitable filler such as powdered cerium oxide.
在另一實施例中，亦可應用注射成型(Injection Molding)或壓縮成型(Compression Molding)之封裝技術形成第二封膠層292。 In another embodiment, the second encapsulation layer 292 can also be formed using an injection molding or compression molding (Packaging Molding) packaging technique.
步驟S538，如圖7S所示，形成複數個金屬球294於第三導線層270上。每一金屬球294之材質可以為金屬，例如是銅。 Step S538, as shown in FIG. 7S, a plurality of metal balls 294 are formed on the third wire layer 270. The material of each of the metal balls 294 may be a metal such as copper.
步驟S540，如圖7T所示，最後再進行切割製程C於第一導線層200、金屬層210、第一介電層220、第二導線層230、第一封膠層260、第三導線層270或防焊層280等至少其中一層而形成如圖5所示之封裝裝置40。 Step S540, as shown in FIG. 7T, finally performing the cutting process C on the first wire layer 200, the metal layer 210, the first dielectric layer 220, the second wire layer 230, the first sealant layer 260, and the third wire layer. At least one of 270 or the solder resist layer 280 or the like forms a package device 40 as shown in FIG.
在此要特別說明，本發明第二實施例之封裝裝置40相較於本發明第一實施例之封裝裝置20，其係將被動元件設置在位置較低於第二導線層之第一導線層上，故可降低電鍍導柱層之高度與製程難度。此外，形成第一封膠層之厚度與研磨第一封膠層之厚度也可因此減少，讓製作更加簡單且節省成本。 It is to be noted that the packaging device 40 of the second embodiment of the present invention is configured to provide a passive component in a first wire layer lower than the second wire layer, compared to the packaging device 20 of the first embodiment of the present invention. Therefore, the height of the electroplated pillar layer and the difficulty of the process can be reduced. In addition, the thickness of the first sealant layer and the thickness of the first sealant layer can be reduced, which makes the production simpler and cost-effective.
綜上所述，本發明第一實施例之封裝裝置，其係利用第一封膠層為無核心基板之主體材料來取代昂貴的傳統之玻璃纖維基板，並以較低成本的三層金屬層電鍍導柱層流程來取代昂貴的傳統之四層金屬層雷射盲埋孔流程，所以加工時間較短且流程簡單，可大幅降低製作成本。 In summary, the packaging device of the first embodiment of the present invention replaces the expensive conventional glass fiber substrate with the first sealing material as the main material of the coreless substrate, and the three-layer metal layer at a lower cost. The electroplating guide layer process replaces the expensive traditional four-layer metal layer laser blind buried hole process, so the processing time is short and the process is simple, which can greatly reduce the production cost.
此外，本發明第二實施例之封裝裝置，其係將被動元件設置在位置較低於第二導線層之第一導線層上，故可降低電鍍導柱層之高度與製程難度。此外，形成第一封膠層之厚度與研磨第一封膠層之厚度也可因此減少，讓製作更加簡單且節省成本。 In addition, in the packaging device of the second embodiment of the present invention, the passive component is disposed on the first wire layer lower than the second wire layer, so that the height of the plating pillar layer and the process difficulty can be reduced. In addition, the thickness of the first sealant layer and the thickness of the first sealant layer can be reduced, which makes the production simpler and cost-effective.
惟以上所述之具體實施例，僅係用於例釋本發明之特點及功效，而非用於限定本發明之可實施範疇，於未脫離本發明上揭之精神與技術範疇下，任何運用本發明所揭示內容而完成之等效改變及修飾，均仍應為下述之申請專利範圍所涵蓋。 However, the specific embodiments described above are merely used to exemplify the features and functions of the present invention, and are not intended to limit the scope of the present invention, and may be applied without departing from the spirit and scope of the present invention. Equivalent changes and modifications made to the disclosure of the present invention are still covered by the scope of the following claims.
20‧‧‧封裝裝置 20‧‧‧Package
200‧‧‧第一導線層 200‧‧‧First wire layer
202‧‧‧第一表面 202‧‧‧ first surface
204‧‧‧第二表面 204‧‧‧Second surface
210‧‧‧金屬層 210‧‧‧metal layer
220‧‧‧第一介電層 220‧‧‧First dielectric layer
230‧‧‧第二導線層 230‧‧‧Second wire layer
240‧‧‧導柱層 240‧‧‧ Guide column
242‧‧‧凹型結構 242‧‧‧ concave structure
244‧‧‧部分區域 244‧‧‧Partial areas
246‧‧‧導柱層之一端 246‧‧ ‧ one end of the guide column
250‧‧‧被動元件 250‧‧‧ Passive components
260‧‧‧第一封膠層 260‧‧‧First adhesive layer
270‧‧‧第三導線層 270‧‧‧ third wire layer
280‧‧‧防焊層 280‧‧‧ solder mask
290‧‧‧外接元件 290‧‧‧External components
292‧‧‧第二封膠層 292‧‧‧Second sealant
294‧‧‧金屬球 294‧‧‧metal ball
Claims (18)
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| TW103104900A TWI534963B (en) | 2014-02-14 | 2014-02-14 | Package apparatus and manufacturing method thereof |
| US14/505,973 US9601402B2 (en) | 2014-02-14 | 2014-10-03 | Package apparatus and manufacturing method thereof |
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| TW103104900A TWI534963B (en) | 2014-02-14 | 2014-02-14 | Package apparatus and manufacturing method thereof |
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| TW201532209A true TW201532209A (en) | 2015-08-16 |
| TWI534963B TWI534963B (en) | 2016-05-21 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106548991A (en) * | 2015-09-21 | 2017-03-29 | 联发科技股份有限公司 | Semiconductor packages, semiconductor element and its manufacture method |
| US10784206B2 (en) | 2015-09-21 | 2020-09-22 | Mediatek Inc. | Semiconductor package |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106548991A (en) * | 2015-09-21 | 2017-03-29 | 联发科技股份有限公司 | Semiconductor packages, semiconductor element and its manufacture method |
| US10186488B2 (en) | 2015-09-21 | 2019-01-22 | Mediatek Inc. | Manufacturing method of semiconductor package and manufacturing method of semiconductor device |
| US10784206B2 (en) | 2015-09-21 | 2020-09-22 | Mediatek Inc. | Semiconductor package |
| US11373957B2 (en) | 2015-09-21 | 2022-06-28 | Mediatek Inc. | Semiconductor package with layer structures, antenna layer and electronic component |
| US11837552B2 (en) | 2015-09-21 | 2023-12-05 | Mediatek Inc. | Semiconductor package with layer structures, antenna layer and electronic component |
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