TW201530125A - Method for measuring and analyzing surface structure of chip or wafer - Google Patents
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本發明是有關於一種晶片的表面結構分析技術,且特別是有關於一種量測與分析晶片或晶圓表面結構的方法。The present invention relates to a surface structure analysis technique for a wafer, and more particularly to a method of measuring and analyzing a wafer or wafer surface structure.
隨著IC製程的線寬持續縮小,製程的關鍵尺寸(CD)的控制與監測也更加重要。以奈米世代半導體技術來看,要精確得到線寬等晶片上的表面結構也更加不易。As the line width of the IC process continues to shrink, the control and monitoring of the critical dimension (CD) of the process is also more important. From the perspective of nanometer semiconductor technology, it is even more difficult to accurately obtain the surface structure on a wafer such as a line width.
傳統上多以關鍵尺寸掃描式電子顯微鏡(CD-SEM)作為晶片線寬量測表面結構分析。然而由於其量測速度相當慢,並且一張相片只輸出少數量之量測資訊無法即時取得多量的量測值。Traditionally, a critical dimension scanning electron microscope (CD-SEM) has been used as a wafer line width measurement surface structure analysis. However, because the measurement speed is quite slow, and a photo only outputs a small amount of measurement information, it is impossible to obtain a large amount of measurement values in real time.
對於奈米世代半導體晶片,目前CD-SEM僅能取得一維影像的數據,如線邊緣粗糙度(line edge roughness,LER)、線寬粗糙度(line width roughness,LWR)等直線圖案的粗糙度量測。至於二維影像的量測則只能藉由特定軟體演算出圓形的接觸窗(contact)的接觸窗邊緣粗糙度(contact edge roughness,CER)。For nano generation semiconductor wafers, CD-SEM can only obtain data of one-dimensional images, such as line edge roughness (LER), line width roughness (LWR) and other linear pattern roughness. Measure. As for the measurement of the two-dimensional image, the contact edge roughness (CER) of the circular contact can only be calculated by the specific software.
因此亟需尋求能夠得到晶片上所有型態之表面結構的量測方法,更甚者是能尋求快速獲得整個晶片(chip)的關鍵尺寸均勻度(CDU)等缺陷資訊的方法。Therefore, there is a need to find a measurement method capable of obtaining surface structures of all types on a wafer, and more even a method for quickly obtaining defect information such as critical dimension uniformity (CDU) of an entire chip.
本發明提供一種量測晶片或晶圓表面結構的方法,能即時且精確得到晶片表面具有的二維結構圖案。The present invention provides a method of measuring the surface structure of a wafer or wafer, which can instantly and accurately obtain a two-dimensional structural pattern of the surface of the wafer.
本發明另提供一種分析晶片或晶圓表面結構的方法,能即時且快速取得整個晶片的表面結構之缺陷資訊。The invention further provides a method for analyzing the surface structure of a wafer or a wafer, which can quickly and quickly obtain defect information of the surface structure of the entire wafer.
本發明又提供一種黃光曝光補值的方法,不須建立模式(model)即可進行補值。The invention further provides a method for supplementing the yellow light exposure, and the complementary value can be performed without establishing a model.
本發明的一實施例之量測晶片或晶圓表面結構的方法,包括利用儀器得到晶片的表面結構的影像,再對所述影像進行影像萃取並轉換為第一電路設計檔。另選取標準影像並轉換為第二電路設計檔,然後比較所述影像中的至少一目標(target)與所述標準影像,而得到所述目標與所述標準影像之差距。根據所述差距產生所述表面結構的線邊緣粗糙度(LER)、線寬粗糙度(LWR)、接觸窗邊緣粗糙度(CER)、關鍵尺寸(critical dimension,CD)、關鍵尺寸偏離值(Bias)、3igma、最大值、最小值等與重複性缺陷(repeating defect)中至少一種數據。A method for measuring a surface structure of a wafer or a wafer according to an embodiment of the present invention includes obtaining an image of a surface structure of the wafer by using an instrument, and performing image extraction on the image and converting the image into a first circuit design file. Another standard image is selected and converted into a second circuit design file, and then at least one target and the standard image in the image are compared to obtain a difference between the target and the standard image. Line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), critical dimension deviation (Bias) of the surface structure are generated according to the gap ), 3igma, maximum, minimum, etc., and at least one of repetitive defects.
在本發明的一實施例中,上述方法還可包括藉由所述數據即時得到整個所述晶片或晶圓的關鍵尺寸均勻度(CDU)與偏離值差異(Bias difference)。In an embodiment of the invention, the method may further include obtaining, by the data, a critical dimension uniformity (CDU) and a Bias difference of the entire wafer or wafer.
在本發明的一實施例中,上述方法還可藉由所述表面結構的所述數據推得所述晶片或晶圓的性能與趨勢(trend)。In an embodiment of the invention, the method may further derive the performance and trend of the wafer or wafer by the data of the surface structure.
在本發明的一實施例中,上述晶片的表面結構包括所述晶圓中單次黃光曝光(shot)的範圍內的表面結構。In an embodiment of the invention, the surface structure of the wafer includes a surface structure within a range of a single yellow light shot in the wafer.
本發明的另一實施例之分析晶片或晶圓表面結構的方法,包括取得一晶圓上欲量測晶片(chip)中的多個缺陷區域,再利用儀器得到至少一個缺陷區域的影像,再對所述影像進行影像萃取並轉換為第一電路設計檔。另選取標準影像並轉換為第二電路設計檔,然後比較所述影像與所述標準影像,而得到影像與標準影像之差距。根據所述差距產生所述缺陷區域的線邊緣粗糙度(LER)、線寬粗糙度(LWR)、接觸窗邊緣粗糙度(CER)、關鍵尺寸(CD)、關鍵尺寸偏離值(Bias)與重複性缺陷中至少一種數據。A method for analyzing a surface structure of a wafer or a wafer according to another embodiment of the present invention includes obtaining a plurality of defective regions in a chip on a wafer, and then using the instrument to obtain an image of at least one defective region, and then The image is image extracted and converted into a first circuit design file. Another standard image is selected and converted into a second circuit design file, and then the image is compared with the standard image to obtain a difference between the image and the standard image. Line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), critical dimension deviation (Bias), and repetition of the defect region are generated according to the gap At least one of the data of a sexual defect.
在本發明的另一實施例中,上述取得所述缺陷區域的方法包括對整個晶片進行量測大小差異作圖(wafer mapping)。In another embodiment of the invention, the method of obtaining the defect region includes performing a wafer mapping of the entire wafer.
在本發明的另一實施例中,上述取得所述缺陷區域的方法包括依經驗法則標示出容易發生缺陷的區域。In another embodiment of the present invention, the method of obtaining the defective area includes marking an area where defects are likely to occur according to a rule of thumb.
在本發明的另一實施例中,上述取得所述缺陷區域的方法包括根據設計法則(design rule)資料,設定超過或低於一設定值的區域作為所述缺陷區域。In another embodiment of the present invention, the method of obtaining the defective area includes setting an area exceeding or lower than a set value as the defective area according to design rule data.
在本發明的另一實施例中,上述的方法還可包括在得到全部缺陷區域的數據之後,推得整個晶片的性能與趨勢。In another embodiment of the present invention, the above method may further include deriving the performance and trend of the entire wafer after obtaining data of all defective regions.
在本發明的另一實施例中,上述量測大小差異作圖是依據與每一所述缺陷區域相關的缺陷量測大小差異嚴重性而被彩色編碼的。In another embodiment of the invention, the measurement magnitude difference mapping is color coded based on the severity of the defect measurement size difference associated with each of the defect regions.
本發明的又一實施例之黃光曝光補值的方法,包括利用電子束檢測工具(E-Beam inspection tool)得到曝光後的晶片的表面結構的影像,再對所述影像進行影像萃取並轉換為第一電路設計檔。另選取標準影像並轉換為第二電路設計檔,然後進行補值計算。A method for supplementing the yellow light exposure according to still another embodiment of the present invention comprises: obtaining an image of the surface structure of the exposed wafer by using an E-Beam inspection tool, and performing image extraction and conversion on the image. Design the file for the first circuit. Another standard image is selected and converted to the second circuit design file, and then the complement calculation is performed.
在本發明的又一實施例中,上述影像包括一晶圓中各所述晶片的缺陷區域的影像或所述晶圓中單次黃光曝光(shot)的範圍內的。In still another embodiment of the present invention, the image includes an image of a defect area of each of the wafers in a wafer or a single yellow light exposure in the wafer.
在本發明的各個實施例中,上述得到影像所用的儀器包括關鍵尺寸掃描式電子顯微鏡(CD-SEM)、電子束檢測工具(E-Beam inspection tool)、掃描式電子顯微鏡檢測拍照機臺(SEM review tool)、搭配波長150nm~800nm光源的亮場檢測(Bright field inspection)設備或搭配雷射光源的暗場檢測(laser light source with Dark field inspection)設備。In various embodiments of the present invention, the apparatus for obtaining an image includes a key size scanning electron microscope (CD-SEM), an electron beam inspection tool (E-Beam inspection tool), and a scanning electron microscope detection camera table (SEM). Review tool), Bright field inspection equipment with a wavelength of 150nm ~ 800nm light source or laser light source with Dark field inspection equipment.
在本發明的各個實施例中,上述第一電路設計檔與所述第二電路設計檔為圖形資料系統檔。In various embodiments of the present invention, the first circuit design file and the second circuit design file are graphical data system files.
在本發明的各個實施例中,上述標準影像例如出自設計資料庫、後光學鄰近效應校正(post-OPC)或由模擬器(simulated tool)所轉換的。In various embodiments of the invention, the standard image is derived, for example, from a design database, post optical proximity effect correction (post-OPC), or converted by a simulated tool.
在本發明的各個實施例中,上述影像萃取包括調整背景的灰階或前景的灰階,以萃取出所述影像的二維(2D)影像的輪廓(contours)。In various embodiments of the invention, the image extraction includes adjusting a grayscale of the background or a grayscale of the foreground to extract contours of the two-dimensional (2D) image of the image.
在本發明的各個實施例中,上述影像萃取還可包括當所述影像的對比差異大於一預設值,執行影像灰階均化;且當所述影像的灰階差異大於另一預設值,則將影像分開。In various embodiments of the present invention, the image extraction may further include performing gray scale equalization when the contrast difference of the image is greater than a preset value; and when the grayscale difference of the image is greater than another preset value , separate the images.
在本發明的各個實施例中,上述影像萃取之前還可包括對其中差異之所述影像進行補值。In various embodiments of the present invention, the image extraction may further include supplementing the image in which the difference is made.
基於上述,根據本發明的實施例所述的方法,能精確得到晶片表面具有的二維結構圖案,並且能藉由先一步對整個晶片或晶圓進行量測大小差異作圖(wafer mapping)得到晶片上的所有缺陷區域變化趨勢,而加快取得整個晶片的表面結構之缺陷資訊。Based on the above, according to the method of the embodiment of the present invention, the two-dimensional structure pattern of the wafer surface can be accurately obtained, and the wafer or the wafer can be measured by the wafer mapping method. All defect areas on the wafer change trend, and the defect information of the surface structure of the entire wafer is accelerated.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1是依照本發明之第一實施例的一種量測晶片表面結構的步驟圖。所謂的表面結構是形成在晶片(chip)上的所有可藉由光學或電子顯微鏡取得影像的結構,譬如光阻層的結構、絕緣層的結構、導體層的結構等。同理,形成在整個晶圓(wafer)上的結構亦可藉由相同的方法進行表面結構的量測。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a timing chart showing the surface structure of a wafer in accordance with a first embodiment of the present invention. The so-called surface structure is a structure formed on a chip by which an image can be obtained by an optical or electron microscope, such as a structure of a photoresist layer, a structure of an insulating layer, a structure of a conductor layer, and the like. Similarly, the structure formed on the entire wafer can also be measured by the same method.
首先進行步驟100,利用儀器得到晶片的表面結構的影像,其中所述儀器可以是關鍵尺寸掃描式電子顯微鏡(CD-SEM)、電子束檢測工具(E-Beam inspection tool)、SEM檢測拍照機臺(SEM review tool)、搭配波長150nm~800nm光源的亮場檢測(Bright field inspection)設備或搭配雷射光源的暗場檢測(laser light source with Dark field inspection)設備。如果使用電子束檢測工具則可採用高解析度(例如解析度在5nm以下)的電子束檢測工具,並且在影像輸出時標示座標;或在已知座標下(例如:直接以 Klarf 座標轉換)直接拍照。First, step 100 is performed to obtain an image of the surface structure of the wafer by using an instrument, wherein the instrument can be a key size scanning electron microscope (CD-SEM), an electron beam inspection tool (E-Beam inspection tool), and an SEM detection camera machine. (SEM review tool), Bright field inspection equipment with a wavelength of 150 nm ~ 800 nm light source or a laser light source with Dark field inspection equipment. If an electron beam inspection tool is used, an electron beam inspection tool with a high resolution (for example, a resolution of 5 nm or less) can be used, and the coordinates can be marked at the time of image output; or under a known coordinate (for example, directly converted by Klarf coordinates) Take a photo.
然後,於步驟102中,對影像進行影像萃取(image extraction)並轉換為第一電路設計檔。上述影像萃取能萃取出二維(2D)影像的輪廓(contours)。至於影像萃取的方法可包括邊緣輪廓萃取(Edge contour extraction)、自仿射繪圖系統(Self-Affine mapping system)、自仿射蛇行模式 (Self- Affine snake model)、主動輪廓模式(Active contour model)、最大期望(expectation-maximisation)演算法、主成分分析(Principal component analysis)、層集(level sets)演算法或蒙地卡羅法(Monte Carlo techniques)。而且上述影像萃取的類形可以包括離線(off-line)萃取或線上(on-line)萃取,其中離線萃取能精確得到結構的輪廓,線上萃取則可藉由快速演算而達到即時處理的功效,並且能標示出座標。至於本實施例中的電路設計檔,一般是指用於半導體電路設計(即晶片)之電路設計檔,譬如圖形資料系統(graphic data system)檔,如GDSII檔或為另一種圖形資料系統OASIS 格式亦可被使用。Then, in step 102, the image is image extracted and converted into a first circuit design file. The above image extraction extracts contours of two-dimensional (2D) images. Methods for image extraction may include Edge contour extraction, Self-Affine mapping system, Self-Affine snake model, Active contour model. , expectation-maximisation algorithm, principal component analysis, level sets algorithm or Monte Carlo techniques. Moreover, the above-mentioned image extraction type may include off-line extraction or on-line extraction, wherein off-line extraction can accurately obtain the contour of the structure, and on-line extraction can achieve immediate treatment by rapid calculation. And can mark the coordinates. As for the circuit design file in this embodiment, it generally refers to a circuit design file for a semiconductor circuit design (ie, a wafer), such as a graphic data system file, such as a GDSII file or another graphic data system OASIS format. Can also be used.
另外,針對影像萃取的步驟,可以進一步藉由調整其配方以符合CD-SEM的結果,譬如調整背景的灰階或前景的灰階,即可得到不同的結果,如圖2A與圖2B。圖2A顯示的是背景灰階為20、前景灰階為14之線寬分布統計圖(statistical chart),其平均線寬約為32nm。圖2B顯示的是背景灰階為20、前景灰階為94之線寬分布統計圖,其平均線寬約為40nm。因此,通過改變萃取配方(extraction recipe)能使CDU符合CD-SEM目標(target)或一標準。此外,當影像的對比差異過大(即大於某預設值),可執行影像灰階均化(image gray level equalization);當灰階差異過大(即大於某預設值),可將影像分開。針對灰階正常之影像進行後續萃取動作, 對差異過大之影像群組先進行補值(correction)再進行影像萃取的工作。In addition, for the image extraction step, different results can be obtained by adjusting the formulation to conform to the CD-SEM results, such as adjusting the gray scale of the background or the gray scale of the foreground, as shown in FIG. 2A and FIG. 2B. Figure 2A shows a statistical chart with a background grayscale of 20 and a foreground grayscale of 14 with an average linewidth of about 32 nm. Figure 2B shows a line width distribution graph with a background gray scale of 20 and a foreground gray scale of 94 with an average linewidth of about 40 nm. Therefore, the CDU can be made to meet the CD-SEM target or a standard by changing the extraction recipe. In addition, when the contrast of the image is too large (ie, greater than a certain preset value), image gray level equalization may be performed; when the grayscale difference is too large (ie, greater than a preset value), the image may be separated. The subsequent extraction operation is performed on the image with normal gray scale, and the image group with excessive difference is first corrected and then image extracted.
步驟104則是選取標準影像並轉換為第二電路設計檔,其中第一電路設計檔與第二電路設計檔是相同類型的檔案。而且可以藉由設計資料庫(design database)、後光學鄰近效應校正(post-OPC)定義上述標準影像、或者由模擬器(simulated tool)所轉換得到上述標準影像。步驟104與步驟102之間並無絕對的先後順序。Step 104 is to select a standard image and convert it into a second circuit design file, wherein the first circuit design file and the second circuit design file are the same type of file. Moreover, the standard image can be defined by a design database, post-OPC, or converted by a simulated tool. There is no absolute sequence between step 104 and step 102.
然後在步驟106中,比較影像中的目標(target)與標準影像,而得到兩者的差距。由於步驟102與步驟104中都已經將資訊轉換為相同檔案,所以能夠對表面結構中想要得到資訊的特定目標區域,迅速與標準影像作比較。而且,如果步驟102與步驟104的數據都標示有座標,則可執行更為精確的比較。Then in step 106, the target and the standard image in the image are compared to obtain the difference between the two. Since the information has been converted to the same file in both step 102 and step 104, it is possible to quickly compare the specific target area of the surface structure in which the information is desired to be compared with the standard image. Moreover, if the data of steps 102 and 104 are both marked with coordinates, a more accurate comparison can be performed.
之後進行步驟108,根據上述差距產生表面結構的線邊緣粗糙度(LER)、線寬粗糙度(LWR)、接觸窗邊緣粗糙度(CER)、關鍵尺寸(CD)、關鍵尺寸偏離值(Bias)、3igma、最大值(maximum)、最小值(minimum)等與晶片重複性缺陷(Repeating Defect)中至少一種數據。舉例來說,可以通過post-OPC比較的方式,可比較發現一些得到與目標有差異之重複性缺陷與型態(morphology)。Then, step 108 is performed to generate line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), and critical dimension deviation value (Bias) of the surface structure according to the above difference. At least one of a 3igma, a maximum, a minimum, and the like, and a repeating defect of the wafer. For example, by means of post-OPC comparison, it is possible to compare and find some repetitive defects and morphologies that are different from the target.
得到以上數據後可選擇進行步驟110,藉由上述數據推得晶片的性能與趨勢(trend)。After obtaining the above data, step 110 can be selected, and the performance and trend of the wafer are derived by the above data.
本發明還可應用於黃光曝光補值(correction)的方法。所謂的黃光曝光補值通常是針對歸因於黃光製程導致的缺陷,而對黃光製程參數進行最佳化的動作。一般而言,黃光補值或黃光曝光補值(dose map)所收集的CDU在一個晶片(chip)或一次曝光(Shot)內是小於20 點的CD-SEM量測,在一晶圓中是小於150 點的CD-SEM量測,因此須要建立模式(model)後來做補值的動作。然而,在本發明中可在一個晶片或一次曝光中量到上千點至上萬點,因此可直接做補值的動作或者重新計算OPC資料(OPC data)再製作光罩(re-tape out mask)並不須要建立模式。The present invention is also applicable to a method of yellow light exposure correction. The so-called yellow light exposure compensation is usually an action that optimizes the yellow light process parameters for defects caused by the yellow light process. In general, the CDU collected by the yellow light complement or yellow light exposure map is less than 20 points CD-SEM measurement in one chip or one shot (shot), on a wafer. Medium is a CD-SEM measurement of less than 150 points, so it is necessary to establish a model and then perform a supplementary action. However, in the present invention, it is possible to measure thousands to tens of thousands of points in one wafer or one exposure, so that it is possible to directly perform a supplementary value operation or recalculate OPC data (re-tape out mask). There is no need to establish a model.
將本實施例的步驟100~106用於黃光曝光補值的缺陷檢測過程,來取代目前繁複且冗長的測試分析建立模式步驟。Steps 100-106 of the present embodiment are used for the defect detection process of the yellow light exposure compensation value, instead of the complicated and lengthy test analysis establishment mode step.
由於利用如高解析度(例如解析度在0.1nm~5nm)的電子束檢測工具的儀器,所以能即時得到曝光後的晶片的影像。在這個實施例中可以取得整個晶圓中各個晶片(chip)的缺陷區域影像後或者僅取一次黃光的範圍內的影像(可能包含2~3個晶片的缺陷區域)。然後當整個晶片的影像經過影像萃取(image extraction)後,再進行補值計算,則可達到改善黃光曝光的CDU數值。Since an instrument such as a high-resolution (for example, a resolution of 0.1 nm to 5 nm) electron beam detecting tool is used, an image of the exposed wafer can be obtained immediately. In this embodiment, an image of a defect area of each chip in the entire wafer or an image of only a range of yellow light (which may include a defect area of 2 to 3 wafers) may be obtained. Then, when the image of the entire wafer is image-extracted and then complemented, the CDU value for improving the yellow exposure can be achieved.
在第一實施例中,按照不同訴求,可以利用軟體在處理器中執行下列一種或多種動作: 1. 拍帶有座標位置的SEM照片或已知位置直接進行拍照動作。 1-1.圖像座標位置解碼。 2. 即時圖像輪廓萃取。 3. 能即時與標準目標資料庫布局database做比較並檢查其差異,然後輸出結果。 4. 即時輸出每個影像與標準目標資料庫布局差異。 5. 在收集所有影像後經與目標物(target)比較找出系統的弱點。 6. 再收集所有影像之差異大小後輸出製程容忍範圍窗 (Process window)。 7. 再收集所有影像或影像萃取後輸出整個晶片的關鍵尺寸均勻度(CD uniformity) 。 8. 再收集所有影像或影像萃取後輸出整個晶片的LER與LWR趨勢。 9. 或可收集接觸窗或連接窗所有影像後輸出整個晶片的CER。 10. 輸出偏離值(線寬或間距與標準目標資料庫布局的差異)、3 sigma、最大值(maximum)、最小值(minimum)等。 11. 即時CD測量和LER/ LWR/ CER測量。In the first embodiment, one or more of the following actions can be performed in the processor by the software according to different appeals: 1. Take a SEM photograph with a coordinate position or a known position to directly take a photographing action. 1-1. Image coordinate position decoding. 2. Instant image contour extraction. 3. Instantly compare and check the difference with the standard target database layout database, and then output the results. 4. Instantly output the difference between each image and the standard target database layout. 5. After collecting all the images, compare the target with the target to find the weakness of the system. 6. Collect the difference between all the images and output the Process window. 7. Collect all image or image extraction and output the CD uniformity of the entire wafer. 8. Collect all image or image extraction and output the LER and LWR trend of the entire wafer. 9. The CER of the entire wafer can be output after collecting all the images of the contact window or the connection window. 10. Output deviation value (difference between line width or spacing and standard target database layout), 3 sigma, maximum (maximum), minimum (minimum), etc. 11. Instant CD measurements and LER/LWR/CER measurements.
當表面結構為圓形接觸窗時,經由第一實施例的步驟100得到的CD-SEM影像在經過影像萃取後,可得到如圖3A或圖3B的輪廓圖。圖3A顯示的是較大的圓形接觸窗300,所以其間隔(spacing)比目標302要小;反之,如果影像萃取後的輪廓如圖3B是較小的圓形接觸窗304,則其間隔會比目標302要大。換句話說,可以藉由晶片或晶圓表面結構的間隔之關鍵尺寸(CD)來監測圓形接觸窗的CD值,並將結果顯示於整個晶圓關鍵尺寸差異大小對應圖(wafer mapping),亦可輸出接觸窗面積大小直接比較。When the surface structure is a circular contact window, the CD-SEM image obtained through the step 100 of the first embodiment can be subjected to image extraction to obtain a contour view as shown in FIG. 3A or FIG. 3B. Figure 3A shows a larger circular contact window 300, so its spacing is smaller than the target 302; conversely, if the image extracted contour is smaller than the circular contact window 304 as shown in Figure 3B, the spacing is Will be larger than target 302. In other words, the CD value of the circular contact window can be monitored by the critical dimension (CD) of the wafer or wafer surface structure, and the results are displayed across the wafer's key size difference map. It can also directly compare the size of the contact window.
除了量測圓形接觸窗之外,當晶片的表面結構是圖4所示的電路布局設計時,可藉由第一實施例的影像萃取的步驟102得到表面結構的輪廓400,並與電路布局設計(即標準影像)402比較,能藉由兩者差異產生最大與最小的關鍵尺寸(CD)並進而得到關鍵尺寸均勻度(CDU)、關鍵尺寸偏離值(Bias)、偏離百分比(Bias%), 3 sigma, maximum, minimum等的數據,以及得到LER、LWR、CER等線寬缺陷資訊。由於第一實施例的方法能得到二維影像的清晰輪廓,所以能夠精確得到缺陷發生的部位404,並藉此修正或改變電路布局及其製程參數,以防止電路斷路等問題發生。In addition to measuring the circular contact window, when the surface structure of the wafer is the circuit layout design shown in FIG. 4, the outline 400 of the surface structure can be obtained by the image extraction step 102 of the first embodiment, and the circuit layout Design (ie, standard image) 402 comparison, can produce maximum and minimum critical dimensions (CD) by the difference between the two and thus obtain critical dimension uniformity (CDU), critical dimension deviation (Bias), deviation percentage (Bias%) , 3 sigma, maximum, minimum and other data, as well as LER, LWR, CER and other line width defect information. Since the method of the first embodiment can obtain a clear outline of the two-dimensional image, the portion 404 where the defect occurs can be accurately obtained, and thereby the circuit layout and the process parameters thereof can be corrected or changed to prevent problems such as circuit breaking.
圖5是依照本發明之第二實施例的一種分析晶片表面結構的步驟圖。所謂的表面結構是形成在晶片上的所有可藉由光學或電子顯微鏡取得影像的結構,譬如光阻層的結構、絕緣層的結構、導體層的結構等,且上述結構是分佈在晶圓上在每個晶片(chip, die)重複的結構。Figure 5 is a step diagram showing the analysis of the surface structure of a wafer in accordance with a second embodiment of the present invention. The so-called surface structure is a structure formed on a wafer by which an image can be obtained by an optical or electron microscope, such as a structure of a photoresist layer, a structure of an insulating layer, a structure of a conductor layer, etc., and the above structure is distributed on a wafer. The structure is repeated on each chip (chip, die).
首先進行步驟500,取得一晶圓上欲量測晶片(chip)中的多個缺陷區域。此步驟的實施方式例如對整個晶片進行量測大小差異作圖(wafer mapping)、依經驗法則標示出容易發生缺陷的區域、或者根據設計法則(design rule)資料,設定超過某數值或低於某數值的區域作為缺陷區域。而且,這些缺陷區域可以依據每一部位相關的缺陷(線寬或間距大小)而被彩色編碼。First, step 500 is performed to obtain a plurality of defective regions in a chip to be measured on a wafer. The implementation of this step is, for example, performing a wafer mapping on the entire wafer, marking an area susceptible to defects according to an empirical rule, or setting a value above or below a certain value according to design rule data. The area of the value is used as the defect area. Moreover, these defective areas can be color coded according to the defects (line width or spacing) associated with each part.
然後進行步驟502,利用儀器得到缺陷區域的影像,其中所使用的儀器如第一實施例所述。而且在此步驟可以只對單一缺陷區域進行影像取得,也可以只選擇目標區內的缺陷區域進行影像取得,當然也可以根據需求對所有缺陷區域進行影像取得。Then, step 502 is performed to obtain an image of the defective area using the instrument, wherein the apparatus used is as described in the first embodiment. Moreover, in this step, image acquisition can be performed only on a single defect area, or only the defect area in the target area can be selected for image acquisition. Of course, image acquisition can be performed on all defect areas according to requirements.
然後,於步驟504中,對影像進行影像萃取並轉換為第一電路設計檔,其中電路設計檔是指用於半導體電路設計之電路設計檔,如GDS檔之類的電路設計檔。所述影像萃取則能萃取出二維(2D)影像的輪廓,而其萃取之輪廓大小可依照第一實施例的步驟102或圖2A~2B所示的方式萃取。至於影像萃取的方法與類型可參照第一實施例所述。Then, in step 504, the image is image extracted and converted into a first circuit design file, wherein the circuit design file refers to a circuit design file for a semiconductor circuit design, such as a circuit design file such as a GDS file. The image extraction can extract the outline of the two-dimensional (2D) image, and the extracted outline size can be extracted in the manner shown in step 102 of the first embodiment or FIGS. 2A-2B. As for the method and type of image extraction, reference can be made to the first embodiment.
步驟506是選取標準影像並轉換為第二電路設計檔,其中第一與第二電路設計檔可為相同類型的檔案。至於標準影像例如是藉由設計資料庫、後光學鄰近效應校正(post-OPC)定義、或者由模擬器(simulated tool)轉換的。步驟504與步驟506之間並無絕對的先後順序。Step 506 is to select a standard image and convert it into a second circuit design file, wherein the first and second circuit design files can be the same type of file. The standard image is for example converted by a design database, post optical proximity correction (post-OPC), or converted by a simulated tool. There is no absolute sequence between step 504 and step 506.
然後在步驟508中,比較上述影像與標準影像,而得到兩者的差距。由於步驟504與步驟508中都已經將資訊轉換為相同檔案,所以能夠即時且快速地比較表面結構中的缺陷區域與標準影像。Then in step 508, the image and the standard image are compared to obtain a difference between the two. Since the information has been converted to the same file in both step 504 and step 508, the defect area and the standard image in the surface structure can be compared instantly and quickly.
之後進行步驟510,根據上述差距產生缺陷區域的線邊緣粗糙度(LER)、線寬粗糙度(LWR)、接觸窗邊緣粗糙度(CER)、關鍵尺寸均勻度(CD)、關鍵尺寸偏離值(Bias)、3 sigma、最大值、最小值等與重複性缺陷中至少一種數據。Then, step 510 is performed to generate line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension uniformity (CD), and critical dimension deviation value of the defect region according to the above difference ( Bias), 3 sigma, maximum, minimum, etc., and at least one of the repetitive defects.
得到以上數據後可選擇進行步驟512,藉由缺陷區域的數據後推得整個晶片的性能與趨勢。因為本實施例可選擇先對整個晶片進行量測大小差異作圖,亦即先進行粗步掃描,得到晶片上的所有缺陷區域,因此能加快取得整個晶片的表面結構或特定目標區域之缺陷資訊。After obtaining the above data, step 512 can be selected to derive the performance and trend of the entire wafer by the data of the defect area. Because the embodiment can select the measurement difference difference of the whole wafer first, that is, the coarse step scanning is performed first to obtain all the defect regions on the wafer, thereby speeding up the defect information of obtaining the surface structure of the entire wafer or a specific target area. .
圖6是依照本發明之第三實施例的一種晶片的關鍵尺寸均勻度量測方法。所謂的關鍵尺寸均勻度可以是形成在晶片上的線寬與間距(width/space)的關鍵尺寸均勻度、接觸窗(contact)的關鍵尺寸均勻度、或不規則圖案之線寬與間距或面積等。6 is a diagram of a method for measuring a critical dimension of a wafer in accordance with a third embodiment of the present invention. The so-called critical dimension uniformity may be the critical dimension uniformity of the line width and width formed on the wafer, the critical dimension uniformity of the contact, or the line width and spacing or area of the irregular pattern. Wait.
首先進行步驟600,取得整個晶圓上欲量測晶片(chip)中的多個缺陷區域,其中的「缺陷區域」意指關鍵尺寸均勻度可能不佳的區域或希望量測的區域。至於如何得到這個缺陷區域,可對整個晶圓中關鍵尺寸均勻度差異大小做對應圖(wafer mapping),並依據每一部位的尺寸彩色編碼,以便顯現出晶片中線寬分布與間距分布。另外,也可依經驗法則標示出容易發生關鍵尺寸均勻度可能不佳的幾個區域;或者,根據設計法則(design rule)資料,設定超過某數值或低於某數值的區域作為缺陷區域,譬如線寬低於0.8µm的全部當作待測的缺陷區域。此外,也可以將整個晶片分區,並將每一區域設定為「缺陷區域」進行量測。First, step 600 is performed to obtain a plurality of defect areas in the chip to be measured on the entire wafer, wherein the "defect area" means an area where the critical dimension uniformity may be poor or a region to be measured. As for how to obtain this defect area, the wafer mapping of the key size uniformity difference in the entire wafer can be performed, and color coding is performed according to the size of each part to visualize the line width distribution and the pitch distribution in the wafer. In addition, it is also possible to mark several areas where the critical dimension uniformity may be unfavorable according to the rule of thumb; or, according to the design rule data, set a region exceeding a certain value or below a certain value as a defective area, for example, All of the line widths below 0.8 μm are regarded as defect areas to be tested. In addition, it is also possible to partition the entire wafer and set each area as a "defect area" for measurement.
然後進行步驟602,利用如高解析度(解析度在5nm以下)的電子束檢測工具即時得到缺陷區域的影像;或者依設計已知量測點轉成Klarf檔案以SEM檢測拍照機臺(SEM review tool) 得到缺陷區域的影像。在此步驟可以全面地對上述缺陷區域進行影像取得。Then, step 602 is performed, and an image of the defect area is obtained instantaneously by using an electron beam detecting tool such as a high resolution (resolution below 5 nm); or a Klarf file is converted into a Klarf file by a known design point to detect the camera machine by SEM (SEM review) Tool) Get an image of the defective area. In this step, image acquisition of the above defect area can be performed comprehensively.
舉例來說,如果晶片如圖7A所示有數條導線,則依經驗法則線寬小的區域容易發生關鍵尺寸均勻度不佳,所以標示出四個區域701~704作為待測的缺陷區域。結果在利用電子束檢測工具取像之後,能收集到如圖7B顯示的測試點。由圖7B可知,即使是較小的區域704也能收集到數百點,比從前用CD-SEM只能看晶片(die)中的2~5個點,能獲得精確且即時的結果。然而本發明並不限於此,也可不標示量測區域,而是根據設計法則(design rule)資料,設定超過某數值或低於某數值的區域作為缺陷區域,其量測範圍為影像萃取的所有位置,其中符合上述設定的線寬與間距(width/space)區間都可快速收集。For example, if the wafer has a plurality of wires as shown in FIG. 7A, the region having a small line width is prone to poor uniformity of key dimensions according to the rule of thumb, so that four regions 701 to 704 are marked as the defect regions to be tested. As a result, after the image was taken by the electron beam detecting tool, the test points as shown in Fig. 7B can be collected. As can be seen from Fig. 7B, even a small area 704 can collect hundreds of points, and only two to five points in the die can be viewed with the CD-SEM, and accurate and immediate results can be obtained. However, the present invention is not limited thereto, and may not mark the measurement area, but set a region exceeding a certain value or lower than a certain value as a defect area according to design rule data, and the measurement range is all of the image extraction. The position, in which the line width and space (width/space) range that meets the above settings can be quickly collected.
然後,於步驟604中,進行影像萃取並轉換為第一電路設計檔,其中電路設計檔是指用於半導體電路設計之電路設計檔,如GDS或OASIS檔之類的電路設計檔。至於影像萃取的方法與類型可參照第一實施例所述。Then, in step 604, image extraction is performed and converted into a first circuit design file, wherein the circuit design file refers to a circuit design file for a semiconductor circuit design, such as a circuit design file such as a GDS or an OASIS file. As for the method and type of image extraction, reference can be made to the first embodiment.
步驟606是選取標準影像並轉換為第二電路設計檔,其中第一與第二電路設計檔可為相同類型的檔案。步驟604與步驟606之間並無絕對的先後順序,且如果只是要量第一電路設計檔大小可不須步驟606。通常上述第二電路設計檔為原始電路設計檔或post OPC 模擬(simulate)結果或是原始電路布局設計。Step 606 is to select a standard image and convert it into a second circuit design file, wherein the first and second circuit design files can be the same type of file. There is no absolute sequence between step 604 and step 606, and step 606 is not required if only the first circuit design file size is to be measured. Typically, the second circuit design file described above is the original circuit design file or the post OPC simulation result or the original circuit layout design.
然後在步驟608中,分析影像萃取後的結果以每隔間距0.0001µm ~0.01µm量測方法量測,以得到關鍵尺寸均勻度(CDU)。圖7B所得到的幾千個點的數據能經軟體轉換得到如圖7C所示的間距分布(space distribution)以及圖7D顯示的線寬分布(width distribution)。而且,根據圖7D的結果依不同區域701~704分別顯示,可藉此得到分布曲線圖7E,所以能夠即時且快速地取得CDU,也能得到偏離值差異(Bias difference)。Then, in step 608, the results of the image extraction are analyzed and measured at intervals of 0.0001 μm to 0.01 μm to obtain critical dimension uniformity (CDU). The data of several thousand points obtained in Fig. 7B can be converted by software to obtain a space distribution as shown in Fig. 7C and a line width distribution shown in Fig. 7D. Further, according to the results of FIG. 7D, the different regions 701 to 704 are respectively displayed, whereby the distribution curve 7E can be obtained, so that the CDU can be acquired instantaneously and quickly, and the difference of the difference (Bias difference) can be obtained.
圖8A與圖8B是第三實施例的另一種應用示意圖。圖8A顯示單一晶片(die)中的某一區域800,在此區域800中包含兩條線802與三個間距區域(space)804。如果利用圖5的步驟對區域800進行關鍵尺寸均勻度量測,則可收集到如圖8B顯示的測試點,其中間距能測到507個點、線寬能測到303個點,遠比從前用CD-SEM只能看晶片(die)中的2~5個點能得到更精確且即時的結果。8A and 8B are schematic views of another application of the third embodiment. FIG. 8A shows a region 800 in a single die in which two lines 802 and three spaced spaces 804 are included. If the key size uniform measurement is performed on the area 800 by using the steps of FIG. 5, the test points as shown in FIG. 8B can be collected, wherein the interval can measure 507 points and the line width can measure 303 points, far more than before. Using CD-SEM can only see 2 to 5 points in the die to get more accurate and immediate results.
圖9A~圖9C是第三實施例的再一種應用示意圖。圖9A是經過高解析度的電子束檢測工具即時得到一晶圓中各個晶片(chip)的缺陷區域影像後,通過影像萃取後經軟體轉換得到的晶圓中關鍵尺寸均勻度差異大小做對應圖(wafer mapping)。在圖9A中是以灰階顯示其數據差異,但實際上是用擴散色彩(diffuse color)來標示,因此能輕易地觀察出差異點。同時,可將整個晶片的線寬分布轉換為統計圖(statistical chart),如圖9B。由圖9B可得到線寬不符合設計資料庫的數值,譬如圖9B右邊圈起來的是顯示超過46的部分,可對應得到如圖9C所示的整個晶圓中關鍵尺寸均勻度對應圖。並由上述步驟得到晶圓在中央與邊緣的線寬變大的趨勢。同理,整個晶圓的間距分布(space distribution)與趨勢也能用同樣的方式得到。9A to 9C are still another application diagram of the third embodiment. FIG. 9A is a diagram showing the difference in the size uniformity of the wafers obtained by the software conversion after image extraction and the image of the defective area of each chip in a wafer after the high-resolution electron beam detecting tool is obtained. (wafer mapping). In Fig. 9A, the data difference is displayed in gray scale, but it is actually marked by a diffuse color, so that the difference point can be easily observed. At the same time, the linewidth distribution of the entire wafer can be converted into a statistical chart, as shown in FIG. 9B. It can be seen from FIG. 9B that the line width does not conform to the value of the design database, and the portion circled on the right side of FIG. 9B is a portion showing more than 46, which can correspond to the key size uniformity map in the entire wafer as shown in FIG. 9C. And by the above steps, the line width of the wafer at the center and the edge becomes larger. Similarly, the space distribution and trend of the entire wafer can be obtained in the same way.
圖10是第三實施例的又一種應用示意圖。在圖10的情形,可利用圖5的步驟502取得影像後,於步驟504~508中,經由影像萃取得到圓形接觸窗洞的寬度,並根據這些數據得到圓形接觸窗洞的CDU或接觸窗之面積;抑或直接量接觸窗洞的直徑與間隔。Fig. 10 is a schematic view showing still another application of the third embodiment. In the case of FIG. 10, after obtaining the image by using step 502 of FIG. 5, in steps 504-508, the width of the circular contact hole is obtained by image extraction, and according to the data, the CDU or the contact window of the circular contact hole is obtained. Area; or direct contact with the diameter and spacing of the window.
綜上所述,根據本發明的實施例,不但能以高解析度的取像儀器得到奈米世代半導體的表面結構,還可結合多種演算法取得如圓形接觸窗之類的二維影像清晰輪廓。另外根據本發明的實施例也可以藉由初步掃描先行得到整個晶片的缺陷區域,並對晶片的特定區域或者整個晶片之上的表面結構作分析,所以能比傳統只用CD-SEM進行影像取得的方式更為快速地獲得整個晶片的結構分析。此外,本發明能快速收集到大量的檢測點,所以能獲得精確且即時的結果。而且本發明還可應用於黃光曝光補值的缺陷檢測過程,藉此取代目前繁複且冗長的測試分析建立模式步驟。In summary, according to the embodiment of the present invention, the surface structure of the nano generation semiconductor can be obtained not only by the high-resolution image capturing instrument, but also the two-dimensional image such as the circular contact window can be obtained by combining various algorithms. profile. In addition, according to the embodiment of the present invention, the defect area of the entire wafer can be obtained by the preliminary scanning, and the surface structure of the specific area of the wafer or the entire wafer can be analyzed, so that the image can be obtained only by CD-SEM. The way to get the structural analysis of the entire wafer is faster. In addition, the present invention can quickly collect a large number of detection points, so that accurate and immediate results can be obtained. Moreover, the present invention can also be applied to a defect detection process for yellow light exposure compensation, thereby replacing the current complicated and lengthy test analysis establishment mode step.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100~110、500~512、600~608‧‧‧步驟
300、304‧‧‧圓形接觸窗
302‧‧‧目標
400‧‧‧輪廓
402‧‧‧電路布局設計
404‧‧‧部位
701~704、800‧‧‧區域
802‧‧‧線
804‧‧‧間距區域100~110, 500~512, 600~608‧‧‧ steps
300, 304‧‧‧ circular contact windows
302‧‧‧ Target
400‧‧‧ contour
402‧‧‧Circuit layout design
404‧‧‧ parts
701~704, 800‧‧‧ areas
802‧‧‧ line
804‧‧‧ spacing area
圖1是依照本發明之第一實施例的一種量測晶片表面結構的步驟圖。 圖2A與圖2B分別是背景灰階相同但前景灰階不同的線寬分布統計圖(statistical chart)。 圖3A代表接觸窗洞與洞間之間距小於標準設計檔(有較大的接觸窗洞)的輪廓圖。 圖3B代表接觸窗洞與洞間之間距大於標準設計檔(有較小的接觸窗洞)的輪廓圖。 圖4是經由第一實施例得到的電路布局設計(design)與影像輪廓的比較圖。 圖5是依照本發明之第二實施例的一種分析晶片表面結構的步驟圖。 圖6是依照本發明之第三實施例的一種晶片的關鍵尺寸均勻度量測方法。 圖7A是第三實施例的部份晶片布局,標註著不同的欲量測區域701、702、703和704。 圖7B顯示不同缺陷區域的測試點樹目條狀圖。 圖7C是缺陷區域的間距分布圖。 圖7D是缺陷區域的線寬分布圖。 圖7E是標示出不同缺陷區域的線寬分布圖。 圖8A是第三實施例的另外部份晶片布局及標註著欲量測區域。 圖8B顯示圖8A之缺陷區域的測試點樹目條狀圖。 圖9A是整個晶圓進行量測大小差異對應圖(wafer mapping)。 圖9B顯示圖9A之晶片的線寬分布圖。 圖9C是整個晶片中線寬過大的區域的晶圓差異大小對應圖。 圖10顯示的是圓形接觸窗洞。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a timing chart showing the surface structure of a wafer in accordance with a first embodiment of the present invention. 2A and 2B are respectively a statistical chart of line widths in which the background gray levels are the same but the foreground gray levels are different. Figure 3A shows a profile of the distance between the contact window and the hole that is smaller than the standard design file (with a larger contact window). Figure 3B represents a contour view of the distance between the contact window and the hole being greater than the standard design (with smaller contact holes). 4 is a comparison diagram of a circuit layout design and an image profile obtained through the first embodiment. Figure 5 is a step diagram showing the analysis of the surface structure of a wafer in accordance with a second embodiment of the present invention. 6 is a diagram of a method for measuring a critical dimension of a wafer in accordance with a third embodiment of the present invention. Figure 7A is a partial wafer layout of a third embodiment, labeled with different areas 701, 702, 703, and 704. Figure 7B shows a bar graph of test points in different defect areas. Fig. 7C is a distribution diagram of the pitch of the defective area. Fig. 7D is a line width distribution map of the defect area. Fig. 7E is a line width distribution diagram indicating different defect regions. Fig. 8A is another portion of the wafer layout of the third embodiment and the area to be measured. Figure 8B shows a bar graph of test points in the defect area of Figure 8A. Figure 9A is a wafer mapping of the entire wafer for measurement size difference. Figure 9B shows a line width profile of the wafer of Figure 9A. Fig. 9C is a wafer difference size map of an area where the line width is too large in the entire wafer. Figure 10 shows a circular contact window.
100~110‧‧‧步驟 100~110‧‧‧Steps
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