TW201519396A - Semiconductor package with package-on-package stacking capability and method of manufacturing the same - Google Patents

Semiconductor package with package-on-package stacking capability and method of manufacturing the same Download PDF

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Publication number
TW201519396A
TW201519396A TW103139082A TW103139082A TW201519396A TW 201519396 A TW201519396 A TW 201519396A TW 103139082 A TW103139082 A TW 103139082A TW 103139082 A TW103139082 A TW 103139082A TW 201519396 A TW201519396 A TW 201519396A
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Taiwan
Prior art keywords
interposer
metal
wafer
build
circuit
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TW103139082A
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Chinese (zh)
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TWI593076B (en
Inventor
Charles W C Lin
Chia-Chung Wang
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Bridge Semiconductor Corp
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Publication of TW201519396A publication Critical patent/TW201519396A/en
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Publication of TWI593076B publication Critical patent/TWI593076B/en

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Abstract

The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides primary fan-out routing and a CTE-match interface for the chip.

Description

具有堆疊式封裝能力之半導體封裝件及其製作方法 Semiconductor package with stacked package capability and manufacturing method thereof

本發明是關於一種具有堆疊式封裝能力之半導體封裝件，尤指一種具有內建散熱座之可堆疊式半導體封裝件及其製造方法，其中該內建散熱座係用於嵌埋晶片。 The present invention relates to a semiconductor package having a stacked package capability, and more particularly to a stackable semiconductor package having a built-in heat sink and a method of fabricating the same, wherein the built-in heat sink is used to embed a wafer.

為了整合行動、通訊以及運算功能，半導體封裝產業面臨極大的散熱、電性以及可靠度挑戰。儘管在文獻中已報導許多堆疊式封裝組體，但該些組體仍然存在許多性能不足的問題。舉例來說，美國專利公開號No.2013/0249106及美國專利案號No.8,438,727、8,410,614中所揭露之堆疊式封裝組體，因為其中嵌埋晶片所產生之熱無法藉由熱絕緣材料例如層壓材或模製化合物適當地散逸，因此可能會造成性能衰減問題。 In order to integrate operations, communications, and computing functions, the semiconductor packaging industry faces enormous thermal, electrical, and reliability challenges. Although many stacked package assemblies have been reported in the literature, there are still many performance deficiencies in these groups. For example, the stacked package assembly disclosed in U.S. Patent Publication No. 2013/0249106 and U.S. Patent Nos. 8,438,727 and 8,410,614, because the heat generated by embedding the wafer cannot be thermally insulated by a material such as a layer. The press or molding compound is properly dissipated and may cause performance degradation problems.

美國專利案號No.5,432,677、6,590,291、6,909,054以及8,410,614中所揭露之堆疊式封裝組體，其係使用雷射或光顯像製程於嵌埋晶片之I/O墊上直接形成微盲孔，以電性連接晶片與增層電路。然而，隨著晶片製造技術的進步，晶片之I/O墊數目持續地增加，造成I/O墊之間隔(間距)減小。因此，使用微盲孔之技術會因為微盲孔彼此非常靠近，而導致相 鄰微盲孔短路。 The stacked package assembly disclosed in U.S. Patent Nos. 5,432,677, 6, 590, 291, 6, 909, 054, and 8,410, 614, which uses a laser or optical imaging process to form a micro-blind hole directly on the I/O pad of the embedded wafer. The connection between the wafer and the build-up circuit. However, as wafer fabrication techniques advance, the number of I/O pads of the wafer continues to increase, resulting in a reduction in the spacing (pitch) of the I/O pads. Therefore, the technique of using micro-blind holes can cause phase because the micro-blind holes are very close to each other. Short-circuited adjacent micro-blind holes.

上述可堆疊式組體之製造方法會造成另一嚴重之缺點是在 封膠或層壓製程時，會造成嵌埋晶片之位移。如美國專利案號No.8,501,544中描述之晶片位移會造成不完全之微盲孔金屬化，其劣化電性連接之品質，因此降低組體之可靠度及生產良率。 Another serious disadvantage of the above-described stackable stack manufacturing method is that During the sealing or lamination process, the displacement of the embedded wafer is caused. Wafer displacement as described in U.S. Patent No. 8,501,544 causes incomplete micro-blind hole metallization which degrades the quality of the electrical connections, thereby reducing the reliability and yield of the assembly.

為了上述理由及以下所述之其他理由，目前亟需發展一種用 於互連嵌埋晶片之新裝置與方法，其無須使用位於I/O墊上之微盲孔，以改善晶片之可靠度，並且不需使用熱絕緣材料(模製化合物或層壓材)封膠晶片，以避免晶片過熱而造成晶片可靠度及電性效能的重大問題。 For the above reasons and other reasons as described below, there is an urgent need to develop a use New devices and methods for interconnecting embedded wafers eliminate the need for micro-blind holes on I/O pads to improve wafer reliability and eliminate the need for thermal insulating materials (molding compounds or laminates) Wafers, to avoid overheating of the wafer, cause significant problems with wafer reliability and electrical performance.

本發明之主要目的係提供一種用於堆疊式封裝 (package-on-package)之半導體封裝件，其中一晶片係藉由複數個凸塊互連至低熱膨脹係數(coefficient of thermal expansion，CTE)之中介層，以解決晶片與增層電路間熱膨脹係數不匹配以及位置辨識問題，藉以改善半導體封裝件之生產良率及可靠度。 The main object of the present invention is to provide a package for stacking (Package-on-package) semiconductor package in which a wafer is interconnected by a plurality of bumps to a low coefficient of thermal expansion (CTE) interposer to solve the thermal expansion coefficient between the wafer and the build-up circuit Mismatch and location identification issues to improve the yield and reliability of semiconductor packages.

本發明之另一目的係提供一種用於堆疊式封裝之半導體封 裝件，其中一晶片-中介層堆疊次組體係貼附至一金屬散熱座，並使該金屬散熱座之一凹穴罩蓋該晶片，以有效地散逸晶片所產生之熱，藉以改善半導體封裝件之信號完整性及電性效能。 Another object of the present invention is to provide a semiconductor package for stacked packages The package, wherein a wafer-interposer stack sub-system is attached to a metal heat sink, and a recess of the metal heat sink covers the wafer to effectively dissipate heat generated by the wafer, thereby improving the semiconductor package Signal integrity and electrical performance.

依據上述及其他目的，本發明提出一具有堆疊式封裝能力之 半導體封裝件，其包括一晶片、一中介層、一黏著劑、一金屬散熱座、雙重增層電路、以及複數個披覆穿孔。該晶片係藉由複數個凸塊電性耦接至 該中介層，並且嵌埋於該金屬散熱座之一凹穴中。該雙重增層電路係為分別設置於該封裝件相反兩面之頂部增層電路及底部增層電路，並且藉由該些披覆穿孔相互電性連接，俾使該封裝件具有堆疊能力。另一半導體封裝件則可設置於該封裝件之頂部增層電路或底部增層電路上，以形成一堆疊式封裝組體。 According to the above and other objects, the present invention provides a stacked package capability The semiconductor package includes a wafer, an interposer, an adhesive, a metal heat sink, a dual build-up circuit, and a plurality of cladding vias. The chip is electrically coupled to the plurality of bumps to The interposer is embedded in a recess of the metal heat sink. The double build-up circuit is a top build-up circuit and a bottom build-up circuit respectively disposed on opposite sides of the package, and is electrically connected to each other by the through-holes, so that the package has a stacking capability. Another semiconductor package can be disposed on the top build-up circuit or the bottom build-up circuit of the package to form a stacked package body.

在本發明之一實施態樣中，本發明提供一種具有堆疊式封裝 能力之半導體封裝件之製作方法，包括以下步驟：提供一晶片；提供一中介層，其包含一第一表面、與該第一表面相反之一第二表面、該第一表面上之複數個第一接觸墊、該第二表面上之複數個第二接觸墊、以及電性耦接該些第一接觸墊與該些第二接觸墊之複數個貫孔；藉由複數個凸塊電性耦接該晶片至該中介層之該些第二接觸墊，以形成一晶片-中介層堆疊次組體；提供一含金屬載體，其具有一第一表面、一相反之第二表面、以及形成於該第一表面之一凹穴；使用一黏著劑貼附該晶片-中介層堆疊次組體至該含金屬載體，並使該晶片***該凹穴中，且該中介層側向延伸於該凹穴外；於該晶片-中介層堆疊次組體貼附至該含金屬載體後，於該中介層之該第一表面上形成一第一增層電路，其中該第一增層電路係藉由該第一增層電路之複數個第一導電盲孔電性耦接至該中介層之該些第一接觸墊；移除該含金屬載體之選定部分，以形成一金屬散熱座，該金屬散熱座係為該含金屬載體之第一剩餘部分，其係罩蓋該凹穴內之該晶片，並且具有對應於該含金屬載體之該第一表面的一第一表面及一相反之第二表面；形成一芯層，其係側向覆蓋該金屬散熱座之側壁；於該金屬散熱座之該第二表面上及該芯層上形成一第二增層電路，其中該第二增層電路較佳包括用於電性 及熱性耦接至該金屬散熱座之複數個第二導電盲孔；以及形成延伸穿過該芯層之複數個披覆穿孔，以提供該第一增層電路與該第二增層電路間之電性及熱性連接。 In an embodiment of the invention, the invention provides a stacked package A method of fabricating a semiconductor package, comprising the steps of: providing a wafer; providing an interposer comprising a first surface, a second surface opposite the first surface, and a plurality of the first surface a contact pad, a plurality of second contact pads on the second surface, and a plurality of through holes electrically coupled to the first contact pads and the second contact pads; electrically coupled by a plurality of bumps Connecting the wafer to the second contact pads of the interposer to form a wafer-interposer stack sub-assembly; providing a metal-containing carrier having a first surface, an opposite second surface, and formed on a recess of the first surface; attaching the wafer-interposer stack sub-assembly to the metal-containing carrier using an adhesive, and inserting the wafer into the recess, and the interposer extends laterally to the recess After the wafer-interposer stack sub-assembly is attached to the metal-containing carrier, a first build-up circuit is formed on the first surface of the interposer, wherein the first build-up circuit is a plurality of first conductive blind holes of the first build-up circuit The first contact pads are coupled to the interposer; the selected portion of the metal-containing carrier is removed to form a metal heat sink, and the metal heat sink is the first remaining portion of the metal-containing carrier Covering the wafer in the recess and having a first surface and an opposite second surface corresponding to the first surface of the metal-containing carrier; forming a core layer laterally covering the metal heat sink a second build-up circuit formed on the second surface of the metal heat sink and the core layer, wherein the second build-up circuit preferably includes an electrical And a plurality of second conductive blind vias thermally coupled to the metal heat sink; and forming a plurality of cladding vias extending through the core layer to provide a connection between the first build-up circuit and the second build-up circuit Electrical and thermal connections.

在本發明之另一實施態樣中，本發明提供一種具有堆疊式封 裝能力之半導體封裝件之另一製作方法，包括以下步驟：提供一晶片；提供一中介層，其包含一第一表面、與該第一表面相反之一第二表面、該第一表面上之複數個第一接觸墊、該第二表面上之複數個第二接觸墊、以及電性耦接該些第一接觸墊與該些第二接觸墊之複數個貫孔；藉由複數個凸塊電性耦接該晶片至該中介層之該些第二接觸墊，以形成一晶片-中介層堆疊次組體；提供一含金屬載體，其具有一第一表面、一相反之第二表面、以及形成於該第一表面之一凹穴；於該含金屬載體之第一表面與第二表面間形成延伸穿過該含金屬載體之複數個貫穿開口；使用一黏著劑貼附該晶片-中介層堆疊次組體至該含金屬載體，並使該晶片***該凹穴中，且該中介層側向延伸於該凹穴外；於該晶片-中介層堆疊次組體貼附至該含金屬載體後，於該中介層之該第一表面上形成一第一增層電路，其中該第一增層電路係藉由該第一增層電路之複數個第一導電盲孔電性耦接至該中介層之該些第一接觸墊；於該含金屬載體之該第二表面上形成一第二增層電路，其中該第二增層電路較佳包括用於電性及熱性耦接至該含金屬載體之複數個第二導電盲孔；以及形成延伸穿過該些貫穿開口之複數個披覆穿孔，以提供該第一增層電路與該第二增層電路間之電性及熱性連接。 In another embodiment of the present invention, the present invention provides a stacked seal Another method of fabricating a semiconductor package includes the steps of: providing a wafer; providing an interposer comprising a first surface, a second surface opposite the first surface, and the first surface a plurality of first contact pads, a plurality of second contact pads on the second surface, and a plurality of through holes electrically coupled to the first contact pads and the second contact pads; Electrically coupling the wafer to the second contact pads of the interposer to form a wafer-interposer stack sub-assembly; providing a metal-containing carrier having a first surface and an opposite second surface, And forming a recess in the first surface; forming a plurality of through openings extending through the metal-containing carrier between the first surface and the second surface of the metal-containing carrier; attaching the wafer using an adhesive-intermediate Stacking the sub-assembly to the metal-containing carrier, and inserting the wafer into the recess, and the interposer extends laterally outside the recess; and attaching the sub-assembly of the wafer-interposer to the metal-containing carrier After the first in the intermediation layer Forming a first build-up circuit on the surface, wherein the first build-up circuit is electrically coupled to the first contact pads of the interposer by a plurality of first conductive vias of the first build-up circuit; Forming a second build-up circuit on the second surface of the metal-containing carrier, wherein the second build-up circuit preferably includes a plurality of second conductive blind vias for electrically and thermally coupling to the metal-containing carrier And forming a plurality of cladding perforations extending through the through openings to provide an electrical and thermal connection between the first build-up circuit and the second build-up circuit.

除非特別描述或必須依序發生之步驟，上述步驟之順序並無 限制於以上所列，且可根據所需設計而變化或重新安排。 Unless otherwise stated or steps that must occur in sequence, the order of the above steps is not Limited to the above list, and can be changed or rearranged according to the desired design.

在本發明之再一實施態樣中，本發明提供一種藉由上述方法 製成之具有堆疊式封裝能力之半導體封裝件，其包括：一晶片、一中介層、一黏著劑、一金屬散熱座、一第一增層電路、一第二增層電路、以及複數個披覆穿孔，其中(i)該晶片係藉由複數個凸塊以電性耦接至該中介層之該些第二接觸墊，並且置放於該金屬散熱座之該凹穴中；(ii)該中介層側向延伸於該凹穴外，並使該中介層之該第二表面貼附至該金屬散熱座之一平坦表面，該平坦表面係鄰接該凹穴之入口且自該凹穴之入口側向延伸；(iii)該黏著劑係夾置於該晶片與該金屬散熱座間、以及該中介層與該金屬散熱座間；(iv)該第一增層電路係設置於該中介層之該第一表面上，並且藉由該第一增層電路之複數個第一導電盲孔電性耦接至該中介層之複數個第一接觸墊；(v)該第二增層電路設置於該金屬散熱座之第二表面上，並且較佳係藉由該第二增層電路之複數個第二導電盲孔電性及熱性耦接至該金屬散熱座；以及(vi)該些披覆穿孔之第一端延伸至該第一增層電路，且第二端延伸至該第二增層電路，以提供該第一增層電路與該第二增層電路間之電性與熱性連接。 In still another embodiment of the present invention, the present invention provides a method by the above A semiconductor package having a stacked package capability, comprising: a wafer, an interposer, an adhesive, a metal heat sink, a first build-up circuit, a second build-up circuit, and a plurality of drapes The through hole is formed by (i) the wafer being electrically coupled to the second contact pads of the interposer by a plurality of bumps and placed in the recess of the metal heat sink; (ii) The interposer extends laterally beyond the recess and the second surface of the interposer is attached to a flat surface of the metal heat sink, the flat surface adjoining the entrance of the recess and from the recess The inlet extends laterally; (iii) the adhesive is sandwiched between the wafer and the metal heat sink, and between the interposer and the metal heat sink; (iv) the first build-up circuit is disposed on the interposer And a plurality of first contact pads electrically coupled to the interposer by the plurality of first conductive vias of the first build-up circuit; (v) the second build-up circuit is disposed on the first surface a second surface of the metal heat sink, and preferably by a plurality of the second build-up circuits The second conductive blind via is electrically and thermally coupled to the metal heat sink; and (vi) the first end of the coated via extends to the first build-up circuit, and the second end extends to the second increase a layer circuit to provide an electrical and thermal connection between the first build-up circuit and the second build-up circuit.

本發明用於堆疊式封裝之半導體封裝件製作方法具有許多 優點。舉例來說，先形成晶片-中介層堆疊次組體後，再貼附至含金屬載體，其可確保電性連接晶片，因此可避免於微盲孔製程中會遭遇的未連接接觸墊之問題。藉由晶片-中介層堆疊次組體將晶片***凹穴中是特別具有優勢的，其原因在於，在製程中無須嚴格控制凹穴之形狀或深度，或是無須嚴格控制用來接合晶片之黏著劑用量。此外，以兩步驟形成連線於嵌埋式晶片之互連基板是具有益處的，其原因在於，中介層可提供初級扇出路由以 及熱膨脹係數匹配之介面，而增層電路則提供上封裝件與下封裝件間的進一步扇出路由及水平互連。 The method for fabricating a semiconductor package for stacked package of the present invention has many advantage. For example, after the wafer-interposer stack sub-assembly is formed, it is attached to the metal-containing carrier, which ensures electrical connection of the wafer, thereby avoiding the problem of unconnected contact pads encountered in the micro-blind hole process. . Inserting the wafer into the recess by the wafer-interposer stack sub-assembly is particularly advantageous because the shape or depth of the recess is not strictly controlled during the process, or the bonding of the wafer is not strictly controlled. Dosage amount. Furthermore, it is advantageous to form the interconnect substrate wired to the embedded wafer in two steps because the interposer can provide a primary fanout route. And the thermal expansion coefficient matching interface, and the build-up circuit provides further fan-out routing and horizontal interconnection between the upper package and the lower package.

本發明之上述及其他特徵與優點可藉由下述較佳實施例之詳細敘述更加清楚明瞭。 The above and other features and advantages of the present invention will become more apparent from the detailed description of the preferred embodiments.

10‧‧‧晶片-中介層堆疊次組體 10‧‧‧ wafer-interposer stack subgroup

100‧‧‧堆疊式封裝組體 100‧‧‧Stacked package body

110‧‧‧半導體封裝件 110‧‧‧Semiconductor package

120‧‧‧半導體封裝件 120‧‧‧Semiconductor package

11‧‧‧中介層面板 11‧‧‧Intermediary panel

11’‧‧‧中介層 11’‧‧‧Intermediary

111‧‧‧第一表面 111‧‧‧ first surface

112‧‧‧第一接觸墊 112‧‧‧First contact pad

113‧‧‧第二表面 113‧‧‧ second surface

114‧‧‧第二接觸墊 114‧‧‧Second contact pad

116‧‧‧貫孔 116‧‧‧through holes

13‧‧‧晶片 13‧‧‧ wafer

131‧‧‧主動面 131‧‧‧Active surface

132‧‧‧I/O墊 132‧‧‧I/O mat

133‧‧‧非主動面 133‧‧‧Inactive surface

15‧‧‧凸塊 15‧‧‧Bumps

16‧‧‧底部填充材料 16‧‧‧Unfilled material

191‧‧‧第一黏著劑 191‧‧‧First Adhesive

200‧‧‧堆疊式封裝組體 200‧‧‧Stacked package body

193‧‧‧第二黏著劑 193‧‧‧Second Adhesive

194‧‧‧黏著劑 194‧‧‧Adhesive

20‧‧‧含金屬載體 20‧‧‧Metal carrier

21‧‧‧金屬板 21‧‧‧Metal plates

210‧‧‧半導體封裝件 210‧‧‧Semiconductor package

211‧‧‧第一表面 211‧‧‧ first surface

212‧‧‧平坦表面 212‧‧‧flat surface

213‧‧‧第二表面 213‧‧‧ second surface

215‧‧‧凹穴 215‧‧ ‧ pocket

217‧‧‧定位件 217‧‧‧ Positioning parts

219‧‧‧貫穿開口 219‧‧‧through opening

22‧‧‧金屬散熱座 22‧‧‧Metal heat sink

220‧‧‧半導體封裝件 220‧‧‧Semiconductor package

23‧‧‧介電層 23‧‧‧Dielectric layer

24‧‧‧金屬柱 24‧‧‧ metal column

25‧‧‧金屬層 25‧‧‧metal layer

251‧‧‧開口 251‧‧‧ openings

257‧‧‧定位件 257‧‧‧ Positioning parts

26‧‧‧芯層 26‧‧‧ core layer

261‧‧‧第一表面 261‧‧‧ first surface

263‧‧‧第二表面 263‧‧‧ second surface

300‧‧‧堆疊式封裝組體 300‧‧‧Stacked package body

301‧‧‧第一增層電路 301‧‧‧First build-up circuit

302‧‧‧第二增層電路 302‧‧‧Second layered circuit

31‧‧‧第一金屬板 31‧‧‧First metal plate

31’‧‧‧第一披覆層 31’‧‧‧First coating

310‧‧‧半導體封裝件 310‧‧‧Semiconductor package

311‧‧‧平衡層 311‧‧‧Equilibrium

312‧‧‧第一絕緣層 312‧‧‧First insulation

313、314‧‧‧第一盲孔 313, 314‧‧‧ first blind hole

315‧‧‧第一導線 315‧‧‧First wire

317、318‧‧‧第一導電盲孔 317, 318‧‧‧ first conductive blind hole

32‧‧‧第二金屬板 32‧‧‧Second metal plate

32’‧‧‧第二披覆層 32’‧‧‧Second coating

320‧‧‧半導體封裝件 320‧‧‧Semiconductor package

322‧‧‧第二絕緣層 322‧‧‧Second insulation

323‧‧‧第二盲孔 323‧‧‧Second blind hole

325‧‧‧第二導線 325‧‧‧second wire

327‧‧‧第二導電盲孔 327‧‧‧Second conductive blind hole

33‧‧‧第三金屬板 33‧‧‧ Third metal plate

33’‧‧‧第三披覆層 33’‧‧‧ Third coating

332‧‧‧第三絕緣層 332‧‧‧ third insulation

333‧‧‧第三盲孔 333‧‧‧ third blind hole

335‧‧‧第三導線 335‧‧‧ Third wire

337‧‧‧第三導電盲孔 337‧‧‧3rd conductive blind hole

34‧‧‧第四金屬板 34‧‧‧fourth metal plate

34’‧‧‧第四披覆層 34’‧‧‧Four coating

342‧‧‧第四絕緣層 342‧‧‧fourth insulation

343‧‧‧第四盲孔 343‧‧‧4th blind hole

345‧‧‧第四導線 345‧‧‧fourth wire

347‧‧‧第四導電盲孔 347‧‧‧4th conductive blind hole

400‧‧‧堆疊式封裝組體 400‧‧‧Stacked package body

401‧‧‧穿孔 401‧‧‧Perforation

403‧‧‧連接層 403‧‧‧Connection layer

41‧‧‧焊料遮罩 41‧‧‧ solder mask

410‧‧‧半導體封裝件 410‧‧‧Semiconductor package

411‧‧‧披覆穿孔 411‧‧‧Cover perforation

415‧‧‧絕緣性填充物 415‧‧‧Insulating filler

420‧‧‧半導體封裝件 420‧‧‧Semiconductor package

51‧‧‧焊球 51‧‧‧ solder balls

參考隨附圖式，本發明可藉由下述較佳實施例之詳細敘述更加清楚明瞭，其中：圖1及2分別為本發明之第一實施態樣中，中介層面板之剖視及頂部立體視圖；圖3為本發明之第一實施態樣中，將凸塊設置於晶片上之剖視圖；圖4及5分別為本發明之第一實施態樣中，圖3晶片電性耦接至圖1及2中介層面板之面板組體剖視及頂部立體視圖；圖6及7分別為本發明之第一實施態樣中，圖4及5之面板組體切割後之剖視及頂部立體視圖；圖8及9分別為本發明之第一實施態樣中，對應於圖6及7切離單元之晶片-中介層堆疊次組體的剖視及頂部立體視圖；圖10及11分別為本發明之第一實施態樣中，含金屬載體之剖視及底部立體視圖；圖12及13分別為本發明之第一實施態樣中，將黏著劑塗佈於圖10及11含金屬載體上之剖視及底部立體視圖；圖14及15分別為本發明之第一實施態樣中，將圖8及9之晶片-中介層堆疊次組體貼附至圖12及13含金屬載體之剖視及底部立體視圖； 圖16及17分別為本發明之第一實施態樣中，圖14及15之結構上具有另一黏著劑之剖視及底部立體視圖；圖18及19分別為本發明之第一實施態樣中，自圖16及17之結構移除過剩黏著劑後之剖視及底部立體視圖；圖20及21分別為本發明之第一實施態樣中，將平衡層、第一絕緣層、以及第一金屬板設置於圖18及19結構上之剖視及頂部立體視圖；圖22及23分別為本發明之第一實施態樣中，自圖20及21之結構形成金屬散熱座後之剖視及頂部立體視圖；圖24及25分別為本發明之第一實施態樣中，將芯層設置於圖22及23結構上之剖視及頂部立體視圖；圖26為本發明之第一實施態樣中，第二絕緣層及第二金屬板設置於圖24結構上之剖視圖；圖27為本發明之第一實施態樣中，於圖26之結構形成盲孔後之剖視圖；圖28為本發明之第一實施態樣中，於圖27之結構形成穿孔後之剖視圖；圖29為本發明之第一實施態樣中，於圖28之結構形成導線及披覆穿孔後之剖視圖；圖30為本發明之第一實施態樣中，第三絕緣層及第三金屬板設置於圖29結構上之剖視圖；圖31為本發明之第一實施態樣中，於圖30之結構形成盲孔後之剖視圖；圖32為本發明之第一實施態樣中，於圖31之結構形成導線，以製作完成半導體封裝件之剖視圖；圖33為本發明之第一實施態樣中，於圖32之半導體封裝件上設置另一 半導體封裝件之堆疊式封裝組體剖視圖；圖34為本發明之第二實施態樣中，含金屬載體之剖視圖；圖35為本發明之第二實施態樣中，將黏著劑塗佈於圖34含金屬載體上之剖視圖；圖36為本發明之第二實施態樣中，圖8晶片-中介層堆疊次組體貼附至圖35含金屬載體之剖視圖；圖37為本發明之第二實施態樣中，圖36之結構具有另一黏著劑之剖視圖；圖38為本發明之第二實施態樣中，自圖37之結構移除過剩黏著劑後之剖視圖；圖39為本發明之第二實施態樣中，平衡層、第一絕緣層、以及第一金屬板設置於圖38結構上之剖視圖；圖40為本發明之第二實施態樣中，自圖38結構形成金屬散熱座與金屬柱後之剖視圖；圖41為本發明之第二實施態樣中，芯層、第二絕緣層、以及第二金屬板設置於圖40結構上之剖視圖；圖42為本發明之第二實施態樣中，於圖41結構形成盲孔與穿孔後之剖視圖；圖43為本發明之第二實施態樣中，於圖42結構形成導線及披覆穿孔，以製作完成一半導體封裝件之剖視圖；圖44為本發明之第二實施態樣中，於圖43半導體封裝件上設置另一半導體封裝件之堆疊式封裝組體剖視圖； 圖45為本發明之第三實施態樣中，含金屬載體之剖視圖；圖46為本發明之第三實施態樣中，於圖45含金屬載體形成貫穿開口後之剖視圖；圖47為本發明之第三實施態樣中，圖8晶片-中介層堆疊次組體貼附至圖46含金屬載體之剖視圖；圖48為本發明之第三實施態樣中，圖47結構具有另一黏著劑之剖視圖；圖49為本發明之第三實施態樣中，自圖48之結構移除過剩黏著劑後之剖視圖；圖50為本發明之第三實施態樣中，平衡層、第一絕緣層、以及第一金屬板設置於圖49結構上之剖視圖；圖51為本發明之第三實施態樣中，於圖50結構形成盲孔與穿孔後之剖視圖；圖52為本發明之第三實施態樣中，於圖51結構形成導線及披覆穿孔，以製作完成一半導體封裝件之剖視圖；圖53為本發明之第三實施態樣中，於圖52半導體封裝件上設置另一半導體封裝件之堆疊式封裝組體剖視圖；圖54為本發明之第四實施態樣中，層壓基板之剖視圖；圖55為本發明之第四實施態樣中，圖54之層壓基板具有定位件之剖視圖；圖56為本發明之第四實施態樣中，具有開口之層壓基板剖視圖；圖57為本發明之第四實施態樣中，圖56之層壓基板具有定位件之剖視圖； 圖58為本發明之第四實施態樣中，於圖55之層壓基板形成凹穴，以製作完成含金屬載體之剖視圖；圖59為本發明之第四實施態樣中，於圖58之含金屬載體形成貫穿開口後之剖視圖；圖60為本發明之第四實施態樣中，晶片-中介層堆疊次組體貼附至圖59金屬散熱座之剖視圖；圖61為本發明之第四實施態樣中，平衡層、第一絕緣層、以及第一金屬板設置於圖60結構上之剖視圖；圖62為本發明之第四實施態樣中，於圖61之結構形成盲孔與穿孔後之剖視圖；圖63為本發明之第四實施態樣中，於圖62之結構形成導線及披覆穿孔，以製作完成一半導體封裝件之剖視圖；圖64為本發明之第四實施態樣中，於圖63半導體封裝件上設置另一半導體封裝件之堆疊式封裝組體剖視圖。 The invention will be more apparent from the following detailed description of the preferred embodiments, wherein: FIGS. 1 and 2 are respectively a cross-sectional view and top of an interposer panel in a first embodiment of the present invention. 3 is a cross-sectional view showing a bump disposed on a wafer in the first embodiment of the present invention; FIGS. 4 and 5 are respectively a first embodiment of the present invention, and the wafer of FIG. 3 is electrically coupled to 1 and 2 are a cross-sectional view of the panel of the interposer panel and a top perspective view; FIGS. 6 and 7 are respectively a cross-sectional view and a top stereo of the panel assembly of FIGS. 4 and 5 in the first embodiment of the present invention. 8 and 9 are respectively a cross-sectional view and a top perspective view of a wafer-interposer stack sub-group corresponding to the excision unit of FIGS. 6 and 7 in the first embodiment of the present invention; FIGS. 10 and 11 are respectively In a first embodiment of the present invention, a cross-sectional view of a metal-containing carrier and a bottom perspective view; and FIGS. 12 and 13 respectively illustrate a first embodiment of the present invention, wherein an adhesive is applied to the metal carrier of FIGS. 10 and 11. The upper cross-sectional view and the bottom perspective view; FIGS. 14 and 15 are respectively the first embodiment of the present invention, 8 and 9 of the wafer - the interposer is attached to the stacked subgroup considerate 12 and 13 of a metal-containing cross-sectional view and a bottom perspective view of the carrier; 16 and 17 are respectively a cross-sectional view and a bottom perspective view of another embodiment of the present invention in the first embodiment of the present invention; FIGS. 18 and 19 are respectively a first embodiment of the present invention; , a cross-sectional view and a bottom perspective view of the structure of FIGS. 16 and 17 after removing the excess adhesive; FIGS. 20 and 21 are respectively a balance layer, a first insulating layer, and a first embodiment of the present invention. A cross-sectional view and a top perspective view of a metal plate disposed on the structures of FIGS. 18 and 19; and FIGS. 22 and 23 are cross-sectional views of the first embodiment of the present invention after forming a metal heat sink from the structures of FIGS. 20 and 21, respectively. And the top perspective view; FIG. 24 and FIG. 25 are respectively a cross-sectional view and a top perspective view of the core layer disposed on the structure of FIGS. 22 and 23 in the first embodiment of the present invention; FIG. 26 is a first embodiment of the present invention; In the sample, the second insulating layer and the second metal plate are disposed on the structure of FIG. 24; FIG. 27 is a cross-sectional view showing the blind hole in the structure of FIG. 26 according to the first embodiment of the present invention; In a first embodiment of the invention, a cross-sectional view of the structure of Fig. 27 after perforation is formed; In a first embodiment of the present invention, a cross-sectional view of the structure of FIG. 28 after forming a wire and a perforated hole is shown; FIG. 30 is a first embodiment of the present invention, wherein the third insulating layer and the third metal plate are disposed in FIG. FIG. 31 is a cross-sectional view showing the structure of FIG. 30 after forming a blind hole in the first embodiment of the present invention; FIG. 32 is a view showing the structure of FIG. To make a cross-sectional view of the completed semiconductor package; FIG. 33 is a first embodiment of the present invention, and another semiconductor package is provided on FIG. Figure 34 is a cross-sectional view of a stacked package of a semiconductor package; Figure 34 is a cross-sectional view of a metal-containing carrier in a second embodiment of the present invention; and Figure 35 is a second embodiment of the present invention, the adhesive is applied to the figure 34 is a cross-sectional view of a metal-containing carrier; FIG. 36 is a cross-sectional view of the wafer-interposer stack sub-assembly of FIG. 8 attached to the metal-containing carrier of FIG. 35 in the second embodiment of the present invention; FIG. 37 is a second embodiment of the present invention. In the aspect, the structure of FIG. 36 has a cross-sectional view of another adhesive; FIG. 38 is a cross-sectional view of the second embodiment of the present invention, after removing the excess adhesive from the structure of FIG. 37; In the second embodiment, the balance layer, the first insulating layer, and the first metal plate are disposed on the structure of FIG. 38; FIG. 40 is a second embodiment of the present invention, and the metal heat sink is formed from the structure of FIG. FIG. 41 is a cross-sectional view showing the core layer, the second insulating layer, and the second metal plate in the structure of FIG. 40 in the second embodiment of the present invention; FIG. 42 is a second embodiment of the present invention. In the aspect, the blind hole and the perforation are formed in the structure of Fig. 41. FIG. 43 is a cross-sectional view showing a semiconductor package formed by forming a wire and a perforation in FIG. 42 according to a second embodiment of the present invention; FIG. 44 is a second embodiment of the present invention. FIG. 43 is a cross-sectional view showing a stacked package body of another semiconductor package disposed on the semiconductor package; Figure 45 is a cross-sectional view showing a metal-containing carrier in a third embodiment of the present invention; and Figure 46 is a cross-sectional view showing a metal carrier in FIG. 45 after forming a through-opening in the third embodiment of the present invention; In a third embodiment, the wafer-interposer stack sub-assembly of FIG. 8 is attached to the metal-containing carrier of FIG. 46; FIG. 48 is a third embodiment of the present invention, and the structure of FIG. 47 has another adhesive. Figure 49 is a cross-sectional view of the third embodiment of the present invention, after removing excess adhesive from the structure of Figure 48; Figure 50 is a third embodiment of the present invention, the balance layer, the first insulating layer, And a cross-sectional view of the first metal plate disposed on the structure of FIG. 49; FIG. 51 is a cross-sectional view showing the blind hole and the perforation in the structure of FIG. 50 in the third embodiment of the present invention; FIG. 52 is a third embodiment of the present invention. In the example, a conductive line is formed in the structure of FIG. 51 and a through-hole is formed to complete a cross-sectional view of a semiconductor package. FIG. 53 is a third embodiment of the present invention, and another semiconductor package is disposed on the semiconductor package of FIG. A cross-sectional view of a stacked package body; 54 is a cross-sectional view of a laminated substrate in a fourth embodiment of the present invention; FIG. 55 is a cross-sectional view of the laminated substrate of FIG. 54 having a positioning member in a fourth embodiment of the present invention; 4 is a cross-sectional view of a laminated substrate having an opening; FIG. 57 is a cross-sectional view of the laminated substrate of FIG. 56 having a positioning member in a fourth embodiment of the present invention; Figure 58 is a cross-sectional view showing the forming of the metal-containing carrier in the laminated substrate of Figure 55 in the fourth embodiment of the present invention; Figure 59 is a fourth embodiment of the present invention, in Figure 58 FIG. 60 is a cross-sectional view showing the wafer-interposer stack sub-assembly attached to the metal heat sink of FIG. 59 in the fourth embodiment of the present invention; FIG. 61 is a fourth embodiment of the present invention. In the aspect, the balance layer, the first insulating layer, and the first metal plate are disposed in a cross-sectional view of the structure of FIG. 60; FIG. 62 is a fourth embodiment of the present invention, after the blind hole and the perforation are formed in the structure of FIG. FIG. 63 is a cross-sectional view showing a semiconductor package formed by forming a wire and a perforation in the structure of FIG. 62 according to the fourth embodiment of the present invention; FIG. 64 is a fourth embodiment of the present invention. A stacked package body cross-sectional view of another semiconductor package is disposed on the semiconductor package of FIG.

在下文中，將提供實施例以詳細說明本發明之實施態樣。本發明之優點以及功效將藉由本發明所揭露之內容而更為顯著。在此說明所附之圖式係簡化過且做為例示用。圖式中所示之元件數量、形狀及尺寸可依據實際情況而進行修改，且元件的配置可能更為複雜。本發明中也可進行其他方面之實踐或應用，且不偏離本發明所定義之精神及範疇之條件下，可進行各種變化以及調整。 In the following, examples will be provided to explain in detail embodiments of the invention. The advantages and effects of the present invention will be more apparent by the disclosure of the present invention. The drawings attached hereto are simplified and are used for illustration. The number, shape and size of the components shown in the drawings can be modified as the case may be, and the configuration of the components may be more complicated. Other variations and modifications can be made without departing from the spirit and scope of the invention as defined in the invention.

[實施例1] [Example 1]

圖1-32為本發明一實施態樣中，一種用於堆疊式封裝之半導 體封裝件製作方法圖，其包括一中介層、複數個晶片、一金屬散熱座、一芯層、雙重增層電路、以及複數個披覆穿孔。 FIG. 1-32 shows a semi-conductor for a stacked package according to an embodiment of the invention. A method for fabricating a body package includes an interposer, a plurality of wafers, a metal heat sink, a core layer, a dual build-up circuit, and a plurality of cladding vias.

如圖32所示，應用於堆疊式封裝之半導體封裝件110包括中 介層11’、晶片13、金屬散熱座22、芯層26、第一增層電路301、第二增層電路302、以及披覆穿孔411。使用第一黏著劑191及第二黏著劑193將中介層11’及晶片13貼附至金屬散熱座22，並使晶片13嵌埋於金屬散熱座22之凹穴215中。芯層26側向覆蓋金屬散熱座22之側壁。第一增層電路301由下方覆蓋中介層11’及芯層26，並且藉由第一導電盲孔317電性耦接至中介層11’之第一接觸墊112。第二增層電路302由上方覆蓋金屬散熱座22及芯層26，並且藉由第二導電盲孔327電性及熱性耦接至金屬散熱座22。披覆穿孔411係與金屬散熱座22彼此保持距離，並且提供第一增層電路301及第二增層電路302間之電性及熱性連接。 As shown in FIG. 32, the semiconductor package 110 applied to the stacked package includes The dielectric layer 11', the wafer 13, the metal heat sink 22, the core layer 26, the first build-up circuit 301, the second build-up circuit 302, and the cladding via 411. The interposer 11' and the wafer 13 are attached to the metal heat sink 22 using the first adhesive 191 and the second adhesive 193, and the wafer 13 is embedded in the recess 215 of the metal heat sink 22. The core layer 26 laterally covers the sidewalls of the metal heat sink 22. The first build-up circuit 301 covers the interposer 11' and the core layer 26 from below, and is electrically coupled to the first contact pad 112 of the interposer 11' by the first conductive via 317. The second build-up circuit 302 covers the metal heat sink 22 and the core layer 26 from above, and is electrically and thermally coupled to the metal heat sink 22 via the second conductive via 327. The cladding perforations 411 are spaced from the metal heat sinks 22 and provide electrical and thermal connections between the first build-up circuitry 301 and the second build-up circuitry 302.

圖1、3、4、6、8為本發明一實施態樣之晶片-中介層堆疊次組體製程剖視圖，圖2、5、7、9分別為對應圖1、4、6、8之頂部立體視圖。 1, 3, 4, 6, and 8 are cross-sectional views of a wafer-interposer stack sub-group process according to an embodiment of the present invention, and Figures 2, 5, 7, and 9 correspond to the tops of Figures 1, 4, 6, and 8, respectively. Stereo view.

圖1及2分別為中介層面板11之剖視及頂部立體視圖，其包括第一表面111、與第一表面111相反之第二表面113、第一表面111上之第一接觸墊112、第二表面113上之第二接觸墊114、以及電性耦接第一接觸墊112與第二接觸墊114之貫孔116。中介層面板11可為矽中介層、玻璃中介層、陶瓷中介層、或石墨中介層，其包含導線圖案，且該導線圖案係由第二接觸墊114之細微間距扇出至第一接觸墊112之粗間距。 1 and 2 are a cross-sectional and top perspective view, respectively, of the interposer panel 11 including a first surface 111, a second surface 113 opposite the first surface 111, a first contact pad 112 on the first surface 111, and a first The second contact pads 114 on the two surfaces 113 and the through holes 116 electrically coupled to the first contact pads 112 and the second contact pads 114. The interposer panel 11 may be a germanium interposer, a glass interposer, a ceramic interposer, or a graphite interposer, including a wire pattern, and the wire pattern is fanned out to the first contact pad 112 by the fine pitch of the second contact pad 114. The coarse pitch.

圖3為凸塊15設置於晶片13上之剖視圖。晶片13包括主動面 131、與主動面131相反之非主動面133、以及位於主動面131上之I/O墊132。凸塊15係設置於晶片13之I/O墊132上，並且該凸塊可為錫凸柱、金凸柱、或銅凸柱。 3 is a cross-sectional view showing the bump 15 disposed on the wafer 13. Wafer 13 includes an active surface 131. An inactive surface 133 opposite the active surface 131 and an I/O pad 132 on the active surface 131. The bump 15 is disposed on the I/O pad 132 of the wafer 13, and the bump may be a tin bump, a gold bump, or a copper bump.

圖4及5分別為面板組體(panel-scale assembly)之剖視圖及頂部立體視圖，其係將複數個晶片13電性耦接至中介層面板11。藉由熱壓、迴焊、或熱超音波接合技術，可將晶片13經由凸塊15電性耦接至中介層面板11之第二接觸墊114。或者，可先沉積凸塊15於中介層面板11之第二接觸墊114上，然後晶片13再藉由凸塊15電性耦接至中介層面板11。此外，可選擇性地進一步提供底部填充材料16以填充中介層面板11與晶片13間之間隙。 4 and 5 are a cross-sectional view and a top perspective view, respectively, of a panel-scale assembly, which electrically couple a plurality of wafers 13 to the interposer panel 11. The wafer 13 can be electrically coupled to the second contact pad 114 of the interposer panel 11 via the bumps 15 by hot pressing, reflow, or thermal ultrasonic bonding. Alternatively, the bumps 15 may be deposited on the second contact pads 114 of the interposer panel 11, and then the wafers 13 are electrically coupled to the interposer panel 11 by the bumps 15. Further, an underfill material 16 may optionally be further provided to fill the gap between the interposer panel 11 and the wafer 13.

圖6及7分別為面板組體切割成個別單件之剖視圖及頂部立體視圖。面板組體沿著切割線“L”被單離成個別的晶片-中介層堆疊次組體(chip-on-interposer subassembly)10。 6 and 7 are respectively a cross-sectional view and a top perspective view of the panel assembly cut into individual pieces. The panel stacks are separated into individual wafer-on-interposer subassemblies 10 along the cutting line "L".

圖8及9分別為個別的晶片-中介層堆疊次組體10之剖視圖及頂部立體視圖。在此圖中，晶片-中介層堆疊次組體10包括兩個晶片13，其係電性耦接至切割後之中介層11’上。當中介層11’之第一接觸墊112之尺寸及墊間之間隔設計為比晶片之I/O墊132大時，中介層11’能提供晶片13之初級扇出路由，以確保下一級增層電路互連具有較高之生產良率。此外，於互連至下一級互連結構前，中介層11’也提供相鄰晶片13間之主要電性連接。 8 and 9 are a cross-sectional view and a top perspective view, respectively, of individual wafer-interposer stack sub-assemblies 10. In this figure, the wafer-interposer stack sub-assembly 10 includes two wafers 13 electrically coupled to the diced interposer 11'. When the size of the first contact pad 112 of the interposer 11' and the spacing between the pads are designed to be larger than the I/O pad 132 of the wafer, the interposer 11' can provide a primary fan-out route of the wafer 13 to ensure the next level increase. Layer circuit interconnections have a high production yield. In addition, the interposer 11' also provides a primary electrical connection between adjacent wafers 13 prior to interconnection to the next level of interconnect structure.

圖10及11分別為含金屬載體20之剖視圖及底部立體視圖，其係有第一表面211、相反之第二表面213、以及凹穴215。可藉由於金屬板21中形成凹穴215以提供含金屬載體20。金屬板21之厚度可於0.1毫米至10毫米 之範圍內，並且可由銅、鋁、不銹鋼、或其合金所製成。在此實施態樣中，金屬板21係為厚度2毫米之銅板。每一凹穴215包括位於第一表面211之入口，並且每一凹穴可以具有不同之尺寸及深度。凹穴之深度可於0.05毫米至1.0毫米之範圍內。在此例示中，凹穴215之深度係為0.16毫米(以容納0.1毫米晶片及0.05毫米導電凸塊)。 10 and 11 are a cross-sectional view and a bottom perspective view, respectively, of a metal-containing carrier 20 having a first surface 211, an opposite second surface 213, and a pocket 215. The metal-containing carrier 20 can be provided by forming a recess 215 in the metal plate 21. The thickness of the metal plate 21 can be from 0.1 mm to 10 mm Within the scope of, and may be made of copper, aluminum, stainless steel, or alloys thereof. In this embodiment, the metal plate 21 is a copper plate having a thickness of 2 mm. Each pocket 215 includes an inlet at the first surface 211, and each pocket can have a different size and depth. The depth of the pocket can range from 0.05 mm to 1.0 mm. In this illustration, the depth of the pocket 215 is 0.16 mm (to accommodate 0.1 mm wafers and 0.05 mm conductive bumps).

圖12及13為含金屬載體20之凹穴215內塗有第一黏著劑191 之剖視及底部立體視圖。第一黏著劑191通常係為導熱黏著劑，並且塗佈於凹穴215之底部上。 12 and 13 are the first adhesive 191 coated in the recess 215 of the metal-containing carrier 20. The cross section and the bottom perspective view. The first adhesive 191 is typically a thermally conductive adhesive and is applied to the bottom of the pocket 215.

圖14及15分別為晶片-中介層堆疊次組體10藉由第一黏著劑 191貼附至含金屬載體20之剖視圖及底部立體視圖。晶片13係***凹穴215中，並且中介層11’位於凹穴215外，同時中介層11’與含金屬載體20之外圍邊緣保持距離。 14 and 15 are wafer-interposer stacked sub-groups 10, respectively, by a first adhesive 191 is attached to a cross-sectional view and a bottom perspective view of the metal-containing carrier 20. The wafer 13 is inserted into the recess 215, and the interposer 11' is located outside the recess 215 while the interposer 11' is spaced from the peripheral edge of the metal-containing carrier 20.

圖16及17分別為第二黏著劑193填充至中介層11’與含金屬 載體20之間，並進一步延伸進入凹穴215中之剖視圖及底部立體視圖。第二黏著劑193通常為電性絕緣之底部填充材料，其塗佈於中介層11’與含金屬載體20之間，且填入凹穴215之剩餘空間中。因此，第一黏著劑191提供晶片13及含金屬載體20間之機械性接合及熱性連接，並且第二黏著劑193提供晶片13及含金屬載體20間、以及中介層11’及含金屬載體20間之機械性接合。 16 and 17 are filled with the second adhesive 193 to the interposer 11' and the metal-containing layer, respectively. A cross-sectional view and a bottom perspective view of the carrier 20 and further extending into the pocket 215. The second adhesive 193 is typically an electrically insulating underfill material that is applied between the interposer 11' and the metal-containing carrier 20 and fills the remaining space of the recess 215. Therefore, the first adhesive 191 provides mechanical bonding and thermal connection between the wafer 13 and the metal-containing carrier 20, and the second adhesive 193 provides between the wafer 13 and the metal-containing carrier 20, and the interposer 11' and the metal-containing carrier 20. Mechanical joint between.

圖18及19分別為將流出中介層11’與含金屬載體20間之過剩 黏著劑移除後之剖視圖及底部立體視圖。或者，可省略此移除過剩黏著劑之步驟，據此過剩之黏著劑變成隨後增層電路之一部分。 Figures 18 and 19 show the excess between the outgoing interposer 11' and the metal-containing carrier 20, respectively. A cross-sectional view and a bottom perspective view of the adhesive after removal. Alternatively, the step of removing the excess adhesive may be omitted, whereby the excess adhesive becomes part of the subsequent build-up circuitry.

圖20及21分別為朝向下方向層壓/塗佈平衡層311、第一絕緣 層312、以及第一金屬板31於中介層11’及含金屬載體20上之剖視圖及頂部立體視圖。平衡層311係接觸含金屬載體20，且自含金屬載體20朝向下方向延伸，並且側向覆蓋、圍繞及共形塗佈中介層11’之側壁，同時自中介層11’側向延伸至該結構之外圍邊緣。第一絕緣層312係接觸中介層11’之第一表面111及平衡層311，且朝向下方向覆蓋及側向延伸於中介層11’之第一表面111及平衡層311上。第一金屬板31係接觸第一絕緣層312，且由下方覆蓋第一絕緣層312。在此實施態樣中，平衡層311具有0.2毫米之厚度，其係接近中介層11’之厚度，並且第一絕緣層312通常具有50微米之厚度。平衡層311及第一絕緣層312可為環氧樹脂、玻璃環氧樹脂、聚醯亞胺、及其類似物所製成。在此實施態樣中，第一金屬板31係為具有25微米厚度之銅層。 20 and 21 respectively laminate/coat the balance layer 311 toward the downward direction, and the first insulation A layer 312 and a cross-sectional view and a top perspective view of the first metal plate 31 on the interposer 11' and the metal-containing carrier 20. The balancing layer 311 is in contact with the metal-containing carrier 20 and extends from the metal-containing carrier 20 in a downward direction, and laterally covers, surrounds, and conformally coats the sidewalls of the interposer 11' while extending laterally from the interposer 11' to the The outer edge of the structure. The first insulating layer 312 contacts the first surface 111 of the interposer 11' and the balancing layer 311, and covers and extends laterally on the first surface 111 and the balancing layer 311 of the interposer 11'. The first metal plate 31 contacts the first insulating layer 312 and covers the first insulating layer 312 from below. In this embodiment, the balance layer 311 has a thickness of 0.2 mm which is close to the thickness of the interposer 11', and the first insulating layer 312 usually has a thickness of 50 μm. The balance layer 311 and the first insulating layer 312 may be made of epoxy resin, glass epoxy resin, polyimide, and the like. In this embodiment, the first metal plate 31 is a copper layer having a thickness of 25 μm.

圖22及23分別為將含金屬載體20之選定部分移除，以形成金 屬散熱座22之剖視及頂部立體視圖，其係藉由微影技術及濕蝕刻移除含金屬載體20之選定部分。含金屬載體20之剩餘部分係相當於金屬散熱座22，其係由上方覆蓋及罩蓋晶片13於其凹穴215中。 Figures 22 and 23 respectively remove selected portions of the metal-containing carrier 20 to form gold It is a cross-sectional and top perspective view of the heat sink 22 that removes selected portions of the metal-containing carrier 20 by lithography and wet etching. The remainder of the metal-containing carrier 20 corresponds to the metal heat sink 22 which is covered by the top and covers the wafer 13 in its recess 215.

圖24及25分別為芯層26層壓/塗佈於平衡層311上方之剖視 圖及頂部立體視圖。芯層26係接觸平衡層311以及自平衡層311朝向上方向延伸，並且側向覆蓋、圍繞及共形塗佈金屬散熱座22之側壁，同時自金屬散熱座22側向延伸至該結構之外圍邊緣。在此實施態樣中，芯層26具有0.2mm之厚度，其係接近金屬散熱座22之厚度，並且可為環氧樹脂、玻璃環氧樹脂、聚醯亞胺、及其類似物所製成。因此，芯層26具有與金屬散熱座22之第一表面211齊平的第一表面261，以及與金屬散熱座22之第二表面213齊平的第二表面263。 24 and 25 are cross-sectional views of the core layer 26 laminated/coated above the balance layer 311, respectively. Figure and top perspective view. The core layer 26 extends in contact with the balancing layer 311 and the self-balancing layer 311, and laterally covers, surrounds, and conformally coats the sidewalls of the metal heat sink 22 while extending laterally from the metal heat sink 22 to the periphery of the structure. edge. In this embodiment, the core layer 26 has a thickness of 0.2 mm, which is close to the thickness of the metal heat sink 22, and can be made of epoxy resin, glass epoxy resin, polyimide, and the like. . Thus, the core layer 26 has a first surface 261 that is flush with the first surface 211 of the metal heat sink 22 and a second surface 263 that is flush with the second surface 213 of the metal heat sink 22.

圖26為第二絕緣層322及第二金屬板32朝向上方向層壓/塗 佈在金屬散熱座22及芯層26上之剖視圖。第二絕緣層322係接觸金屬散熱座22之第二表面213以及芯層26之第二表面263、並且朝向上方向覆蓋且側向延伸於金屬散熱座22之第二表面213以及芯層26之第二表面263上。第二金屬板32係接觸第二絕緣層322，且由上方覆蓋第二絕緣層322。在此實施態樣中，第二絕緣層322通常具有50微米之厚度，並且可為環氧樹脂、玻璃環氧樹脂、聚醯亞胺、及其類似物所製成。本實施態樣之第二金屬板32係為具有25微米厚度之銅層。 Figure 26 is a second insulating layer 322 and a second metal plate 32 laminated/coated in the upward direction A cross-sectional view of the metal heat sink 22 and the core layer 26. The second insulating layer 322 contacts the second surface 213 of the metal heat sink 22 and the second surface 263 of the core layer 26 and covers the second surface 213 of the metal heat sink 22 and the core layer 26 On the second surface 263. The second metal plate 32 contacts the second insulating layer 322 and covers the second insulating layer 322 from above. In this embodiment, the second insulating layer 322 typically has a thickness of 50 microns and may be made of epoxy resin, glass epoxy resin, polyimide, and the like. The second metal plate 32 of this embodiment is a copper layer having a thickness of 25 μm.

圖27為形成第一盲孔313及第二盲孔323後之剖視圖。第一盲 孔313延伸穿過第一金屬板31及第一絕緣層312，並且對準中介層11’之第一接觸墊112。第二盲孔323延伸穿透第二金屬板32及第二絕緣層322，並且對準金屬散熱座22之選定部分。第一盲孔313及第二盲孔323可藉由各種技術形成，其包括雷射鑽孔、電漿蝕刻、及微影技術，且通常具有50微米之直徑。可使用脈衝雷射提高雷射鑽孔效能。或者，可使用金屬光罩以及雷射光束。舉例來說，可先蝕刻銅板以製造一金屬窗口後再照射雷射光束。較佳為，第一盲孔313及第二盲孔323係使用相同方式形成，且具有相同尺寸。 FIG. 27 is a cross-sectional view showing the first blind via 313 and the second blind via 323. First blind The hole 313 extends through the first metal plate 31 and the first insulating layer 312 and is aligned with the first contact pad 112 of the interposer 11'. The second blind via 323 extends through the second metal plate 32 and the second insulating layer 322 and is aligned with selected portions of the metal heat sink 22. The first blind via 313 and the second blind via 323 can be formed by a variety of techniques including laser drilling, plasma etching, and lithography, and typically have a diameter of 50 microns. Pulsed lasers can be used to improve laser drilling performance. Alternatively, a metal reticle and a laser beam can be used. For example, the copper plate can be etched first to create a metal window and then irradiate the laser beam. Preferably, the first blind hole 313 and the second blind hole 323 are formed in the same manner and have the same size.

圖28為形成穿孔401後之剖視圖。穿孔401朝垂直方向延伸穿 過第一金屬板31、第一絕緣層312、平衡層311、芯層26、第二絕緣層322、以及第二金屬板32。穿孔401可藉由機械鑽孔形成，但亦可藉由其他技術製作，例如雷射鑽孔、電漿蝕刻、或電漿蝕刻與濕蝕刻之組合。 Figure 28 is a cross-sectional view showing the formation of the perforations 401. The perforation 401 extends in a vertical direction The first metal plate 31, the first insulating layer 312, the balancing layer 311, the core layer 26, the second insulating layer 322, and the second metal plate 32 are passed through. The perforations 401 can be formed by mechanical drilling, but can also be fabricated by other techniques, such as laser drilling, plasma etching, or a combination of plasma etching and wet etching.

參照圖29，藉由沉積第一披覆層31’於第一金屬板31上及第 一盲孔313中，沉積第二披覆層32’於第二金屬板32上及第二盲孔323中，然 後圖案化第一及第二金屬板31、32以及其上之第一及第二披覆層31’、32’，以分別形成位於第一絕緣層312及第二絕緣層322上之第一導線315及第二導線325。或者，當前述製程中未有第一及第二金屬板31、32層壓於第一及第二絕緣層312、322上時，第一及第二絕緣層312、322可直接金屬化以形成第一及第二導線315、325。第一導線315自第一絕緣層312朝向下方向延伸，同時側向延伸於第一絕緣層312上，並且朝向上方向延伸進入第一盲孔313中，以形成直接接觸中介層11’之第一接觸墊112的第一導電盲孔317。因此，第一導線315可提供X及Y方向的水平信號路由以及穿過第一盲孔313的垂直路由，以作為中介層11’的信號連接。第二導線325自第二絕緣層322朝向上方向延伸，同時側向延伸於第二絕緣層322上，並且朝向下方向延伸進入第二盲孔323中，以形成直接接觸金屬散熱座22選定部分之第二導電盲孔327。據此，第二導線325可提供金屬散熱座22之接地連接以及散熱途徑。 Referring to FIG. 29, the first cladding layer 31' is deposited on the first metal plate 31 and In a blind via 313, a second cladding layer 32' is deposited on the second metal plate 32 and the second blind via 323, The first and second metal plates 31, 32 and the first and second cladding layers 31', 32' thereon are patterned to form first on the first insulating layer 312 and the second insulating layer 322, respectively. Wire 315 and second wire 325. Alternatively, when the first and second metal plates 31, 32 are not laminated on the first and second insulating layers 312, 322 in the foregoing process, the first and second insulating layers 312, 322 may be directly metallized to form First and second wires 315, 325. The first wire 315 extends from the first insulating layer 312 toward the lower direction while extending laterally on the first insulating layer 312 and extends upward into the first blind via 313 to form a direct contact interposer 11' A first conductive blind via 317 of a contact pad 112. Thus, the first wire 315 can provide horizontal signal routing in the X and Y directions and a vertical route through the first blind hole 313 to serve as a signal connection for the interposer 11'. The second wire 325 extends upward from the second insulating layer 322 while extending laterally on the second insulating layer 322 and extends into the second blind via 323 in a downward direction to form a direct contact with the selected portion of the metal heat sink 22 The second conductive blind hole 327. Accordingly, the second wire 325 can provide a ground connection of the metal heat sink 22 and a heat dissipation path.

圖29亦揭示沉積連接層403於穿孔401中，以提供披覆穿孔 411。連接層403之形狀係為中空管，其係側向覆蓋穿孔401之內側壁，並且朝垂直方向延伸以電性連接第一導線315及第二導線325。或者，連接層403可填滿穿孔401。在連接層403填滿穿孔401之態樣中，披覆穿孔411係為金屬柱，且穿孔401中沒有容納絕緣性填充物之空間。 Figure 29 also discloses depositing a tie layer 403 in the perforation 401 to provide a perforation 411. The connecting layer 403 is shaped as a hollow tube that laterally covers the inner side wall of the through hole 401 and extends in a vertical direction to electrically connect the first wire 315 and the second wire 325. Alternatively, the tie layer 403 can fill the perforations 401. In the aspect in which the connection layer 403 fills the perforations 401, the cladding perforations 411 are metal posts, and there is no space in the perforations 401 for accommodating the insulating filler.

第一及第二披覆層31’、32’以及連接層403可藉由各種技術 形成單層或多層，其包括電鍍、無電電鍍、蒸鍍、濺鍍、及其組合。舉例來說，首先藉由將該結構浸入活化劑溶液中，使第一及第二絕緣層312、322與無電鍍銅產生觸媒反應，接著以無電電鍍方式被覆一薄銅層做為晶種層，然後以電鍍方式將所需厚度之第二銅層形成於晶種層上。或者，於晶 種層上沉積電鍍銅層前，該晶種層可藉由濺鍍方式形成如鈦/銅之晶種層薄膜。一旦達到所需之厚度，即可使用各種技術圖案化被覆層以形成第一及第二導線315、325，其包括濕蝕刻、電化學蝕刻、雷射輔助蝕刻及其組合，並使用蝕刻光罩(圖未示)，以定義出第一及第二導線315、325。較佳地，第一及第二披覆層31’、32’以及連接層403係使用相同材料並使用相同方法同時沉積，並且具有相同厚度。 The first and second cladding layers 31', 32' and the connection layer 403 can be fabricated by various techniques A single layer or multiple layers are formed which includes electroplating, electroless plating, evaporation, sputtering, and combinations thereof. For example, first, by immersing the structure in an activator solution, the first and second insulating layers 312 and 322 are reacted with electroless copper to form a catalyst, and then a thin copper layer is coated as a seed crystal by electroless plating. The layer is then electroplated to form a second layer of copper of the desired thickness on the seed layer. Or, Yu Jing The seed layer may be formed by a sputtering method such as a titanium/copper seed layer film before the electroplated copper layer is deposited on the seed layer. Once the desired thickness is achieved, the coating can be patterned using various techniques to form first and second leads 315, 325 including wet etching, electrochemical etching, laser assisted etching, and combinations thereof, and using an etch mask (not shown) to define first and second conductors 315, 325. Preferably, the first and second cladding layers 31', 32' and the bonding layer 403 are simultaneously deposited using the same material and using the same method, and have the same thickness.

為了便於圖示，第一及第二金屬板31、32、第一及第二披覆 層31’,32’以及連接層403係以單一層表示。由於銅為同質披覆，金屬層間之界線可能不易察覺甚至無法察覺。然而，第一披覆層31’與第一絕緣層312間之界線、第二披覆層32’與第二絕緣層322間之界線、連接層403與第一絕緣層312間之界線、連接層403與平衡層311間之界線、連接層403與芯層26間之界線、以及連接層403與第二絕緣層322間之界線則清楚可見。 For convenience of illustration, the first and second metal plates 31, 32, the first and second covers Layers 31', 32' and tie layer 403 are represented by a single layer. Since copper is a homogeneous coating, the boundaries between metal layers may be difficult to detect or even detect. However, the boundary between the first cladding layer 31' and the first insulating layer 312, the boundary between the second cladding layer 32' and the second insulating layer 322, the boundary between the connection layer 403 and the first insulating layer 312, and the connection The boundary between the layer 403 and the balancing layer 311, the boundary between the connecting layer 403 and the core layer 26, and the boundary between the connecting layer 403 and the second insulating layer 322 are clearly visible.

圖30為第三絕緣層332及第三金屬板33層壓/塗佈於第一絕 緣層312及第一導線315上、以及第四絕緣層342及第四金屬板34層壓/塗佈於第二絕緣層322及第二導線325上之剖視圖。第三絕緣層332係夾置於第一絕緣層312/第一導線315以及第三金屬板33間，並且其係朝向上方向延伸進入穿孔401之剩餘空間中。同樣地，第四絕緣層342夾置於第二絕緣層322/第二導線325以及第四金屬板34間，並且其係朝向下方向延伸進入穿孔401之剩餘空間中。第三及第四絕緣層332、342可為環氧樹脂、玻璃環氧樹脂、聚醯亞胺、及其類似物所製成，並且通常具有50微米之厚度。第三及第四金屬板33、34分別為厚度25微米之銅層。第一、第二、第三、及第四絕緣層312、322、332、342較佳係由相同材料形成。 FIG. 30 is a third insulating layer 332 and a third metal plate 33 laminated/coated on the first A cross-sectional view of the edge layer 312 and the first conductive line 315, and the fourth insulating layer 342 and the fourth metal plate 34 are laminated/coated on the second insulating layer 322 and the second conductive line 325. The third insulating layer 332 is interposed between the first insulating layer 312 / the first wire 315 and the third metal plate 33 and extends in the upward direction into the remaining space of the through hole 401. Similarly, the fourth insulating layer 342 is interposed between the second insulating layer 322 / the second wire 325 and the fourth metal plate 34, and extends in the downward direction into the remaining space of the through hole 401. The third and fourth insulating layers 332, 342 may be made of epoxy resin, glass epoxy resin, polyimide, and the like, and typically have a thickness of 50 microns. The third and fourth metal plates 33, 34 are each a copper layer having a thickness of 25 μm. The first, second, third, and fourth insulating layers 312, 322, 332, 342 are preferably formed of the same material.

圖31為形成第三及第四盲孔333、343後之剖視圖，其係顯露第一及第二導線315、325之選定部分。第三盲孔333延伸穿過第三金屬板33及第三絕緣層332，並且對準第一導線315之選定部分。第四盲孔343延伸穿過第四金屬板34及第四絕緣層342，並且對準第二導線325之選定部分。如同第一及第二盲孔313、323，第三及第四盲孔333、343可藉由各種技術形成，其包括雷射鑽孔、電漿蝕刻及微影技術，且通常具有50微米之直徑。第一、第二、第三、及第四盲孔313、323、333、343較佳係具有相同尺寸。 31 is a cross-sectional view showing the third and fourth blind vias 333, 343 showing selected portions of the first and second leads 315, 325. The third blind via 333 extends through the third metal plate 33 and the third insulating layer 332 and is aligned with selected portions of the first conductive trace 315. The fourth blind via 343 extends through the fourth metal plate 34 and the fourth insulating layer 342 and is aligned with a selected portion of the second wire 325. Like the first and second blind holes 313, 323, the third and fourth blind holes 333, 343 can be formed by various techniques including laser drilling, plasma etching, and lithography, and typically have a thickness of 50 microns. diameter. The first, second, third, and fourth blind holes 313, 323, 333, 343 are preferably of the same size.

參照圖32，藉由沉積第三披覆層33’於第三金屬板33上及第三盲孔333中，沉積第四披覆層34’於第四金屬板34上及第四盲孔343中，然後圖案化第三及第四金屬板33、34以及其上之第三及第四披覆層33’、34’，以分別形成位於第三絕緣層332及第四絕緣層342上之第三導線335及第四導線345。或者，當前述製程中未有第三及第四金屬板33、34層壓於第三及第四絕緣層332、342上時，第三及第四絕緣層332、342可直接金屬化以形成第三及第四導線335、345。第三導線335自第三絕緣層332朝向下方向延伸，同時側向延伸於第三絕緣層332上，並且朝向上方向延伸進入第三盲孔333中，以形成直接接觸第一導線315之第三導電盲孔337。第四導線345自第四絕緣層342朝向上方向延伸，同時側向延伸於第四絕緣層342上，並且朝向下方向延伸進入第四盲孔343中，以形成直接接觸第二導線325之第四導電盲孔347。第一、第二、第三、及第四導線315、325、335、345較佳係由相同材料形成且具有相同厚度。 Referring to FIG. 32, a fourth cladding layer 34' is deposited on the fourth metal plate 34 and the fourth blind via 343 by depositing a third cladding layer 33' on the third metal plate 33 and the third blind via 333. Then, the third and fourth metal plates 33, 34 and the third and fourth cladding layers 33', 34' thereon are patterned to be formed on the third insulating layer 332 and the fourth insulating layer 342, respectively. The third wire 335 and the fourth wire 345. Alternatively, when the third and fourth metal plates 33, 34 are not laminated on the third and fourth insulating layers 332, 342 in the foregoing process, the third and fourth insulating layers 332, 342 may be directly metallized to form Third and fourth wires 335, 345. The third wire 335 extends from the third insulating layer 332 toward the lower direction while extending laterally on the third insulating layer 332 and extends into the third blind hole 333 in the upward direction to form a direct contact with the first wire 315. Three conductive blind holes 337. The fourth wire 345 extends from the fourth insulating layer 342 in the upward direction while extending laterally on the fourth insulating layer 342 and extends into the fourth blind hole 343 in a downward direction to form a direct contact with the second wire 325. Four conductive blind holes 347. The first, second, third, and fourth wires 315, 325, 335, 345 are preferably formed of the same material and have the same thickness.

據此，如圖32所示，完成之半導體封裝件110係包括中介層11’、晶片13、金屬散熱座22、芯層26、第一增層電路301、第二增層電路302、 以及披覆穿孔411。在此圖中，第一增層電路301包括平衡層311、第一絕緣層312、第一導線315、第三絕緣層332、以及第三導線335；第二增層電路302包括第二絕緣層322、第二導線325、第四絕緣層342、以及第四導線345。 藉由覆晶製程，將晶片13電性耦接至預製之中介層11’，以形成晶片-中介層堆疊次組體10。使用第一及第二黏著劑191、193，將晶片-中介層堆疊次組體10貼附至金屬散熱座22，並使晶片13置放於凹穴215中，且中介層11’側向延伸於凹穴215外。第一黏著劑191提供晶片13及金屬散熱座22間之機械性接合及熱性連接，並且第二黏著劑193提供晶片13及金屬散熱座22間、以及中介層11’及金屬散熱座22間之機械性接合。芯層26側向覆蓋金屬散熱座22之側壁。第一增層電路301係藉由第一導電盲孔317電性耦接至中介層11’，第一導電盲孔317係直接接觸中介層11’之第一接觸墊112，因此中介層11’與第一增層電路301間的電性連接無須用到焊接材料。第二增層電路302係藉由第二導電盲孔327電性及熱性耦接至金屬散熱座22，第二導電盲孔327可作為散熱管，以將熱自金屬散熱座22散逸至第二增層電路302之外側導電層。披覆穿孔411實質上係由芯層26、第一增層電路301、以及第二增層電路302共用，並且提供第一增層電路301及第二增層電路302間之電性及熱性連接。 Accordingly, as shown in FIG. 32, the completed semiconductor package 110 includes an interposer 11', a wafer 13, a metal heat sink 22, a core layer 26, a first build-up circuit 301, a second build-up circuit 302, And a perforated 411. In this figure, the first build-up circuit 301 includes a balance layer 311, a first insulating layer 312, a first wire 315, a third insulating layer 332, and a third wire 335; the second build-up circuit 302 includes a second insulating layer. 322, a second wire 325, a fourth insulating layer 342, and a fourth wire 345. The wafer 13 is electrically coupled to the pre-fabricated interposer 11' by a flip chip process to form a wafer-interposer stack sub-assembly 10. Using the first and second adhesives 191, 193, the wafer-interposer stack sub-assembly 10 is attached to the metal heat sink 22, and the wafer 13 is placed in the recess 215, and the interposer 11' is laterally extended. Outside the pocket 215. The first adhesive 191 provides mechanical bonding and thermal connection between the wafer 13 and the metal heat sink 22, and the second adhesive 193 provides between the wafer 13 and the metal heat sink 22, and between the interposer 11' and the metal heat sink 22. Mechanical joint. The core layer 26 laterally covers the sidewalls of the metal heat sink 22. The first build-up circuit 301 is electrically coupled to the interposer 11' by the first conductive via 317. The first conductive via 317 directly contacts the first contact pad 112 of the interposer 11', so the interposer 11' The electrical connection with the first build-up circuit 301 does not require the use of solder material. The second build-up circuit 302 is electrically and thermally coupled to the metal heat sink 22 via the second conductive via 327. The second conductive via 327 can serve as a heat sink to dissipate heat from the metal heat sink 22 to the second. The outer layer of the layering circuit 302 is electrically conductive. The cladding via 411 is substantially shared by the core layer 26, the first build-up circuit 301, and the second build-up circuit 302, and provides electrical and thermal connections between the first build-up circuit 301 and the second build-up circuit 302. .

圖33為堆疊式封裝組體100之剖視圖，其係另一半導體封裝 件120設置於圖32半導體封裝件110之第一增層電路301上。半導體封裝件120可以為任何種類之封裝件。例如，半導體封裝件120可為傳統的IC封裝件或本發明所設想的任何種類封裝件。在此圖中，半導體封裝件110更具有位於第一及第二增層電路301、302上之焊料遮罩41。焊料遮罩41包括焊料 遮罩開口，其係顯露第三及第四導線335、345之選定部分。據此，半導體封裝件20可經由焊球51設置於半導體封裝件110之第三導線335顯露部分上。 33 is a cross-sectional view of a stacked package body 100, which is another semiconductor package The device 120 is disposed on the first build-up circuit 301 of the semiconductor package 110 of FIG. The semiconductor package 120 can be any kind of package. For example, the semiconductor package 120 can be a conventional IC package or any kind of package contemplated by the present invention. In this figure, the semiconductor package 110 further has a solder mask 41 on the first and second build-up circuits 301, 302. Solder mask 41 includes solder A mask opening that reveals selected portions of the third and fourth conductors 335, 345. Accordingly, the semiconductor package 20 can be disposed on the exposed portion of the third wire 335 of the semiconductor package 110 via the solder balls 51.

[實施例2] [Embodiment 2]

圖34-43為本發明另一實施態樣之另一具有堆疊式封裝能力之半導體封裝件製法剖視圖，其中該半導體封裝件具有用於中介層貼附步驟之定位件，以及用於接地連接之金屬柱。 34-43 are cross-sectional views showing another manufacturing method of a semiconductor package having a stacked package capability according to another embodiment of the present invention, wherein the semiconductor package has a positioning member for an interposer attaching step, and a ground connection Metal column.

為了簡要說明之目的，上述實施例1中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。 For the purpose of brief description, any description of the same application in the above-described embodiment 1 is hereby made, and the same description is not repeated.

圖34為含金屬載體20之凹穴215入口周圍設有定位件217之剖視圖。可藉由移除金屬板21之選定部分，或是藉由於金屬板21之第一表面211沉積金屬材料或塑膠材料之圖案，以形成定位件217。定位件217通常係藉由電鍍、蝕刻、或機械切割而製成。據此，定位件217自含金屬載體20中鄰接凹穴入口之平坦表面212朝向下方向延伸，並且可具有5至200微米之厚度。在此實施態樣中，厚度50微米之定位件217係側向延伸至含金屬載體20之外圍邊緣，並且具有與隨後設置的中介層四側邊相符之內周圍邊緣。 Figure 34 is a cross-sectional view showing the positioning member 217 around the entrance of the recess 215 containing the metal carrier 20. The positioning member 217 can be formed by removing a selected portion of the metal plate 21 or by depositing a pattern of a metal material or a plastic material from the first surface 211 of the metal plate 21. The positioning member 217 is typically made by electroplating, etching, or mechanical cutting. Accordingly, the positioning member 217 extends downward from the flat surface 212 of the metal-containing carrier 20 adjacent to the pocket inlet, and may have a thickness of 5 to 200 microns. In this embodiment, the keeper 50 of thickness 50 microns extends laterally to the peripheral edge of the metal-containing carrier 20 and has an inner peripheral edge that conforms to the four sides of the interposer layer that is subsequently disposed.

圖35為含金屬載體20之凹穴215內塗有第一黏著劑191之剖視圖。第一黏著劑191通常為導熱黏著劑，並且塗佈於凹穴之底部上。 Figure 35 is a cross-sectional view of the recess 215 containing the metal carrier 20 coated with a first adhesive 191. The first adhesive 191 is typically a thermally conductive adhesive and is applied to the bottom of the pocket.

圖36為晶片-中介層堆疊次組體10藉由第一黏著劑191貼附至含金屬載體20之剖視圖。中介層11’及晶片13係貼附至含金屬載體20，且晶片13係***凹穴215中，而定位件217則側向對準且靠近中介層11’之外圍邊緣。定位件217可控制中介層置放之準確度。定位件217朝向下方向延伸 超過中介層11’之第二表面113，並且位於中介層11’之四側表面外，同時側向對準中介層11’之四側表面。由於定位件217側向靠近且符合中介層11’四側表面，故其可避免晶片-中介層堆疊次組體10於黏著劑固化時發生任何不必要的位移。中介層11’與定位件217間之間隙較佳係於約5至50微米之範圍內。中介層之貼附步驟亦可不使用定位件217。雖然無法藉由凹穴215來控制晶片-中介層堆疊次組體10置放之準確度(其原因在於，很難精準地控制凹穴之尺寸與深度)，但是因為中介層11’具有較大之接觸墊尺寸及間距，因此並不會造成隨後於中介層11’上形成增層電路時，微盲孔的連接失敗。 36 is a cross-sectional view of the wafer-interposer stack sub-assembly 10 attached to the metal-containing carrier 20 by the first adhesive 191. The interposer 11' and the wafer 13 are attached to the metal-containing carrier 20, and the wafer 13 is inserted into the recess 215, and the positioning member 217 is laterally aligned and adjacent to the peripheral edge of the interposer 11'. The positioning member 217 can control the accuracy of the placement of the interposer. The positioning member 217 extends downward The second surface 113 of the interposer 11' is over and located outside the four side surfaces of the interposer 11' while laterally aligning the four side surfaces of the interposer 11'. Since the positioning member 217 is laterally adjacent and conforms to the four side surfaces of the interposer 11', it can prevent any unnecessary displacement of the wafer-interposer stack sub-assembly 10 when the adhesive is cured. The gap between the interposer 11' and the positioning member 217 is preferably in the range of about 5 to 50 microns. The attaching step of the interposer may also not use the positioning member 217. Although it is impossible to control the accuracy of placement of the wafer-interposer stack sub-group 10 by the recesses 215 (the reason is that it is difficult to precisely control the size and depth of the recesses), since the interposer 11' has a larger The size and spacing of the contact pads do not cause subsequent failure of the connection of the micro-blind holes when the build-up circuit is formed on the interposer 11'.

圖37為第二黏著層193填充於中介層11’與含金屬載體20之 間並進一步延伸進入凹穴215中之剖視圖。第二黏著層193通常係為電性絕緣之底部填充材料，其係塗佈於中介層11’與含金屬載體20之間，並填入凹穴215內的剩餘空間中。 37 is a second adhesive layer 193 filled in the interposer 11' and the metal-containing carrier 20 A cross-sectional view that is further extended into the pocket 215. The second adhesive layer 193 is typically an electrically insulating underfill material that is applied between the interposer 11' and the metal-containing carrier 20 and fills the remaining space within the recess 215.

圖38為移除溢出於定位件217上之過剩黏著劑後之剖視圖。 或者，可省略移除過剩黏著劑之步驟，據此過剩之黏著劑變成隨後增層電路之一部分。 Figure 38 is a cross-sectional view showing the excess adhesive that has overflowed from the positioning member 217. Alternatively, the step of removing the excess adhesive may be omitted, whereby the excess adhesive becomes part of the subsequent build-up circuit.

圖39為平衡層311、第一絕緣層312、以及第一金屬板31層壓 /塗佈於中介層11’及含金屬載體20上之剖視圖。平衡層311係接觸含金屬載體20，且自含金屬載體20朝向下方向延伸，並且側向覆蓋、圍繞及共形塗佈中介層11’之側壁，並自中介層11’側向延伸至該結構之外圍邊緣。第一絕緣層312係接觸第一金屬板31、中介層11’、以及平衡層311，並且提供第一金屬板31與中介層11’間、以及第一金屬板31與平衡層311間之堅固機械性接合。 39 is a laminated layer 311, a first insulating layer 312, and a first metal plate 31 laminated / Cross-sectional view applied to the interposer 11' and the metal-containing carrier 20. The balancing layer 311 is in contact with the metal-containing carrier 20 and extends from the metal-containing carrier 20 in a downward direction, and laterally covers, surrounds, and conformally coats the sidewalls of the interposer 11' and extends laterally from the interposer 11' to the The outer edge of the structure. The first insulating layer 312 contacts the first metal plate 31, the interposer 11', and the balance layer 311, and provides a strong between the first metal plate 31 and the interposer 11', and between the first metal plate 31 and the balance layer 311. Mechanical joint.

圖40為將含金屬載體20選定部分移除後，以形成金屬散熱座 22及金屬柱24之剖視圖，其係藉由微影技術及濕蝕刻移除含金屬載體20之選定部分。金屬散熱座22係對應於含金屬載體20之第一剩餘部分，其係於向上方向覆蓋及罩蓋晶片13於其凹穴215中。金屬柱24對應於含金屬載體20之第二剩餘部分，其係與與金屬散熱座22彼此保持距離。在此圖中，金屬柱24係與金屬散熱座22之第二表面213於向上方向共平面，並且與定位件217於向下方向共平面。 Figure 40 is a view showing the selected portion of the metal-containing carrier 20 removed to form a metal heat sink 22 and a cross-sectional view of the metal post 24, which remove selected portions of the metal-containing carrier 20 by lithography and wet etching. The metal heat sink 22 corresponds to the first remaining portion of the metal-containing carrier 20 that is covered in the upward direction and covers the wafer 13 in its recess 215. The metal posts 24 correspond to a second remaining portion of the metal-containing carrier 20 that is spaced from each other from the metal heat sink 22. In this figure, the metal post 24 is coplanar with the second surface 213 of the metal heat sink 22 in the upward direction and coplanar with the positioning member 217 in the downward direction.

圖41為芯層26、第二絕緣層322、以及第二金屬板32朝向上 方向層壓/塗佈於金屬散熱座22、金屬柱24、以及平衡層311上之剖視圖。芯層26係接觸平衡層311，且自平衡層311朝向上方向延伸，並且側向覆蓋、圍繞及共形塗佈金屬散熱座22及金屬柱24之側壁，同時自金屬散熱座22及金屬柱24側向延伸至該結構之外圍邊緣。第二絕緣層322係接觸金屬散熱座22之第二表面213、金屬柱24、以及芯層26，且朝向上方向覆蓋及側向延伸於金屬散熱座22之第二表面213、金屬柱24、以及芯層26上。第二金屬板32係接觸第二絕緣層322，且朝向上方向覆蓋第二絕緣層322。 41 is a core layer 26, a second insulating layer 322, and a second metal plate 32 facing upward A cross-sectional view of the direction lamination/coating on the metal heat sink 22, the metal post 24, and the balance layer 311. The core layer 26 is in contact with the balance layer 311 and extends from the balance layer 311 in the upward direction, and laterally covers, surrounds, and conformally coats the sidewalls of the metal heat sink 22 and the metal pillars 24, and simultaneously from the metal heat sink 22 and the metal pillars. 24 extends laterally to the peripheral edge of the structure. The second insulating layer 322 contacts the second surface 213 of the metal heat sink 22, the metal pillars 24, and the core layer 26, and covers and extends laterally to the second surface 213 of the metal heat sink 22, the metal pillars 24, And on the core layer 26. The second metal plate 32 contacts the second insulating layer 322 and covers the second insulating layer 322 in an upward direction.

圖42為形成第一盲孔313、314、第二盲孔323、以及穿孔401 後之剖視圖。第一盲孔313係延伸穿過第一金屬板31及第一絕緣層312，並且對準中介層11’之第一接觸墊112。此外，額外之第一盲孔314延伸穿過第一金屬板31、第一絕緣層312以及平衡層311，並且對準金屬柱24。第二盲孔323延伸穿過第二金屬板32及第二絕緣層322，並且對準金屬散熱座22之選定部分及金屬柱24。穿孔401朝垂直方向延伸穿過第一金屬板31、第一絕緣層312、平衡層311、芯層26、第二絕緣層322以及第二金屬板32。 42 is a first blind hole 313, 314, a second blind hole 323, and a through hole 401. Rear section view. The first blind via 313 extends through the first metal plate 31 and the first insulating layer 312 and is aligned with the first contact pad 112 of the interposer 11'. In addition, an additional first blind via 314 extends through the first metal plate 31, the first insulating layer 312, and the balancing layer 311, and is aligned with the metal pillars 24. The second blind via 323 extends through the second metal plate 32 and the second insulating layer 322 and is aligned with selected portions of the metal heat sink 22 and the metal posts 24. The through hole 401 extends through the first metal plate 31, the first insulating layer 312, the balance layer 311, the core layer 26, the second insulating layer 322, and the second metal plate 32 in a vertical direction.

參照圖43，藉由沉積第一披覆層31’於第一金屬板31上及第 一盲孔313、314中，沉積第二披覆層32’於第二金屬板32上及第二盲孔323中，然後圖案化第一及第二金屬板31、32以及其上之第一及第二披覆層31’、32’，以分別形成於第一絕緣層312及第二絕緣層322上之第一導線315及第二導線325。連接層403亦沉積於穿孔401中以形成披覆穿孔411。第一導線315自第一絕緣層312朝向下方向延伸，且側向延伸於第一絕緣層312上，並且朝向上方向延伸進入第一盲孔313、314中，以形成直接接觸中介層11’之第一接觸墊112與金屬柱24之第一導電盲孔317、318，藉以提供中介層11’之信號路由及接地連接。第二導線325自第二絕緣層322朝向上方向延伸，且側向延伸於第二絕緣層322上，並且朝向下方向延伸進入第二盲孔323中，以形成直接接觸金屬散熱座22選定部分及金屬柱24之第二導電盲孔327，其係作為接地連接用。披覆穿孔411之第一端延伸至第一導線315，第二端延伸至第二導線325，以提供垂直信號連接通路。 Referring to FIG. 43, by depositing the first cladding layer 31' on the first metal plate 31 and In a blind hole 313, 314, a second cladding layer 32' is deposited on the second metal plate 32 and the second blind hole 323, and then the first and second metal plates 31, 32 and the first one thereof are patterned. And the second cladding layers 31 ′, 32 ′ are respectively formed on the first insulating layer 312 and the second insulating layer 322 on the first conductive line 315 and the second conductive line 325 . A tie layer 403 is also deposited in the perforations 401 to form a covered perforation 411. The first wire 315 extends from the first insulating layer 312 in a downward direction and extends laterally on the first insulating layer 312 and extends into the first blind holes 313, 314 in an upward direction to form a direct contact interposer 11' The first contact pads 112 and the first conductive blind vias 317, 318 of the metal posts 24 provide signal routing and ground connections for the interposer 11'. The second wire 325 extends upward from the second insulating layer 322 and extends laterally on the second insulating layer 322 and extends into the second blind via 323 in a downward direction to form a direct contact with the selected portion of the metal heat sink 22 And a second conductive blind via 327 of the metal post 24, which serves as a ground connection. The first end of the cladding via 411 extends to the first wire 315 and the second end extends to the second wire 325 to provide a vertical signal connection path.

據此，如圖43所示，完成之半導體封裝件210係包括中介層 11’、晶片13、金屬散熱座22、金屬柱24、芯層26、第一增層電路301、第二增層電路302、以及披覆穿孔411。在此圖中，第一增層電路301包括平衡層311、第一絕緣層312、以及第一導線315；第二增層電路302包括第二絕緣層322以及第二導線325。藉由覆晶製程，將晶片13電性耦接至預製之中介層11’，以形成晶片-中介層堆疊次組體10。使用第一及第二黏著劑191、193，將晶片-中介層堆疊次組體10貼附至金屬散熱座22，並使晶片13置放於凹穴215中，且中介層11’側向延伸於凹穴215外。第一黏著劑191提供晶片13及金屬散熱座22間之機械性接合及熱性連接，並且第二黏著劑193提供晶片13與 金屬散熱座22間、以及中介層11’與金屬散熱座22間之機械性接合。金屬散熱座22之定位件217朝向下方向延伸超過中介層11’之第二表面113，且靠近中介層11’之外圍邊緣，以控制中介層11’置放之準確度。金屬柱24與金屬散熱座22彼此保持距離，並且與金屬散熱座22於向上方向共平面，以及與定位件217於向下方向共平面。芯層26係側向覆蓋金屬散熱座22及金屬柱24之側壁。第一增層電路301藉由第一導電盲孔317、318電性耦接至中介層11’及金屬柱24。第二增層電路302藉由第二導電盲孔327電性及熱性耦接至金屬散熱座22，並且電性耦接至金屬柱24。披覆穿孔411電性耦接至第一及第二導線315、325，以提供具有堆疊能力之半導體封裝件。 Accordingly, as shown in FIG. 43, the completed semiconductor package 210 includes an interposer. 11', wafer 13, metal heat sink 22, metal post 24, core layer 26, first build-up circuit 301, second build-up circuit 302, and cladding vias 411. In this figure, the first build-up circuit 301 includes a balance layer 311, a first insulating layer 312, and a first wire 315; the second build-up circuit 302 includes a second insulating layer 322 and a second wire 325. The wafer 13 is electrically coupled to the pre-fabricated interposer 11' by a flip chip process to form a wafer-interposer stack sub-assembly 10. Using the first and second adhesives 191, 193, the wafer-interposer stack sub-assembly 10 is attached to the metal heat sink 22, and the wafer 13 is placed in the recess 215, and the interposer 11' is laterally extended. Outside the pocket 215. The first adhesive 191 provides mechanical bonding and thermal connection between the wafer 13 and the metal heat sink 22, and the second adhesive 193 provides the wafer 13 and Mechanical engagement between the metal heat sinks 22 and the interposer 11' and the metal heat sinks 22. The positioning member 217 of the metal heat sink 22 extends downward in the downward direction beyond the second surface 113 of the interposer 11' and near the peripheral edge of the interposer 11' to control the accuracy of the placement of the interposer 11'. The metal post 24 and the metal heat sink 22 are spaced apart from each other and are coplanar with the metal heat sink 22 in the upward direction and coplanar with the positioning member 217 in the downward direction. The core layer 26 laterally covers the metal heat sink 22 and the sidewalls of the metal posts 24. The first build-up circuit 301 is electrically coupled to the interposer 11' and the metal post 24 via the first conductive vias 317, 318. The second build-up circuit 302 is electrically and thermally coupled to the metal heat sink 22 via the second conductive via 327 and electrically coupled to the metal pillars 24 . The cladding via 411 is electrically coupled to the first and second wires 315, 325 to provide a semiconductor package having a stacking capability.

圖44為堆疊式封裝組體200之剖視圖，其係另一半導體封裝 件220設置於圖43半導體封裝件210之第二增層電路302上。在此圖中，半導體封裝件210更具有位於穿孔401內剩餘空間之絕緣性填充物415，以及位於第一及第二增層電路301、302上之焊料遮罩41。焊料遮罩41包括焊料遮罩開口，其係顯露第一及第二導線315、325之選定部分。據此，半導體封裝件220可經由焊球51設置於半導體封裝件210之第二導線325顯露部分上。 44 is a cross-sectional view of a stacked package body 200, which is another semiconductor package. The device 220 is disposed on the second build-up circuit 302 of the semiconductor package 210 of FIG. In this figure, the semiconductor package 210 further has an insulating filler 415 located in the remaining space in the via 401, and a solder mask 41 on the first and second build-up circuits 301, 302. The solder mask 41 includes a solder mask opening that reveals selected portions of the first and second wires 315, 325. Accordingly, the semiconductor package 220 can be disposed on the exposed portion of the second wire 325 of the semiconductor package 210 via the solder ball 51.

[實施例3] [Example 3]

圖45-52為本發明再一實施態樣之具有堆疊式封裝能力之再一半導體封裝件製法剖視圖，該半導體封裝件包括金屬散熱座，其係側向延伸至該封裝之外圍邊緣。 45-52 are cross-sectional views showing still another semiconductor package having a stacked package capability according to still another embodiment of the present invention, the semiconductor package including a metal heat sink extending laterally to a peripheral edge of the package.

為了簡要說明之目的，上述實施例中任何可作相同應用之敘述皆併於此，且無須再重複相同敘述。 For the purpose of brevity, the description of any of the above embodiments that can be used for the same application is the same, and the same description is not repeated.

圖45為含金屬載體20之凹穴215入口周圍設有定位件217之 剖視圖，其中凹穴215係位於含金屬載體20之第一表面211。可藉由移除金屬板21之選定部分，或是藉由沉積圖案於金屬板21上，以形成定位件217，其中沉積圖案之方式包括電鍍、無電電鍍、蒸鍍、濺鍍及其組合，並同時使用微影技術。此實施態樣係藉由沉積圖案於金屬板21上，以形成定位件217，定位件217係側向延伸至含金屬載體20之外圍邊緣，且其內周圍邊緣係與隨後設置之中介層四側邊相符。 45 is a positioning member 217 around the entrance of the recess 215 containing the metal carrier 20. A cross-sectional view in which the pocket 215 is located on the first surface 211 of the metal-containing carrier 20. The positioning member 217 can be formed by removing selected portions of the metal plate 21 or by depositing a pattern on the metal plate 21, wherein the pattern is deposited by electroplating, electroless plating, evaporation, sputtering, and combinations thereof. And use lithography at the same time. This embodiment is formed by depositing a pattern on the metal plate 21 to form the positioning member 217. The positioning member 217 extends laterally to the peripheral edge of the metal-containing carrier 20, and the inner peripheral edge thereof is followed by the interposer 4 The sides match.

圖46為含金屬載體20之凹穴215外設有貫穿開口219之剖視 圖。貫穿開口219於垂直方向延伸穿過第一表面211以及第二表面213間之含金屬載體20，其可藉由機械鑽孔形成。 Figure 46 is a cross-sectional view of the recess 215 containing the metal carrier 20 provided with a through opening 219. Figure. The through opening 219 extends in a vertical direction through the metal-containing carrier 20 between the first surface 211 and the second surface 213, which may be formed by mechanical drilling.

圖47為晶片-中介層堆疊次組體10藉由第一黏著劑191貼附 至含金屬載體20之剖視圖。中介層11’及晶片13貼附至含金屬載體20，且晶片13係***凹穴215中，而定位件217則側向對準且靠近中介層11’之外圍邊緣。第一黏著劑191接觸凹穴底部及晶片13，藉以提供晶片13及含金屬載體20之機械性接合及熱性連接。定位件217朝向下方向延伸超過中介層11’之第二表面113，並且靠近中介層11’外圍邊緣，以控制中介層11’置放之準確度。 47 is a wafer-interposer stack sub-assembly 10 attached by a first adhesive 191 A cross-sectional view to the metal-containing carrier 20. The interposer 11' and the wafer 13 are attached to the metal-containing carrier 20, and the wafer 13 is inserted into the recess 215, and the positioning member 217 is laterally aligned and adjacent to the peripheral edge of the interposer 11'. The first adhesive 191 contacts the bottom of the pocket and the wafer 13 to provide mechanical and thermal bonding of the wafer 13 and the metal-containing carrier 20. The positioning member 217 extends downward in the downward direction beyond the second surface 113 of the interposer 11' and near the peripheral edge of the interposer 11' to control the accuracy of placement of the interposer 11'.

圖48為第二黏著層193填充於中介層11’與含金屬載體20之 間，並進一步延伸進入凹穴215中之剖視圖。第二黏著層193通常為電性絕緣之底部填充材料，其係塗佈於中介層11’與含金屬載體20之間，並填入凹穴215內的剩餘空間中。 Figure 48 is a view showing that the second adhesive layer 193 is filled in the interposer 11' and the metal-containing carrier 20 A cross-sectional view that extends further into the pocket 215. The second adhesive layer 193 is typically an electrically insulating underfill material that is applied between the interposer 11' and the metal-containing carrier 20 and fills the remaining space within the recess 215.

圖49為移除溢出在定位件217上之過剩黏著劑後之剖視圖。 或者，可省略移除過剩黏著劑之步驟，據此過剩之黏著劑變成隨後增層電路之一部分。 Figure 49 is a cross-sectional view showing the excess adhesive that has overflowed on the positioning member 217. Alternatively, the step of removing the excess adhesive may be omitted, whereby the excess adhesive becomes part of the subsequent build-up circuit.

圖50為平衡層311、第一絕緣層312、以及第一金屬板31層壓 /塗佈於中介層11’及含金屬載體20上，以及第二絕緣層322及第二金屬板32層壓/塗佈於含金屬載體20之第二表面213上之剖視圖。平衡層311係接觸含金屬載體20，且自含金屬載體20朝向下方向延伸，並且朝向上方向延伸進入貫穿開口219中，以及側向覆蓋、圍繞及共形塗佈中介層11’之側壁，同時自中介層11’側向延伸至該結構之外圍邊緣。第一絕緣層312係側向延伸於中介層11’之第一表面111上以及平衡層311上，且接觸第一金屬板31、中介層11’、以及平衡層311，並且提供第一金屬板31與中介層11’間、以及第一金屬板31與平衡層311間之堅固機械性接合。第二絕緣層322側向延伸於含金屬載體20之第二表面213上，且接觸第二金屬板32以及含金屬載體20，並且提供第二金屬板32與含金屬載體20間之堅固機械性接合。 50 is a laminate of the balance layer 311, the first insulating layer 312, and the first metal plate 31. / Applied to the interposer 11' and the metal-containing carrier 20, and a cross-sectional view of the second insulating layer 322 and the second metal plate 32 laminated/coated on the second surface 213 of the metal-containing carrier 20. The balancing layer 311 is in contact with the metal-containing carrier 20 and extends from the metal-containing carrier 20 in a downward direction and extends into the through-opening 219 in an upward direction, and laterally covers, surrounds, and conformally coats the sidewalls of the interposer 11'. At the same time, the interposer 11' extends laterally to the peripheral edge of the structure. The first insulating layer 312 extends laterally on the first surface 111 of the interposer 11' and on the balancing layer 311, and contacts the first metal plate 31, the interposer 11', and the balancing layer 311, and provides a first metal plate. A strong mechanical bond between the 31 and the interposer 11' and between the first metal plate 31 and the balance layer 311. The second insulating layer 322 extends laterally on the second surface 213 of the metal-containing carrier 20 and contacts the second metal plate 32 and the metal-containing carrier 20, and provides strong mechanical properties between the second metal plate 32 and the metal-containing carrier 20. Engage.

圖51為形成第一及第二盲孔313、323以及穿孔401後之剖視 圖。第一盲孔313係延伸穿過第一金屬板31及第一絕緣層312，並且對準中介層11’之第一接觸墊112。第二盲孔323係延伸穿過第二金屬板32及第二絕緣層322，並且對準金屬散熱座22之選定部分。穿孔401對準貫穿開口219，並且朝垂直方向延伸穿過第一金屬板31、第一絕緣層312、平衡層311、第二絕緣層322以及第二金屬板32。 Figure 51 is a cross-sectional view showing the first and second blind holes 313, 323 and the perforations 401 Figure. The first blind via 313 extends through the first metal plate 31 and the first insulating layer 312 and is aligned with the first contact pad 112 of the interposer 11'. The second blind via 323 extends through the second metal plate 32 and the second insulating layer 322 and is aligned with selected portions of the metal heat sink 22. The through hole 401 is aligned with the through opening 219 and extends through the first metal plate 31, the first insulating layer 312, the balance layer 311, the second insulating layer 322, and the second metal plate 32 in the vertical direction.

參照圖52，藉由沉積第一披覆層31’於第一金屬板31上及第 一盲孔313中，沉積第二披覆層32’於第二金屬板32上及第二盲孔323中，然後圖案化第一及第二金屬板31、32以及其上之第一及第二披覆層31’、32’，以分別形成於第一絕緣層312及第二絕緣層322上之第一導線315及第二導線325。連接層403亦沉積於穿孔401中以形成披覆穿孔411。第一導線315自 第一絕緣層312朝向下方向延伸，且側向延伸於第一絕緣層312上，並且朝向上方向延伸進入第一盲孔313中，以形成直接接觸中介層11’之第一接觸墊112之第一導電盲孔317，藉以提供中介層11’之信號路由。第二導線325自第二絕緣層322朝向上方向延伸，且側向延伸於第二絕緣層322上，並且朝向下方向延伸進入第二盲孔323中，以形成直接接觸含金屬載體20選定部分之第二導電盲孔327，其係作為散熱及接地連接用。披覆穿孔411之第一端延伸至第一導線315，第二端延伸至第二導線325，以提供垂直信號連接通路。 Referring to FIG. 52, the first cladding layer 31' is deposited on the first metal plate 31 and In a blind via 313, a second cladding layer 32' is deposited on the second metal plate 32 and the second blind via 323, and then the first and second metal plates 31, 32 and the first and the first thereon are patterned. The second cladding layers 31', 32' are formed on the first insulating layer 312 and the second insulating layer 322, respectively, by a first conductive line 315 and a second conductive line 325. A tie layer 403 is also deposited in the perforations 401 to form a covered perforation 411. First wire 315 from The first insulating layer 312 extends in a downward direction and extends laterally on the first insulating layer 312 and extends into the first blind via 313 in an upward direction to form a first contact pad 112 directly contacting the interposer 11'. The first conductive blind via 317 provides signal routing for the interposer 11'. The second wire 325 extends upward from the second insulating layer 322 and extends laterally on the second insulating layer 322 and extends downward into the second blind via 323 to form a direct contact with the selected portion of the metal-containing carrier 20. The second conductive blind via 327 is used for heat dissipation and ground connection. The first end of the cladding via 411 extends to the first wire 315 and the second end extends to the second wire 325 to provide a vertical signal connection path.

據此，如圖52所示，完成之半導體封裝件310係包括中介層 11’、晶片13、含金屬載體20、第一增層電路301、第二增層電路302、以及披覆穿孔411。在此圖中，第一增層電路301包括平衡層311、第一絕緣層312、以及第一導線315；第二增層電路302包括第二絕緣層322、第二導線325。藉由覆晶製程，將晶片13電性耦接至預製之中介層11’，以形成晶片-中介層堆疊次組體10。使用第一及第二黏著劑191、193，將晶片-中介層堆疊次組體10貼附至作為金屬散熱座22之含金屬載體20，並使晶片13置放於凹穴215中，且中介層11’側向延伸於凹穴215外。第一黏著劑191提供晶片13及金屬散熱座22間之機械性接合及熱性連接，並且第二黏著劑193提供晶片13及金屬散熱座22間、以及中介層11’與金屬散熱座22間之機械性接合。金屬散熱座22之定位件217朝向下方向延伸超過中介層11’之第二表面113，且靠近中介層11’之外圍邊緣，以控制中介層11’置放之準確度。第一增層電路301藉由第一導電盲孔317電性耦接至中介層11’。第二增層電路302藉由第二導電盲孔327電性及熱性耦接至金屬散熱座22。披覆穿孔411係實質上由含金屬載體20、第一增層電路301、以及第二增層電路302共用，並且延伸穿 過含金屬載體之貫穿開口219，以提供第一增層電路301及第二增層電路302間之電性及熱性連接。 Accordingly, as shown in FIG. 52, the completed semiconductor package 310 includes an interposer. 11', wafer 13, metal-containing carrier 20, first build-up circuit 301, second build-up circuit 302, and cladding vias 411. In this figure, the first build-up circuit 301 includes a balance layer 311, a first insulating layer 312, and a first wire 315; the second build-up circuit 302 includes a second insulating layer 322 and a second wire 325. The wafer 13 is electrically coupled to the pre-fabricated interposer 11' by a flip chip process to form a wafer-interposer stack sub-assembly 10. Using the first and second adhesives 191, 193, the wafer-interposer stack sub-assembly 10 is attached to the metal-containing carrier 20 as the metal heat sink 22, and the wafer 13 is placed in the recess 215, and the intermediate Layer 11' extends laterally beyond pocket 215. The first adhesive 191 provides mechanical bonding and thermal connection between the wafer 13 and the metal heat sink 22, and the second adhesive 193 provides between the wafer 13 and the metal heat sink 22, and between the interposer 11' and the metal heat sink 22. Mechanical joint. The positioning member 217 of the metal heat sink 22 extends downward in the downward direction beyond the second surface 113 of the interposer 11' and near the peripheral edge of the interposer 11' to control the accuracy of the placement of the interposer 11'. The first build-up circuit 301 is electrically coupled to the interposer 11' by the first conductive via 317. The second build-up circuit 302 is electrically and thermally coupled to the metal heat sink 22 via the second conductive via 327. The cladding perforation 411 is substantially shared by the metal-containing carrier 20, the first build-up circuit 301, and the second build-up circuit 302, and extends through The through opening 219 of the metal-containing carrier is provided to provide an electrical and thermal connection between the first build-up circuit 301 and the second build-up circuit 302.

圖53為堆疊式封裝組體300之剖視圖，其係另一半導體封裝 件320設置於圖52半導體封裝件310之第二增層電路302上。在此圖中，半導體封裝件310更具有位於穿孔401內剩餘空間之絕緣性填充物415，以及位於第一及第二增層電路301、302上之焊料遮罩41。焊料遮罩41包括焊料遮罩開口，其係顯露第一及第二導線315、325之選定部分。據此，半導體封裝件320可經由焊球51設置於半導體封裝件310之第二導線325顯露部分上。 53 is a cross-sectional view of a stacked package body 300, which is another semiconductor package. The device 320 is disposed on the second build-up circuit 302 of the semiconductor package 310 of FIG. In this figure, the semiconductor package 310 further has an insulating filler 415 located in the remaining space in the via 401, and a solder mask 41 on the first and second build-up circuits 301, 302. The solder mask 41 includes a solder mask opening that reveals selected portions of the first and second wires 315, 325. Accordingly, the semiconductor package 320 can be disposed on the exposed portion of the second wire 325 of the semiconductor package 310 via the solder ball 51.

[實施例4] [Example 4]

圖54-63為本發明又一實施態樣之具有堆疊式封裝能力之又 一半導體封裝件製法剖視圖，該半導體封裝件係使用一層壓基板作為金屬散熱座。 54-63 show another embodiment of the present invention with stacked package capability A cross-sectional view of a semiconductor package using a laminated substrate as a metal heat sink.

為了簡要說明之目的，上述實施例中任何可作相同應用之敘述皆可合併於此處，且無須再重複相同敘述。 For the purpose of brief description, any description of the above embodiments that can be used for the same application can be incorporated herein, and the same description is not repeated.

圖54及55為本發明一實施態樣之定位件製程剖視圖，其係形成於層壓基板之介電層上。 54 and 55 are cross-sectional views showing a process of forming a positioning member according to an embodiment of the present invention, which is formed on a dielectric layer of a laminate substrate.

圖54為層壓基板之剖視圖，其包括金屬板21、介電層23、以及金屬層25。介電層23係夾置於金屬板21及金屬層25間。介電層23通常係為環氧樹脂、玻璃環氧樹脂、聚醯亞胺、及其類似物所製成，並且具有50微米之厚度。金屬層25通常為銅所製成，但亦可使用銅合金或其他材料(例如鋁、不銹鋼、或其合金)。金屬層25厚度可於5至200微米之範圍內。在此實施態樣中，金屬層25係為具有50微米厚度之銅板。 Figure 54 is a cross-sectional view of a laminate substrate including a metal plate 21, a dielectric layer 23, and a metal layer 25. The dielectric layer 23 is interposed between the metal plate 21 and the metal layer 25. The dielectric layer 23 is typically made of epoxy, glass epoxy, polyimide, and the like, and has a thickness of 50 microns. The metal layer 25 is typically made of copper, but copper alloys or other materials (such as aluminum, stainless steel, or alloys thereof) may also be used. The metal layer 25 may have a thickness in the range of 5 to 200 microns. In this embodiment, the metal layer 25 is a copper plate having a thickness of 50 μm.

圖55為於介電層23上形成定位件257之剖視圖。可藉由使用 微影技術及濕蝕刻，以移除金屬層25之選定部分，進而形成定位件257。在此圖中，定位件257係由複數個金屬凸柱組成，且排列成與隨後設置之中介層四側邊相符的矩形邊框陣列。然而，定位件之圖案不限於此，其可具有防止隨後設置之中介層發生不必要位移之其他各種圖案。舉例來說，定位件257可由一連續或不連續之凸條所組成，並與隨後設置之中介層四側邊、兩對角、或四角相符。 FIG. 55 is a cross-sectional view showing the positioning member 257 formed on the dielectric layer 23. By using The lithography technique and wet etching remove selected portions of the metal layer 25 to form the keeper 257. In this figure, the positioning member 257 is composed of a plurality of metal studs and arranged in an array of rectangular frames conforming to the four sides of the interposer layer which is subsequently disposed. However, the pattern of the positioning member is not limited thereto, and may have other various patterns that prevent unnecessary displacement of the interposer layer that is subsequently disposed. For example, the positioning member 257 may be composed of a continuous or discontinuous ridge and conform to the four sides, two diagonals, or four corners of the interposer layer that is subsequently disposed.

圖56及57為於層壓基板之介電層上形成定位件之另一製程 剖視圖。 Figures 56 and 57 are another process for forming a positioning member on a dielectric layer of a laminated substrate. Cutaway view.

圖56為具有一組開口251之層壓基板剖視圖。該層壓基板包 括上述之金屬板21、介電層23、以及金屬層25，並且藉由移除金屬層25之選定部分以形成開口251。 Figure 56 is a cross-sectional view of a laminate substrate having a plurality of openings 251. The laminated substrate package The metal plate 21, the dielectric layer 23, and the metal layer 25 described above are included, and the opening 251 is formed by removing selected portions of the metal layer 25.

圖57為介電層23上形成定位件257之剖視圖。定位件257可藉 由將光敏性塑膠材料(例如環氧樹脂、聚醯亞胺等)或非光敏性材料塗佈或印刷於開口251中，接著移除整體金屬層25而形成。據此，定位件257係由複數個樹脂凸柱組成，且具有防止隨後設置之中介層發生不必要位移之圖案。 57 is a cross-sectional view showing the positioning member 257 formed on the dielectric layer 23. The positioning member 257 can borrow It is formed by coating or printing a photosensitive plastic material (for example, an epoxy resin, a polyimide, or the like) or a non-photosensitive material in the opening 251, followed by removing the integral metal layer 25. Accordingly, the positioning member 257 is composed of a plurality of resin studs and has a pattern for preventing unnecessary displacement of the interposer layer which is subsequently disposed.

圖58為含金屬載體20中形成凹穴215之剖視圖。凹穴215延伸穿過介電層23，並且進一步延伸進入金屬板21中。 Figure 58 is a cross-sectional view showing the formation of the recess 215 in the metal-containing carrier 20. The pocket 215 extends through the dielectric layer 23 and further into the metal plate 21.

圖59為含金屬載體20之凹穴215外設有貫穿開口219之剖視圖。貫穿開口219係延伸穿過含金屬載體20，其可藉由機械鑽孔形成。 Figure 59 is a cross-sectional view showing the through hole 219 outside the recess 215 of the metal containing carrier 20. The through opening 219 extends through the metal-containing carrier 20, which can be formed by mechanical drilling.

圖60為晶片-中介層堆疊次組體10藉由黏著劑194貼附至含金屬載體20之剖視圖。在此，晶片-中介層堆疊次組體10與圖8所示結構類 似，惟差異處在於，此圖中之中介層11’上僅設有單個覆晶式晶片13。晶片13係置放於凹穴215中，而中介層11’位於凹穴215外，同時中介層11’之第二表面113係貼附於介電層23上。藉由塗佈黏著劑194於凹穴之底部上，然後將晶片-中介層堆疊次組體10之晶片13***凹穴215中，以將晶片13設置於含金屬載體20上。凹穴215中之黏著劑194(通常為導熱但不導電之黏著劑)受到晶片13擠壓，進而往下流入晶片13與凹穴側壁間的間隙，並且溢流至介電層23之平坦表面上。因此，黏著劑194圍繞嵌埋之晶片13，且擠出之部分亦作為中介層貼附黏著劑。定位件257自介電層23朝向下方向延伸，且延伸超過中介層11’之第二表面113，並且靠近中介層11’之外圍邊緣，以控制中介層11’置放之準確度。 60 is a cross-sectional view of the wafer-interposer stack sub-assembly 10 attached to the metal-containing carrier 20 by an adhesive 194. Here, the wafer-interposer stack sub-group 10 and the structure class shown in FIG. The only difference is that only a single flip chip 13 is provided on the interposer 11' in this figure. The wafer 13 is placed in the recess 215, and the interposer 11' is located outside the recess 215, while the second surface 113 of the interposer 11' is attached to the dielectric layer 23. The wafer 13 is placed on the metal-containing carrier 20 by applying an adhesive 194 to the bottom of the recess and then inserting the wafer 13 of the wafer-interposer stack sub-assembly 10 into the recess 215. The adhesive 194 (usually a thermally conductive but non-conductive adhesive) in the recess 215 is pressed by the wafer 13 and flows downward into the gap between the wafer 13 and the sidewall of the recess and overflows to the flat surface of the dielectric layer 23. on. Therefore, the adhesive 194 surrounds the embedded wafer 13, and the extruded portion also serves as an interposer to which the adhesive is attached. The positioning member 257 extends from the dielectric layer 23 in the downward direction and extends beyond the second surface 113 of the interposer 11' and near the peripheral edge of the interposer 11' to control the accuracy of the placement of the interposer 11'.

圖61為平衡層311、第一絕緣層312、以及第一金屬板31層壓 /塗佈於中介層11’及含金屬載體20上，以及第二絕緣層322及第二金屬板32層壓/塗佈於含金屬載體20之第二表面213上之剖視圖。平衡層311係接觸及覆蓋含金屬載體20之介電層23以及中介層11’之側壁，並且延伸進入貫穿開口219中。第一絕緣層312係側向延伸於中介層11’及平衡層311上，且接觸第一金屬板31、中介層11’、及平衡層311，並且提供第一金屬板31與中介層11’間、以及第一金屬板31與平衡層311間之堅固機械性接合。第二絕緣層322係側向延伸於含金屬載體20之第二表面213上，且接觸第二金屬板32以及含金屬載體20，並且提供第二金屬板32與含金屬載體20間之堅固機械性接合。 61 is a laminate of the balance layer 311, the first insulating layer 312, and the first metal plate 31. / Applied to the interposer 11' and the metal-containing carrier 20, and a cross-sectional view of the second insulating layer 322 and the second metal plate 32 laminated/coated on the second surface 213 of the metal-containing carrier 20. The balancing layer 311 contacts and covers the dielectric layer 23 of the metal-containing carrier 20 and the sidewalls of the interposer 11' and extends into the through opening 219. The first insulating layer 312 extends laterally on the interposer 11' and the balancing layer 311, and contacts the first metal plate 31, the interposer 11', and the balancing layer 311, and provides the first metal plate 31 and the interposer 11' A strong mechanical bond between the first metal plate 31 and the balance layer 311. The second insulating layer 322 extends laterally on the second surface 213 of the metal-containing carrier 20 and contacts the second metal plate 32 and the metal-containing carrier 20, and provides a strong mechanical mechanism between the second metal plate 32 and the metal-containing carrier 20. Sexual engagement.

圖62為形成第一及第二盲孔313、323以及穿孔401後之剖視 圖。第一盲孔313係延伸穿過第一金屬板31及第一絕緣層312，並且對準中介層11’之第一接觸墊112。第二盲孔323係延伸穿過第二金屬板32及第二絕 緣層322，並且對準含金屬載體20之選定部分。穿孔401對準貫穿開口219，並且朝垂直方向延伸穿過第一金屬板31、第一絕緣層312、平衡層311、第二絕緣層322、以及第二金屬板32。 62 is a cross-sectional view showing the first and second blind holes 313, 323 and the through holes 401 Figure. The first blind via 313 extends through the first metal plate 31 and the first insulating layer 312 and is aligned with the first contact pad 112 of the interposer 11'. The second blind hole 323 extends through the second metal plate 32 and the second The edge layer 322 is aligned with selected portions of the metal-containing carrier 20. The through hole 401 is aligned with the through opening 219 and extends through the first metal plate 31, the first insulating layer 312, the balance layer 311, the second insulating layer 322, and the second metal plate 32 in the vertical direction.

參照圖63，藉由沉積第一披覆層31’於第一金屬板31上及第 一盲孔313中，沉積第二披覆層32’於第二金屬板32上及第二盲孔323中，然後圖案化第一及第二金屬板31、32以及其上之第一及第二披覆層31’、32’，以分別形成位於第一絕緣層312及第二絕緣層322上之第一導線315及第二導線325。連接層403亦沉積於穿孔401中，以形成披覆穿孔411。第一導線315自第一絕緣層312朝向下方向延伸，且側向延伸於第一絕緣層312上，並且朝向上方向延伸進入第一盲孔313中，以形成直接接觸中介層11’之第一接觸墊112之第一導電盲孔317，藉以提供中介層11’之信號路由。第二導線325自第二絕緣層322朝向上方向延伸，且側向延伸於第二絕緣層322上，並且朝向下方向延伸進入第二盲孔323中，以形成直接接觸含金屬載體20選定部分之第二導電盲孔327，其係作為散熱及接地連接用。披覆穿孔411之第一端延伸至第一導線315，第二端延伸至第二導線325，以提供垂直信號連接通路。 Referring to FIG. 63, the first cladding layer 31' is deposited on the first metal plate 31 and In a blind via 313, a second cladding layer 32' is deposited on the second metal plate 32 and the second blind via 323, and then the first and second metal plates 31, 32 and the first and the first thereon are patterned. The two cladding layers 31', 32' are formed to form a first wire 315 and a second wire 325 on the first insulating layer 312 and the second insulating layer 322, respectively. A tie layer 403 is also deposited in the perforations 401 to form a covered perforation 411. The first wire 315 extends downward from the first insulating layer 312 and extends laterally on the first insulating layer 312 and extends into the first blind via 313 in an upward direction to form a direct contact interposer 11' A first conductive blind via 317 of a contact pad 112 provides signal routing for the interposer 11'. The second wire 325 extends upward from the second insulating layer 322 and extends laterally on the second insulating layer 322 and extends downward into the second blind via 323 to form a direct contact with the selected portion of the metal-containing carrier 20. The second conductive blind via 327 is used for heat dissipation and ground connection. The first end of the cladding via 411 extends to the first wire 315 and the second end extends to the second wire 325 to provide a vertical signal connection path.

據此，如圖63所示，完成之半導體封裝件410係包括中介層 11’、晶片13、含金屬載體20、第一增層電路301、第二增層電路302、以及披覆穿孔411。藉由覆晶製程，將晶片13電性耦接至預製之中介層11’，以形成晶片-中介層堆疊次組體10。作為金屬散熱座22之含金屬載體20係包括凹穴215，其係延伸穿過介電層23以及延伸進入金屬板21中。使用黏著劑194，將晶片-中介層堆疊次組體10貼附至含金屬載體20，並使晶片13置放於凹穴 215中，同時定位件257側向對準且靠近中介層11’之外圍邊緣。黏著劑194圍繞嵌埋之晶片13，且黏著劑194擠出之部分係接觸中介層11’之第二表面113及介電層23，並且夾置於中介層11’之第二表面113及介電層23間，以作為中介層貼附黏著劑。含金屬載體20之定位件257係自介電層23朝向下方向延伸，且延伸超過中介層11’之第二表面113，並且靠近中介層11’之外圍邊緣，以控制中介層11’置放之準確度。第一增層電路301係藉由第一導電盲孔317電性耦接至中介層11’，以提供扇出路由/互連。第二增層電路302係藉由第二導電盲孔327熱性及電性耦接至含金屬載體20，以作為散熱及接地連接用。披覆穿孔411係電性耦接至第一及第二導線315、325，以提供具有堆疊能力之半導體封裝件。 Accordingly, as shown in FIG. 63, the completed semiconductor package 410 includes an interposer. 11', wafer 13, metal-containing carrier 20, first build-up circuit 301, second build-up circuit 302, and cladding vias 411. The wafer 13 is electrically coupled to the pre-fabricated interposer 11' by a flip chip process to form a wafer-interposer stack sub-assembly 10. The metal-containing carrier 20 as the metal heat sink 22 includes a recess 215 that extends through the dielectric layer 23 and into the metal plate 21. The wafer-interposer stack sub-assembly 10 is attached to the metal-containing carrier 20 using the adhesive 194, and the wafer 13 is placed in the recess. In 215, simultaneously the positioning member 257 is laterally aligned and adjacent to the peripheral edge of the interposer 11'. The adhesive 194 surrounds the embedded wafer 13, and the extruded portion of the adhesive 194 contacts the second surface 113 of the interposer 11' and the dielectric layer 23, and is sandwiched between the second surface 113 of the interposer 11' and The electrical layer 23 is attached as an interposer with an adhesive. The positioning member 257 of the metal-containing carrier 20 extends from the dielectric layer 23 in the downward direction and extends beyond the second surface 113 of the interposer 11' and is adjacent to the peripheral edge of the interposer 11' to control the interposer 11'. The accuracy. The first build-up circuit 301 is electrically coupled to the interposer 11' by a first conductive via 317 to provide a fan-out routing/interconnect. The second build-up circuit 302 is thermally and electrically coupled to the metal-containing carrier 20 via the second conductive via 327 for heat dissipation and ground connection. The cladding vias 411 are electrically coupled to the first and second leads 315, 325 to provide a semiconductor package having stacking capabilities.

圖64為堆疊式封裝組體400之剖視圖，其係另一半導體封裝 件420設置於圖63半導體封裝件410之第一增層電路301上。在此圖中，半導體封裝件310更具有位於穿孔401內剩餘空間之絕緣性填充物415，以及位於第一及第二增層電路301、302上之焊料遮罩41。焊料遮罩41包括焊料遮罩開口，其係顯露第一及第二導線315、325之選定部分。據此，半導體封裝件420可經由焊球51設置於半導體封裝件410之第一導線315顯露部分上。 64 is a cross-sectional view of a stacked package body 400, which is another semiconductor package. The device 420 is disposed on the first build-up circuit 301 of the semiconductor package 410 of FIG. In this figure, the semiconductor package 310 further has an insulating filler 415 located in the remaining space in the via 401, and a solder mask 41 on the first and second build-up circuits 301, 302. The solder mask 41 includes a solder mask opening that reveals selected portions of the first and second wires 315, 325. Accordingly, the semiconductor package 420 can be disposed on the exposed portion of the first wire 315 of the semiconductor package 410 via the solder ball 51.

上述之封裝件與組體僅為說明範例，本發明尚可透過其他多 種實施例實現。此外，上述實施例可基於設計及可靠度之考量，彼此混合搭配使用或與其他實施例混合搭配使用。一晶片可獨自使用一凹穴，或與其他晶片共用一凹穴。舉例來說，一凹穴可容納單一晶片，且金屬散熱座可包括排列成陣列形狀之複數凹穴以容納複數晶片。或者，單一凹穴內能放置數個晶片。同樣地，一晶片可獨自使用一中介層，或與其他晶片共用 一中介層。舉例來說，單一晶片可電性耦接至一中介層。或者，數個晶片可耦接至一中介層。舉例來說，可將四枚排列成2x2陣列之小型晶片耦接至一中介層，並且該中介層可包括額外的接觸墊，以接收額外晶片墊，並提供額外晶片墊之路由。增層電路亦可包括額外的導線，以連接該中介層之額外的接觸墊。 The above package and assembly are only illustrative examples, and the present invention can still pass other An embodiment implementation. In addition, the above embodiments may be used in combination with each other or in combination with other embodiments based on design and reliability considerations. A wafer can use a recess alone or share a recess with other wafers. For example, a recess can accommodate a single wafer, and the metal heat sink can include a plurality of pockets arranged in an array to accommodate a plurality of wafers. Alternatively, several wafers can be placed in a single pocket. Similarly, a wafer can use an interposer alone or be shared with other wafers. An intermediary layer. For example, a single wafer can be electrically coupled to an interposer. Alternatively, several wafers can be coupled to an interposer. For example, four small wafers arranged in a 2x2 array can be coupled to an interposer, and the interposer can include additional contact pads to receive additional wafer pads and provide routing of additional wafer pads. The build-up circuitry may also include additional wires to connect the additional contact pads of the interposer.

如上述實施態樣所示，本發明建構出一種應用於堆疊式封裝 之獨特的半導體封裝件，其可展現優越之散熱性能與可靠度，且包括一晶片、一中介層、一黏著劑、一金屬散熱座、一第一增層電路、一第二增層電路、以及複數披覆穿孔。 As shown in the above embodiment, the present invention constructs a package for use in a stacked package. The unique semiconductor package exhibits superior heat dissipation performance and reliability, and includes a wafer, an interposer, an adhesive, a metal heat sink, a first build-up circuit, a second build-up circuit, And a plurality of drape perforations.

晶片藉由凸塊電性耦接至中介層，以形成晶片-中介層堆疊 次組體。晶片可為已封裝或未封裝之晶片。此外，晶片可為裸晶，或是晶圓級封裝晶片等。 The wafer is electrically coupled to the interposer by bumps to form a wafer-interposer stack Subgroup. The wafer can be a packaged or unpackaged wafer. In addition, the wafer can be a bare crystal, or a wafer level package wafer.

金屬散熱座可延伸至半導體封裝件之外圍邊緣，以提供晶 片、中介層、第一增層電路、以及第二增層電路之機械性支撐。或者，金屬散熱座可與半導體封裝件之外圍邊緣彼此保持距離。在一較佳之實施態樣中，金屬散熱座包括金屬板，其係提供嵌埋晶片之散熱與電磁屏蔽。金屬板之厚度可為0.1至10毫米。金屬板之材料可包括銅、鋁、不銹鋼、或其合金。金屬散熱座更包括延伸進入金屬板中之凹穴，並且該金屬散熱座罩蓋凹穴中之晶片。因此，凹穴之金屬材質底部及側壁能提供嵌埋晶片之散熱接觸表面，以及嵌埋晶片之垂直與水平方向之電磁屏蔽。 A metal heat sink extends to the peripheral edge of the semiconductor package to provide crystal Mechanical support of the sheet, the interposer, the first build-up circuit, and the second build-up circuit. Alternatively, the metal heat sink can be spaced from each other by the peripheral edges of the semiconductor package. In a preferred embodiment, the metal heat sink includes a metal plate that provides heat dissipation and electromagnetic shielding of the embedded wafer. The metal plate may have a thickness of 0.1 to 10 mm. The material of the metal plate may include copper, aluminum, stainless steel, or an alloy thereof. The metal heat sink further includes a recess extending into the metal plate, and the metal heat sink covers the wafer in the recess. Therefore, the bottom of the metal material of the recess and the sidewall can provide a heat-dissipating contact surface for embedding the wafer, and electromagnetic shielding of the vertical and horizontal directions of the embedded wafer.

金屬散熱座可為單層或多層結構，並且可由定位件設置於凹 穴外之含金屬載體製成。具有定位件之含金屬載體可由下列步驟製成：提供 金屬板；於該金屬板中形成凹穴；藉由移除該金屬板之選定部分，或是藉由於該金屬板上沉積金屬或塑膠材料之圖案，以形成圍繞凹穴入口之定位件。因此，由含金屬載體製成之金屬散熱座係為金屬板，該金屬板具有位於其中之凹穴以及自該凹穴入口側向延伸之平坦表面。或者，具有定位件之含金屬載體係由下列步驟製成：提供層壓基板，其包括介電層及金屬板；藉由移除位於介電層上之金屬層選定部分，或是藉由於介電層上沉積金屬或塑膠材料之圖案，以形成位於介電層上之定位件；形成凹穴，其係延伸穿過介電層且延伸進入金屬板中。因此，由含金屬載體製成之金屬散熱座係為層壓基板，其包括金屬板、介電層，並且具有延伸穿過介電層且延伸進入金屬板中之凹穴。關於延伸至半導體封裝件外圍邊緣之金屬散熱座態樣，其係保留整個含金屬載體，以作為金屬散熱座。關於與半導體封裝件外圍邊緣彼此保持距離之金屬散熱座另一態樣，其係移除含金屬載體之選定部分，以形成金屬散熱座，該金屬散熱座係為含金屬載體之選定保留部分，芯層進一步填充含金屬載體之移除部分，且覆蓋金屬散熱座之側壁。 芯層之第一表面實質上與含金屬散熱座之第一表面呈共平面，而芯層之第二表面則實質上與含金屬散熱座之第二表面呈共平面。此外，除了作為金屬散熱座之上述選定保留部分外，可保留含金屬載體之另外選定金屬部分，以作為電源/接地或信號連接用之金屬柱，並且芯層亦側向覆蓋金屬柱之側壁。金屬柱與金屬散熱座係藉由芯層彼此分隔，並且該金屬柱實質上於第一及第二垂直方向分別與芯層以及金屬散熱座之金屬平坦表面共平面(為了方便描述，中介層之第一表面所面對的方向定義為第一垂直方向，中介層之第二表面所面對的方向定義為第二垂直方向)。芯層材料可包括環氧 樹脂、BT、聚醯亞胺、或其他種類之樹脂或樹脂/玻璃複合物，並且於側向提供金屬散熱座及可選擇性形成的金屬柱之機械性支撐。 The metal heat sink can be a single layer or a multi-layer structure, and can be disposed in the concave by the positioning member Made of a metal-containing carrier outside the hole. A metal-containing carrier having a positioning member can be made by the following steps: a metal plate; forming a recess in the metal plate; or removing a selected portion of the metal plate or by depositing a pattern of metal or plastic material on the metal plate to form a positioning member surrounding the entrance of the cavity. Thus, the metal heat sink made of a metal-containing carrier is a metal plate having a recess therein and a flat surface extending laterally from the inlet of the pocket. Alternatively, the metal-containing carrier having the positioning member is made by providing a laminated substrate comprising a dielectric layer and a metal plate; by removing a selected portion of the metal layer on the dielectric layer, or by A pattern of metal or plastic material is deposited over the electrical layer to form a locating feature on the dielectric layer; a recess is formed that extends through the dielectric layer and into the metal sheet. Thus, the metal heat sink made of a metal-containing carrier is a laminate substrate that includes a metal plate, a dielectric layer, and has recesses that extend through the dielectric layer and into the metal plate. Regarding the metal heat sink pattern extending to the peripheral edge of the semiconductor package, it retains the entire metal-containing carrier as a metal heat sink. In another aspect of the metal heat sink that is spaced from the peripheral edges of the semiconductor package, the selected portion of the metal-containing carrier is removed to form a metal heat sink that is a selected retention portion of the metal-containing carrier. The core layer is further filled with a removed portion of the metal-containing carrier and covers the sidewalls of the metal heat sink. The first surface of the core layer is substantially coplanar with the first surface of the metal containing heat sink, and the second surface of the core layer is substantially coplanar with the second surface of the metal containing heat sink. In addition, in addition to the selected retention portion of the metal heat sink, an additional selected metal portion of the metal-containing carrier may be retained for use as a metal post for power/ground or signal connections, and the core layer also laterally covers the sidewalls of the metal post. The metal post and the metal heat sink are separated from each other by a core layer, and the metal pillar is substantially coplanar with the metal flat surface of the core layer and the metal heat sink in substantially the first and second vertical directions (for convenience of description, the interposer The direction in which the first surface faces is defined as the first vertical direction, and the direction in which the second surface of the interposer faces is defined as the second vertical direction). Core material may include epoxy Resin, BT, polyimine, or other types of resin or resin/glass composite, and provide lateral support for metal heat sinks and selectively formed metal posts.

定位件可自金屬散熱座中鄰接凹穴入口之平坦表面朝第一 垂直方向延伸，並且延伸超過中介層之第二表面。因此，藉由定位件側向對準與靠近中介層之外圍邊緣，可控制中介層置放之準確度。定位件可為金屬、光敏性塑膠材料或非光敏性材料所製成。舉例來說，定位件可實質上由銅、鋁、鎳、鐵、錫或其合金組成。定位件亦可包括環氧樹脂或聚醯亞胺，或是由環氧樹脂或聚醯亞胺組成。再者，定位件可具有防止中介層發生不必要位移之各種圖案。舉例來說，定位件可包括一連續或不連續之凸條、或是凸柱陣列。或者，定位件可側向延伸至金屬散熱座之外圍邊緣，且其內周圍邊緣與中介層之外圍邊緣相符。具體來說，定位件可側向對準中介層之四側邊，以定義出與中介層形狀相同或相似之區域，並且避免中介層之側向位移。舉例來說，定位件可對準並符合中介層之四側邊、兩對角、或四角，並且定位件與中介層間之間隙較佳於5至50微米之範圍內。因此，位在中介層外之定位件可控制晶片-中介層堆疊次組體置放之準確度。 此外，設置於凹穴入口外之定位件較佳具有位於5至200微米範圍內之高度。 The positioning member can be from the flat surface of the metal heat sink adjacent to the entrance of the pocket toward the first Extending in the vertical direction and extending beyond the second surface of the interposer. Therefore, the accuracy of the placement of the interposer can be controlled by lateral alignment of the positioning member and proximity to the peripheral edge of the interposer. The positioning member can be made of metal, photosensitive plastic material or non-photosensitive material. For example, the locating member can consist essentially of copper, aluminum, nickel, iron, tin, or alloys thereof. The positioning member may also comprise an epoxy resin or a polyimide or an epoxy resin or a polyimide. Further, the positioning member may have various patterns that prevent the interposer from being unnecessarily displaced. For example, the positioning member can include a continuous or discontinuous rib or an array of studs. Alternatively, the positioning member may extend laterally to the peripheral edge of the metal heat sink and the inner peripheral edge thereof conforms to the peripheral edge of the interposer. In particular, the locating members can be laterally aligned with the four sides of the interposer to define regions of the same or similar shape as the interposer and to avoid lateral displacement of the interposer. For example, the positioning member can be aligned and conform to the four sides, two diagonals, or four corners of the interposer, and the gap between the positioning member and the interposer is preferably in the range of 5 to 50 microns. Therefore, the positioning member located outside the interposer can control the accuracy of the wafer-interposer stack sub-group placement. Further, the positioning member disposed outside the entrance of the pocket preferably has a height in the range of 5 to 200 microns.

金屬散熱座之凹穴可在其入口處具有較其底部更大之直徑或尺寸，並且具有0.05毫米至1.0毫米之深度。舉例來說，凹穴可具有橫切之圓錐或方錐形狀，其直徑或大小係朝第一垂直方向自底部向入口遞增。或者，凹穴可為具有固定直徑之圓柱形狀。凹穴亦可在其入口及底部具有圓形、正方形或矩形之周緣。 The recess of the metal heat sink can have a larger diameter or size at its entrance than its bottom and has a depth of 0.05 mm to 1.0 mm. For example, the pockets may have a cross-sectional conical or square pyramid shape with a diameter or size that increases from the bottom toward the inlet toward the first vertical direction. Alternatively, the pocket may be in the shape of a cylinder having a fixed diameter. The recess may also have a circumference of a circle, a square or a rectangle at its entrance and bottom.

黏著劑可先塗佈於凹穴底部上，然後當晶片***凹穴中時， 部分黏著劑擠出凹穴外。因此，黏著劑可接觸及圍繞金屬散熱座凹穴中之嵌埋晶片，並且黏著劑之擠出部分可接觸中介層之第二表面及自金屬散熱座中凹穴入口側向延伸之之平坦表面，並夾置於中介層之第二表面及自金屬散熱座中凹穴入口側向延伸之平坦表面間。或者，可將導熱黏著劑塗佈於凹穴底部，且當晶片***凹穴中時，導熱黏著劑仍位於凹穴中。然後可將第二黏著劑(通常為電性絕緣之底部填充材料)塗佈並填入凹穴中之剩餘空間中，並延伸至中介層之第二表面及自金屬散熱座中凹穴入口側向延伸之平坦表面間。據此，第一黏著劑提供晶片與金屬散熱座間之機械性接合及熱性連接，而第二黏著劑提供中介層與金屬散熱座間之機械性接合。 The adhesive can be applied to the bottom of the pocket first, and then when the wafer is inserted into the pocket, Part of the adhesive is squeezed out of the pocket. Therefore, the adhesive can contact and surround the embedded wafer in the recess of the metal heat sink, and the extruded portion of the adhesive can contact the second surface of the interposer and the flat surface extending laterally from the entrance of the recess in the metal heat sink. And sandwiched between the second surface of the interposer and the flat surface extending laterally from the entrance of the recess in the metal heat sink. Alternatively, a thermally conductive adhesive can be applied to the bottom of the pocket and the thermally conductive adhesive remains in the pocket as the wafer is inserted into the pocket. A second adhesive (typically an electrically insulating underfill material) can then be applied and filled into the remaining space in the pocket and extended to the second surface of the interposer and from the entrance side of the recess in the metal heat sink Between the flat surfaces that extend. Accordingly, the first adhesive provides a mechanical bond and a thermal bond between the wafer and the metal heat sink, and the second adhesive provides a mechanical bond between the interposer and the metal heat sink.

中介層係側向延伸於凹穴外，並且可使該中介層之第二表面 面對金屬散熱座，以貼附至金屬散熱座中鄰接凹穴入口之平坦表面。中介層之材料可為矽、玻璃、陶瓷或石墨，其具有50至500微米之厚度，中介層可包含導線圖案，且該導線圖案係由第二接觸墊之細微間距扇出至第一接觸墊之粗間距。因此，中介層能提供嵌埋晶片之第一級扇出路由/互連。此外，因為中介層通常係由高彈性係數材料製成，且該高彈性係數材料具有與晶片匹配之熱膨脹係數(例如，每攝氏3至10ppm)，因此，可大幅降低或補償熱膨脹係數不匹配所導致之晶片及其電性互連處之內部應力。 The interposer extends laterally beyond the recess and can provide a second surface of the interposer Facing the metal heat sink to attach to the flat surface of the metal heat sink that abuts the entrance of the pocket. The material of the interposer may be tantalum, glass, ceramic or graphite having a thickness of 50 to 500 microns, the interposer may comprise a wire pattern, and the wire pattern is fanned out to the first contact pad by the fine pitch of the second contact pad The coarse pitch. Thus, the interposer can provide a first level of fanout routing/interconnecting of the embedded wafer. In addition, since the interposer is usually made of a high modulus of elasticity material and the coefficient of thermal expansion matches the thermal expansion coefficient of the wafer (for example, 3 to 10 ppm per Celsius), the thermal expansion coefficient mismatch can be greatly reduced or compensated. Internal stresses caused by the wafer and its electrical interconnections.

第一及第二增層電路可分別設置於鄰接中介層之第一表面 及金屬散熱座之第二表面，並且可提供第二扇出路由/互連。此外，第一及第二增層電路可進一步藉由作為接地連接用之額外導電盲孔，以電性耦接至金屬散熱座之金屬表面或/及可選擇性形成的金屬柱。第一增層電路係包括一平衡層、一第一絕緣層、以及一或複數第一導線。第二增層電路係包 括一第二絕緣層、以及一或複數第二導線。平衡層係側向覆蓋中介層之側壁，且第一絕緣層形成於中介層之第一表面及平衡層上。第二絕緣層係覆蓋金屬散熱座之第二表面及芯層。對於移除含金屬載體選定部分之態樣，其係於移除含金屬載體之選定部分前形成平衡層，且於移除含金屬載體之選定部分及形成芯層後形成第二絕緣層。第一導線側向延伸於第一絕緣層上，並且延伸穿過位於第一絕緣層中之第一盲孔，以形成與中介層之第一接觸墊直接接觸之第一導電盲孔，並且其可選擇性地與金屬散熱座或選擇性形成的金屬柱直接接觸。第二導線係側向延伸於第二絕緣層上，並且延伸穿過第二絕緣層中選擇性形成之一或更多第二盲孔，以形成一或更多之第二導電盲孔，其係直接接觸金屬散熱座及/或選擇性形成的金屬柱。據此，第一導線可直接接觸中介層之第一接觸墊，以提供中介層之信號路由，因此中介層與第一增層電路間之電性連接無須使用焊接材料。此外，因為第一導電盲孔係直接接觸金屬散熱座，其可作為散熱管，因此，晶片產生之熱可藉由導電盲孔散逸至第一及第二增層電路之外側導電層。 The first and second build-up circuits are respectively disposed on the first surface adjacent to the interposer And a second surface of the metal heat sink, and a second fan-out routing/interconnection is provided. In addition, the first and second build-up circuits can be further electrically coupled to the metal surface of the metal heat sink or/and the selectively formable metal post by an additional conductive via as a ground connection. The first build-up circuit includes a balance layer, a first insulating layer, and one or a plurality of first wires. Second layering circuit package A second insulating layer and one or more second wires are included. The balancing layer laterally covers the sidewall of the interposer, and the first insulating layer is formed on the first surface of the interposer and the balancing layer. The second insulating layer covers the second surface of the metal heat sink and the core layer. For the removal of selected portions of the metal-containing support, a balance layer is formed prior to removal of selected portions of the metal-containing support, and a second insulating layer is formed after removal of selected portions of the metal-containing support and formation of the core layer. The first wire extends laterally on the first insulating layer and extends through the first blind via located in the first insulating layer to form a first conductive via hole in direct contact with the first contact pad of the interposer, and It can be selectively in direct contact with a metal heat sink or a selectively formed metal post. The second wire extends laterally on the second insulating layer and extends through the second insulating layer to selectively form one or more second blind holes to form one or more second conductive blind holes. Direct contact with metal heat sinks and/or selectively formed metal posts. Accordingly, the first wire can directly contact the first contact pad of the interposer to provide signal routing of the interposer, so that the electrical connection between the interposer and the first build-up circuit does not require the use of a solder material. In addition, since the first conductive blind via directly contacts the metal heat sink, it can serve as a heat sink. Therefore, the heat generated by the wafer can be dissipated to the outer conductive layer of the first and second build-up circuits by the conductive blind via.

假如需要更多的信號路由，第一及第二增層電路可進一步包 括額外之絕緣層、額外之盲孔、以及額外之導線。第一及第二增層電路之最外側導線可分別連接導電接點，例如焊球，以與另一半導體封裝件電性傳輸及機械連接。據此，藉由使用位於最外側導線上之導電接點，即可設置另一半導體封裝件於第一或第二增層電路上，以提供一堆疊式封裝組體。 If more signal routing is required, the first and second build-up circuits can be further packaged Includes additional insulation, additional blind holes, and additional wires. The outermost wires of the first and second build-up circuits may be respectively connected to conductive contacts, such as solder balls, for electrical and mechanical connection with another semiconductor package. Accordingly, another semiconductor package can be disposed on the first or second build-up circuit by using the conductive contacts on the outermost wires to provide a stacked package body.

披覆穿孔之第一端可延伸及電性連接至第一增層電路之外 側或內側導電層，第二端可延伸及電性連接至第二增層電路之外側或內側導電層，以於垂直方向提供第一增層電路及第二增層電路間之信號路由。 在以上任何情況下，披覆穿孔可提供第一增層電路及第二增層電路間的電性及熱性連接。 The first end of the cladding perforation can be extended and electrically connected to the first build-up circuit The side or inner conductive layer, the second end is extendable and electrically connected to the outer side or the inner conductive layer of the second build-up circuit to provide signal routing between the first build-up circuit and the second build-up circuit in a vertical direction. In any of the above cases, the coated perforations provide electrical and thermal connections between the first build-up circuitry and the second build-up circuitry.

可藉由以下步驟形成披覆穿孔：形成於第一端垂直延伸至第 一增層電路，以及於第二端垂直延伸至第二增層電路之穿孔；然後沉積連接層於穿孔之內側壁上。對於金屬散熱座與半導體封裝件之外圍邊緣彼此保持距離之態樣，披覆穿孔係延伸穿過覆蓋金屬散熱座側壁之芯層。據此，藉由以下步驟形成披覆穿孔：形成延伸穿過芯層之穿孔；然後沉積連接層於穿孔之內側壁上。在此態樣中，可於形成平衡層、芯層、以及第一及第二絕緣層後形成穿孔，其可朝垂直方向延伸穿過平衡層、芯層、以及增層電路之一或複數絕緣層。對於金屬散熱座延伸至半導體封裝件之外圍邊緣之另一態樣，金屬散熱座包括貫穿開口，貫穿開口具有延伸進入其中之平衡層，且披覆穿孔對準金屬散熱座之貫穿開口且延伸穿過平衡層。據此，可藉由以下步驟形成披覆穿孔：形成延伸穿過平衡層且對準貫穿開口之穿孔；然後沉積連接層於穿孔之內側壁上。因此，可於形成平衡層、第一及第二絕緣層後形成穿孔，其可朝垂直方向延伸穿過平衡層以及增層電路之一或複數絕緣層。此外，當形成增層電路之外側或內側之導線時，可同時沉積披覆穿孔之連接層。 The coated perforation can be formed by the following steps: forming a vertical extension to the first end a build-up circuit and a via extending perpendicularly to the second build-up circuit at the second end; and then depositing a tie layer on the inner sidewall of the via. For the metal heat sink and the peripheral edge of the semiconductor package to maintain a distance from each other, the cladding perforation extends through the core layer covering the sidewall of the metal heat sink. Accordingly, the coated perforations are formed by forming a perforation extending through the core layer; then depositing a tie layer on the inner sidewall of the perforation. In this aspect, a via hole may be formed after forming the balance layer, the core layer, and the first and second insulating layers, which may extend vertically in the vertical direction through the balance layer, the core layer, and one or more of the build-up circuits Floor. In another aspect in which the metal heat sink extends to a peripheral edge of the semiconductor package, the metal heat sink includes a through opening having a balance layer extending into the through opening, and the through hole is aligned with the through hole of the metal heat sink and extends through Overbalanced layer. Accordingly, the coated perforations can be formed by forming a perforation extending through the balancing layer and aligned with the through opening; and then depositing the connecting layer on the inner sidewall of the perforation. Therefore, a through hole may be formed after forming the balance layer, the first and second insulating layers, and may extend through the balance layer and one of the build-up circuits or the plurality of insulating layers in a vertical direction. Further, when the wires on the outer side or the inner side of the build-up circuit are formed, the connection layer covering the perforations may be simultaneously deposited.

「覆蓋」一詞意指於垂直及/或側面方向上不完全以及完全 覆蓋。例如，在凹穴朝向下方向之狀態下，金屬板於向上方向覆蓋晶片，不論另一元件例如黏著劑是否位於金屬板及晶片中。 The term "coverage" means incomplete and complete in the vertical and / or lateral directions cover. For example, in a state where the pocket faces downward, the metal plate covers the wafer in an upward direction regardless of whether another member such as an adhesive is located in the metal plate and the wafer.

「對準」一詞意指元件間之相對位置，不論元件之間是否彼 此保持距離或鄰接，或一元件***且延伸進入另一元件中。例如，當假想 之水平線與定位件及中介層相交時，定位件側向對準於中介層，不論定位件與中介層之間是否具有其他與假想之水平線相交之元件，且不論是否具有另一與中介層相交但不與定位件相交、或與定位件相交但不與中介層相交之假想水平線。同樣地，例如第一盲孔對準中介層之第一接觸墊。 The term "alignment" means the relative position between components, regardless of whether they are between components. This remains a distance or abutment, or an element is inserted and extends into another element. For example, when imagining When the horizontal line intersects the positioning member and the interposer, the positioning member is laterally aligned with the interposer, regardless of whether there are other elements intersecting the imaginary horizontal line between the positioning member and the interposer, and whether or not there is another intersecting with the interposer An imaginary horizontal line that does not intersect the locating member or intersects the locating member but does not intersect the interposer. Likewise, for example, the first blind via is aligned with the first contact pad of the interposer.

「靠近」一詞意指元件間之間隙的寬度不超過最大可接受範 圍。如本領域習知通識，當中介層以及定位件間之間隙不夠窄時，由於中介層於間隙中之側向位移而導致之位置誤差可能會超過可接受之最大誤差限制。在某些情況下，一旦中介層之位置誤差超過最大極限時，則不可能使用雷射光束對準中介層之預定位置，而導致中介層以及增層電路間之電性連接失敗。根據中介層之接觸墊的尺寸，於本領域之技術人員可經由試誤法以確認中介層以及定位件間之間隙的最大可接受範圍，以確保導電盲孔與中介層之接觸墊對準。由此，「定位件靠近中介層之外圍邊緣」之用語係指中介層之外圍邊緣與定位件間之間隙係窄到足以防止中介層之位置誤差超過可接受之最大誤差限制。 The term "close" means that the width of the gap between components does not exceed the maximum acceptable range. Wai. As is known in the art, when the inter-layer and the gap between the locating members are not sufficiently narrow, the positional error due to the lateral displacement of the interposer in the gap may exceed the acceptable maximum error limit. In some cases, once the positional error of the interposer exceeds the maximum limit, it is impossible to align the predetermined position of the interposer with the laser beam, resulting in failure of the electrical connection between the interposer and the build-up circuit. Depending on the size of the contact pads of the interposer, one skilled in the art can determine the maximum acceptable range of interstices and gaps between the spacers by trial and error to ensure alignment of the conductive vias with the contact pads of the interposer. Thus, the term "the locating member is adjacent to the peripheral edge of the interposer" means that the gap between the peripheral edge of the interposer and the locating member is narrow enough to prevent the positional error of the interposer from exceeding an acceptable maximum error limit.

「電性連接」、以及「電性耦接」之詞意指直接或間接電性 連接。例如，第一導線直接接觸並且電性連接至中介層之第一接觸墊，以及第三導線與中介層之第一接觸墊保持距離，並且藉由第一導線電性連接至中介層之第一接觸墊。 The terms "electrical connection" and "electrical coupling" mean direct or indirect electrical properties. connection. For example, the first wire is in direct contact and electrically connected to the first contact pad of the interposer, and the third wire is kept at a distance from the first contact pad of the interposer, and is electrically connected to the interposer by the first wire. Contact pad.

「第一垂直方向」及「第二垂直方向」並非取決於封裝件之 定向，凡熟悉此項技藝之人士即可輕易瞭解其實際所指之方向。例如，中介層之第一表面係面朝第一垂直方向，且中介層之第二表面係面朝第二垂直方向，此與封裝件是否倒置無關。同樣地，定位件係沿一側向平面「側 向」對準中介層，此與封裝件是否倒置、旋轉或傾斜無關。因此，該第一及第二垂直方向係彼此相反且垂直於側面方向，且側向對準之元件係與垂直於第一與第二垂直方向之側向平面相交。再者，在凹穴朝上之位置，第一垂直方向係為向上方向，第二垂直方向係為向下方向；在凹穴朝下之位置，第一垂直方向係為向下方向，第二垂直方向係為向上方向。 "First vertical direction" and "second vertical direction" are not dependent on the package Orientation, anyone familiar with the art can easily understand the direction in which they actually refer. For example, the first surface of the interposer faces in a first vertical direction and the second surface of the interposer faces in a second vertical direction, regardless of whether the package is inverted. Similarly, the positioning member is along the side of the plane "side" Align to the interposer, regardless of whether the package is inverted, rotated or tilted. Thus, the first and second vertical directions are opposite to each other and perpendicular to the side direction, and the laterally aligned elements intersect the lateral planes perpendicular to the first and second perpendicular directions. Furthermore, in the position where the pocket is upward, the first vertical direction is an upward direction, and the second vertical direction is a downward direction; at a position where the recess is downward, the first vertical direction is a downward direction, and the second The vertical direction is the upward direction.

本發明應用於堆疊式封裝之半導體封裝件具有許多優點。舉 例來說，藉由習知之覆晶接合製程例如熱壓或迴焊，將晶片電性耦接至中介層，其可避免使用黏著載體作為暫時接合時，會遭遇位置準確度問題。 中介層提供嵌埋晶片之第一級扇出路由/互連，而增層電路則提供第二級扇出路由/互連。當增層電路形成於具有較大接觸墊尺寸及間距之中介層上，與傳統之增層電路直接形成在晶片之I/O墊上，並且不具扇出路由之技術相比，前者具有較後者大幅改善之生產良率。定位件可控制中介層置放之準確度。因此，容置嵌埋晶片之凹穴，其形狀或深度在製程中不再是需要嚴格控制之重要參數。金屬散熱座可提供嵌埋晶片之散熱、電磁屏蔽、以及濕氣阻障，並且提供晶片、中介層、以及增層電路之機械性支撐。中介層以及增層電路係直接電性連接，且無須使用焊料，因此有利於展現高I/O值以及高性能。雙重增層電路可提供具有簡單電路圖案之信號路由，或具有複雜電路圖案之可撓性多層信號路由。披覆穿孔可提供雙重增層電路間之垂直信號路由，藉以提供具有堆疊能力之封裝件。藉由此方法製備成的封裝件係為可靠度高、價格低廉、且非常適合大量製造生產。 The semiconductor package of the present invention applied to a stacked package has many advantages. Lift For example, the wafer is electrically coupled to the interposer by a conventional flip chip bonding process such as hot pressing or reflow, which avoids the problem of positional accuracy when using the adhesive carrier as a temporary bond. The interposer provides a first level of fanout routing/interconnect for the embedded wafer, while the build-up circuitry provides a second level of fanout routing/interconnect. When the build-up circuit is formed on the interposer having a large contact pad size and pitch, the conventional build-up circuit is formed directly on the I/O pad of the chip, and the former has a larger value than the latter without the fan-out route. Improve production yield. The positioning member can control the accuracy of the placement of the interposer. Therefore, the shape or depth of the cavity in which the embedded wafer is accommodated is no longer an important parameter that needs to be strictly controlled in the process. The metal heat sink provides heat dissipation, electromagnetic shielding, and moisture barrier for the embedded wafer and provides mechanical support for the wafer, interposer, and build-up circuitry. The interposer and the build-up circuit are directly electrically connected and do not require the use of solder, thus facilitating the presentation of high I/O values and high performance. Dual build-up circuits can provide signal routing with simple circuit patterns or flexible multilayer signal routing with complex circuit patterns. The drape perforation provides vertical signal routing between the dual build-up circuits to provide a package with stacking capability. The package prepared by this method is highly reliable, inexpensive, and is very suitable for mass production.

本案之製作方法具有高度適用性，且係以獨特、進步之方式 結合運用各種成熟之電性及機械性連接技術。此外，本案之製作方法不需 昂貴工具即可實施。因此，相較於傳統技術，此製作方法可大幅提升產量、良率、效能與成本效益。 The production method of this case is highly applicable and is in a unique and progressive way. Combine the use of a variety of mature electrical and mechanical connection technology. In addition, the production method of this case is not required Expensive tools can be implemented. Therefore, compared to the traditional technology, this production method can greatly increase the yield, yield, efficiency and cost-effectiveness.

在此所述之實施例係為例示之用，其中該些實施例可能會簡化或省略本技術領域已熟知之元件或步驟，以免模糊本發明之特點。同樣地，為使圖式清晰，圖式亦可能省略重覆或非必要之元件及元件符號。 The embodiments described herein are illustrative, and the elements or steps that are well known in the art may be simplified or omitted in order to avoid obscuring the features of the present invention. Similarly, in order to make the drawings clear, the drawings may also omit redundant or non-essential components and component symbols.

11’‧‧‧中介層 11’‧‧‧Intermediary

112‧‧‧第一接觸墊 112‧‧‧First contact pad

200‧‧‧堆疊式封裝組體 200‧‧‧Stacked package body

217‧‧‧定位件 217‧‧‧ Positioning parts

220‧‧‧半導體封裝件 220‧‧‧Semiconductor package

26‧‧‧芯層 26‧‧‧ core layer

301‧‧‧第一增層電路 301‧‧‧First build-up circuit

302‧‧‧第二增層電路 302‧‧‧Second layered circuit

311‧‧‧平衡層 311‧‧‧Equilibrium

312‧‧‧第一絕緣層 312‧‧‧First insulation

313‧‧‧第一盲孔 313‧‧‧First blind hole

314‧‧‧第一盲孔 314‧‧‧First blind hole

315‧‧‧第一導線 315‧‧‧First wire

317‧‧‧第一導電盲孔 317‧‧‧First conductive blind hole

318‧‧‧第一導電盲孔 318‧‧‧First conductive blind hole

322‧‧‧第二絕緣層 322‧‧‧Second insulation

325‧‧‧第二導線 325‧‧‧second wire

401‧‧‧穿孔 401‧‧‧Perforation

41‧‧‧焊料遮罩 41‧‧‧ solder mask

415‧‧‧絕緣性填充物 415‧‧‧Insulating filler

51‧‧‧焊球 51‧‧‧ solder balls

Claims (15)

一種具有堆疊式封裝能力之半導體封裝件製作方法，包含以下步驟：提供一晶片；提供一中介層，其包含一第一表面、與該第一表面相反之一第二表面、該第一表面上之複數個第一接觸墊、該第二表面上之複數個第二接觸墊、以及電性耦接該些第一接觸墊與該些第二接觸墊之複數個貫孔；藉由複數個凸塊電性耦接該晶片至該中介層之該些第二接觸墊，以形成一晶片-中介層堆疊次組體；提供一含金屬載體，其具有一第一表面、相反之一第二表面、以及形成於該第一表面之一凹穴；使用一黏著劑貼附該晶片-中介層堆疊次組體至該含金屬載體，並使該晶片***該凹穴中，且該中介層側向延伸於該凹穴外；於該晶片-中介層堆疊次組體貼附至該含金屬載體後，於該中介層之該第一表面上形成一第一增層電路，其中該第一增層電路係藉由該第一增層電路之複數個第一導電盲孔電性耦接至該中介層之該些第一接觸墊；移除該含金屬載體之選定部分，以形成一金屬散熱座，該金屬散熱座係為罩蓋該凹穴內之該晶片的該金屬載體之一第一剩餘部分，並且具有對應於該含金屬載體之該第一表面的一第一表面及相反之一第二表面；形成一芯層，其係側向覆蓋該金屬散熱座之側壁；於該金屬散熱座之該第二表面上及該芯層上形成一第二增層電路；以及形成延伸穿過該芯層之複數個披覆穿孔，以提供該第一增層電路與該第二增層電路間之電性及熱性連接。 A method of fabricating a semiconductor package having a stacked package capability, comprising the steps of: providing a wafer; providing an interposer comprising a first surface, a second surface opposite the first surface, the first surface a plurality of first contact pads, a plurality of second contact pads on the second surface, and a plurality of through holes electrically coupled to the first contact pads and the second contact pads; The block electrically couples the wafer to the second contact pads of the interposer to form a wafer-interposer stack sub-assembly; and provides a metal-containing carrier having a first surface and an opposite second surface And forming a recess in the first surface; attaching the wafer-interposer stack sub-assembly to the metal-containing carrier using an adhesive, and inserting the wafer into the recess, and the interposer is laterally Extending from the recess; after the wafer-interposer stack sub-assembly is attached to the metal-containing carrier, a first build-up circuit is formed on the first surface of the interposer, wherein the first build-up circuit By the complex of the first build-up circuit The first conductive blind vias are electrically coupled to the first contact pads of the interposer; the selected portion of the metal-containing carrier is removed to form a metal heat sink, and the metal heat sink is covered by the recess a first remaining portion of the metal carrier of the wafer, and having a first surface and a second surface opposite the first surface of the metal-containing carrier; forming a core layer laterally Covering a sidewall of the metal heat sink; forming a second build-up circuit on the second surface of the metal heat sink and the core layer; and forming a plurality of cladding vias extending through the core layer to provide the The first build-up circuit is electrically and thermally connected to the second build-up circuit. 如申請專利範圍第1項所述之方法，其中該電性耦接該晶片至該中介層之該些第二接觸墊的步驟係以面板規模進行，並且於該貼附該晶片-中介層堆疊次組體至該含金屬載體之步驟前執行一單片化步驟，以分離個別的晶片-中介層堆疊次組體。 The method of claim 1, wherein the step of electrically coupling the wafer to the second contact pads of the interposer is performed on a panel scale, and the wafer-interposer stack is attached to the wafer. A singulation step is performed prior to the step of sub-assembly to the metal-containing support to separate individual wafer-interposer stack sub-assemblies. 如申請專利範圍第1項所述之方法，其中該含金屬載體更包括位於該凹穴外之一定位件，並且該晶片-中介層堆疊次組體係藉由該定位件側向對準與靠近該中介層之外圍邊緣，以貼附至該含金屬載體。 The method of claim 1, wherein the metal-containing carrier further comprises a positioning member located outside the recess, and the wafer-interposer stack sub-system is laterally aligned and approached by the positioning member. The peripheral edge of the interposer is attached to the metal-containing carrier. 如申請專利範圍第1項所述之方法，其中該第二增層電路包含複數個第二導電盲孔，以電性及熱性耦接至該金屬散熱座。 The method of claim 1, wherein the second build-up circuit comprises a plurality of second conductive vias electrically and thermally coupled to the metal heat sink. 如申請專利範圍第1項所述之方法，其中移除該含金屬載體選定部分之該步驟亦形成一金屬柱，其係為該含金屬載體之一第二剩餘部分，並與該第一剩餘部分彼此保持距離。 The method of claim 1, wherein the step of removing the selected portion of the metal-containing carrier also forms a metal post which is the second remaining portion of the metal-containing carrier and the first remaining portion Parts are kept away from each other. 一種具有堆疊式封裝能力之半導體封裝件製作方法，包含以下步驟：提供一晶片；提供一中介層，其包含一第一表面、與該第一表面相反之一第二表面、該第一表面上之複數個第一接觸墊、該第二表面上之複數個第二接觸墊、以及電性耦接該些第一接觸墊與該些第二接觸墊之複數個貫孔；藉由複數個凸塊電性耦接該晶片至該中介層之該些第二接觸墊，以形成一晶片-中介層堆疊次組體；提供一含金屬載體，其具有一第一表面、相反之一第二表面、以及形成於該第一表面之一凹穴；於該含金屬載體之該第一表面與該第二表面間形成延伸穿過該含金屬載體 之複數個貫穿開口；使用一黏著劑貼附該晶片-中介層堆疊次組體至該含金屬載體，並使該晶片***該凹穴中，且該中介層側向延伸於該凹穴外；於該晶片-中介層堆疊次組體貼附至該含金屬載體後，於該中介層之該第一表面上形成一第一增層電路，其中該第一增層電路係藉由該第一增層電路之複數個第一導電盲孔電性耦接至該中介層之該些第一接觸墊；於該含金屬載體之該第二表面上形成一第二增層電路；以及形成延伸穿過該些貫穿開口之複數個披覆穿孔，以提供該第一增層電路與該第二增層電路間之電性及熱性連接。 A method of fabricating a semiconductor package having a stacked package capability, comprising the steps of: providing a wafer; providing an interposer comprising a first surface, a second surface opposite the first surface, the first surface a plurality of first contact pads, a plurality of second contact pads on the second surface, and a plurality of through holes electrically coupled to the first contact pads and the second contact pads; The block electrically couples the wafer to the second contact pads of the interposer to form a wafer-interposer stack sub-assembly; and provides a metal-containing carrier having a first surface and an opposite second surface And forming a recess in the first surface; forming an extension between the first surface and the second surface of the metal-containing carrier through the metal-containing carrier a plurality of through openings; attaching the wafer-interposer stack sub-assembly to the metal-containing carrier using an adhesive, and inserting the wafer into the recess, and the interposer extends laterally outside the recess; After the wafer-interposer stack sub-assembly is attached to the metal-containing carrier, a first build-up circuit is formed on the first surface of the interposer, wherein the first build-up circuit is a plurality of first conductive vias electrically coupled to the first contact pads of the interposer; a second build-up circuit formed on the second surface of the metal-containing carrier; and forming an extension through The plurality of cladding perforations are formed through the opening to provide electrical and thermal connection between the first build-up circuit and the second build-up circuit. 如申請專利範圍第6項所述之方法，其中該含金屬載體更包括位於該凹穴外之一定位件，並且該晶片-中介層堆疊次組體係藉由該定位件側向對準與靠近該中介層之外圍邊緣，以貼附至該含金屬載體。 The method of claim 6, wherein the metal-containing carrier further comprises a positioning member located outside the recess, and the wafer-interposer stack sub-system is laterally aligned and approached by the positioning member. The peripheral edge of the interposer is attached to the metal-containing carrier. 如申請專利範圍第6項所述之方法，其中該第二增層電路包含複數個第二導電盲孔，以電性及熱性耦接至該含金屬載體。 The method of claim 6, wherein the second build-up circuit comprises a plurality of second conductive blind vias electrically and thermally coupled to the metal-containing carrier. 一種具有堆疊式封裝能力之半導體封裝件，其包含：一晶片；一中介層，其具有一第一表面、與該第一表面相反之一第二表面、該第一表面上之複數個第一接觸墊，該第二表面上之複數個第二接觸墊、以及電性耦接該些第一接觸墊與該些第二接觸墊之複數個貫孔；一金屬散熱座，其具有一第一表面、相反之一第二表面、以及形成於該第一表面之一凹穴；一第一增層電路，其係形成在該中介層之該第一表面上，其中該第一增層 電路係藉由該第一增層電路之複數個第一導電盲孔電性耦接至該中介層之該些第一接觸墊；一芯層，其係側向覆蓋該金屬散熱座之側壁；一第二增層電路，其係形成於該金屬散熱座之該第二表面上及該芯層上；以及複數個披覆穿孔，其係延伸穿過該芯層，以提供該第一增層電路與該第二增層電路間之電性及熱性連接，其中該晶片係藉由複數個凸塊電性耦接至該中介層之該些第二接觸墊，以形成一晶片-中介層堆疊次組體；且該晶片-中介層堆疊次組體係藉由一黏著劑貼附至該金屬散熱座，並且該凹穴係罩蓋該晶片，且該中介層係側向延伸於該凹穴外。 A semiconductor package having a stacked package capability, comprising: a wafer; an interposer having a first surface, a second surface opposite the first surface, and a plurality of first surfaces on the first surface a plurality of second contact pads on the second surface, and a plurality of through holes electrically coupled to the first contact pads and the second contact pads; a metal heat sink having a first a surface, an opposite second surface, and a recess formed in the first surface; a first build-up circuit formed on the first surface of the interposer, wherein the first build-up layer The circuit is electrically coupled to the first contact pads of the interposer by a plurality of first conductive vias of the first build-up circuit; a core layer laterally covering sidewalls of the metal heat sink; a second build-up circuit formed on the second surface of the metal heat sink and on the core layer; and a plurality of cladding vias extending through the core layer to provide the first build-up layer An electrical and thermal connection between the circuit and the second build-up circuit, wherein the chip is electrically coupled to the second contact pads of the interposer by a plurality of bumps to form a wafer-interposer stack a sub-assembly; and the wafer-interposer stack sub-system is attached to the metal heat sink by an adhesive, and the recess covers the wafer, and the interposer extends laterally outside the recess . 如申請專利範圍第9項所述之半導體封裝件，其中該金屬散熱座更包括位於該凹穴外之一定位件，並且該晶片-中介層堆疊次組體係藉由該定位件側向對準與靠近該中介層之外圍邊緣，以貼附至該金屬散熱座。 The semiconductor package of claim 9, wherein the metal heat sink further comprises a positioning member located outside the recess, and the wafer-interposer stack sub-system is laterally aligned by the positioning member. And adjacent to the peripheral edge of the interposer to attach to the metal heat sink. 如申請專利範圍第9項所述之半導體封裝件，其中該第二增層電路係藉由該第二增層電路之複數個第二導電盲孔，以電性及熱性耦接至該金屬散熱座。 The semiconductor package of claim 9, wherein the second build-up circuit is electrically and thermally coupled to the metal by a plurality of second conductive vias of the second build-up circuit. seat. 如申請專利範圍第9項所述之半導體封裝件，更包含一金屬柱，其係與該金屬散熱座彼此保持距離。 The semiconductor package of claim 9, further comprising a metal post that is spaced apart from the metal heat sink. 一種具有堆疊式封裝能力之半導體封裝件，其包含：一晶片；一中介層，其具有一第一表面、與該第一表面相反之一第二表面、該第一 表面上之複數個第一接觸墊、該第二表面上之複數個第二接觸墊、以及電性耦接該些第一接觸墊與該些第二接觸墊之複數個貫孔；一含金屬載體，其具有一第一表面、相反之一第二表面、一形成於第一表面之一凹穴、以及複數個貫穿開口，其中該些複數個貫穿開口係延伸穿過該含金屬載體之該第一表面與該第二表面之間；一第一增層電路，其形成於該中介層之該第一表面上，其中該第一增層電路係藉由該第一增層電路之複數個第一導電盲孔，以電性耦接至該中介層之該些第一接觸墊；一第二增層電路，其形成於該含金屬載體之該第二表面上；以及複數個披覆穿孔，其係延伸穿過該含金屬載體之該些貫穿開口，以提供該第一增層電路與該第二增層電路間之電性及熱性連接，其中該晶片係藉由複數個凸塊電性耦接至該中介層之該些第二接觸墊，以形成一晶片-中介層堆疊次組體；且該晶片-中介層堆疊次組體係藉由一黏著劑貼附至該含金屬載體，並且該凹穴係罩蓋該晶片，且該中介層係側向延伸於該凹穴外。 A semiconductor package having a stacked package capability, comprising: a wafer; an interposer having a first surface, a second surface opposite the first surface, the first a plurality of first contact pads on the surface, a plurality of second contact pads on the second surface, and a plurality of through holes electrically coupled to the first contact pads and the second contact pads; a carrier having a first surface, an opposite second surface, a recess formed in the first surface, and a plurality of through openings, wherein the plurality of through openings extend through the metal-containing carrier Between the first surface and the second surface; a first build-up circuit formed on the first surface of the interposer, wherein the first build-up circuit is formed by a plurality of the first build-up circuits a first conductive via hole electrically coupled to the first contact pads of the interposer; a second build-up circuit formed on the second surface of the metal-containing carrier; and a plurality of overlying perforations Extending through the through openings of the metal-containing carrier to provide an electrical and thermal connection between the first build-up circuit and the second build-up circuit, wherein the die is electrically connected by a plurality of bumps Sexually coupled to the second contact pads of the interposer to form a wafer-interposer stack sub-group; and the wafer-interposer stack sub-system is attached to the metal-containing carrier by an adhesive, and the recess covers the wafer, and the interposer is laterally extended Outside the pocket. 如申請專利範圍第13項所述之半導體封裝件，其中該含金屬載體更包括位於該凹穴外之一定位件，並且該晶片-中介層堆疊次組體係藉由該定位件側向對準與靠近該中介層之外圍邊緣，以貼附至該含金屬載體。 The semiconductor package of claim 13, wherein the metal-containing carrier further comprises a positioning member located outside the recess, and the wafer-interposer stack sub-system is laterally aligned by the positioning member. And a peripheral edge adjacent to the interposer for attaching to the metal-containing carrier. 如申請專利範圍第13項所述之半導體封裝件，其中該第二增層電路係藉由該第二增層電路之複數個第二導電盲孔，以電性及熱性耦接至該含金屬載體。 The semiconductor package of claim 13, wherein the second build-up circuit is electrically and thermally coupled to the metal-containing layer by a plurality of second conductive blind vias of the second build-up circuit Carrier.
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