TW201519334A - Method of package for sensor chip - Google Patents
Method of package for sensor chip Download PDFInfo
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- TW201519334A TW201519334A TW102141339A TW102141339A TW201519334A TW 201519334 A TW201519334 A TW 201519334A TW 102141339 A TW102141339 A TW 102141339A TW 102141339 A TW102141339 A TW 102141339A TW 201519334 A TW201519334 A TW 201519334A
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- sensor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本發明係與感應晶片封裝方法有關，特別是關於一種可有效保護晶片之感應晶片封裝方法。 The present invention relates to a method of inductive chip packaging, and more particularly to an inductive chip packaging method that can effectively protect a wafer.
請參閱第1圖，習用之感應晶片封裝方法，係先將一諸如電荷耦合元件(charge coupled device；簡稱CCD)或一具感應之互補式金屬氧化物半導體(complementary metal-oxide-semiconductor；簡稱CMOS)感應晶片(10)設置於一電路基板(11)上，接著再銲設一金屬導線(12)連接該感應晶片(10)之導電接點與該電路基板(11)之導電接點；接著，於該感應晶片(10)與該導電接點之間塗佈一黏著劑(16)；接著，於該黏著劑(16)上設置一玻璃板(14)，並使得該玻璃板(14)位於該感應晶片(10)之一感測區(15)上方；接著，再利用特殊封裝材料於該電路基板(11)、該感應晶片(10)及該玻璃板(14)上藉由壓模技術成型一封裝體(13)；藉此，該金屬導線(12)係受該封裝體(13)包覆固定而不易斷裂，且該感應晶片(10)之感測區(15)係受到該玻璃板(14)的保護，可感測該玻璃板(14)外側之感應訊號或狀態。 Referring to FIG. 1 , a conventional method for inductive chip packaging is to first charge a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS). The sensing chip (10) is disposed on a circuit substrate (11), and then a metal wire (12) is soldered to connect the conductive contacts of the sensing chip (10) to the conductive contacts of the circuit substrate (11); Applying an adhesive (16) between the sensing wafer (10) and the conductive contact; then, providing a glass plate (14) on the adhesive (16), and making the glass plate (14) Located above one of the sensing regions (15) of the sensing chip (10); and then using a special packaging material on the circuit substrate (11), the sensing wafer (10) and the glass plate (14) by compression molding The technology forms a package (13); thereby, the metal wire (12) is covered by the package (13) and is not easily broken, and the sensing area (15) of the sensing chip (10) is subjected to the The protection of the glass plate (14) senses the inductive signal or state outside the glass plate (14).
然而根據前述之感應晶片封裝方法，該感應晶片(10)之感測區(15)與該玻璃板(14)之間的距離因受限於該黏著劑(16)所塗佈的高度而太過於接近，故對該感應晶片(10)之感應訊號或狀態將有不良之影響；因此，前述感應晶片封裝方法之生產良率較低而需有待改善。 However, according to the aforementioned induction chip packaging method, the distance between the sensing region (15) of the sensing wafer (10) and the glass plate (14) is limited by the height to which the adhesive (16) is applied. Too close, the sensing signal or state of the sensing chip (10) will have an adverse effect; therefore, the production yield of the sensing chip packaging method is low and needs to be improved.
請參閱第2圖，為改善前述之感應晶片封裝方法所衍生出的問題，便將其感應晶片封裝方法變化如後續所列，首先將該感應晶片(10)設置於該電路基板(11)上，接著再銲設該金屬導線(12)連接該感應晶片(10)之導電接點與該電路基板(11)之導電接點；接著，於該電路基板(11)上設置一框件(17)，該框件(17)設有一自頂面貫穿的通孔，且可遮掩住該金屬導線(12)；接著，於該框件(17)之頂面黏貼一玻璃板(14)，使得該玻璃板(14)透過該框件貫穿的通孔設置於該感應晶片(10)之感測區(15)的上方，並形成一感測空間(18)；藉此，該感應晶片(10)之感測區(15)係受到該玻璃板(14)的保護，更可感測該玻璃板(14)外側之感應訊號或狀態。 Referring to FIG. 2, in order to improve the problems arising from the foregoing method of inductive chip packaging, the method of inductive chip packaging is changed as listed later. First, the sensing wafer (10) is disposed on the circuit substrate (11). And then soldering the metal wire (12) to connect the conductive contact of the sensing chip (10) to the conductive contact of the circuit substrate (11); then, providing a frame member on the circuit substrate (11) The frame member (17) is provided with a through hole penetrating from the top surface, and can cover the metal wire (12); then, a glass plate (14) is adhered to the top surface of the frame member (17), so that The through hole of the glass plate (14) penetrating through the frame member is disposed above the sensing region (15) of the sensing chip (10), and forms a sensing space (18); thereby, the sensing chip (10) The sensing area (15) is protected by the glass plate (14), and the sensing signal or state outside the glass plate (14) is sensed.
然而根據前述之感應晶片封裝方法，該金屬導線(12)因無輔助固定的方式，故於封裝製程成形過程中易致使該金屬導線(12)斷裂的風險性增加，進而造成該感應晶片(10)之生產良率降低，因此，前述感應晶片封裝方法仍有待改善。 However, according to the foregoing method of inductive chip packaging, the metal wire (12) is unassisted and fixed, so that the risk of the metal wire (12) being broken during the packaging process is increased, thereby causing the sensing chip (10). The production yield is lowered, and therefore, the aforementioned induction chip packaging method still needs to be improved.
有鑑於上述之缺失，本發明之主要目的在於提供一種感應晶片封裝方法，主要為提高感應晶片之生產良率與產品效能。 In view of the above-mentioned shortcomings, the main object of the present invention is to provide an inductive chip packaging method mainly for improving the production yield and product performance of the sensing wafer.
為達成上述之目的，本發明所提供之感應晶片封裝方法包含有下列步驟：a)提供一感應晶片，該感應晶片設有複數導電接點以及一感測區；b)將該感應晶片藉由一黏著劑黏著貼合於一電路基板上，該電路基板設有複數導電接點，用以與該感應晶片之複數導電接點相互連接；c)將一模壩容設於該感應晶片之感測區與該導電接點之間的區域；d)將複數導線分別連接於該電路基板之導電接點與該感應晶片之導電接點；以及e)將一封裝體設置於該電路基板上及該感應晶片上；且該封裝體包覆該等導線與該模壩。 In order to achieve the above object, the inductive chip packaging method provided by the present invention comprises the following steps: a) providing a sensing chip, the sensing chip is provided with a plurality of conductive contacts and a sensing region; b) using the sensing chip An adhesive is adhered to a circuit substrate, the circuit substrate is provided with a plurality of conductive contacts for interconnecting with a plurality of conductive contacts of the sensing chip; c) a sense of accommodating a mold dam on the sensing chip a region between the measurement region and the conductive contact; d) connecting the plurality of wires to the conductive contacts of the circuit substrate and the conductive contacts of the sensing chip; and e) disposing a package on the circuit substrate and The sensing wafer is mounted on the wafer; and the package encloses the wires and the mold dam.
藉此，於前述該步驟c)至該步驟e)之製程過程中，該模壩可緩衝該感應晶片於壓模製程所產生的應力破壞，避免該感應晶片損傷；並於壓模製程後形成一開放感測空間，進而令該感應晶片之感測區所感應到的訊號或狀態機率大大增加，故該感應晶片封裝方法可著實提升生產良率。 Thereby, during the process of the step c) to the step e), the mold dam can buffer the stress damage generated by the induction wafer in the molding process, thereby avoiding the damage of the induction wafer; and forming after the molding process The open sensing space further increases the signal or state probability induced by the sensing area of the sensing chip, so the sensing chip packaging method can improve the production yield.
有關本發明所提供之感應晶片封裝方法的詳細構造、特點、組裝或使用方式，將於後續的實施方式詳細說明中予以描述。然而，在本發明領域中具有通常知識者應能清楚瞭解，該等詳細說明以及實施本發明所列舉的特定實施例，僅係用於說明本發明，並非用以限制本發明之專利申請範圍。 The detailed construction, features, assembly or use of the inductive wafer packaging method provided by the present invention will be described in the detailed description of the subsequent embodiments. However, it is to be understood that the invention is not limited by the scope of the invention.
10‧‧‧感應晶片 10‧‧‧Induction chip
11‧‧‧電路基板 11‧‧‧ circuit board
12‧‧‧金屬導線 12‧‧‧Metal wire
13‧‧‧封裝體 13‧‧‧Package
14‧‧‧玻璃板 14‧‧‧ glass plate
15‧‧‧感測區 15‧‧‧Sensing area
16‧‧‧黏著劑 16‧‧‧Adhesive
17‧‧‧框件 17‧‧‧ frame
18‧‧‧感測空間 18‧‧‧Sensing space
20‧‧‧封裝結構 20‧‧‧Package structure
21‧‧‧電路基板 21‧‧‧ circuit board
212‧‧‧導電接點 212‧‧‧Electrical contacts
22‧‧‧感應晶片 22‧‧‧Inductive Wafer
222‧‧‧導電接點 222‧‧‧Electrical contacts
224‧‧‧感測區 224‧‧‧Sensing area
23‧‧‧導線 23‧‧‧Wire
24‧‧‧黏著劑 24‧‧‧Adhesive
25‧‧‧模壩 25‧‧‧ mold dam
26‧‧‧封裝體 26‧‧‧Package
262‧‧‧頂面 262‧‧‧ top surface
264‧‧‧凹槽 264‧‧‧ Groove
27‧‧‧黏著劑 27‧‧‧Adhesive
28‧‧‧遮蓋件 28‧‧‧ Covering parts
282‧‧‧通孔 282‧‧‧through hole
29‧‧‧感測空間 29‧‧‧Sensing space
30‧‧‧封裝結構 30‧‧‧Package structure
32‧‧‧遮蓋件 32‧‧‧ Covering parts
322‧‧‧鏡筒 322‧‧‧Mirror tube
324‧‧‧鏡片 324‧‧‧ lenses
第1圖及第2圖係習用之感應晶片封裝方法所產生之封裝結構剖視圖；第3圖至第6圖係本發明所提供之感應晶片封裝方法暨應用於一第一較佳實施例所提供之封裝結構主要步驟剖視圖；第7圖至第9圖係本發明所提供之感應晶片封裝方法暨應用於一第二較佳實施例所提供之封裝結構時的部分步驟之結構剖視示意圖；以及第10圖係本發明一第三較佳實施例所提供之封裝結構剖視示意圖。 1 and 2 are cross-sectional views of a package structure produced by a conventional inductive chip packaging method; FIGS. 3 to 6 are a method of packaging a sensing chip provided by the present invention and applied to a first preferred embodiment. FIG. 7 to FIG. 9 are schematic cross-sectional views showing a part of the steps of the inductive chip packaging method provided by the present invention and the package structure provided by a second preferred embodiment; Figure 10 is a cross-sectional view showing a package structure according to a third preferred embodiment of the present invention.
以下將藉由所列舉之實施例配合隨附之圖式，詳述本發明之技術內容及特徵，其中： 誠如第3圖至第6圖所示，係本發明所提供之感應晶片封裝方法暨應用於一第一較佳實施例所提供之封裝結構主要步驟剖視圖；第7圖至第9圖係本發明所提供之感應晶片封裝方法暨應用於一第二較佳實施例所提供之封裝結構時的部分步驟之結構剖視示意圖；以及誠如第10圖係本發明一第三較佳實施例所提供之封裝結構剖視示意圖。 The technical contents and features of the present invention will be described in detail below by the accompanying embodiments in conjunction with the accompanying drawings. As shown in FIG. 3 to FIG. 6 , the invention relates to an inductive chip packaging method and a main process sectional view of a package structure provided by a first preferred embodiment; FIG. 7 to FIG. 9 are diagrams. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 10 is a schematic cross-sectional view showing a part of the steps of the method for applying the inductive chip package and the package structure provided by a second preferred embodiment; and FIG. 10 is a third preferred embodiment of the present invention. A schematic cross-sectional view of the package structure provided.
首先在此說明，在以下將要介紹之各實施例以及圖式中，相同之參考號碼，表示相同或類似之物件或其結構特徵。 First of all, in the embodiments and the drawings which will be described below, the same reference numerals denote the same or similar items or structural features thereof.
請先參閱第3圖至第6圖所示，係顯示本發明之一第一較佳實施例所提供之封裝結構(20)(誠如第6圖所示)主要製程步驟的示意圖，係利用本發明所提供之感應晶片封裝方法，以下將以該封裝結構(20)為例並用來說明本發明感應晶片封裝方法。 Please refer to FIG. 3 to FIG. 6 , which are schematic diagrams showing the main process steps of the package structure ( 20 ) (as shown in FIG. 6 ) provided by the first preferred embodiment of the present invention. The inductive chip packaging method provided by the present invention will be exemplified by the package structure (20) and used to explain the inductive chip packaging method of the present invention.
本發明所提之感應晶片封裝方法包含有下列步驟：a)誠如第3圖所示，提供一感應晶片(22)，該感應晶片(22)設有複數導電接點(222)以及一感測區(224)；b)誠如第3圖所示，將該感應晶片(22)藉由一黏著劑(24)黏著貼合於一電路基板(21)上，該電路基板(21)設有複數導電接點(212)，用以與該感應晶片(22)之複數導電接點(222)相互連接；c)誠如第4圖所示，將一模壩(25)容設於該感應晶片(22)之感測區(224)與該導電接點(222)之間的區域；d)誠如第5圖所示，將複數導線(23)分別連接於該電路基板(21)之導電接點(212)與該感應晶片(22)之導電接點(222)；以及e)誠如第6圖所示，將一封裝體(26)設置於該電路基板(21) 上及該感應晶片(22)上；該封裝體(26)包覆該等導線(23)與該模壩(25)，且該封裝體(26)並未包覆該感應晶片(22)之感測區(224)。 The inductive chip packaging method of the present invention comprises the following steps: a) as shown in FIG. 3, an inductive wafer (22) is provided, the inductive wafer (22) is provided with a plurality of conductive contacts (222) and a sense The measuring area (224); b) as shown in FIG. 3, the sensing chip (22) is adhered to a circuit substrate (21) by an adhesive (24), and the circuit substrate (21) is provided. There are a plurality of conductive contacts (212) for interconnecting the plurality of conductive contacts (222) of the sensing chip (22); c) as shown in FIG. 4, a die dam (25) is accommodated therein Sensing the area between the sensing region (224) of the wafer (22) and the conductive contact (222); d) as shown in FIG. 5, connecting the plurality of wires (23) to the circuit substrate (21) a conductive contact (212) and a conductive contact (222) of the sensing chip (22); and e) as shown in FIG. 6, a package (26) is disposed on the circuit substrate (21) And the sensing chip (22); the package (26) covers the wires (23) and the die dam (25), and the package (26) does not cover the sensing chip (22) Sensing area (224).
承上所述，步驟c)中該模壩(25)所容設之數量及大小並無限制，可依實際需求而設置；可將步驟c)製程設置於步驟b)製程之前，其後再接續完成步驟d)製程及步驟e)製程，並不影響該整體感應晶片封裝結構(20)之成型。 As stated above, the number and size of the mold dam (25) in step c) are not limited and can be set according to actual needs; the process of step c) can be set before the process of step b), and then The subsequent completion of the step d) process and the step e) process does not affect the molding of the overall inductive chip package structure (20).
承上所述，步驟d)中該等導線(23)之數量並無限制，可依實際需求而設置；步驟d)係與習用者無異，可將步驟d)製程設置於步驟c)製程之前，其後再接續完成步驟c)製程及步驟e)製程，不影響該整體感應晶片封裝結構(20)之成型。 As stated above, the number of the wires (23) in the step d) is not limited and can be set according to actual needs; the step d) is the same as the conventional one, and the process of the step d) can be set in the process of the step c) Previously, the process of step c) and the process of step e) are subsequently continued, without affecting the molding of the overall sensing chip package structure (20).
承上所述，透過該模壩(25)與該封裝體(26)之設置，可有效緩衝該感應晶片(22)於壓模製程中所產生的應力衝擊，亦可於壓模製程後自形成一開放感測空間(29)；該模壩(25)係利用一般習知之塗佈製程容設於該感應晶片(22)之感測區(224)與該導電接點(222)之間的區域，亦可利用一般習知之網印製程直接網印塗佈於該感應晶片(22)之感測區(224)與該導電接點(222)之間的區域，亦可透過一般習知之鑄模製程將該模壩(25)鑄模成型後，再設置於該感應晶片(22)之感測區(224)與該導電接點(222)之間的區域；該封裝體(26)係利用特殊封裝材料藉由壓模方式而形成，用以包覆固定該等導線(23)與該模壩(25)並令其不易斷裂損傷，進而提升產品良率之效果。 As described above, the arrangement of the mold dam (25) and the package body (26) can effectively buffer the stress shock generated by the induction wafer (22) during the compression molding process, and can also be self-pressed after the compression molding process. Forming an open sensing space (29); the mold dam (25) is accommodated between the sensing region (224) of the sensing wafer (22) and the conductive contact (222) by a conventional coating process The area can be directly screen printed on the area between the sensing area (224) of the sensing chip (22) and the conductive contact (222) by using a conventional screen printing process, or by conventional means. The molding process is formed by molding the mold dam (25), and then disposed in a region between the sensing region (224) of the sensing wafer (22) and the conductive contact (222); the package (26) is utilized The special encapsulating material is formed by compression molding to cover and fix the wires (23) and the die dam (25) and to make them difficult to break and damage, thereby improving the product yield.
請參閱第7圖至第9圖所示，係本發明一第二較佳實施例之封裝結構剖視示意圖；於該封裝體(26)之一頂面(262)上設置一可透光性的遮蓋件(28)(誠如第7圖所示)，使得該感應晶片(22)之感測區(224)位於該遮蓋件(28)之下方，且自形成該感測空間(29)。 FIG. 7 is a cross-sectional view showing a package structure according to a second preferred embodiment of the present invention; a light transmissive property is disposed on a top surface (262) of the package body (26). a cover member (28) (as shown in FIG. 7), such that the sensing region (224) of the sensing wafer (22) is located below the covering member (28), and the sensing space (29) is formed .
承上所述，在本實施例中，該遮蓋件(28)為一具有良好透光 性之玻璃材質物件，係藉由一黏著劑(27)與該封裝體(26)之頂面(262)黏著抵觸；藉此，該感應晶片(22)之感測區(224)可受到該遮蓋件(28)所保護，並可感測該遮蓋件(28)外側之感應訊號或狀態。 As described above, in the embodiment, the covering member (28) has a good light transmission. The glass material is adhered to the top surface (262) of the package (26) by an adhesive (27); thereby, the sensing area (224) of the sensing chip (22) can be subjected to the The cover member (28) protects and senses the sensing signal or state outside the cover member (28).
請參閱第8圖所示，在本實施例中，自該封裝體(26)之頂面(262)朝向該感應晶片(22)之感測區(224)方向凹陷形成環繞於該感測區(224)上方之一凹槽(264)，將具有良好透光性之玻璃材質遮蓋件(28)藉由該黏著劑(27)貼合設置於該凹槽(264)之中；請參閱第9圖所示，在本實施例中，該遮蓋件(28)具有一貫穿的通孔(282)，該通孔(282)位於該感應晶片(22)之感測區(224)的上方；藉此，可有效縮小該封裝結構(20)整體高度，以達到晶片積體空間薄型化之需求，亦可透過該遮蓋件(28)之通孔(282)讓下方該感應晶片(22)之感測區(224)受到感應訊號或狀態更有顯著效益，適合應用於相關薄型化之電子產品諸如相機、手機、筆記型電腦、溫度感測器、濕度感測器、壓力感測器、血糖感測計、心電圖感測器、雷達感測器等等。 Referring to FIG. 8, in the embodiment, the top surface (262) of the package (26) is recessed toward the sensing region (224) of the sensing wafer (22) to form a surrounding area. (224) a groove (264) above, a glass material covering member (28) having good light transmittance is disposed in the groove (264) by the adhesive (27); In the present embodiment, the cover member (28) has a through hole (282) therethrough, and the through hole (282) is located above the sensing region (224) of the sensing chip (22); Therefore, the overall height of the package structure (20) can be effectively reduced to meet the requirement of thinning the integrated space of the wafer, and the through-hole (282) of the cover member (28) can be used to lower the sensing chip (22). The sensing area (224) is more susceptible to inductive signals or states and is suitable for use in related thinned electronic products such as cameras, cell phones, notebook computers, temperature sensors, humidity sensors, pressure sensors, blood glucose Sensors, ECG sensors, radar sensors, etc.
請參閱第10圖所示，係本發明一第三較佳實施例所提供之封裝結構(30)剖視示意圖。該實施例所提供之封裝結構(30)與前述該封裝結構(20)之差異在於，該封裝結構(30)之遮蓋件(32)為一鏡頭，該鏡頭係與習用者無異，包含有一鏡筒(322)以及複數晶片(324)。本發明所提供之感應晶片封裝方法應用於該封裝結構(30)時，係將該遮蓋件(32)之鏡筒(322)設置於該封裝體(26)的凹槽(264)之中，該封裝體(26)之高度小於或等於該遮蓋件(32)之高度。藉此，只要將該封裝結構(30)直接裝設於相機、手機、筆記型電腦等等電子產品中，該電子產品可同時包含影像感應晶片與鏡頭，可不另外再加工設置鏡頭，組裝上相當方便。 Referring to FIG. 10, a schematic cross-sectional view of a package structure (30) according to a third preferred embodiment of the present invention is shown. The package structure (30) provided in this embodiment is different from the package structure (20) described above in that the cover member (32) of the package structure (30) is a lens, which is similar to the conventional one, and includes a lens. A lens barrel (322) and a plurality of wafers (324). When the sensing chip packaging method provided by the present invention is applied to the package structure (30), the lens barrel (322) of the covering member (32) is disposed in the recess (264) of the package body (26). The height of the package (26) is less than or equal to the height of the cover (32). Therefore, if the package structure (30) is directly installed in an electronic product such as a camera, a mobile phone, a notebook computer, or the like, the electronic product can simultaneously include an image sensing chip and a lens, and the lens can be assembled without being assembled. Convenience.
事實上，於前述本發明所提供之感應晶片封裝方法中，該遮蓋件並非以玻璃材質及鏡頭物件為限，亦可為其他材質或結構所組成的遮 蓋件，只要讓該感應晶片(22)之感測區(224)能感測該遮蓋件外側之感應訊號或狀態即可。 In fact, in the sensing chip packaging method provided by the present invention, the covering member is not limited to the glass material and the lens object, and may be covered by other materials or structures. The cover member can be configured such that the sensing area (224) of the sensing chip (22) can sense the sensing signal or state outside the covering member.
最後，必須再次說明，本發明於前揭實施例中所揭露之構成元件，僅為舉例說明，並非用來限制本案之範圍，其他等效元件的替代或變化，亦應為本案之申請專利範圍所涵蓋。 Finally, it is to be noted that the constituent elements disclosed in the foregoing embodiments are merely illustrative and are not intended to limit the scope of the present invention. Covered.
20‧‧‧封裝結構 20‧‧‧Package structure
21‧‧‧電路基板 21‧‧‧ circuit board
212‧‧‧導電接點 212‧‧‧Electrical contacts
22‧‧‧感應晶片 22‧‧‧Inductive Wafer
222‧‧‧導電接點 222‧‧‧Electrical contacts
224‧‧‧感測區 224‧‧‧Sensing area
23‧‧‧導線 23‧‧‧Wire
24‧‧‧黏著劑 24‧‧‧Adhesive
25‧‧‧模壩 25‧‧‧ mold dam
26‧‧‧封裝體 26‧‧‧Package
262‧‧‧頂面 262‧‧‧ top surface
27‧‧‧黏著劑 27‧‧‧Adhesive
28‧‧‧遮蓋件 28‧‧‧ Covering parts
29‧‧‧感測空間 29‧‧‧Sensing space
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102141339A TW201519334A (en) | 2013-11-13 | 2013-11-13 | Method of package for sensor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102141339A TW201519334A (en) | 2013-11-13 | 2013-11-13 | Method of package for sensor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201519334A true TW201519334A (en) | 2015-05-16 |
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ID=53721040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| TW102141339A TW201519334A (en) | 2013-11-13 | 2013-11-13 | Method of package for sensor chip |
Country Status (1)
| Country | Link |
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| TW (1) | TW201519334A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085580A (en) * | 2019-05-27 | 2019-08-02 | 星科金朋半导体（江阴）有限公司 | A kind of chip-packaging structure and its packaging method being implanted into damper |
| CN113526449A (en) * | 2020-04-14 | 2021-10-22 | 鹰克国际股份有限公司 | Chip packaging structure and manufacturing method thereof |
-
2013
- 2013-11-13 TW TW102141339A patent/TW201519334A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085580A (en) * | 2019-05-27 | 2019-08-02 | 星科金朋半导体（江阴）有限公司 | A kind of chip-packaging structure and its packaging method being implanted into damper |
| CN110085580B (en) * | 2019-05-27 | 2024-05-24 | 星科金朋半导体（江阴）有限公司 | Chip packaging structure of implanted damper and packaging method thereof |
| CN113526449A (en) * | 2020-04-14 | 2021-10-22 | 鹰克国际股份有限公司 | Chip packaging structure and manufacturing method thereof |
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