TW201507224A - Noble metal/non-noble metal electrode for RRAM applications - Google Patents
Noble metal/non-noble metal electrode for RRAM applications Download PDFInfo
- Publication number
- TW201507224A TW201507224A TW102129266A TW102129266A TW201507224A TW 201507224 A TW201507224 A TW 201507224A TW 102129266 A TW102129266 A TW 102129266A TW 102129266 A TW102129266 A TW 102129266A TW 201507224 A TW201507224 A TW 201507224A
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- metal material
- precious metal
- switching
- titanium
- Prior art date
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
本申請要求2012年8月14日提交,申請號為13/585,759,名稱為“NOBLE METAL/NON-NOBLE METAL ELECTRODE FOR RRAM APPLICATIONS”的美國非臨時專利申請案的優先權,其通過引用的方式被全部併入。 The present application claims priority to US Non-Provisional Patent Application No. 13/585,759, entitled "NOBLE METAL/NON-NOBLE METAL ELECTRODE FOR RRAM APPLICATIONS", which is incorporated by reference. All incorporated.
本發明係關於一種供可變電阻式記憶體用之貴金屬/非貴金屬電極。 The present invention relates to a noble metal/non-precious metal electrode for use in a variable resistance memory.
本發明的發明人認知到半導體裝置的成功主要是藉由集中的電晶體微小化程序。然而,當場效電晶體(field effect transistors,FETs)接近尺寸小於100nm,物理問題例如短通道效應開始妨礙正常的裝置運作。對於以電晶體為基礎的記憶體,例如廣知的快閃記憶體,其他性能減損或問題可能隨裝置尺寸變小而發生。對於快閃記憶體,高電壓通常被需求以供此類記憶體編製程序,然而,當裝置尺寸變小,高編製程序電壓可以造成介電崩潰及其他問題。類似的問題可發生在快閃記憶體以外的其他類型的非揮發性記憶體裝置。 The inventors of the present invention have recognized that the success of semiconductor devices is primarily achieved by a centralized transistor miniaturization process. However, when field effect transistors (FETs) are close to size less than 100 nm, physical problems such as short channel effects begin to interfere with normal device operation. For transistor-based memories, such as the well-known flash memory, other performance impairments or problems may occur as the device size becomes smaller. For flash memory, high voltages are often required for such memory programming, however, as device sizes become smaller, high programming voltages can cause dielectric breakdown and other problems. Similar problems can occur with other types of non-volatile memory devices other than flash memory.
本發明的發明人認知到許多其他類型的非揮發性隨機存取記憶體裝置已經被開發作為下一代記憶體裝置,例如鐵電體隨機存取記憶體、磁阻式隨機存取記憶體、有機隨機存取記憶體、相變化隨機存取記憶體、及其他。 The inventors of the present invention have recognized that many other types of non-volatile random access memory devices have been developed as next-generation memory devices, such as ferroelectric random access memory, magnetoresistive random access memory, organic Random access memory, phase change random access memory, and others.
這些記憶體裝置的一個共通缺點包含他們通常需要與傳統CMOS製程不相容的新材料。例如有機隨機存取記憶體需要有機化合物其目前與大尺寸以矽為基礎的製造技術及製造所不相容。其他例如鐵電體隨機存取記憶體及磁阻式隨機存取記憶體通常需要使用高溫退火步驟的材料,因此這類裝置通常不可與大尺寸以矽為基礎的的製造技術整合。 A common disadvantage of these memory devices involves new materials that they typically need to be incompatible with conventional CMOS processes. For example, organic random access memories require organic compounds that are currently incompatible with large-scale, germanium-based manufacturing techniques and manufacturing. Other materials such as ferroelectric random access memory and magnetoresistive random access memory typically require materials that use a high temperature annealing step, and such devices are generally not integrated with large size germanium based fabrication techniques.
這些裝置額外的缺點包含這類記憶體胞通常缺乏一個或更多的非揮發性記憶體需要的關鍵特性。例如鐵電體隨機存取記憶體及磁阻式隨機存取記憶體一般具有快速切換(即”0”到”1”)特性及好的編製程序耐受度,然而,這類記憶體胞難以被縮至小尺寸。舉有機隨機存取記憶體裝置為例,這類記憶體的可靠性通常不佳。另外的例子,相變化隨機存取記憶體通常包含焦耳加熱及非期望地需要高能量損耗。 An additional disadvantage of these devices is that such memory cells typically lack the key characteristics required for one or more non-volatile memories. For example, ferroelectric random access memory and magnetoresistive random access memory generally have fast switching (ie, "0" to "1") characteristics and good programming tolerance. However, such memory is difficult to use. Shrinked to a small size. Taking an organic random access memory device as an example, the reliability of such a memory is generally poor. As another example, phase change random access memory typically includes Joule heating and undesirably requires high energy losses.
基於以上,新的半導體裝置結構及集成是被需求的。 Based on the above, new semiconductor device structures and integrations are required.
本發明關於一種阻抗切換裝置。更具體地,根據本發明的實施例關於方法及裝置供控制氧等級在阻抗切換裝置中。根據本發明的實施例可以被用於非揮發性記憶體裝置但應認知到本發明可以有範圍更廣的應用。 The present invention relates to an impedance switching device. More specifically, embodiments are directed to methods and apparatus for controlling oxygen levels in impedance switching devices in accordance with embodiments of the present invention. Embodiments in accordance with the present invention may be used in non-volatile memory devices but it will be appreciated that the invention may have a broader range of applications.
在一特定實施例中,一種供形成一非揮發性記憶體裝置的方法包含形成一底部金屬電極;形成一接合層與底部金屬電極電性接觸,其含有一導電含矽材料(例如p-摻雜多晶矽、p-摻雜矽化鍺等);以及形成一切換層在接合層上,其具有一未摻雜非晶含矽材料(例如未摻雜非晶矽、未摻雜SiOx、SixGeyOz,其中x、y及z是整數,等等)在一特定實施例中,一具有非貴金屬材料(例如鈦、鋁、鎢、鈦合金、鋁合金、鎢合金、氮化鈦、氮化鎢、氮化鋁、銅、銅合金,或相似者)的阻隔層被形成在切換層上;一含有貴金屬材料(例如銀、金、鉑、鈀、或相似者)的活性層被形成在阻隔層上;以及另一阻隔層(頂部層)被形成在活性層上。其後,一頂部金屬電極被形成與頂部層及活性層電性接觸。 In a specific embodiment, a method for forming a non-volatile memory device includes forming a bottom metal electrode; forming a bonding layer in electrical contact with a bottom metal electrode, the conductive layer containing a conductive material (eg, p-doped a heteropolycrystalline germanium, a p-doped germanium germanium, or the like; and a switching layer formed on the bonding layer having an undoped amorphous germanium-containing material (eg, undoped amorphous germanium, undoped SiOx, SixGeyOz, wherein x, y, and z are integers, etc.) In a particular embodiment, a non-precious metal material (eg, titanium, aluminum, tungsten, titanium alloy, aluminum alloy, tungsten alloy, titanium nitride, tungsten nitride, nitride) a barrier layer of aluminum, copper, copper alloy, or the like is formed on the switching layer; an active layer containing a noble metal material such as silver, gold, platinum, palladium, or the like is formed on the barrier layer; Another barrier layer (top layer) is formed on the active layer. Thereafter, a top metal electrode is formed in electrical contact with the top layer and the active layer.
在多種實施例中,剛鍍好或剛形成的層被安排接收氧及被氧 化。作為一個實施例,用於此層的非貴金屬材料是鈦,且當鈦接收氧,其轉化為二氧化鈦,或者其他的鈦氧化態。用於將鈦氧化的氧可引自切換層、活性層或者來自任意其他來源(例如來自大氣)經由擴散通過切換層、活性層或相似者。在氧化態,此層可具有一厚度範圍在約2nm至約3nm。 In various embodiments, the just-plated or newly formed layer is arranged to receive oxygen and oxygen Chemical. As an example, the non-noble metal material used for this layer is titanium, and when titanium receives oxygen, it is converted to titanium dioxide, or other titanium oxidation state. Oxygen used to oxidize titanium may be directed from the switching layer, the active layer, or from any other source (eg, from the atmosphere) via diffusion through the switching layer, the active layer, or the like. In the oxidized state, the layer can have a thickness ranging from about 2 nm to about 3 nm.
根據本發明的一觀點,形成一非揮發性記憶體裝置的方法被描述。一程序包含沈積一含有一摻雜含矽材料之接合層,其與一第一導電材料電性接觸;以及形成一含有一未摻雜非晶含矽材料之切換層在該接合層的至少一部份之上。一技術包含設置一包含一非貴金屬材料之阻隔層在該切換層的至少一部份之上,以及設置一包含一貴金屬材料之活性金屬層在阻隔層的至少一部份之上。一方法可包含形成一額外的阻隔層在活性金屬層的頂部,隨後使第二導電材料與活性金屬層電性接觸。 In accordance with an aspect of the invention, a method of forming a non-volatile memory device is described. A process comprising depositing a bonding layer comprising a doped germanium-containing material in electrical contact with a first conductive material; and forming a switching layer comprising an undoped amorphous germanium-containing material in at least one of the bonding layers Part of it. A technique includes disposing a barrier layer comprising a non-precious metal material over at least a portion of the switching layer and disposing an active metal layer comprising a noble metal material over at least a portion of the barrier layer. A method can include forming an additional barrier layer on top of the active metal layer and subsequently electrically contacting the second conductive material with the active metal layer.
根據本發明的另一觀點,一非揮發性記憶體裝置被描述。一裝置可包含一含有一摻雜含矽材料之接合層,其與一第一導電材料電性接觸;以及一含有一未摻雜非晶含矽材料之切換層,形成在該接合層的至少一部份之上。一記憶體可包含一包含一貴重金屬的第一層設置在切換層的至少一部份上,一第二導電材料與第一層電性連接,以及一包含非貴金屬材料的氧化態的層形成在第一層的至少一部份及切換層的至少一部份之間。 According to another aspect of the invention, a non-volatile memory device is described. A device may include a bonding layer containing a doped germanium-containing material in electrical contact with a first conductive material; and a switching layer containing an undoped amorphous germanium-containing material formed on the bonding layer Part of it. A memory may include a first layer comprising a precious metal disposed on at least a portion of the switching layer, a second conductive material electrically coupled to the first layer, and a layer comprising an oxidized state comprising a non-noble metal material. Between at least a portion of the first layer and at least a portion of the switching layer.
許多好處可以藉由本發明的方式達成。例如,根據本發明的實施例提供一種方法供增加一非揮發性記憶體裝置的表現,例如裝置可靠度、裝置關閉狀態電流一致性、裝置厚度一致性、裝置固持性、及相似者。此方法使用傳統半導體設備及技術無須調整。依實施例,一個或更多的這些優點可以被達成。本領域技術人員可以認知到其他變異、調整及替代選擇。 Many benefits can be achieved by the means of the present invention. For example, embodiments in accordance with the present invention provide a method for increasing the performance of a non-volatile memory device, such as device reliability, device off state current consistency, device thickness uniformity, device retention, and the like. This method uses conventional semiconductor devices and techniques without adjustment. According to an embodiment, one or more of these advantages can be achieved. Other variations, adjustments, and alternatives will be apparent to those skilled in the art.
102‧‧‧半導體基材 102‧‧‧Semiconductor substrate
104‧‧‧表面區域 104‧‧‧Surface area
202‧‧‧半導體基材 202‧‧‧Semiconductor substrate
302‧‧‧第一接線材料 302‧‧‧First wiring material
304‧‧‧第一黏著材料 304‧‧‧First Adhesive Material
306‧‧‧擴散阻隔材料 306‧‧‧Diffuse barrier material
402‧‧‧接合材料 402‧‧‧Material materials
502‧‧‧阻抗切換材料 502‧‧‧ Impedance switching material
600‧‧‧層 600‧‧ layers
602‧‧‧活性導電材料 602‧‧‧Active conductive materials
702‧‧‧擴散阻隔材料 702‧‧‧Diffuse barrier material
802‧‧‧硬質遮罩材料 802‧‧‧hard mask material
902‧‧‧圖案層 902‧‧‧pattern layer
1202‧‧‧柱狀結構 1202‧‧‧column structure
1302‧‧‧介電材料 1302‧‧‧ dielectric materials
1304‧‧‧表面區域 1304‧‧‧Surface area
1306‧‧‧平面化表面 1306‧‧‧Flat surface
1402‧‧‧第二接線材料 1402‧‧‧Second wiring material
為了更完整瞭解本發明,參考隨附圖式。應瞭解此些圖式並不必須符合比例且不被考慮作為本發明的限制。描述的30個實施例及本發明最能被描述理解經由藉著額外的細節經由使用以下圖示,其中: 圖1是簡化圖顯示程序步驟根據本發明的多種實施例;圖2是簡化圖顯示程序步驟根據本發明的多種實施例;圖3是簡化圖顯示程序步驟根據本發明的多種實施例;圖4是簡化圖顯示程序步驟根據本發明的多種實施例;圖5是簡化圖顯示程序步驟根據本發明的多種實施例;圖6是簡化圖顯示程序步驟根據本發明的多種實施例;圖7是簡化圖顯示程序步驟根據本發明的多種實施例;圖8是簡化圖顯示程序步驟根據本發明的多種實施例;圖9是簡化圖顯示程序步驟根據本發明的多種實施例;圖10是簡化圖顯示程序步驟根據本發明的多種實施例;圖11是簡化圖顯示程序步驟根據本發明的多種實施例;圖12是簡化圖顯示程序步驟根據本發明的多種實施例;以及圖13顯示表現數據的圖根據本發明的多種實施例。 For a more complete understanding of the invention, reference is made to the accompanying drawings. It should be understood that such figures are not necessarily to scale and are not considered as limiting. The 30 embodiments described and the invention can be best understood by using the following illustrations by means of additional details, wherein: 1 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 2 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 3 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 5 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; FIG. 6 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; The figure shows program steps in accordance with various embodiments of the present invention; Figure 8 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Figure 9 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Figure 10 is a simplified diagram display The program steps are in accordance with various embodiments of the present invention; Figure 11 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; Figure 12 is a simplified diagram showing program steps in accordance with various embodiments of the present invention; and Figure 13 is a diagram showing performance data. According to various embodiments of the invention.
根據本發明的實施例導向阻抗切換裝置。更具體地,根據本發明的實施例提供方法以形成一銀結構供阻抗切換裝置 此方法被應用於非揮發性記憶體裝置的製造但應認知到根據本發明的實施例可具有更寬廣範圍的應用。 The impedance switching device is guided according to an embodiment of the invention. More specifically, methods are provided in accordance with embodiments of the present invention to form a silver structure for impedance switching devices. This method is applied to the fabrication of non-volatile memory devices, but it will be appreciated that embodiments in accordance with the present invention may have a broader range. application.
對於使用非晶矽作為切換材料的阻抗切換裝置,金屬材料被作為至少其中之一的電極。非晶矽材料的阻抗被改變根據一個或者更多的導體顆粒得自導體電極在電極的電壓差上圖1到12顯示一種根據本發明多種實施例的形成供記憶體裝置用的阻抗切換裝置的方法。如圖1所示,一具有一表面區域104的半導體基材102被提供。半導體基材102依實施例可以是單晶矽晶圓、矽鍺材料、在絕緣體上的矽(通常簡稱SOI)。在特定的實施例中,半導體基材202可以具有一個或更多的MOS裝置形成在其上或其內。此一個或更多的MOS裝置可以是供阻抗切換裝置的控制電路,或者類似者在一些實施例中。 For an impedance switching device using amorphous germanium as a switching material, a metal material is used as an electrode of at least one of them. The impedance of the amorphous germanium material is changed. According to one or more conductor particles derived from the conductor electrode, the voltage difference between the electrodes is shown in FIGS. 1 to 12, which shows an impedance switching device for forming a memory device according to various embodiments of the present invention. method. As shown in FIG. 1, a semiconductor substrate 102 having a surface region 104 is provided. The semiconductor substrate 102 may be a single crystal germanium wafer, a germanium material, or a germanium on insulator (commonly referred to as SOI), depending on the embodiment. In a particular embodiment, semiconductor substrate 202 can have one or more MOS devices formed thereon or therein. The one or more MOS devices may be control circuits for impedance switching devices, or the like, in some embodiments.
如圖2所示,此方法的實施例包含沈積一第一介電材料202在半導體基材102上。第一介電材料202可以是氧化矽、氮化矽、氧化矽及氮化矽的選擇層的介電堆疊(例如,一個ONO堆疊)、低K介電、高K介電、或其組合、及其他,根據應用。第一介電材料202可以被沈積使用例如化學氣相沈積的技術,包含低壓化學氣象沈積、電漿增強化學氣相沈積、高密度電漿化學氣相沈積、原子層沈積(atomic layer deposition,ALD)、物理氣相沈積技術,包含這些的任意組合,以及其他。 As shown in FIG. 2, an embodiment of the method includes depositing a first dielectric material 202 on a semiconductor substrate 102. The first dielectric material 202 can be a dielectric stack of selected layers of hafnium oxide, tantalum nitride, hafnium oxide, and tantalum nitride (eg, an ONO stack), low K dielectric, high K dielectric, or a combination thereof, And others, depending on the application. The first dielectric material 202 can be deposited using techniques such as chemical vapor deposition, including low pressure chemical weather deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, atomic layer deposition (ALD). ), physical vapor deposition techniques, including any combination of these, and others.
如圖3所示,本方法的實施例包含沈積一第一接線材料302在第一介電材料上。第一接線材料302可為適合的金屬材料包含金屬合金,或者具有適合的傳導特性的半導體材料。在一些實施例中,金屬材料可為鎢、鋁、銅或銀及其他。在不同實施例中,這些金屬材料可被沈積使用物理氣相沈積程序、化學氣相沈積程序、電鍍、或無電鍍沈積程序、這些的任意組合,以及其他。在一些實施例中,半導體材料可以為例如p型摻雜矽材料、導電性多晶矽、或類似者。 As shown in FIG. 3, an embodiment of the method includes depositing a first wiring material 302 on the first dielectric material. The first wiring material 302 can be a suitable metal material comprising a metal alloy, or a semiconductor material having suitable conductive properties. In some embodiments, the metallic material can be tungsten, aluminum, copper, or silver, among others. In various embodiments, these metallic materials can be deposited using physical vapor deposition procedures, chemical vapor deposition procedures, electroplating, or electroless deposition processes, any combination of these, and others. In some embodiments, the semiconductor material can be, for example, a p-type doped germanium material, a conductive polysilicon, or the like.
在特定實施例中,一第一黏著材料304在第一接線材料302沈積前被首先形成在第一介電材料202上以優化第一接線材料302黏著於第一介電材料202。在特定實施例中一擴散阻隔材料306亦可形成在第一接線材料302上以防止例如導電材料、金屬材料、氣體、氧或類似者污染裝置的其他部份。 In a particular embodiment, a first adhesive material 304 is first formed on the first dielectric material 202 prior to deposition of the first wiring material 302 to optimize adhesion of the first wiring material 302 to the first dielectric material 202. In a particular embodiment, a diffusion barrier material 306 can also be formed over the first wiring material 302 to prevent, for example, conductive materials, metallic materials, gases, oxygen, or the like from contaminating other portions of the device.
如圖4所示,方法包含形成一接合材料402至少在第一接線材料302(或第一擴散阻隔材料306,如果有使用的話)上。在特定實施例中,第一接合材料402可為p-摻雜含矽材料(例如p++多晶矽、p-摻雜矽鍺、或類似者)。p++多晶矽可以被形成藉由使用沈積程序像是低壓化學氣象沈積、電漿增強化學氣相沈積依應用使用矽甲烷或二矽烷或適合的氯矽烷。選擇性的,第一矽材料可以被沈積使用物理氣相沈積程序來自一適合的矽靶材。沈積溫度的範圍可介於約380℃到約450℃,且較佳不超過440℃。在特定實施例中,p++多晶矽材料被沈積使用低壓化學氣相沈積程序使用矽烷在介於約400℃到約460℃的沈積溫度。 As shown in FIG. 4, the method includes forming a bonding material 402 on at least the first wiring material 302 (or the first diffusion barrier material 306, if used). In a particular embodiment, the first bonding material 402 can be a p-doped germanium-containing material (eg, p++ polycrystalline germanium, p-doped germanium, or the like). The p++ polycrystalline germanium can be formed by using a deposition procedure such as low pressure chemical weather deposition, plasma enhanced chemical vapor deposition depending on the application using methane or dioxane or a suitable chlorodecane. Alternatively, the first tantalum material can be deposited using a physical vapor deposition process from a suitable tantalum target. The deposition temperature can range from about 380 ° C to about 450 ° C, and preferably does not exceed 440 ° C. In a particular embodiment, the p++ polysilicon material is deposited using a low pressure chemical vapor deposition process using a decane at a deposition temperature of between about 400 °C and about 460 °C.
如圖5所示,本方法沈積一阻抗切換材料502在接合材料 402上。阻抗接合材料502可以是矽材料。矽材料可以是非晶矽材料或多晶矽材料及其他類似者,依實施例。在特定實施例,阻抗切換材料502包含非晶矽材料。切換材料被以狀態定義,例如,阻抗狀態依附於切換材料中的一電場。在特定實施例中,切換材料是非晶矽材料。阻抗切換材料502在特定實施例中具有實質上真實的半導體特性且無意被摻雜。在不同實施例中,非晶矽亦指非結晶矽。非結晶矽非揮發性阻抗切換裝置可使用現存CMOS技術製造。 As shown in FIG. 5, the method deposits an impedance switching material 502 at the bonding material. 402. The impedance bonding material 502 can be a germanium material. The tantalum material may be an amorphous tantalum material or a polycrystalline germanium material and the like, by way of example. In a particular embodiment, the impedance switching material 502 comprises an amorphous germanium material. The switching material is defined by a state, for example, an impedance state is attached to an electric field in the switching material. In a particular embodiment, the switching material is an amorphous germanium material. Impedance switching material 502 has substantially true semiconductor characteristics in a particular embodiment and is not intended to be doped. In various embodiments, amorphous germanium is also referred to as amorphous germanium. The amorphous 矽 non-volatile impedance switching device can be fabricated using existing CMOS technology.
沈積技術可包含化學氣相沈積程序、物理氣相沈積程序、原子層氣相沈積程序及其他。化學氣相沈積可以是低壓化學氣象沈積、電漿增強化學氣相沈積,使用前驅物例如矽甲烷或二矽烷或適合的氯矽烷在還原環境、其組合、或其他。沈積溫度範圍可介於250℃到約500℃。在一些案例中,沈積溫度範圍介於約400℃到約440℃且不超過約450℃。在一示範的程序中,一矽烷(45sccm)和氦(500sccm)被用於形成一a-Si層藉由在PECVD程序中以每分鐘80nm的沈積速率(溫度為260℃,壓力為600mTorr)。在另一示範的程序中,矽烷(190sccm)和氦(100sccm)被用於形成一a-Si層藉由在PECVD程序中以每分鐘2.8A的沈積速率(溫度為380℃,壓力為2.2Torr)。在另一示範的程序中,矽烷(80sccm)或二矽烷被用於形成一a-Si層藉由在LPCVD程序中以每分鐘2.8nm的沈積速率(溫度為585℃,壓力為100mTorr)。部份的複晶矽顆粒可在LPCVD程序中形成並造成一非晶複晶矽曾。在不同實施例中,無p型、n型、或金屬不純物被有意地加入沈積腔室內當形成非晶矽材料時。據此,在沈積時,非晶矽材料實質上沒有任何的p型、n型、或金屬不純物,亦即非晶矽材料是未摻雜的。 Deposition techniques may include chemical vapor deposition procedures, physical vapor deposition procedures, atomic layer vapor deposition procedures, and others. Chemical vapor deposition can be low pressure chemical weather deposition, plasma enhanced chemical vapor deposition, use of precursors such as methane or dioxane or suitable chlorodecane in a reducing environment, combinations thereof, or others. The deposition temperature can range from 250 °C to about 500 °C. In some cases, the deposition temperature ranges from about 400 °C to about 440 °C and no more than about 450 °C. In an exemplary procedure, monodecane (45 sccm) and ruthenium (500 sccm) were used to form an a-Si layer by a deposition rate of 80 nm per minute in a PECVD process (temperature 260 ° C, pressure 600 mTorr). In another exemplary procedure, decane (190 sccm) and ruthenium (100 sccm) were used to form an a-Si layer by a deposition rate of 2.8 A per minute in a PECVD process (temperature 380 ° C, pressure 2.2 Torr) ). In another exemplary procedure, decane (80 sccm) or dioxane was used to form an a-Si layer by a deposition rate of 2.8 nm per minute in a LPCVD procedure (temperature 585 ° C, pressure 100 mTorr). Part of the polycrystalline germanium particles can be formed in the LPCVD process and cause an amorphous polycrystalline germanium. In various embodiments, no p-type, n-type, or metal impurities are intentionally added to the deposition chamber when forming an amorphous germanium material. Accordingly, the amorphous germanium material does not substantially have any p-type, n-type, or metal impurities during deposition, that is, the amorphous germanium material is undoped.
在不同實施例中,非晶矽材料的厚度通常在介於約10nm到約30nm的範圍。在其他實施例中,其他厚度可被採用,依據所需的特定表現特性(例如切換電壓、保持力特性、電流、或類似者)。 In various embodiments, the thickness of the amorphous germanium material is typically in the range of from about 10 nm to about 30 nm. In other embodiments, other thicknesses may be employed depending on the particular performance characteristics desired (eg, switching voltage, retention characteristics, current, or the like).
在另一實施例中,阻抗切換材料502可形成自接合材料402(例如p+多晶含矽層)的一上部區域(例如遠離第一接線層302)。在不同實施例中,接合材料402的被暴露的表面被以電漿蝕刻使用氬、矽、氧、 或其組合以影響接合材料402與上部區域的非晶化。在一些例子中,電漿蝕刻可使用範圍在將近30瓦到將近120瓦的偏壓以轉化接合材料402的一上部區域成為阻抗切換材料502。 In another embodiment, the impedance switching material 502 can form an upper region of the bonding material 402 (eg, a p+ poly germanium containing layer) (eg, away from the first wiring layer 302). In various embodiments, the exposed surface of bonding material 402 is plasma etched using argon, helium, oxygen, Or a combination thereof to affect the amorphization of the bonding material 402 and the upper region. In some examples, plasma etching can use a bias voltage ranging from approximately 30 watts to approximately 120 watts to convert an upper region of bonding material 402 into impedance switching material 502.
在一些特定案例,當接合材料402是有摻雜的多晶矽材料,非晶化程序創造出SiOx材料供阻抗切換材料502。在另外一些特定案例,當接合材料402是有摻雜的矽鍺材料,非晶化程序創造出SixGeyOz(x、y、z為整數)材料供作為阻抗切換材料502。在一些例子中,成果的阻抗切換材料502可具有厚度範圍在將近2nm到將近5nm。在其他實施例,其他厚度是被考慮的,端視特定的工程需求。 In some specific cases, when the bonding material 402 is a doped polysilicon material, the amorphization process creates an SiOx material for the impedance switching material 502. In other specific cases, when the bonding material 402 is a doped germanium material, the amorphization process creates a SixGeyOz (x, y, z is an integer) material for the impedance switching material 502. In some examples, the resulting impedance switching material 502 can have a thickness ranging from approximately 2 nm to approximately 5 nm. In other embodiments, other thicknesses are considered, depending on the particular engineering requirements.
如圖6所示,在不同實施例中,方法包含沈積可能是阻隔層的一個層600在阻抗切換材料502上。在不同實施例中,阻隔層600可以具體為非貴金屬,例如鈦、鋁、鎢、鈦合金、鋁合金、鎢合金、氮化鈦、氮化鎢、氮化鋁、銅、銅合金、或類似者。非貴金屬用作氧化、吸收及鎖住氧。如一個例子,若層600為鈦,鈦氧化以形成氧化鈦,或者其他非導電層。 As shown in FIG. 6, in various embodiments, the method includes depositing a layer 600, which may be a barrier layer, on the impedance switching material 502. In various embodiments, the barrier layer 600 can be specifically a non-noble metal such as titanium, aluminum, tungsten, titanium alloy, aluminum alloy, tungsten alloy, titanium nitride, tungsten nitride, aluminum nitride, copper, copper alloy, or the like. By. Non-noble metals are used to oxidize, absorb and lock oxygen. As an example, if layer 600 is titanium, titanium is oxidized to form titanium oxide, or other non-conductive layer.
在一些實施例,層600可具有剛沈積的厚度範圍將近1nm到將近5nm,且在氧化後,層600可具有稍大的厚度。如一個例子,層600可由一個2.5nm的剛沈積厚度增加到一個3nm的氧化厚度。 In some embodiments, layer 600 can have a thickness that is just deposited ranging from approximately 1 nm to approximately 5 nm, and after oxidation, layer 600 can have a slightly greater thickness. As an example, layer 600 can be increased from a 2.5 nm just deposited thickness to a 3 nm oxidized thickness.
在不同實施例中,氧的來源可能來自任何數目的來源,包含大氣氧在層600形成後;氧存在於形成期間或之後的阻抗切換材料502;氧存在於一形成在阻抗切換材料502之後的活性導電材料602(描述於下);氧擴散經過形成在阻抗切換材料502之後的活性導電材料602;或類似者。 In various embodiments, the source of oxygen may be from any number of sources, including atmospheric oxygen after formation of layer 600; oxygen is present in impedance switching material 502 during or after formation; oxygen is present after formation of impedance switching material 502 Active conductive material 602 (described below); oxygen diffuses through active conductive material 602 formed after impedance switching material 502; or the like.
在一些實施例中,阻隔層600的氧化不必然發生在製程中的任何特定時間。相反的,在不同實施例中,當來自任何來源的氧到達層600,非貴重金屬可能氧化。如此,做為例子的,在一製造批次中,若有長延遲在層600形成後直到後續層被形成,氧化可能發生在此延遲期間;在另一製造批次,若有長延遲在接續的活性導電材料602被形成在層600上且當一擴散阻隔材料702(描述於下)被形成,氧化可能發生在此延遲期間;或類 似者。 In some embodiments, oxidation of barrier layer 600 does not necessarily occur at any particular time in the process. Conversely, in various embodiments, when oxygen from any source reaches layer 600, the non-precious metal may oxidize. Thus, as an example, in a manufacturing lot, if a long delay is formed after layer 600 is formed until a subsequent layer is formed, oxidation may occur during this delay; in another manufacturing lot, if there is a long delay in the continuation Active conductive material 602 is formed over layer 600 and when a diffusion barrier material 702 (described below) is formed, oxidation may occur during this delay; or Like.
在不同實施例中,目前相信一旦在層600中的非貴金屬材料被氧化,其提供額外的防護對於其後的氧擴散下到切換材料502。例如,若層600原本為氮化鈦材料,氧化後,氮氧化鈦材料阻止氧擴散自活性導電材料602進入切換材料502。 In various embodiments, it is presently believed that once the non-noble metal material in layer 600 is oxidized, it provides additional protection for subsequent diffusion of oxygen down to switching material 502. For example, if layer 600 is originally a titanium nitride material, the oxynitride material prevents oxygen from diffusing from active conductive material 602 into switching material 502 after oxidation.
在一些實施例中,這些氧化層可能不利於防止活性導電材料602的導體材料的擴散,描述如下,到阻抗切換材料502。 In some embodiments, these oxide layers may be detrimental to preventing diffusion of the conductive material of the active conductive material 602, as described below, to the impedance switching material 502.
如圖6所示,在一些實施例中,方法包含沈積一活性導電材料602在層600上。活性導電材料602可以是貴金屬材料例如銀、金、鉑、鈀、其合金、或其他。活性導電材料602被特定以合適的擴散性在阻抗切換材料中在一電場存在的一特定實施例。對於非晶矽材料作為阻抗切換材料502,金屬材料可以是銀或銀合金。在一些例子中,銀合金包含至少80%的銀。 As shown in FIG. 6, in some embodiments, the method includes depositing an active conductive material 602 on layer 600. The active conductive material 602 may be a noble metal material such as silver, gold, platinum, palladium, alloys thereof, or others. The active conductive material 602 is specific to a particular embodiment in which an appropriate electric field exists in the impedance switching material in an electric field. For the amorphous germanium material as the impedance switching material 502, the metal material may be silver or a silver alloy. In some examples, the silver alloy contains at least 80% silver.
在一些實施例中,其活性導電材料602為銀,銀金屬刺穿層600並在切換材料502(例如非晶矽材料,SiOx,SixGeyO或類似者)的一部份形成一銀區域在電場的施做上。銀區域包含複數個銀顆粒,含有銀離子、銀叢集、銀原子、或其組合。在特定實施例中複數個銀顆粒被形成在切換材料的缺陷位置。銀區域進一步包含銀絲狀結構由金屬(活性導電材料602)源,例如銀/銀離子,延伸到第一接線材料302。 In some embodiments, the active conductive material 602 is silver, the silver metal pierces the layer 600 and forms a silver region in the portion of the switching material 502 (eg, amorphous germanium material, SiOx, SixGeyO, or the like) in the electric field. Do it. The silver region comprises a plurality of silver particles comprising silver ions, silver clusters, silver atoms, or a combination thereof. In a particular embodiment a plurality of silver particles are formed at the defect location of the switching material. The silver region further comprises a silver filamentous structure extending from the source of metal (active conductive material 602), such as silver/silver ions, to the first wiring material 302.
在不同實施例中,絲狀結構被特定以長,在銀顆粒間的的距離,及在絲狀結構及第一電極結構間的距離。在一特定實施例,阻抗切換材料502(例如,非晶矽材料,SiOx,SixGeyOz)被特定以阻抗至少基於一長度,一銀顆粒間的長度,以及一絲狀結構及第一電極結構(第一接線材料302)間的長度。在一些案例中,由於材料不搭配,缺失密度在一形成自非晶矽材料(例如切換材料502)以及第一接線材料(例如第一接線材料302)的介面區域是高的,切可能造成短路。在特定實施例中接合層(例如接合材料402)(例如,p+複結晶矽鍺材料)控制介面的缺陷密度供阻抗切換裝置合適的切換性能。 In various embodiments, the filamentary structure is specified to be long, the distance between the silver particles, and the distance between the filamentary structure and the first electrode structure. In a particular embodiment, the impedance switching material 502 (eg, amorphous germanium material, SiOx, SixGeyOz) is specifically characterized by an impedance based at least on a length, a length between silver particles, and a filamentary structure and first electrode structure (first The length between the wiring materials 302). In some cases, the missing density is high in the interface region formed from the amorphous germanium material (eg, switching material 502) and the first wiring material (eg, first wiring material 302) due to material mismatch, which may cause a short circuit . In a particular embodiment, the bonding layer (e.g., bonding material 402) (e.g., p+ complex crystalline germanium material) controls the defect density of the interface for proper switching performance of the impedance switching device.
在一些實施例中,銀材料是直接接觸於在特定實施例中作為 阻抗切換材料的非晶矽。在其他實施例,材料的一薄層,例如氧化物、氮化物,在作為阻抗切換材料的非晶矽的頂部的銀材料的沈積前被形成。***的材料的薄層可為自然或特意長成或形成。在一些實施例中,一個或更多的蝕刻操作(例如HF蝕刻、氬蝕刻)可幫助控制這層的厚度。在一些實施例中,在銀材料的沈積前的這材料(例如氧化物、氮化物)的厚度範圍可在約20A到約50A;在其他實施例,厚度範圍可在約30A到約40A;或類似者。 In some embodiments, the silver material is in direct contact with the particular embodiment as The amorphous material of the impedance switching material. In other embodiments, a thin layer of material, such as an oxide, a nitride, is formed prior to deposition of the silver material on top of the amorphous germanium as the impedance switching material. A thin layer of the inserted material may be naturally or intentionally grown or formed. In some embodiments, one or more etching operations (eg, HF etching, argon etching) can help control the thickness of this layer. In some embodiments, the thickness of the material (eg, oxide, nitride) prior to deposition of the silver material can range from about 20 A to about 50 A; in other embodiments, the thickness can range from about 30 A to about 40 A; Similar.
在一些實施例中,一非晶矽的額外層可被設置在薄層(例如氧化物、氮化物)的頂部上,在銀材料的沈積前。此非晶矽(非特意摻雜)的額外層可用於幫助固定銀材料到材料的薄層(例如氧化物、氮化物、阻隔物)。在一些實施例中,厚度可在20-50A的大小。在一例子中,層的順序可為:未摻雜非晶矽用作阻抗切換材料,一材料的薄層(例如氧化物、氮化物、阻隔物),一非晶矽的薄層,以及銀材料。 In some embodiments, an additional layer of amorphous germanium may be disposed on top of a thin layer (eg, oxide, nitride) prior to deposition of the silver material. An additional layer of this amorphous germanium (unintentionally doped) can be used to help secure the silver material to a thin layer of material (eg, oxides, nitrides, barriers). In some embodiments, the thickness can be between 20 and 50 amps. In one example, the order of the layers can be: undoped amorphous germanium used as an impedance switching material, a thin layer of a material (eg, oxide, nitride, barrier), an amorphous tantalum, and silver material.
在另一實施例中,層600及活性導電材料602可被形成在相同的沈積步驟。例如,貴金屬或非貴金屬材料的混合物可被沈積在單一步驟,交替的層的貴金屬與非貴金屬材料可被沈積於複數步驟,或類似者。在不同實施例中,非貴金屬相對於貴金屬材料的百分比可以變異,例如百分比可能變異自約0.1%到約10%,或類似者。那是被相信的非貴金屬材料在此混合物也將被氧化並減少氧到達或存在切換材料502的量。 In another embodiment, layer 600 and active conductive material 602 can be formed in the same deposition step. For example, a mixture of precious metal or non-precious metal materials can be deposited in a single step, alternating layers of precious metal and non-precious metal materials can be deposited in a plurality of steps, or the like. In various embodiments, the percentage of non-noble metal relative to the precious metal material may vary, for example, the percentage may vary from about 0.1% to about 10%, or the like. It is believed that the non-precious metal material will also be oxidized in this mixture and reduce the amount of oxygen reaching or presenting the switching material 502.
如圖7所示,方法包含形成一第二擴散阻隔材料702在活性導電材料602上。對於銀作為活性導電材料602,第二擴散阻隔層702可為非貴金屬例如鈦、氮化鈦材料、鎢、或類似者。第二擴散阻隔材料702可形成藉由物理氣相沈積程序使用鈦或鎢靶材材料。一氮化物材料可被形成使用物理氣相沈積程序、或化學氣相沈積程序或原子層沈積程序或藉由氮與鈦材料反應。 As shown in FIG. 7, the method includes forming a second diffusion barrier material 702 on the active conductive material 602. For silver as the active conductive material 602, the second diffusion barrier layer 702 can be a non-noble metal such as titanium, titanium nitride material, tungsten, or the like. The second diffusion barrier material 702 can form a titanium or tungsten target material by a physical vapor deposition process. A nitride material can be formed using a physical vapor deposition process, or a chemical vapor deposition process or an atomic layer deposition process or by reacting nitrogen with a titanium material.
在不同實施例中,第二擴散阻隔材料702被形成在活性導電材料602行程後的一個短暫時間。如例,此短暫時間可以少於10分鐘、20分鐘、1小時、4小時或類似者。在一些例子中,此短暫時間被定義為少於或等於一天。藉由特定一個短暫時間,大氣氧被阻止吸收進入活性導電材 料602及/或移動到阻抗切換材料502、層600(例如在活性導電材料602級阻抗切換材料502間的介面),或類似者。 In various embodiments, the second diffusion barrier material 702 is formed a short time after the travel of the active conductive material 602. As an example, this short time can be less than 10 minutes, 20 minutes, 1 hour, 4 hours or the like. In some examples, this short time is defined as less than or equal to one day. At a specific short time, atmospheric oxygen is prevented from being absorbed into the active conductive material. Material 602 and/or moved to impedance switching material 502, layer 600 (eg, interface between active conductive material 602 level impedance switching material 502), or the like.
在其他實施例中,欲減少氧被吸收或被阻抗切換材料502或活性導電材料602包含在內的量,部份完成的裝置被放置在氧還原環境(例如實質上無氧)內一個短暫時間在活性導電材料602被沈積後。在一些實施例中,此短暫時間可以少於15分鐘、30分鐘、2小時、4小時或類似者。在一些例子中,此短暫時間被定義為少於或等於一天。在不同實施例中,部份完成的裝置被放置在氧還原環境(例如實質上無氧)內直到第二擴散阻隔(覆蓋)材料702被沈積後。在一特定實施例,方法包含形成一硬質遮罩材料802在第二擴散阻隔材料702上如圖8所示。硬質遮罩材料802可為介電材料、金屬材料、半導體材料、或類似者,依應用而定。在特定實施例中,硬質遮罩材料可為介電材料例如氧化矽、氮化矽、氧化矽及氮化矽的介電疊層(例如ONO疊層)、高K介電、低K介電,及其他。 In other embodiments, to reduce the amount of oxygen absorbed or contained by the impedance switching material 502 or the active conductive material 602, the partially completed device is placed in an oxygen reducing environment (eg, substantially oxygen free) for a brief period of time. After the active conductive material 602 is deposited. In some embodiments, this brief time can be less than 15 minutes, 30 minutes, 2 hours, 4 hours, or the like. In some examples, this short time is defined as less than or equal to one day. In various embodiments, the partially completed device is placed in an oxygen reducing environment (e.g., substantially oxygen free) until the second diffusion barrier (cover) material 702 is deposited. In a particular embodiment, the method includes forming a hard masking material 802 on the second diffusion barrier material 702 as shown in FIG. The hard mask material 802 can be a dielectric material, a metal material, a semiconductor material, or the like, depending on the application. In a particular embodiment, the hard mask material can be a dielectric material such as tantalum oxide, tantalum nitride, tantalum oxide, and tantalum nitride dielectric stack (eg, ONO stack), high K dielectric, low K dielectric ,and others.
在不同實施例中,硬質介電材料802被用以第一圖案化及蝕刻程序以形成一圖案層902如圖9所示。第一圖案化及蝕刻程序可包含陳積一光阻層在硬質遮罩材料上、圖案化此光阻材料、及使用此圖案化的光阻材料蝕刻此硬質遮罩材料在其他實施例中,其他傳統形式的蝕刻被期待。 In various embodiments, the hard dielectric material 802 is used in a first patterning and etching process to form a pattern layer 902 as shown in FIG. The first patterning and etching process can include depositing a photoresist layer on the hard mask material, patterning the photoresist material, and etching the hard mask material using the patterned photoresist material. In other embodiments, Other conventional forms of etching are expected.
如圖10所示,方法包含使用硬質遮罩902作為遮罩層對包含擴散阻隔材料702、活性導電材料602、層600、阻抗切換材料502、接合材料402等的材料堆疊進行一個或更多的蝕刻程序以形成一柱狀結構1202。在不同實施例中,阻抗記憶體裝置被形成自活性導電材料602、層600、阻抗切換材料502及接合材料402。 As shown in FIG. 10, the method includes using the hard mask 902 as a mask layer to perform one or more stacks of materials including the diffusion barrier material 702, the active conductive material 602, the layer 600, the impedance switching material 502, the bonding material 402, and the like. The etching process is performed to form a columnar structure 1202. In various embodiments, the impedance memory device is formed from active conductive material 602, layer 600, impedance switching material 502, and bonding material 402.
方法隨後移除在前述蝕刻程序後留下的介電硬質遮罩材料,並且形成一介電材料1302在每一第一結構上且填滿第一結構間的間隙如圖11所示。介電材料1302可為氧化矽、氮化矽、氧化矽及氮化矽的介電疊層(例如ONO疊層)、高K介電、低K介電,及其他。介電材料1302可以被沈積使用例如化學氣相沈積程序,包含低壓化學氣相沈積程序、電漿強化化學氣相沈積程序、高密度電漿化學氣相沈積程序、原子層沈積程序、及其他,依應用而定。介電材料1302可進一步被平面化以暴露阻隔(或 覆蓋)材料(例如702)的一表面區域1304以隔離每一第一結構並形成平面化表面1306,如圖11所示。 The method then removes the dielectric hard mask material remaining after the aforementioned etching process and forms a dielectric material 1302 on each of the first structures and fills the gap between the first structures as shown in FIG. Dielectric material 1302 can be a dielectric stack of hafnium oxide, tantalum nitride, hafnium oxide, and tantalum nitride (eg, an ONO stack), a high K dielectric, a low K dielectric, and others. The dielectric material 1302 can be deposited using, for example, a chemical vapor deposition process, including a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, and the like, Depending on the application. Dielectric material 1302 can be further planarized to expose the barrier (or A surface region 1304 of the material (e.g., 702) is covered to isolate each of the first structures and form a planarized surface 1306, as shown in FIG.
如圖12所示,一第二接線材料1402被形成在介電材料1302的平面化表面及表面區域1304,或類似者。第二接線材料1402可為金屬材料例如銅、鎢、鋁及其他。第二接線材料1402亦可為適當摻雜的半導體材料例如摻雜的覆晶材料及類似者,依應用而定。 As shown in FIG. 12, a second wiring material 1402 is formed over the planarized surface and surface region 1304 of the dielectric material 1302, or the like. The second wiring material 1402 may be a metal material such as copper, tungsten, aluminum, and others. The second wiring material 1402 can also be a suitably doped semiconductor material such as a doped flip chip material and the like, depending on the application.
第二接線材料1402被用於圖案化及蝕刻程序以形成一個或更多的第二接線結構。此一個或更多的第二接線結構在形狀上被伸長且被成型以延伸在一第二方向正交於第一接線結構的第一方向。此外,在特定實施例中至少阻抗切換單元被成型在第一接線結構和第二接線結構的一相交區域。方法可進一步包含形成鈍化層及球狀互連供記憶體裝置,在其他之間以完成此裝置。 A second wiring material 1402 is used for the patterning and etching process to form one or more second wiring structures. The one or more second wiring structures are elongated in shape and shaped to extend in a first direction orthogonal to the first direction of the first wiring structure. Moreover, in a particular embodiment at least the impedance switching unit is formed in an intersection region of the first wiring structure and the second wiring structure. The method can further include forming a passivation layer and a ball interconnect for the memory device, among others to complete the device.
在其他實施例中,其他配置及結構被考慮供非揮發性記憶體結構。在一例中,一個矽鍺層被沈積隨後為一二氧化矽層。一開口然後被打開且矽鍺的上表面被非晶化以形成非晶層在一些實施例中,此層具有厚度在將近2到將近3nm。在一些實施例中,例如,此程序可被進行在一單一氬電漿蝕刻步驟。在另一些實施例中,矽鍺的上表面可在二氧化矽沈積前被非晶化。隨後,鈦、銀、及/或鎢等層被沈積。在製程中的一些時間,或其他方面,底部鈦層吸收氧且氧化成為氧化鈦,或其他非導電層。在一些實施例中,此氧化層具有將近3到將近4nm的厚度。 In other embodiments, other configurations and structures are contemplated for non-volatile memory structures. In one example, a layer of tantalum is deposited followed by a layer of germanium dioxide. An opening is then opened and the upper surface of the crucible is amorphized to form an amorphous layer. In some embodiments, this layer has a thickness of approximately 2 to approximately 3 nm. In some embodiments, for example, the process can be performed in a single argon plasma etch step. In other embodiments, the upper surface of the crucible can be amorphized prior to the deposition of the hafnium oxide. Subsequently, layers of titanium, silver, and/or tungsten are deposited. At some time during the process, or otherwise, the bottom titanium layer absorbs oxygen and oxidizes to titanium oxide, or other non-conductive layers. In some embodiments, the oxide layer has a thickness of approximately 3 to approximately 4 nm.
圖13顯示表現數據的圖根據本發明的多種實施例。更具體地,在多個邊製程序及消除的週期後,圖13顯示了形成的非揮發性記憶體裝置的一些優點。一個特定的優點是此記憶體裝置在多個不同週期後一致的穩定性。 Figure 13 shows a representation of performance data in accordance with various embodiments of the present invention. More specifically, Figure 13 shows some of the advantages of the formed non-volatile memory device after multiple side-by-side procedures and elimination cycles. A particular advantage is the consistent stability of this memory device over a number of different cycles.
作為另一例子,在一實施例中,接合層402及切換層502可以被形成為柱狀結構被氧化層所環繞。隨後,層600、活性導電材料602、等等被沈積及接觸柱狀結構的上表面。 As another example, in an embodiment, the bonding layer 402 and the switching layer 502 may be formed such that the columnar structure is surrounded by the oxide layer. Subsequently, layer 600, active conductive material 602, and the like are deposited and contact the upper surface of the columnar structure.
雖然前述的描述及圖式已揭示本發明之較佳實施例,必須瞭解到各種增添、許多修改和取代可能使用於本發明較佳實施例,而不會 脫離如所附申請專利範圍所界定的本發明原理之精神及範圍。熟悉本發明所屬技術領域之一般技藝者將可體會,本發明可使用於許多形式、結構、佈置、比例、材料、元件和組件的修改。因此,本文於此所揭示的實施例應被視為用以說明本發明,而非用以限制本發明。本發明的範圍應由後附申請專利範圍所界定,並涵蓋其合法均等物,並不限於先前的描述。 While the foregoing description and drawings have disclosed the preferred embodiments of the invention The spirit and scope of the principles of the invention as defined by the appended claims. Modifications of many forms, structures, arrangements, ratios, materials, components and components can be made by those skilled in the art to which the invention pertains. Therefore, the embodiments disclosed herein are to be considered as illustrative and not restrictive. The scope of the present invention is defined by the scope of the appended claims, and the legal equivalents thereof are not limited to the foregoing description.
102‧‧‧半導體基材 102‧‧‧Semiconductor substrate
202‧‧‧半導體基材 202‧‧‧Semiconductor substrate
302‧‧‧第一接線材料 302‧‧‧First wiring material
304‧‧‧第一黏著材料 304‧‧‧First Adhesive Material
306‧‧‧擴散阻隔材料 306‧‧‧Diffuse barrier material
1302‧‧‧介電材料 1302‧‧‧ dielectric materials
1402‧‧‧第二接線材料 1402‧‧‧Second wiring material
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102129266A TWI604645B (en) | 2013-08-15 | 2013-08-15 | Noble metal/non-noble metal electrode for rram appli cations |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW102129266A TWI604645B (en) | 2013-08-15 | 2013-08-15 | Noble metal/non-noble metal electrode for rram appli cations |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201507224A true TW201507224A (en) | 2015-02-16 |
TWI604645B TWI604645B (en) | 2017-11-01 |
Family
ID=53019516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW102129266A TWI604645B (en) | 2013-08-15 | 2013-08-15 | Noble metal/non-noble metal electrode for rram appli cations |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI604645B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107591479A (en) * | 2016-07-07 | 2018-01-16 | 华邦电子股份有限公司 | Resistive random access memory |
-
2013
- 2013-08-15 TW TW102129266A patent/TWI604645B/en active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107591479A (en) * | 2016-07-07 | 2018-01-16 | 华邦电子股份有限公司 | Resistive random access memory |
CN107591479B (en) * | 2016-07-07 | 2020-05-29 | 华邦电子股份有限公司 | Resistive random access memory |
Also Published As
Publication number | Publication date |
---|---|
TWI604645B (en) | 2017-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9735358B2 (en) | Noble metal / non-noble metal electrode for RRAM applications | |
US8946667B1 (en) | Barrier structure for a silver based RRAM and method | |
US9793474B2 (en) | Low temperature P+ polycrystalline silicon material for non-volatile memory device | |
TW399330B (en) | Semiconductor device, memory cell, and processes for forming them | |
WO2009096363A1 (en) | Resistance nonvolatile memory device and method for manufacturing same | |
TWI602284B (en) | Resistive switching device for a non-volatile memory device and method of forming the same | |
JP2013532378A (en) | Columnar structure and method for memory device | |
TW201010007A (en) | A memory cell that includes a carbon-based memory element and methods of forming the same | |
TWI720645B (en) | Transistors including heterogeneous channels, and related devices, electronic systems, and methods | |
US10192927B1 (en) | Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory | |
US8716098B1 (en) | Selective removal method and structure of silver in resistive switching device for a non-volatile memory device | |
US8883603B1 (en) | Silver deposition method for a non-volatile memory device | |
TWI604645B (en) | Noble metal/non-noble metal electrode for rram appli cations | |
US12027363B2 (en) | Methods of forming electronic devices comprising silicon carbide materials | |
US9269897B2 (en) | Device structure for a RRAM and method | |
US9401475B1 (en) | Method for silver deposition for a non-volatile memory device | |
US8889521B1 (en) | Method for silver deposition for a non-volatile memory device | |
US10700276B2 (en) | Preparation method of Cu-based resistive random access memory, and memory | |
US10305035B2 (en) | Preparation method of Cu-based resistive random access memory | |
US8765566B2 (en) | Line and space architecture for a non-volatile memory device | |
US9070859B1 (en) | Low temperature deposition method for polycrystalline silicon material for a non-volatile memory device | |
TW594934B (en) | Method of fabricating a semiconductor memory |