TW201503321A - 印刷複合式電子電路 - Google Patents

印刷複合式電子電路 Download PDF

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Publication number
TW201503321A
TW201503321A TW103109833A TW103109833A TW201503321A TW 201503321 A TW201503321 A TW 201503321A TW 103109833 A TW103109833 A TW 103109833A TW 103109833 A TW103109833 A TW 103109833A TW 201503321 A TW201503321 A TW 201503321A
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Taiwan
Prior art keywords
devices
circuit
groups
substrate
electrode
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TW103109833A
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English (en)
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TWI549257B (zh
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William Johnstone Ray
Richard Austin Blanchard
Mark David Lowenthal
Bradley Steven Oraw
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Nthdegree Tech Worldwide Inc
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Publication of TW201503321A publication Critical patent/TW201503321A/zh
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Abstract

本發明揭示一種可程式化電路，其包含微觀電晶體或二極體之經印刷群組之一陣列。裝置經預成形且印刷為一墨水與經固化。各群組中之該等裝置經並聯連接，使得各群組充當一單個裝置。在一實施例中，各群組中包含大約10個裝置，因此冗餘使得各群組非常可靠。各群組具有至少一電引線，其終接在基板上之一補片區域中。一互連導體圖案使該補片區域中之該等群組之至少一些該等引線互連，以針對通用電路之一客製化應用形成邏輯電路。該等群組亦可被互連為邏輯閘，且閘引線終接在該補片區域中。該互連導體圖案隨後使該等閘互連以形成複合式邏輯電路。

Description

印刷複合式電子電路 [相關申請案之交叉參考]
本申請案係基於由William Johnstone Ray等人於2013年3月14日申請之美國臨時申請案第61/785,292號，其被讓渡給本受讓人且以引用的方式併入本文中。
本發明係關於在一基板上以單獨群組印刷預成形微觀半導體裝置，諸如電晶體及二極體，其中各群組中之隨機分佈裝置經並聯連接且使群組互連以產生複合式電路，諸如邏輯電路。
藉由本受讓人自身之工作瞭解如何以適當定向在一導電基板上形成及印刷微觀兩端垂直發光二極體(LED)及將LED並聯連接以形成一光板。可於標題為Method of Manufacturing a Printable Composition of Liquid or Gel Suspension of Diodes之美國申請公開案US 2012/0164796中找到LED之此印刷之細節，該案被讓渡給本受讓人且以引用的方式併入本文中。
圖1係可使用下列程序印刷之LED 16之一層之一截面圖。各LED 16包含標準半導體GaN層，包含一n層及主動層以及一p層。
一LED晶圓(含有數千個垂直LED)經製作使得各LED 16之底部金屬陰極電極18包含一反射層。各LED 16之頂部金屬陽極電極20係小的以允許幾乎所有LED光逸出陽極側。藉由一黏著層接合至LED晶圓 之「頂部」表面之一載體晶圓可用於接達至LED之兩側以進行金屬化。隨後，諸如藉由圍繞各LED向下蝕刻溝槽至黏著層及溶解暴露黏著層或藉由薄化載體晶圓而單件化LED 16。
隨後，將微觀LED均勻浸透於包含一黏度改質聚合物樹脂之一溶劑中，以形成用於印刷(諸如網版印刷或膠版印刷)之一LED墨水。
若陽極電極20需在印刷後定向在與基板22相反之一方向上，則將電極20製成高使得LED 16在其等安定在基板表面上時藉由液壓而在溶劑中旋轉。LED 16旋轉至最小電阻之一定向。已達成超過90%類似定向。
在圖1中，提供一起始基板22。若基板22本身不導電，則諸如藉由印刷在基板22上沈積一反射導體層24(例如，鋁)。基板22可為薄及可撓性。
隨後，諸如藉由膠版印刷而在導體層24上印刷LED 16，其中一旋轉板上之一圖案判定用於捲軸式程序之沈積，或藉由使用一適當網進行網版印刷以允許LED穿過且控制層之厚度。由於相對較低濃度，LED 16將被印刷為一單層，且相當均勻地分佈在導體層24上方。
隨後，使用例如紅外線爐加熱而使溶劑蒸發。在固化後，LED 16保持附接至下伏導體層24，其中溶解在LED墨水中之少量殘餘樹脂作為一黏度改質劑。樹脂之黏著性質及在固化期間LED 16下方之樹脂之體積減小將底部LED電極18壓抵於下伏導體24，從而製成與其之歐姆接觸。
隨後，在表面上方印刷一介電層26以囊封LED 16且進一步將其等固定在適當位置中。
隨後，在介電層26上方印刷一頂部透明導體層28以電接觸電極20且在適於所使用之透明導體類型之爐中固化頂部透明導體層28。
若需要散佈電流，則金屬匯流排條30至33隨後沿著導體層24及 28之相對邊緣印刷且分別電終接在陽極及陰極引線(未展示)用於供電給LED 16。匯流排條30至33最終將連接至一正或負驅動電壓。
圖2係圖1之俯視圖。圖2之截面係圖3之水平對分。LED 16在經印刷層中之位置係隨機的。
若將一適當電壓差施加至陽極及陰極引線，則具有適當定向之所有LED 16將被照明。圖1展示一光線38。
上述程序嚴格結合具有一頂部電極及一底部電極之兩端裝置使用，此係因為LED在基板上之位置係隨機的，且LED可僅藉由將LED夾置於任意厚度之兩個導電層之間而互連。此外，上述程序嚴格用於形成用於產生光之LED陣列。LED不旨在執行任意類型之邏輯功能，此係因為並聯連接之LED之陣列僅形成一單個二極體。
將期望調適上述印刷/固化程序以產生涉及三端電晶體、二極體及可能的額外類型之組件之複合式印刷電路以執行邏輯功能。
本發明大體上係關於在一基板(諸如一撓性電路)上以小的單獨群組印刷預成形微觀(例如，介於10微米至200微米之間之尺寸)電子裝置，包含電晶體及二極體。各群組可含有例如大約10個裝置。各群組中之裝置使用經印刷導體層並聯連接。
各群組充當一單個裝置(例如，一單個電晶體或一單個二極體)，此係因為相同裝置在各群組中並聯連接。在群組形成後的任意時間，群組隨後經互連(程式化)以形成一客製化電路，諸如用於執行一指定功能之一邏輯電路。
在一實施例中，印刷裝置係電晶體或二極體且程式化步驟形成複數個邏輯閘。在另一實施例中，基板經初步處理以從群組形成邏輯閘之一陣列，且一後續「程式化」步驟藉由使閘互連以形成一複合式邏輯電路而客製化基板。因此，經印刷基板可形成一可程式化閘陣 列。
在一實施例中，「程式化」以形成電路係藉由以下步驟執行：在基板上形成一疏水遮罩；界定互連圖案；及隨後沈積一導電材料以在基板上形成互連金屬跡線。在另一實施例中，互連跡線藉由膠版印刷或網版印刷直接印刷在基板上。
裝置之群組可皆為相同裝置(例如，電晶體)或多種裝置(例如，電晶體及二極體)。電路可為除邏輯電路以外之電路，諸如控制電路、切換電路、類比電路等。
許多類型之電組件使用三個端子，諸如MOSFET、雙極電晶體、JFET、閘流電晶體、矽控整流器等。此等組件之習知者通常針對橫向裝置在頂部上具有三個端子或，針對垂直裝置在頂部上具有兩個端子且在底部上具有一個端子。已知藉由在一基板上方印刷各種電晶體層而形成薄膜電晶體，但是此等經印刷電晶體之效能歸因於印刷一單晶體之困難而不良。若電晶體(或其他三端裝置)可更習知地形成在一半導體晶圓中且隨後經單件化以產生作為一墨水印刷之微觀裝置，則裝置之品質可為當前最先進技術。但是，迄今為止，未知如何設計此等裝置或在印刷後使此等三端微觀裝置互連以執行複合功能。
在一實施例中，形成三端裝置(諸如電晶體)之一半導體(例如，矽)晶圓。電晶體經形成在晶圓中以具有一底部電極、一頂部電極及定位於裝置之頂部與底部之間之某處之一架子上之一中間電極。起始晶圓最終藉由一黏著劑貼附至一載體晶圓以在製作電晶體時接達至該等電晶體之兩個表面。
藉由圍繞各電晶體形成溝槽而將電晶體單件化為個別電晶體，諸如以形成六邊形裝置。溝槽向下延伸至黏著層且黏著層溶解在一溶液中，從而自載體晶圓釋放所有電晶體。
隨後，將電晶體均勻混合至一溶液中以形成一墨水。電晶體之 形狀導致其等之大多數以所要定向印刷在一基板上。
隨後，將電晶體印刷在一基板上方之相關聯第一導體層部分上以形成電晶體之群組之一陣列，且使墨水固化(加熱及蒸發)，使得各電晶體之底部電極歐姆接觸至此等第一導體層部分。歸因於溶液中電晶體之相對低密度，電晶體將被印刷為一鬆散單層。產品中之任意層之印刷可藉由膠版印刷(尤其適於捲軸式程序)、網版印刷(在形成平板時尤其適用)或其他類型之印刷。
隨後，在第一導體層部分上方印刷一第一介電層。第一介電層未覆蓋中間電極。隨後，印刷與第一導體層部分對準之第二導體層部分，其等接觸中間電極但未覆蓋頂部電極。各種薄的經印刷層藉由強表面張力而自平坦化，使得層未覆蓋「高於」層之厚度之任意特徵。或者，層可在固化後經毯覆式蝕刻以暴露任意電極。
隨後，在第二導體層部分上方印刷一第二介電層，但未覆蓋頂部電極。隨後，印刷頂部(第三)導體層部分以接觸各群組中之電晶體的頂部電極。
因此，使電晶體之頂部電極並聯連接，使底部電極並聯連接，且使中間電極(或其等之子集)並聯連接，以傳導廣泛範圍之電流。
如上所述，隨後，可在一程式化步驟中，使群組互連以形成邏輯閘或更複雜電路。
可印刷微觀垂直二極體來代替電晶體且僅需兩個導體層以使各群組中之二極體並聯連接。
對於簡單被動裝置(諸如電阻器)，電阻材料本身(而非印刷含有個別電阻器之墨水)可被印刷在一小區域中，且藉由一導體沿著其長度在何處接觸電阻器來判定電阻。
基板之不同區域可印刷有不同裝置或相同裝置，且各區域中之裝置被並聯連接。因此，各區域本質上係一單個裝置。導體層終接在 基板上緊鄰各區域之連接器區域中。
在一實施例中，基板可具有一指定「補片(patch)」區域，其中製成群組或閘之互連。此簡化經程式化互連之設計，此係因為補片區域可針對程式化步驟而最佳化。
裝置經形成使得在一群組中之一些裝置經顛倒印刷或製成一不良連接的情況下對群組中之適當定向裝置的功能無不利影響。
印刷程序可使用大氣壓力下之捲軸式程序。經印刷可程式化基板的成本比使用習知技術形成之可比較可程式化基板的成本低得多。
揭示其他實施例。
16‧‧‧發光二極體(LED)
18‧‧‧底部金屬陰極電極/底部發光二極體(LED)電極
20‧‧‧頂部金屬陽極電極
22‧‧‧基板
24‧‧‧反射導體層/下伏導體
26‧‧‧介電層
28‧‧‧頂部透明導體層
30‧‧‧金屬匯流排條
31‧‧‧金屬匯流排條
32‧‧‧金屬匯流排條
33‧‧‧金屬匯流排條
38‧‧‧光線
40‧‧‧三端裝置/裝置
40A‧‧‧裝置
40B‧‧‧npn雙極電晶體/裝置
40C‧‧‧p通道MOSFET/裝置
42‧‧‧下區段
44‧‧‧上區段
46‧‧‧金屬頂部電極
48‧‧‧金屬中間電極
50‧‧‧起始基板
52‧‧‧導體層
54‧‧‧導電通孔
56‧‧‧金屬層
58‧‧‧底部電極
60‧‧‧介電層
62‧‧‧中間導體層
64‧‧‧介電層
66‧‧‧頂部導體層
67‧‧‧印刷步驟
68‧‧‧金屬層
69‧‧‧固化步驟
72‧‧‧群組
74‧‧‧群組
75‧‧‧導電跡線
76‧‧‧供應電壓端子
78‧‧‧供應電壓端子
80‧‧‧輸入端子
82‧‧‧輸入端子
84‧‧‧輸出端子
85‧‧‧導電跡線/跡線
86‧‧‧補片區域
87‧‧‧可程式化電路板/電路板
88‧‧‧端子
90‧‧‧程式化跡線
94‧‧‧疏水遮罩
96‧‧‧區域
98‧‧‧導體
100‧‧‧疏水遮罩
102‧‧‧連接器
103‧‧‧連接器
106‧‧‧電路板
108‧‧‧基板
110‧‧‧群組
112‧‧‧群組
114‧‧‧跡線
116‧‧‧跡線
118‧‧‧通孔
120‧‧‧電路板
122‧‧‧電路板
124‧‧‧電路板
126‧‧‧端子
128‧‧‧區域
130‧‧‧導電黏著劑
132‧‧‧跡線
134‧‧‧跡線
136‧‧‧輥
138‧‧‧輥
r1‧‧‧電阻器
r2‧‧‧電阻器
R1‧‧‧電阻器
R2‧‧‧電阻器
R3‧‧‧電阻器
圖1係可使用受讓人之先前技術程序形成之經印刷微觀垂直LED之一鬆散單層之一截面。
圖2係圖1之結構之一俯視圖，其中圖1係跨水平對分之圖2取得。
圖3係根據本發明之一實施例之已從一晶圓單件化之一單個三端電晶體之一透視圖。電晶體經混合至一溶液中以形成用於印刷在一基板上之一墨水。
圖4係使用導體層之三個平面並聯連接之圖3之電晶體之一經印刷層之一小部分之一截面。可在各單獨群組中印刷大約10個並聯連接電晶體，且在基板上方印刷群組之一陣列。
圖5圖解說明圖3之電晶體如何可為一npn雙極電晶體。
圖6圖解說明圖3之電晶體如何可為一p通道MOSFET。
圖7及圖8圖解說明一些電晶體在印刷時可如何藉由電晶體之不當定向而「不正確地」互連，其中互連未不利影響不當定向之電晶體之功能。
圖9係識別MOSFET及雙極電晶體之頂部電極、底部電極及中間 電極之較佳功能之一圖表。
圖10圖解說明使電晶體之群組互連以形成一邏輯電路。
圖11圖解說明裝置之各種群組之引線可如何被帶至基板之一補片區域以用於使群組互連。在另一實施例中，可將由群組製成之邏輯閘(例如，NAND閘)之引線帶至補片區域。
圖12係使用一疏水遮罩圖案化之導體之一俯視圖。
圖13係使用圖12之遮罩形成之導體線之一者之一截面圖。
圖14圖解說明疏水遮罩可如何用於形成導體線以使裝置之群組互連以形成邏輯電路。
圖15圖解說明可如何藉由導體接觸經印刷電阻材料之位置判定電阻器值。
圖16圖解說明裝置可如何被印刷在一基板之兩側上且藉由一通孔互連。
圖17圖解說明電路可如何被印刷在相對較小基板上且經測試，隨後小基板在一客製化步驟期間附接至一較大「基底」基板。
圖18圖解說明圖17之小基板上之電極可如何接合至基底基板上之電極。
圖19圖解說明可用於形成電路之一捲軸式程序。
在各種圖中，類似或相同之元件用相同數字標記。
本發明之經印刷可程式化電路可使用被動裝置(例如，電容器、電阻器)、兩端無機半導體裝置(例如，二極體)及三端無機半導體裝置(例如，電晶體)之任意組合。待印刷及電連接至之最複雜裝置係三端裝置。在一些情況中，三端裝置(諸如一雙極電晶體)可藉由僅使用兩個端子或將兩個端子連接至相同導體而用作二極體。
本發明之實施例中所使用之三端裝置可小於人類頭髮之直徑， 從而使該等裝置在跨一基板稀疏散佈時對於裸眼本質上不可見。裝置之大小可在大約10微米至200微米之範圍內。每單位面積之微裝置之數目可在將微裝置施加至基板時自由調整。裝置可使用膠版印刷、網版印刷或其他形式之印刷而印刷為墨水。三端裝置之習知設計可易於經調適用於形成本發明之微裝置。光微影之精度恰好在形成微裝置所需之精度內。由於許多微裝置將平行操作，故各微裝置之效率並非至關重要。
圖3係可懸浮在一溶劑中且作為一墨水印刷在一基板上之三端裝置40之一透視圖。裝置40可為一雙極電晶體、一MOSFET、一JFET、三MOS裝置或任意其他三端裝置，大致包含兩個載流端子及一控制端子。裝置40可為一橫向或垂直電晶體，此係因為三個電極之位置未指示在裝置40內部之半導體層/區域或閘極之位置。電極可使用通孔接觸裝置40中之任意位置。
裝置40藉由在處理期間使用一或多個載體晶圓以接達至用於金屬化之兩個表面而完全形成在一半導體晶圓上(包含電極金屬化)。雖然生長晶圓可為矽，但是載體晶圓可為任意材料。矽晶圓使用一黏著劑或其他適當材料貼附至載體晶圓。各裝置40之形狀藉由遮罩及蝕刻界定。各種層或區域可使用經遮罩植入或藉由在磊晶生長的同時摻雜層而摻雜。在裝置形成在晶圓上之後，圍繞各裝置40在晶圓之前表面中光微影界定溝槽且向下蝕刻溝槽至黏著層。各裝置40之一較佳形狀係六邊形。溝槽蝕刻暴露下伏晶圓接合黏著劑。隨後，黏著劑溶解在一溶液中以自載體晶圓釋放裝置40。可代替性地藉由薄化載體晶圓之後表面直至單件化裝置40而執行單件化。隨後，微觀裝置40被均勻浸透在包含一黏度改質聚合物樹脂之一溶劑中，以形成用於印刷(諸如網版印刷或膠版印刷)之一墨水。
可使用一類似技術以形成兩端裝置，諸如一垂直二極體，其中 一電極處於頂部上且另一電極處於底部上。二極體可具有類似於圖3中所示之形狀之一形狀但無中間電極。
有關在一晶圓中塑形垂直LED(兩端裝置)且隨後單件化LED用於作為墨水印刷之細節描述於標題為Method of Manufacturing a Printable Composition of Liquid or Gel Suspension of Diodes之美國申請公開案US 2012/0164796中，該案被讓渡給本受讓人且以引用的方式併入本文中。熟習此項技術者可調適此等程序用於形成三端裝置40及非LED二極體。
裝置40具有兩個區段：一下區段42(或基底部分)及一上區段44。 上區段44被製成相對較高及窄，使得裝置40在其等安定於基板表面上時藉由液壓在溶劑中旋轉。裝置40旋轉至最小電阻之一定向。已達成超過90%類似定向，但是令人滿意的效能可在超過75%的裝置40處於相同定向之情況下達成。
下區段42應經塑形使得裝置40在墨水固化後平放在基板上。圖4圖解說明三個經印刷裝置40，其中僅兩個經印刷裝置40以正確定向印刷。
裝置40包含一金屬頂部電極46、一金屬中間電極48及一金屬底部電極(圖3中未展示)。中間電極48之形狀提供一大的側表面積用於與一中間導體層良好電接觸。
中間電極48應相對於裝置40之中間偏移使得裝置40在印刷後之一不當定向導致中間電極48未電接觸中間導體層。在實例中，中間電極48處在裝置之中間下方(即，H2<½H1)。
在圖4中，提供一起始基板50。針對輕量、低成本、良好熱傳導至空氣或一散熱器及便於處理，基板50較佳係薄且可撓性。基板50可為一適當聚合物，諸如聚碳酸酯、PMMA或PET且可為可撓性以自一輥施配。基板50可為適於最終產品之任意大小。基板50可為一習知撓 性電路基板，其中金屬(例如，銅)跡線已在下文處理步驟之前藉由習知方式形成在基板50上。
若基板50尚未如撓性電路般在其上形成金屬跡線，則諸如藉由印刷在基板50上沈積一導體層52(例如，銀、鋁、銅)。可使用穿過基板50之導電通孔54以將導體層52耦合至形成在基板50之底部表面上之一金屬層56。在各種實例中，導體層52被印刷為基板50上之圓點之一陣列(見圖11)。點彼此電隔離以允許裝置40之群組以任意方式互連以形成邏輯電路。代替圓點，導體層52可被印刷為方點或其他形狀的點。
隨後，諸如藉由膠版印刷或藉由使用一適當網進行網版印刷而將裝置40印刷在導體層52上以允許裝置40穿過且控制層之厚度。由於相對較低濃度，裝置40將被印刷為一鬆散單層，且相當均勻地分佈在導體層52上方。裝置40之經印刷位置與導體層52之經印刷點之位置對準。
隨後，藉由使用(例如)紅外線爐加熱而使溶劑蒸發。在固化後，裝置40保持附接至下伏導體層52，其中溶解在墨水中之少量殘餘樹脂作為一黏度改質劑。樹脂之黏著性質及在固化期間裝置40下方之樹脂之體積減小將底部電極58壓抵於下伏導體層52，從而製成與其之歐姆接觸。
隨後，印刷一薄介電層60以覆蓋導體層52，且進一步將裝置40固定在適當位置中。介電層60經設計以在固化期間藉由表面張力自平坦化，以拉離頂部電極46及中間電極48，或使其等去除潤濕。因此，無需蝕刻介電層60。若介電層60覆蓋電極46/48，則可使用一毯覆式蝕刻以暴露電極46/48。
隨後，在介電層60上方印刷與導電層52之點對準之一中間導體層62以電接觸中間電極48，且在適於所使用之導體之類型之一爐中固 化中間導體層62。各種導體層可為金屬(或含有金屬)或可為任意其他類型之可印刷導體層。
在中間導體層62上方印刷另一薄介電層64以不覆蓋頂部電極46。
隨後，在介電層64上方印刷與中間導體層62之點對準之一頂部導體層66以電接觸頂部電極46，且在適於所使用之導體之類型之一爐中固化頂部導體層66。
隨後，可在導體層66上方印刷一較厚金屬層68，用於改良導電性及/或熱傳導。中間導體層62從點之邊緣延伸出以形成裝置40之群組之一端子。
圖4圖解說明形成圖4之結構所需之唯一步驟係印刷步驟67及固化步驟69。裝置40之隨機圖案可類似圖2中之LED 16之圖案。
圖4圖解說明最右裝置40A經定向在相反方向上。但是，中間電極48保持浮動，因此裝置40A並未操作且對所得電路無影響。
經印刷裝置40藉由導體層並聯連接。將適當的操作電壓及控制電壓施加至導體層以操作裝置40。在圖4之實例中，頂部電極46係裝置40之控制電極(例如，用於閘極或基極)。剩餘兩個電極係載流電極(例如，源極/汲極、射極/集極)。由於不當定向之裝置40A的中間電極48係浮動的，故裝置40保持關閉且為一開路。
圖5圖解說明裝置40如何可為一npn雙極電晶體40B，其中中間電極48係基極電極。中間電極48可使用一通孔連接至裝置40B中之任意其他半導體層。
圖6圖解說明裝置40如何可為一p通道MOSFET 40C，其中中間電極48係源極電極。中間電極48可使用一通孔連接至裝置40C中之任意其他層。
若裝置40將連接為二極體，則僅可使用導體層62及52或66及 62。因此，可藉由哪兩個導體層係用以接觸二極體來選擇二極體的有效極性。或者，兩個導電層可經遠端連接以形成二極體。
任意數目個裝置40可並聯連接在一群組中，用於處置廣泛範圍之電流。在一實施例中，大約10個裝置40被定位在各群組中。裝置40之群組係諸如藉由在一膠版印刷程序中使用一輥上之一圖案或藉由使用一網版印刷網上之一遮罩而印刷為群組之二維陣列，且各種導體層可經類似圖案化，使得各群組中之裝置40並聯連接，但各群組彼此電隔離。因此，各群組形成一單獨組件。隨後，可使用基板50上之「程式化」導體跡線來選擇性地使群組互連以形成更複雜電路，諸如邏輯電路。基板50上之一金屬撓性電路圖案可用於使裝置40之群組互連以形成邏輯電路。在一實施例中，由於各群組可小至每側一毫米或直徑一毫米，故此等群組之二維陣列可超過數千個群組。一小區域內之群組可經互連以形成邏輯閘，且該等閘之端子可在程式化期間互連以執行任意邏輯功能。
圖7圖解說明圖4中之裝置40A之不當定向如何未不利影響群組中並聯連接之適當定向裝置40之操作。裝置40/40A被假設為一npn雙極電晶體，其具有用作基極之一頂部電極46、用作射極之一底部電極58及用作集極之一中間電極48。由於裝置40A在印刷期間非所要地顛倒定向(圖4中所示)，故其基極短接至裝置40之射極且其射極短接至裝置40之基極。當裝置40之基極/射極接面經正向偏壓以開啟裝置40時，裝置40A保持關閉且對裝置40之操作無影響。注意，藉由使用自裝置40之中間偏移之一中間電極48(如圖3及圖4中所示)，裝置40A之中間電極48將係浮動的，從而使其效應更加明顯。
圖8類似於圖9，但是裝置40及40A係MOSFET。
圖9係一表，其展示形成為一MOSFET或一雙極電晶體使得不當定向未不利影響並聯連接之適當定向裝置40之功能之裝置40之頂部電 極、底部電極及中間電極之可能連接。
圖10圖解說明經印刷npn雙極電晶體(例如，裝置40)之兩個群組72及74，其中各群組中之電晶體經並聯連接，使得各群組充當一單個電晶體。裝置40及導體層之印刷圖案作為圓點形成群組，但可使用任意形狀之點。圖4中之群組之互連使電路成為一AND閘。導電跡線75針對各群組連接至圖4中之各種導體層。兩個電晶體(即，群組72及74)串聯連接在供應電壓端子76與78之間，電晶體之基極連接至輸入端子80及82，且輸出端子84連接至由群組74形成之電晶體之射極。各種端子可在基板50之邊緣附近或鄰近群組。
電阻器r1及r2被展示為連接在輸入端子80/82與基極之間用於電流控制。歸因於電阻器之簡單，電阻材料可運用一經圖案化輥使用膠版印刷或用於印刷電阻材料之一篩網上之一遮罩直接圖案化在基板上。電阻材料之形狀可判定電阻或連接器沿著其長度之位置可判定電阻。一電阻器亦可包含在各裝置40上。電容器亦可藉由印刷電容器之層而形成。
基板50可含有數百或數千個此等AND閘或其他閘，且該等閘可經互連以形成更複雜之功能。在此一情況中，該等閘等效於一可程式化閘陣列。對於一更可撓電路，群組最初可未連接，且互連之程式化遮罩可判定最終電路。三維程式化可用於允許跡線之交叉。可產生閘及其他邏輯電路之任意組合。一些群組可包含電晶體且其他群組可含有其他裝置，諸如二極體。類比電路亦可藉由使各種群組互連而形成。
歸因於裝置40在墨水中隨機但實質上均勻之分佈，相同面積之各群組將具有近似相同數目之裝置40。一群組中裝置40之數目之細微差異將不影響一邏輯電路之效能。在一實施例中，歸因於所需之低電流，在各群組中可存在大約10個相同裝置。單個群組(其表示一單個 電晶體)中之裝置40之成本為大約0.143美分。因此，所得電路板可製成相對廉價。
如圖11中所示，為了簡化可印刷為一有序二維陣列之群組之程式化，源於所有群組之導體層(圖4)之導電跡線85可終接在基板50之一補片區域86處，其中產品現為一可程式化電路板87。此等跡線85可為電路板87之「標準」設計之部分，其隨後接著經客製化用於一特定用途。此使得用於形成跡線85之印刷程序能夠經最佳化以連接至群組中之導體層且使程式化程序能夠經最佳化用於使端子88之末端互連。例如，程式化程序可在已製作電路板87之後之一時間執行且程式化步驟可由特殊設備在電腦控制下執行。此外，互連之圖案可比將電晶體端子電連接至補片區域86之跡線85複雜得多。
在圖11之實例中，補片區域86中之程式化形成圖10之AND閘。對於更複雜的電路，程式化跡線90可能需交叉且多個層可經形成以避免跡線之短路。
在另一實施例中，裝置40之群組最初可鄰近群組互連以形成單獨邏輯閘，諸如AND、NAND、NOR閘，且各閘之引線終接在補片區域86中用於隨後程式化以針對一特定客戶客製化基板。因此，通用電路形成一可程式化閘陣列。
複數個間隔之補片區域可被提供在電路板87上以簡化互連之佈線。在一實施例中，針對所有輸入信號之端子被提供在一補片區域中之一層級上且輸出端子被提供在另一層級上。
若互連之程式化係複雜的，則將互連直接印刷在基板50上之一X-Y平面中可能係不夠的。導體直接印刷在基板上係受限的，此係因為導體之間之一最小間隔係大約30微米以避免交叉橋接，且薄導體具有藉由表面張力破裂之傾向。
在不期望直接印刷導體線之情況中，首先在基板上形成一遮罩 層，接著如下般在遮罩層上方沈積導體墨水。
圖案化互連跡線或圖案化電路板87上之任意其他跡線或圖案化裝置40之群組之一途徑係形成疏水遮罩。遮罩可藉由印刷(例如，使用一經圖案化輥或網版印刷)而沈積或可藉由一光微影程序(若印刷無法達成所要精度)圖案化。一適當遮罩物質係浸透於一溶液中作為墨水之經徹底清潔之矽藻土粒子。以相對於所要配接線/裝置圖案為凹之一圖案印刷墨水。在固化後，所得膜經由一氟化程序活化，從而產生一超疏水表面(即，其不會被導體墨水或裝置墨水潤濕)。由膜暴露之基板之區域將適度親水或超親水(即，其會被導體墨水或裝置墨水潤濕)。
為形成跡線，一親水導電墨水經製備且沈積在疏水遮罩上方。暴露之基板區域將被墨水覆蓋，且已沈積在疏水遮罩表面上之導電墨水將堆積在暴露區域中。此產生導電墨水之更大截面積(針對良好導電性及機械強度)且防止交叉橋。
圖12係界定暴露基板之區域96之疏水遮罩94之一俯視圖。圖13係展示形成在區域96之一者中之一單個導體98之一截面圖。注意，導體98比遮罩94厚。導體98之高度係由沈積在遮罩上方之導電墨水量判定。對於界定基板之一大暴露區域之遮罩，需沈積更多導電墨水以確保暴露區域被墨水完全覆蓋。在跡線之終接區域處，諸如為了將跡線之末端連接至其他導體，一擴大之襯墊區域應經形成以緩解針對一後續印刷層之對準容限且改良所得電連接。
在固化導電墨水之後，隨後在相同遮罩上方沈積一介電墨水，其中介電墨水含有足夠的表面活性劑以覆蓋遮罩表面及導體且中和遮罩之疏水效應。額外遮罩及跡線層可經形成以產生互連之三維矩陣。垂直通孔可用於導體層之間之互連。
圖14圖解說明當產生群組72與74之間之互連以形成一AND閘時 在圖11之電路板87上方使用一疏水遮罩100。在另一實施例中，遮罩10僅用在補片區域86中用於程式化，且引至各種群組之跡線85在印刷群組之各種導體層時形成。
此一般遮罩程序亦可用於圖案化裝置40之群組及導體層。相同或不同裝置之群組可經堆疊以允許形成非常複雜的電路。
在已形成電路板87之標準特徵之後，可在捲軸式程序中對大量可撓性電路板87廉價地執行程式化程序。在最終程式化之後，電路板87可從輥單件化。如所見，未使用真空處理或危險材料以製作電路板87及對其程式化。
圖15圖解說明圖14中之電阻器R1及R2可如何藉由將電阻材料膠版印刷或網版印刷在基板上而形成，其中篩網上之一遮罩界定電阻材料之形狀。可使用其他沈積技術。電阻材料之形狀(長度、寬度、高度)可判定電阻或連接器102或103沿著其長度之位置可判定電阻。若連接器之位置判定電阻，則所有電阻器可相同地形成。電阻亦可藉由將電阻器串聯及/或並聯互連而選擇。
圖16圖解說明一電路板106之一仰視圖及一截面圖，其中已在基板108之兩側上印刷裝置之群組，諸如底部上之群組72及74及頂部上之其他群組110及112。跡線114及116使群組互連。通孔118將一側上之電路連接至另一側上之電路。在印刷互連層之前，通孔在基板108中打孔且填充有例如UV固化之孔填充導體。若形成鏡像，則此簡化互連設計，此係因為兩側上之補片區域可相同。
取代通孔，可使用環繞式連接器。
由於基板108可為一非常薄及可撓性膜(如一撓性電路)，故所得電路板106可經摺疊以減小其大小。由墨水形成之可撓性導體可購得。可在基板108上存在特殊區域，其等界定可摺疊電路板106而不損壞電路之位置。
為了改良電路板之使用之可靠性及靈活性，一「基底」電路板120(圖17)可經製作以具有特定基本特徵及連接端子。在電路板120已經測試及認可後，額外電路板122及124可電附接至基底電路板120以針對一特定應用客製化效能。
在圖17之實施例中，經測試及認可之電路板122及124具有施加至其表面之一黏著劑，其將黏著至基底電路板120。電路板122及124之端子126與基底電路板120上之端子對準。該等端子126塗佈有一導電黏著劑。電路板122及124隨後與基底電路板120對準且黏著至基底電路板120之表面。在一實施例中，電路板122及124之「裝置側」面向基底電路板120之裝置側。藉由單獨形成各種功能單元，測試期間各單元之通過率將更高且功能單元可以各種組合連接以增加更多功能可能性。
在一實施例中，電路板122/124在一捲軸式程序中形成且在測試之後，在最終站施加黏著劑。電路板122/124可具有在單件化期間切割之測試突片。在單件化之後，電路板122/124黏著至基底電路板120。作為一任意實例，一電路板122可為一A/D轉換器且另一電路板可為一D/A轉換器。
圖18圖解說明用於將電路板122安裝至基底電路板120之另一技術。在圖18中，在區域128處之電連接位置處對電路板122穿孔。隨後，使用一介電黏著劑塗佈電路板122之底側(非裝置側)，且將電路板122黏著至基底電路板120，因此穿孔係在基底電路板120上之連接端子上方。隨後，透過穿孔沈積一導電黏著劑130以將基底電路板120之端子連接至電路板122之頂部端子。例如，跡線132及134藉由導電黏著劑130連接。
此技術亦可結合圖16之雙側電路板使用。
使用裝置之大量冗餘陣列(例如，圖11中之裝置40)以及補片區域 86中之標準被動裝置(例如，圖11中之電阻器R1至R3)允許電路板具有非常高的通過率且產生隨後可經程式化以根據需要製成獨有裝置之可程式化電路板。
對於更高密度之裝置群組，可印刷群組之多個絕緣層以形成三維結構。垂直通孔可用於接達至各種層。裝置之群組可使用垂直對準之群組串聯連接。
圖19示意圖解說明用於藉由在一捲軸式程序中印刷而製造電路之一可能組裝線。輥136含有基板材料且輥138係一捲取輥。標記各種站。程序依序印刷各種層並固化層。膠版印刷較佳用於使用一捲軸式程序印刷。層之數目取決於所印刷之電路及裝置之複雜性。取決於一特定客戶需求，捲軸式程序可產生未經程式化之電路板且一單獨系統可用於最終程式化步驟。
如本文中使用之各種方向屬性(諸如，底部、頂部及垂直)不應解釋為傳達相對於地球表面之絕對方向而是用於傳達當圖表被垂直固持時相對於附圖之定向。在一實際實施例中，此等術語仍適用於產品，而不管產品相對於地球表面之絕對定向。
雖然已展示並描述本發明之特定實施例，但是熟習此項技術者應瞭解可進行改變及修改而不脫離本發明之較寬泛態樣，且因此隨附申請專利範圍將在其等之範疇內涵蓋落在本發明之真實精神及範疇內之所有此等改變及修改。
40‧‧‧三端裝置/裝置
50‧‧‧起始基板
72‧‧‧群組
74‧‧‧群組
85‧‧‧導電跡線/跡線
86‧‧‧補片區域
87‧‧‧可程式化電路板/電路板
88‧‧‧端子
90‧‧‧程式化跡線
R1‧‧‧電阻器
R2‧‧‧電阻器
R3‧‧‧電阻器

Claims (20)

  1. 一種電路，其包括：一基板；複數個預成形半導體電裝置之單獨群組，其等已被混合在一溶液中，沈積在該基板上方且固化，各群組含有並聯連接於各群組內之複數個實質上相同電裝置，該等電裝置隨機分佈在該基板上之各群組內；及一互連導體圖案，其將該等群組之至少一些群組互連在一起以達成一電功能。
  2. 如請求項1之電路，其中各群組具有從其相關聯群組延伸之至少一電連接器，其中各電連接器終接在一終接區域處，且其中該互連導體圖案包括在該等終接區域處電連接至該等群組之導體。
  3. 如請求項1之電路，其中該等裝置係藉由印刷而沈積。
  4. 如請求項1之電路，其中該等裝置具有小於200微米之一最大尺寸。
  5. 如請求項1之電路，其中該複數個單獨群組中之各群組含有實質上相同之第一裝置，其中該複數個單獨群組係第一複數個單獨群組，該電路進一步包括第二複數個單獨群組，其中具有該第二複數個之該等群組含有與該等第一裝置不同之第二裝置。
  6. 如請求項1之電路，其中該等裝置包括電晶體或二極體中之至少一者。
  7. 如請求項1之電路，其中該等裝置係三端裝置，其等具有一第一電極、一第二電極及一第三電極，其中該第一電極係該等裝置之一底部電極，該第三電極係該等裝置之一頂部電極，且該第 二電極係垂直定位在該頂部電極與該底部電極之間之一中間電極，該電路進一步包括：一第一導體層，其在該基板上方，其中該等裝置之該第一電極係電連接至該第一導體層；一第一介電層，其上覆於該第一導體層；一第二導體層，其上覆於該第一介電層以電接觸該第二電極；及一第二介電層，其在該第二導體層上方；及一第三導體層，其上覆於該第二介電層以電接觸該第三電極，其中該等裝置係藉由該第一導體層、該第二導體層及該第三導體層之一組合並聯電連接。
  8. 如請求項7之電路，其中該等裝置經形成以具有比該等裝置之一上部寬之一下部，該下部形成一架子，其中該第二電極係形成在該架子上。
  9. 如請求項7之電路，其中該第二電極自該等裝置上該第一電極與該第三電極之間之一中途點偏移。
  10. 如請求項7之電路，其中電信號耦合至該第一導體層、該第二導體層及該第三導體層以平行操作該等裝置。
  11. 如請求項1之電路，其中該基板具有一補片區域，其中各群組具有從其相關聯群組延伸且終接在該補片區域中之至少一電連接器，且其中該互連導體圖案包括在該補片區域處電連接至該等群組之導體。
  12. 如請求項1之電路，其中該互連導體圖案使該等群組互連以形成邏輯閘。
  13. 如請求項1之電路，其中該互連導體圖案使該等群組互連以執行 邏輯功能。
  14. 如請求項1之電路，其中該互連導體圖案使該等群組互連以產生類比電路。
  15. 如請求項1之電路，其中該基板係一第一基板，該電路進一步包括含有電子電路之至少一第二基板，其中該第二基板具有貼附至該第一基板之一表面之一表面，且其中該第一基板上之端子連接至該第二基板上之端子。
  16. 如請求項1之電路，其中該等群組以一二維陣列沈積。
  17. 一種用於形成一電路之方法，其包括：提供一墨水，其含有混合在一溶劑中之複數個預成形半導體電裝置，該等裝置之各者具有至少一第一電極及一第二電極；在一基板上印刷該墨水，以形成該等預成形半導體電裝置之複數個單獨群組，各群組含有隨機分佈在該基板上之各群組內之複數個實質相同上電裝置；形成至少一導體層，以使各群組中之該等電裝置並聯連接；及使用一互連圖案使該等群組之至少一些群組互連以達成一電功能。
  18. 如請求項17之方法，其中該等電裝置之各者包含三個電極。
  19. 如請求項17之方法，其中該等電裝置包含電晶體或二極體中之至少一者。
  20. 如請求項17之方法，其中使該等群組之至少一些群組互連之該步驟包括使該等群組之至少一些群組互連以形成邏輯閘。
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