TW201447988A - Semiconductor process - Google Patents
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- TW201447988A TW201447988A TW102120395A TW102120395A TW201447988A TW 201447988 A TW201447988 A TW 201447988A TW 102120395 A TW102120395 A TW 102120395A TW 102120395 A TW102120395 A TW 102120395A TW 201447988 A TW201447988 A TW 201447988A
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Abstract
Description
本發明係關於一種半導體製程，且特別係關於一種在磊晶層上形成保護層的半導體製程。 The present invention relates to a semiconductor process, and more particularly to a semiconductor process for forming a protective layer on an epitaxial layer.
隨著半導體製程進入到深次微米時代，例如65奈米(nm)以下之製程，對於MOS電晶體元件的驅動電流(drive current)的提昇已顯得日益重要。為了改善元件的效能，目前業界已發展出所謂的「應變矽(strained-silicon)技術」，其原理主要是使閘極通道部分的矽晶格產生應變，使電荷在通過此應變之閘極通道時的移動力增加，進而達到使MOS電晶體運作更快的目的。在目前已知的技術中，已有使用應變矽(strained silicon)作為基底的MOS電晶體，其利用矽鍺(SiGe)或矽碳(SiC)的晶格常數與單晶矽(single crystal Si)不同的特性，使矽鍺磊晶層或矽碳磊晶層產生結構上應變而形成應變矽。由於矽鍺磊晶層或矽碳磊晶層的晶格常數(lattice constant)比矽大或小，這使得矽的帶結構(band structure)發生改變，而造成載子移動性增加，因此可增加MOS電晶體的速度。 As semiconductor processes enter the deep submicron era, such as processes below 65 nanometers (nm), the drive current of MOS transistor components has become increasingly important. In order to improve the performance of components, the so-called "strained-silicon technology" has been developed in the industry. The principle is mainly to strain the germanium lattice of the gate channel portion, so that the charge passes through the strain gate channel. The movement force at the time increases, thereby achieving the purpose of making the MOS transistor operate faster. Among the currently known techniques, MOS transistors using strained silicon as a substrate have been used which utilize the lattice constant of bismuth (SiGe) or bismuth carbon (SiC) and single crystal Si (single crystal Si). Different characteristics cause the epitaxial layer or the tantalum carbon epitaxial layer to be structurally strained to form strain enthalpy. Since the lattice constant of the germanium epitaxial layer or the germanium carbon epitaxial layer is larger or smaller than that of the germanium, this causes a change in the band structure of the germanium, which causes an increase in carrier mobility, and thus can be increased. The speed of the MOS transistor.
然而，當磊晶層應用於MOS電晶體時，如何整合磊晶製程以及其他例如形成源/汲極等半導體製程，以防止磊晶層因其他製程而劣化，即成為一重要課題。 However, when the epitaxial layer is applied to a MOS transistor, how to integrate the epitaxial process and other semiconductor processes such as forming a source/drain to prevent the epitaxial layer from deteriorating due to other processes becomes an important issue.
本發明提出一種半導體製程，其形成保護層於磊晶層上， 俾使其他例如形成源/汲極等半導體製程，不會污染或消耗磊晶層。 The invention provides a semiconductor process for forming a protective layer on an epitaxial layer, Other semiconductor processes, such as source/drain formation, do not contaminate or consume the epitaxial layer.
本發明提供一種半導體製程，包含有下述步驟。首先，形成一第一閘極以及一第二閘極於一基底上。接著，形成一第一間隙壁材料順應覆蓋第一閘極以及第二閘極。接續，蝕刻覆蓋第一閘極的第一間隙壁材料，以形成一第一間隙壁於第一閘極側邊的基底上，但保留覆蓋第二閘極的第一間隙壁材料。接續，形成一第一磊晶層於第一間隙壁側邊的基底中。續之，形成一第二間隙壁材料覆蓋第一閘極以及位於第一閘極側邊的基底。繼之，蝕刻覆蓋第二閘極的第一間隙壁材料，以形成一第二間隙壁。其後，形成一第二磊晶層於第二間隙壁側邊的基底中。之後，移除第二間隙壁材料。而後，形成一雙材料層覆蓋第一閘極、第二閘極以及基底，其中雙材料層具有一底層以及一頂層。然後，蝕刻頂層但保留第一磊晶層以及第二磊晶層上的底層，以形成一第三間隙壁。 The present invention provides a semiconductor process comprising the steps described below. First, a first gate and a second gate are formed on a substrate. Next, a first spacer material is formed to cover the first gate and the second gate. Subsequently, the first spacer material covering the first gate is etched to form a first spacer on the substrate of the first gate side, but the first spacer material covering the second gate is left. Subsequently, a first epitaxial layer is formed in the substrate on the side of the first spacer. Further, a second spacer material is formed to cover the first gate and the substrate on the side of the first gate. Next, the first spacer material covering the second gate is etched to form a second spacer. Thereafter, a second epitaxial layer is formed in the substrate on the side of the second spacer. Thereafter, the second spacer material is removed. Then, a double material layer is formed to cover the first gate, the second gate and the substrate, wherein the double material layer has a bottom layer and a top layer. Then, the top layer is etched but the first epitaxial layer and the bottom layer on the second epitaxial layer are left to form a third spacer.
基於上述，本發明提出一種半導體製程，其係依序為覆蓋一第一間隙壁材料；蝕刻部分第一間隙壁材料，以形成一第一間隙壁以及一第一磊晶層於第一閘極側邊；然後全面覆蓋一第二間隙壁材料，再移除覆蓋第二閘極的第二間隙壁材料並蝕刻下方的第一間隙壁材料，以形成一第二間隙壁並再形成一第二磊晶層於第二閘極側邊；完全移除第二間隙壁材料；全面覆蓋一雙材料層，蝕刻一頂層以形成一第三間隙壁，並保留一底層於第一磊晶層以及第二磊晶層上。如此一來，由於本發明採用形成第一磊晶層以後隨即覆蓋第二間隙壁材料於其上的方法，故在蝕刻第二間隙壁並形成第二磊晶層時，不會污染或損傷第一磊晶層。再者，本發明形成底層於第一磊晶層以及第二磊晶層上以作為保護層，故當蝕刻頂層以形成第三 間隙壁時，後續移除第三間隙壁時，或者進行其他製程時，不會污染或損傷第一磊晶層以及第二磊晶層，因此可提升第一磊晶層以及第二磊晶層的效能。 Based on the above, the present invention provides a semiconductor process for sequentially covering a first spacer material; etching a portion of the first spacer material to form a first spacer and a first epitaxial layer at the first gate a side spacer; then completely covering a second spacer material, removing the second spacer material covering the second gate and etching the underlying first spacer material to form a second spacer and forming a second The epitaxial layer is on the side of the second gate; the second spacer material is completely removed; a double material layer is completely covered, a top layer is etched to form a third spacer, and a bottom layer is retained on the first epitaxial layer and On the second epitaxial layer. In this way, since the present invention adopts a method of forming a first epitaxial layer and then covering the second spacer material thereon, when the second spacer is etched and the second epitaxial layer is formed, no pollution or damage is caused. An epitaxial layer. Furthermore, the present invention forms an underlayer on the first epitaxial layer and the second epitaxial layer as a protective layer, so when etching the top layer to form a third When the spacer is removed, when the third spacer is subsequently removed, or when other processes are performed, the first epitaxial layer and the second epitaxial layer are not contaminated or damaged, thereby improving the first epitaxial layer and the second epitaxial layer Performance.
10‧‧‧絕緣結構 10‧‧‧Insulation structure
110‧‧‧基底 110‧‧‧Base
112‧‧‧鰭狀結構 112‧‧‧Fin structure
120’、120’b‧‧‧第一間隙壁材料 120’, 120’b‧‧‧ first spacer material
120a‧‧‧第一間隙壁 120a‧‧‧First gap
120b‧‧‧第二間隙壁 120b‧‧‧Second gap
122‧‧‧閘極介電層 122‧‧‧ gate dielectric layer
124‧‧‧犧牲電極層 124‧‧‧Sacrificial electrode layer
126‧‧‧蓋層 126‧‧‧ cover
126a、160a‧‧‧底層 126a, 160a‧‧‧ bottom
126b、160b‧‧‧頂層 126b, 160b‧‧‧ top
130‧‧‧第一磊晶層 130‧‧‧First epitaxial layer
140’、140’a‧‧‧第二間隙壁材料 140’, 140’a‧‧‧ second spacer material
150‧‧‧第二磊晶層 150‧‧‧Second epilayer
160‧‧‧雙材料層 160‧‧‧Double material layer
160b’‧‧‧第三間隙壁 160b’‧‧‧ third gap
G1‧‧‧第一閘極 G1‧‧‧ first gate
G2‧‧‧第二閘極 G2‧‧‧second gate
R‧‧‧凹槽 R‧‧‧ groove
第1-8圖係繪示本發明一實施例之半導體製程之剖面示意圖。 1-8 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.
第1-8圖係繪示本發明一實施例之半導體製程之剖面示意圖。本發明可應用於平面或非平面之場效電晶體，因此本實施例係以一三閘極場效電晶體為例，但本發明不以此為限。再者，以下所對應之各部位的個數，例如閘極、凹槽以及磊晶層等的個數係僅為便於清晰描述而繪示，但本發明之各部位的個數非限於此，可視實際需要調整，其中為方便描述，文中僅以圖示中的二閘極加以說明。 1-8 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. The present invention can be applied to a planar or non-planar field effect transistor. Therefore, the present embodiment is exemplified by a three-gate field effect transistor, but the invention is not limited thereto. In addition, the number of parts corresponding to the following, such as the number of gates, grooves, and epitaxial layers, is only for convenience of description, but the number of parts of the present invention is not limited thereto. It can be adjusted according to actual needs. For the convenience of description, only the two gates in the figure are explained.
如第1圖所示，首先，提供一基底110。基底110例如是一矽基底、一含矽基底、一三五族覆矽基底(例如GaN-on-silicon)、一石墨烯覆矽基底(graphene-on-silicon)或一矽覆絕緣(silicon-on-insulator，SOI)基底等半導體基底。基底110包含複數個鰭狀結構112。詳細而言，形成鰭狀結構112的方法可如下所述，但不以此為限。例如，提供一塊狀底材(未繪示)，在其上形成硬遮罩層(未繪示)，並將其圖案化以定義出其下之塊狀底材中欲對應形成之鰭狀結構112的位置。接著，進行一蝕刻製程，於塊狀底材(未繪示)中形成鰭狀結構112。如此，完成鰭狀結構112於基底110中之製作。在本實施例中，形成鰭狀結構112後即移除硬遮罩層(未繪示)，故可於後續製程中形成三閘極場效電晶體(tri-gate MOSFET)。如此一來，由於鰭狀結構112與後續形成之介電層之間具有三直接接觸面(包含二接觸側面及一接觸頂面)，因此被稱作三閘極場效電晶體(tri-gate MOSFET)。相較於平面場效電晶體，三閘極場效電晶體可藉由將上述三直接接觸面作為載子流通之通道，而在同樣的閘極長度下具有較寬的載子通道寬度，俾使在相同之驅動電壓下可獲得加倍的汲極驅動電流。而在另一實施例中，亦可保留硬遮罩層(未繪示)，而於後續製程中形成另一具有鰭狀結構之多閘極場效電晶體(multi-gate MOSFET)-鰭式場效電晶體(fin field effect transistor,Fin FET)。鰭式場效電晶體中，由於保留了硬遮罩層(未繪示)，鰭狀結構112與後續將形成之介電層之間僅有兩接觸側面。 As shown in Fig. 1, first, a substrate 110 is provided. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate. Substrate 110 includes a plurality of fin structures 112. In detail, the method of forming the fin structure 112 can be as follows, but is not limited thereto. For example, a piece of substrate (not shown) is provided, a hard mask layer (not shown) is formed thereon, and patterned to define a fin shape to be formed correspondingly in the underlying substrate. The location of structure 112. Next, an etching process is performed to form the fin structure 112 in a bulk substrate (not shown). As such, the fabrication of the fin structure 112 in the substrate 110 is completed. In this embodiment, after forming the fin structure 112, the hard mask layer (not shown) is removed, so that a three-gate field effect transistor (tri-gate) can be formed in the subsequent process. MOSFET). As a result, since the fin structure 112 has three direct contact faces (including two contact sides and a contact top surface) between the subsequently formed dielectric layers, it is called a tri-gate field effect transistor (tri-gate). MOSFET). Compared with the planar field effect transistor, the three-gate field effect transistor can have a wider carrier channel width under the same gate length by using the above three direct contact surfaces as a channel through which the carrier flows. Double the drain drive current at the same drive voltage. In another embodiment, a hard mask layer (not shown) may be left, and another multi-gate MOSFET-fin field having a fin structure is formed in a subsequent process. Fin field effect transistor (Fin FET). In a fin field effect transistor, since a hard mask layer (not shown) is left, there are only two contact sides between the fin structure 112 and a dielectric layer to be formed later.
接著，形成一絕緣結構10於(鰭狀結構112之間的)基底110上，以電性絕緣各電晶體。絕緣結構10例如為一淺溝隔離(shallow trench isolation,STI)結構，其例如以一淺溝隔離製程形成，詳細形成方法為本領域所熟知故不再贅述，但本發明不以此為限。 Next, an insulating structure 10 is formed on the substrate 110 (between the fin structures 112) to electrically insulate the respective transistors. The insulating structure 10 is, for example, a shallow trench isolation (STI) structure, which is formed, for example, by a shallow trench isolation process. The detailed formation method is well known in the art and will not be described again, but the invention is not limited thereto.
接續，由下而上依序形成一閘極介電層(未繪示)、一犧牲電極層(未繪示)以及一蓋層(未繪示)覆蓋基底110以及鰭狀結構112；隨之，將蓋層(未繪示)、犧牲電極層(未繪示)以及閘極介電層(未繪示)圖案化，以形成一閘極介電層122、一犧牲電極層124以及一蓋層126於基底110以及鰭狀結構112上。此時則由閘極介電層122、犧牲電極層124以及蓋層126，分別形成一第一閘極G1以及一第二閘極G2位於基底110上(並朝紙面方向跨設鰭狀結構112)。在本實施例中，第一閘極G1為用以形成一PMOS電晶體的一閘極，而第二閘極G2為用以形成一NMOS電晶體的一閘極，但本發明不以此為限。 Connecting, sequentially forming a gate dielectric layer (not shown), a sacrificial electrode layer (not shown), and a cap layer (not shown) covering the substrate 110 and the fin structure 112; a cap layer (not shown), a sacrificial electrode layer (not shown), and a gate dielectric layer (not shown) are patterned to form a gate dielectric layer 122, a sacrificial electrode layer 124, and a cap Layer 126 is on substrate 110 and fin structure 112. At this time, a first gate G1 and a second gate G2 are respectively formed on the substrate 110 by the gate dielectric layer 122, the sacrificial electrode layer 124, and the cap layer 126 (and the fin structure 112 is spanned toward the paper surface). ). In this embodiment, the first gate G1 is a gate for forming a PMOS transistor, and the second gate G2 is a gate for forming an NMOS transistor, but the present invention does not limit.
本實施例係以一後置高介電常數後閘極(Gate-Last for High-K Last)製程為例時，故閘極介電層122將於後續製程中被移除，再另外填入高介電常數閘極介電層，故此實施態樣下之閘極介電層122可僅為一般方便於後續製程中移除之犧牲材料，例如為一氧化層。犧牲電極層124可例如由多晶矽所形成，但本發明不以此為限。蓋層126則可為氮化層或氧化層等所組成之單層或多層結構，作為一圖案化的硬遮罩。在本實施例中，蓋層126由下而上可包含一底層126a以及一頂層126b，且底層126a例如為一氧化層，而頂層126b可例如為一氮化層，但本發明不以此為限。 In this embodiment, a Gate-Last for High-K Last process is taken as an example, so the gate dielectric layer 122 will be removed in the subsequent process, and then filled in separately. The high dielectric constant gate dielectric layer, so the gate dielectric layer 122 in this embodiment can be only a sacrificial material that is generally convenient for removal in subsequent processes, such as an oxide layer. The sacrificial electrode layer 124 may be formed, for example, of polysilicon, but the invention is not limited thereto. The cap layer 126 may be a single layer or a multilayer structure composed of a nitride layer or an oxide layer or the like as a patterned hard mask. In this embodiment, the cap layer 126 may include a bottom layer 126a and a top layer 126b from bottom to top, and the bottom layer 126a is, for example, an oxide layer, and the top layer 126b may be, for example, a nitride layer, but the present invention does not limit.
在其他本實施例中，本發明亦可應用於一前置高介電常數後閘極(Gate-Last for High-K First)製程，因此本實施例之閘極介電層122為一高介電常數閘極介電層，其可選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鑭(lanthanum oxide，La2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化釔(yttrium oxide，Y2O3)、氧化鋯(zirconium oxide，ZrO2)、鈦酸鍶(strontium titanate oxide，SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4)、鋯酸鉿(hafnium zirconium oxide，HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)與鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)所組成之群組，但本發明不以此為限。另外，可形成一阻障層(未繪示)於閘極介電層122上，用以於移除犧牲電極層124時當作蝕刻停止層來保護閘極介電層122，並可防止後續位於其上之金屬成分向下擴散污染閘極介電層122。阻障層(未繪示)例如為氮化鉭(tantalum nitride，TaN)、氮化鈦(titanium nitride，TiN)等之單層結構或複合層結構。 In other embodiments, the present invention can also be applied to a Gate-Last for High-K First process. Therefore, the gate dielectric layer 122 of the present embodiment is a high dielectric. An electric constant gate dielectric layer, which may be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), and aluminum oxide. (aluminum oxide, Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide , SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate Titanate, PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST) are grouped, but the invention is not limited thereto. In addition, a barrier layer (not shown) may be formed on the gate dielectric layer 122 to protect the gate dielectric layer 122 as an etch stop layer when the sacrificial electrode layer 124 is removed, and may prevent subsequent The metal component located thereon diffuses downward to contaminate the gate dielectric layer 122. The barrier layer (not shown) is, for example, tantalum nitride (TaN), titanium nitride (titanium) A single layer structure or a composite layer structure of nitride, TiN) or the like.
續之，請繼續參閱第1圖，形成一第一間隙壁材料120’順應覆蓋第一閘極G1以及第二閘極G2。在本實施例中，第一間隙壁材料120’為一氮化層，但本發明不以此為限。 Further, referring to FIG. 1, a first spacer material 120' is formed to cover the first gate G1 and the second gate G2. In the present embodiment, the first spacer material 120' is a nitride layer, but the invention is not limited thereto.
續之，蝕刻覆蓋第一閘極G1的第一間隙壁材料120’，以形成一第一間隙壁120a於第一閘極G1側邊的基底110上，但保留覆蓋第二閘極G2的第一間隙壁材料120’b，如第2圖所示。詳細而言，可進行微影暨蝕刻製程，例如先以一圖案化光祖(未繪示)覆蓋第二閘極G2以及其側邊的基底110，然後蝕刻暴露出第一閘極G1上的第一間隙壁材料120’，如此則可一方面形成第一間隙壁120a的同時，保留覆蓋第二閘極G2的第一間隙壁材料120’b。在本實施例中，係以乾蝕刻製程蝕刻第一間隙壁材料120’，但本發明不以此為限。在其他實施例中，可以乾蝕刻製程或/及濕蝕刻製程蝕刻第一間隙壁材料120’。 Then, the first spacer material 120' covering the first gate G1 is etched to form a first spacer 120a on the substrate 110 on the side of the first gate G1, but the second gate G2 is covered. A spacer material 120'b is shown in FIG. In detail, a lithography and etching process may be performed. For example, the second gate G2 and the substrate 110 on the side thereof are covered by a patterned photo-precursor (not shown), and then etched to expose the first gate G1. The first spacer material 120' can thus retain the first spacer material 120'b covering the second gate G2 while forming the first spacer 120a. In the present embodiment, the first spacer material 120' is etched by a dry etching process, but the invention is not limited thereto. In other embodiments, the first spacer material 120' may be etched by a dry etch process or/and a wet etch process.
再者，本實施例在形成第一間隙壁120a的同時，更進一步向下蝕刻而於第一閘極G1側邊的基底110中形成二凹槽R。凹槽R為選擇性形成，因而在其他實施例中，亦可不形成凹槽R。在一實施例中，可以相同製程形成第一間隙壁120a與形成凹槽R；但在其他實施例中，第一間隙壁120a與凹槽R可以不同製程分別形成。或者，可先以乾蝕刻製程形成第一間隙壁120a以及蝕刻出凹槽R的深度，然後再進行濕蝕刻製程以蝕刻形成所需之凹槽R的形狀等，但本發明不以此為限。 Furthermore, in the present embodiment, while the first spacer 120a is formed, the second recess R is formed further in the substrate 110 on the side of the first gate G1. The groove R is selectively formed, and thus in other embodiments, the groove R may not be formed. In an embodiment, the first spacers 120a and the recesses R may be formed in the same process; however, in other embodiments, the first spacers 120a and the recesses R may be formed separately by different processes. Alternatively, the first spacer 120a may be formed by a dry etching process and the depth of the recess R may be etched, and then a wet etching process may be performed to etch the shape of the desired recess R, etc., but the invention is not limited thereto. .
如第3圖所示，形成一第一磊晶層130於第一間隙壁120a側邊的基底110中。在本實施例中，因已先形成凹槽R於第一間隙壁120a側邊的基底110中，故直接將第一磊晶層130成長於凹槽R 中，但本發明不以此為限。在其他實施例中，可不形成凹槽R，而直接將第一磊晶層130形成於基底110中。再者，在本實施例中第一閘極G1為一PMOS電晶體的閘極，故第一磊晶層130係為適用於PMOS電晶體的磊晶層，例如第一磊晶層130為一矽鍺磊晶層，但本發明不以此為限。 As shown in FIG. 3, a first epitaxial layer 130 is formed in the substrate 110 on the side of the first spacer 120a. In this embodiment, since the recess R is formed in the base 110 on the side of the first spacer 120a, the first epitaxial layer 130 is directly grown in the recess R. However, the invention is not limited thereto. In other embodiments, the first epitaxial layer 130 may be formed directly in the substrate 110 without forming the recess R. Furthermore, in the present embodiment, the first gate G1 is a gate of a PMOS transistor, so the first epitaxial layer 130 is an epitaxial layer suitable for a PMOS transistor, for example, the first epitaxial layer 130 is矽锗 晶 layer, but the invention is not limited thereto.
如第4-5圖所示，形成一第二間隙壁材料140’a覆蓋第一閘極G1以及位於第一閘極G1側邊的基底110，並蝕刻覆蓋第二閘極G2的第一間隙壁材料120’b，以形成一第二間隙壁120b。詳細而言，如第4圖所示，全面覆蓋一第二間隙壁材料140’於第一閘極G1、第二閘極G2以及基底110，意即全面覆蓋第二間隙壁材料140’於第一間隙壁120a以及覆蓋第二閘極G2的第一間隙壁材料120’b。如第5圖所示，可例如以微影暨蝕刻的方法，移除覆蓋第二閘極G2的第二間隙壁材料140’，並進一步蝕刻覆蓋第二閘極G2的第一間隙壁材料120’b，以形成第二間隙壁120b。 As shown in FIGS. 4-5, a second spacer material 140'a is formed to cover the first gate G1 and the substrate 110 on the side of the first gate G1, and etch the first gap covering the second gate G2. The wall material 120'b forms a second spacer 120b. In detail, as shown in FIG. 4, a second spacer material 140' is completely covered on the first gate G1, the second gate G2, and the substrate 110, that is, the second spacer material 140' is completely covered. A spacer wall 120a and a first spacer material 120'b covering the second gate G2. As shown in FIG. 5, the second spacer material 140' covering the second gate G2 may be removed, for example, by lithography and etching, and the first spacer material 120 covering the second gate G2 may be further etched. 'b to form the second spacer 120b.
在本實施例中，可先以例如一微縮(trimming)製程移除覆蓋第二閘極G2的第二間隙壁材料140’，其中微縮製程可例如為一濕蝕刻製程，且在本實施例中可搭配第二間隙壁材料140’為氮化間隙壁材料，而以含磷酸的蝕刻液進行蝕刻，但本發明不以此為限；接著，例如先以一圖案化光阻(未繪示)覆蓋第一閘極G1以及其側邊的基底110，然後蝕刻暴露出的第二閘極G2上的第一間隙壁材料120’b，之後以一蝕刻製程，蝕刻覆蓋第二閘極G2的第一間隙壁材料120’b，以形成第二間隙壁120b，其中蝕刻製程較佳為一乾蝕刻製程，以形成具有陡峭側壁的第二間隙壁120b，但本發明不以此為限。因此，第二間隙壁120b係僅含第一間隙壁材料120’，且在一較佳的實施態樣中，第二間隙壁120b與前製程中之第一間隙壁120a具有相同的厚度，俾使第一閘極G1以及第二閘極G2具有相 似之結構，而能提升後續同時進行於此二閘極結構的製程的均勻度。再者，由於本發明係先以第二間隙壁材料140’覆蓋第一閘極G1，才蝕刻形成第二間隙壁120b，故不會在蝕刻時損傷位於第二間隙壁材料140’下方的第一磊晶層130。而且蝕刻各凹槽R時，第一間隙壁120a以及第二間隙壁120b都僅包含第一間隙壁材料120’。 In this embodiment, the second spacer material 140 ′ covering the second gate G 2 may be removed by, for example, a trimming process, wherein the miniaturization process may be, for example, a wet etching process, and in this embodiment. The second spacer material 140 ′ can be used as the nitride spacer material, and is etched with a phosphoric acid-containing etching solution, but the invention is not limited thereto; then, for example, a patterned photoresist (not shown) is used first. Covering the first gate G1 and the substrate 110 on the side thereof, and then etching the exposed first spacer material 120'b on the exposed second gate G2, and then etching the second gate G2 by an etching process A spacer material 120'b is formed to form the second spacer 120b, wherein the etching process is preferably a dry etching process to form the second spacer 120b having steep sidewalls, but the invention is not limited thereto. Therefore, the second spacer 120b only contains the first spacer material 120', and in a preferred embodiment, the second spacer 120b has the same thickness as the first spacer 120a in the front process, Making the first gate G1 and the second gate G2 have phases Similar to the structure, it can improve the uniformity of the subsequent process of the two gate structures. Moreover, since the second spacer G1 is formed by etching the first gate G1 with the second spacer material 140', the second spacer 120b is etched, so that the second spacer material 140' is not damaged during etching. An epitaxial layer 130. Further, when each groove R is etched, both the first spacer 120a and the second spacer 120b contain only the first spacer material 120'.
再者，在本實施例中，形成第二間隙壁120b之後，更選擇性進一步形成二凹槽R於第二間隙壁120b側邊的基底110中。在本實施例中，第二間隙壁120b與凹槽R可以同一製程形成。在其他實施例中，第二間隙壁120b與凹槽R可以不同製程分別形成。或者，可先以乾蝕刻製程形成第二間隙壁120b以及蝕刻出凹槽R的深度，然後再進行濕蝕刻製程以蝕刻形成所需之凹槽R的形狀等，但本發明不以此為限。 Furthermore, in the present embodiment, after the second spacer 120b is formed, the two recesses R are further selectively formed in the substrate 110 on the side of the second spacer 120b. In this embodiment, the second spacer 120b and the recess R can be formed in the same process. In other embodiments, the second spacer 120b and the recess R may be formed separately by different processes. Alternatively, the second spacer 120b may be formed by a dry etching process and the depth of the recess R may be etched, and then a wet etching process may be performed to etch the shape of the desired recess R, etc., but the invention is not limited thereto. .
接續，形成一第二磊晶層150於第二間隙壁120b側邊的基底110中，隨後即可完全移除第二間隙壁材料140’a，如第6圖所示。由於第二閘極G2係為一NMOS電晶體的一閘極，故第二磊晶層150則為適用於NMOS電晶體的磊晶層，本實施例之第二磊晶層150則為一矽磷磊晶層，但本發明不以此為限。再者，移除第二間隙壁材料140’a的方法，可例如以一微縮(trimming)製程移除。微縮製程可例如為一濕蝕刻製程，但本發明不以此為限。 Subsequently, a second epitaxial layer 150 is formed in the substrate 110 on the side of the second spacer 120b, and then the second spacer material 140'a is completely removed, as shown in FIG. Since the second gate G2 is a gate of an NMOS transistor, the second epitaxial layer 150 is an epitaxial layer suitable for the NMOS transistor, and the second epitaxial layer 150 of the embodiment is a stack. Phosphorus epitaxial layer, but the invention is not limited thereto. Further, the method of removing the second spacer material 140'a can be removed, for example, by a trimming process. The microfabrication process can be, for example, a wet etching process, but the invention is not limited thereto.
在一較佳的實施例中，第一間隙壁材料120’的蝕刻率低於第二間隙壁材料140’的蝕刻率，俾能分別移除第一間隙壁材料120’以及第二間隙壁材料140’，特別是當移除第二間隙壁材料140’時減少消耗第一間隙壁材料120’。在本實施例中，第一間隙壁材料120’以及第二間隙壁材料140’皆為氮化間隙壁材料，但二者之製程參數不同而使結構密度等不同，而較佳為第一間隙壁材料120’對於 磷酸的蝕刻率低於第二間隙壁材料140’對於磷酸的蝕刻率，因此可易於分別對於第二間隙壁材料140’以及第一間隙壁材料120’進行移除或蝕刻，但本發明不以此為限。 In a preferred embodiment, the first spacer material 120' has an etch rate lower than that of the second spacer material 140', and the first spacer material 120' and the second spacer material are removed, respectively. 140', in particular when the second spacer material 140' is removed, the first spacer material 120' is consumed. In this embodiment, the first spacer material 120' and the second spacer material 140' are both nitrided spacer materials, but the process parameters of the two are different, and the structure density is different, and the first gap is preferred. Wall material 120' for The etching rate of phosphoric acid is lower than the etching rate of the second spacer material 140' for phosphoric acid, so that the second spacer material 140' and the first spacer material 120' can be easily removed or etched separately, but the present invention does not This is limited.
如第7圖所示，形成一雙材料層160全面覆蓋第一閘極G1、第二閘極G2以及基底110，意即覆蓋第一閘極G1、第二閘極G2、基底110、第一間隙壁120a以及第二間隙壁120b，其中雙材料層160具有一底層160a以及一頂層160b。接著，如第8圖所示，蝕刻頂層160b，以形成一第三間隙壁160b’，但保留第一磊晶層130以及第二磊晶層150上的底層160a。在一較佳的實施例中，底層160a則作為蝕刻頂層160b的一蝕刻停止層，因此底層160a對於形成第三間隙壁160b’的蝕刻製程的蝕刻率低於頂層160b的蝕刻率。在一實施例中，底層160a為一氧化層，而頂層160b則為一氮化層，但本發明不以此為限。接續，在形成第三間隙壁160b’之後，則可以第三間隙壁160b’自動對準形成一源/汲極(未繪示)分別於第一閘極G1與第二閘極G2側邊的基底110中。在此強調，由於底層160a覆蓋第一磊晶層130以及第二磊晶層150，是以當蝕刻形成第三間隙壁160b’時，後續為移除第三間隙壁160b’時，甚至後續進行其他蝕刻製程時，可避免損耗或污染第一磊晶層130以及第二磊晶層150，進而能提升第一磊晶層130以及第二磊晶層150的效能。 As shown in FIG. 7, a double material layer 160 is formed to cover the first gate G1, the second gate G2, and the substrate 110, that is, to cover the first gate G1, the second gate G2, the substrate 110, and the first The spacer 120a and the second spacer 120b, wherein the dual material layer 160 has a bottom layer 160a and a top layer 160b. Next, as shown in Fig. 8, the top layer 160b is etched to form a third spacer 160b', but the first epitaxial layer 130 and the underlayer 160a on the second epitaxial layer 150 are retained. In a preferred embodiment, the bottom layer 160a serves as an etch stop for the etched top layer 160b, so that the etch rate of the underlayer 160a for the etch process that forms the third spacer 160b' is lower than the etch rate of the top layer 160b. In one embodiment, the bottom layer 160a is an oxide layer, and the top layer 160b is a nitride layer, but the invention is not limited thereto. Then, after the third spacer 160b' is formed, the third spacer 160b' can be automatically aligned to form a source/drain (not shown) on the sides of the first gate G1 and the second gate G2, respectively. In the substrate 110. It is emphasized here that since the bottom layer 160a covers the first epitaxial layer 130 and the second epitaxial layer 150, when the third spacer 160b is formed by etching, the subsequent removal of the third spacer 160b' is performed even afterwards. In other etching processes, loss or contamination of the first epitaxial layer 130 and the second epitaxial layer 150 can be avoided, thereby improving the performance of the first epitaxial layer 130 and the second epitaxial layer 150.
綜上所述，本發明提出一種半導體製程，其係依序為覆蓋一第一間隙壁材料；蝕刻部分第一間隙壁材料，以形成一第一間隙壁以及一第一磊晶層於第一閘極側邊；然後全面覆蓋一第二間隙壁材料，再移除覆蓋第二閘極的第二間隙壁材料並蝕刻下方的第一間隙壁材料，以形成一第二間隙壁並再形成一第二磊晶層於第二閘極側邊；完全移除第二間隙壁材料；全面覆蓋一雙材料層，蝕刻一頂 層以形成一第三間隙壁，並保留一底層於第一磊晶層以及第二磊晶層上。如此一來，由於本發明採用形成第一磊晶層以後隨即覆蓋第二間隙壁材料於其上的方法，故在蝕刻第二間隙壁並形成第二磊晶層時，不會污染或損傷第一磊晶層。再者，本發明以將第一間隙壁材料分別形成第一間隙壁以及第二間隙壁的方法，可使第一閘極以及第二閘極側邊的間隙壁具有相同之材質，甚至相同之厚度，俾可提升後續同時進行於第一閘極以及第二閘極上的製程的均勻度。另外，本發明形成底層於第一磊晶層以及第二磊晶層上以作為保護層，故當蝕刻頂層以形成一第三間隙壁時，後續移除第三間隙壁時，或者進行其他製程時，不會污染或損傷第一磊晶層以及第二磊晶層，故可提升第一磊晶層以及第二磊晶層的效能。 In summary, the present invention provides a semiconductor process for sequentially covering a first spacer material; etching a portion of the first spacer material to form a first spacer and a first epitaxial layer. a gate side; then completely covering a second spacer material, removing the second spacer material covering the second gate and etching the underlying first spacer material to form a second spacer and forming a second spacer The second epitaxial layer is on the side of the second gate; the second spacer material is completely removed; a double layer of material is completely covered, and a top is etched The layer forms a third spacer and retains a bottom layer on the first epitaxial layer and the second epitaxial layer. In this way, since the present invention adopts a method of forming a first epitaxial layer and then covering the second spacer material thereon, when the second spacer is etched and the second epitaxial layer is formed, no pollution or damage is caused. An epitaxial layer. Furthermore, in the method of forming the first spacer wall and the second spacer respectively, the spacers of the first gate and the second gate have the same material, or even the same. The thickness, 俾, can improve the uniformity of the subsequent processes performed simultaneously on the first gate and the second gate. In addition, the present invention forms a bottom layer on the first epitaxial layer and the second epitaxial layer as a protective layer, so when the top layer is etched to form a third spacer, when the third spacer is subsequently removed, or other processes are performed When the first epitaxial layer and the second epitaxial layer are not contaminated or damaged, the performance of the first epitaxial layer and the second epitaxial layer can be improved.
再者，本發明之第一間隙壁材料低於第二間隙壁材料的蝕刻率，俾能分別移除第一間隙壁材料以及第二間隙壁材料，特別是當移除第二間隙壁材料時不會傷及第一間隙壁材料。在本發明之半導體製程中，係可以微縮製程分別移除部分的第二間隙壁材料，並以乾蝕刻製程分別蝕刻部分的第一間隙壁材料，因而將第一間隙壁材料分別形成為第一間隙壁以及第二間隙壁。 Furthermore, the first spacer material of the present invention is lower than the etching rate of the second spacer material, and the first spacer material and the second spacer material can be removed, respectively, especially when the second spacer material is removed. Does not hurt the first spacer material. In the semiconductor process of the present invention, a portion of the second spacer material may be removed by a micro-reduction process, and a portion of the first spacer material is separately etched by a dry etching process, thereby forming the first spacer material as the first a spacer and a second spacer.
10‧‧‧絕緣結構 10‧‧‧Insulation structure
110‧‧‧基底 110‧‧‧Base
112‧‧‧鰭狀結構 112‧‧‧Fin structure
120a‧‧‧第一間隙壁 120a‧‧‧First gap
120b‧‧‧第二間隙壁 120b‧‧‧Second gap
122‧‧‧閘極介電層 122‧‧‧ gate dielectric layer
124‧‧‧犧牲電極層 124‧‧‧Sacrificial electrode layer
126‧‧‧蓋層 126‧‧‧ cover
160a‧‧‧底層 160a‧‧‧ bottom
130‧‧‧第一磊晶層 130‧‧‧First epitaxial layer
150‧‧‧第二磊晶層 150‧‧‧Second epilayer
160b’‧‧‧第三間隙壁 160b’‧‧‧ third gap
G1‧‧‧第一閘極 G1‧‧‧ first gate
G2‧‧‧第二閘極 G2‧‧‧second gate
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| TWI718221B (en) * | 2016-01-29 | 2021-02-11 | 台灣積體電路製造股份有限公司 | Finfet device and method of forming the same |
| CN106683990B (en) * | 2015-11-06 | 2021-03-30 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| US20080121985A1 (en) * | 2006-11-07 | 2008-05-29 | International Business Machines Corporation | Structure and method to improve short channel effects in metal oxide semiconductor field effect transistors |
| TWI326472B (en) * | 2007-01-10 | 2010-06-21 | United Microelectronics Corp | Method of fabricating strained silicon channel metal oxide semiconductor transistor |
| US8487354B2 (en) * | 2009-08-21 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving selectivity of epi process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106683990B (en) * | 2015-11-06 | 2021-03-30 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| TWI718221B (en) * | 2016-01-29 | 2021-02-11 | 台灣積體電路製造股份有限公司 | Finfet device and method of forming the same |
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