TW201443602A

TW201443602A - Driving circuit

Info

Publication number: TW201443602A
Application number: TW102144772A
Authority: TW
Inventors: Yeong-Sheng Lee
Original assignee: Via Tech Inc
Priority date: 2013-05-13
Filing date: 2013-12-06
Publication date: 2014-11-16
Also published as: TWI510878B; CN103780242B; CN106505992A; CN103780242A; US8786324B1; CN106505992B

Abstract

A driving circuit is provided. The driving circuit comprises: a level shifter, configured to receive a reference voltage having a second voltage level and an input signal having a first voltage level to generate a reference signal; a differential amplifier, having a first input terminal coupled to the reference signal, a second input terminal coupled to the input signal, and an output terminal, wherein an operation voltage having a third voltage level is supplied to the differential amplifier, and an output stage, configured to receive the input signal and the operation voltage to generate the output signal, wherein the second input terminal of the differential amplifier is coupled to the output terminal of the differential amplifier according to the input signal, wherein the first voltage level is smaller than the third voltage level, and the second voltage level is between the first voltage level and the third voltage level.

Description

驅動電路 Drive circuit

本發明係有關於驅動電路，特別是有關於可解決目前可攜式系統中之混合電壓問題的驅動電路。 The present invention relates to drive circuits, and more particularly to drive circuits that address the problem of mixed voltages in current portable systems.

現今的混合電壓源已常用在可攜式系統或電子系統中之積體電路(IC)的不同的元件上，例如類比電路及數位電路。舉例來說，在一IC中的類比電路及數位電路往往使用不同的電壓位準。除此之外，因為IC製程之緣故，在同一個IC中往往也需使用到除了用於類比電路及數位電路之兩個電壓位準之外的一額外電壓位準。意即該額外的電壓位準需提供至該IC中的某些單元或元件。因此，在傳統的IC中往往使用一複雜的驅動電路以提供該額外電壓位準，其不利於IC的微型化且會增加功率消耗。 Today's hybrid voltage sources have been commonly used on different components of integrated circuits (ICs) in portable systems or electronic systems, such as analog circuits and digital circuits. For example, analog circuits and digital circuits in an IC often use different voltage levels. In addition, due to the IC process, an additional voltage level in addition to the two voltage levels for the analog circuit and the digital circuit is often used in the same IC. This means that the additional voltage level needs to be supplied to certain units or components in the IC. Therefore, a complex driver circuit is often used in conventional ICs to provide this additional voltage level, which is detrimental to the miniaturization of the IC and increases power consumption.

本發明係提供一種驅動電路，用以依據一輸入信號及一參考電壓產生一輸出信號，該驅動電路包括：一位準調節器，用以接收具有一第二電壓位準之該參考電壓及具有一第一電壓位準之該輸入信號以產生一參考信號；一差動放大器，耦接至該位準調節器，其具有一第一輸入端耦接至該參考信號，一第二輸入端耦接至該輸出信號，以及一輸出端，其中具有一第三電壓位準之一操作電壓係提供至該差動放大器；以及一輸出級，耦接至該差動放大器之該第二輸入端及該輸出端，用以接收該輸入信號及該操作電壓以產生該輸出信號，其中該差動放大器之該第二輸入端係依據該輸入信號以耦接至該差動放大器之該輸出端，其中該第一電壓位準係小於該第三電壓位準，且該第二電壓位準係介於該第一電壓位準及該第三電壓位準之間。 The present invention provides a driving circuit for generating an output signal according to an input signal and a reference voltage, the driving circuit comprising: a quasi-regulator for receiving the reference voltage having a second voltage level and having a first voltage level of the input signal to generate a reference signal; a differential amplifier coupled to the level regulator having a first input coupled to the reference signal and a second input coupled Connected to the output signal, and an output terminal An operating voltage is provided to the differential amplifier; and an output stage coupled to the second input of the differential amplifier and the output for receiving the input signal and the operation a voltage is generated to generate the output signal, wherein the second input of the differential amplifier is coupled to the output of the differential amplifier according to the input signal, wherein the first voltage level is less than the third voltage level And the second voltage level is between the first voltage level and the third voltage level.

本發明更提供一種驅動電路，用以依據具有一第一電壓位準之一輸入信號及具有一第二電壓位準之一參考電壓以產生一輸出信號，該驅動電路包括：一差動放大器，其具有一第一輸入端耦接至該參考電壓，一第二輸入端耦接至該輸出信號，以及一輸出端，其中具有一第三電壓位準之一操作電壓係提供至該差動放大器；以及一輸出級，耦接至該差動放大器之該第二輸入端及該輸出端，用以接收該輸入信號及該操作電壓以產生該輸出信號，其中該第二輸入端係依據該輸入信號以耦接至該差動放大器之該輸出端，其中該第一電壓位準係小於該第三電壓位準，且該第二電壓位準係介於該第一電壓位準及該第三電壓位準之間。 The present invention further provides a driving circuit for generating an output signal according to an input signal having a first voltage level and a reference voltage having a second voltage level, the driving circuit comprising: a differential amplifier, The first input terminal is coupled to the reference voltage, the second input terminal is coupled to the output signal, and an output terminal, wherein an operating voltage having a third voltage level is provided to the differential amplifier And an output stage coupled to the second input end of the differential amplifier and the output end for receiving the input signal and the operating voltage to generate the output signal, wherein the second input is based on the input The signal is coupled to the output of the differential amplifier, wherein the first voltage level is less than the third voltage level, and the second voltage level is between the first voltage level and the third Between voltage levels.

本發明更提供一種驅動電路，用以依據來自具有一第一電壓位準之一輸入級電壓所產生的一輸入信號及具有第二電壓位準之一參考電壓產生一輸出信號。該驅動電路包括：一差動放大器，具有一第一輸入端耦接至該參考電壓、一第二輸入端耦接至該輸出信號、以及一輸出端，其中該差動放大器之電力係由具有一第三電壓位準之一操作電壓所提供；一輸出級，耦接至該差動放大器之該第二輸入端及該輸出端，用以接收該輸入信號及該操作電壓以產生該輸出信號，其中該第二輸入端係依據該輸入信號耦接至該差動放大器之該輸出端，其中該第一電壓位準係低於該第三電壓位準，且該第二電壓位準係介於該第一電壓位準及該第三電壓位準之間，其中該操作電壓係依據該輸入信號及該輸入級電壓所產生。 The invention further provides a driving circuit for generating an output signal according to an input signal generated from an input stage voltage having a first voltage level and a reference voltage having a second voltage level. The driving circuit includes: a differential amplifier having a first input coupled to the reference voltage, a second input coupled to the output signal, and an output, wherein the differential amplifier is powered by Provided by one of the third voltage levels; An output stage coupled to the second input end of the differential amplifier and the output end for receiving the input signal and the operating voltage to generate the output signal, wherein the second input end is coupled according to the input signal To the output of the differential amplifier, wherein the first voltage level is lower than the third voltage level, and the second voltage level is between the first voltage level and the third voltage level Between the operation voltage is generated according to the input signal and the input stage voltage.

100‧‧‧驅動電路 100‧‧‧ drive circuit

110‧‧‧位準調節器 110‧‧‧ level regulator

120‧‧‧差動放大器 120‧‧‧Differential Amplifier

130‧‧‧輸出級 130‧‧‧Output level

300‧‧‧帶差電壓參考電路 300‧‧‧Differential voltage reference circuit

310‧‧‧運算放大器 310‧‧‧Operational Amplifier

320-360‧‧‧雙載子接面電晶體 320-360‧‧‧Double carrier junction transistor

600、600A‧‧‧切換式電容升壓器 600, 600A‧‧‧Switching Capacitor Booster

601‧‧‧反相器 601‧‧‧Inverter

610‧‧‧電容調整電路 610‧‧‧Capacitor adjustment circuit

620‧‧‧充電控制器 620‧‧‧Charging controller

621-622、631-632‧‧‧邏輯閘 621-622, 631-632‧‧‧ logic gate

623‧‧‧比較器 623‧‧‧ comparator

641-643‧‧‧時序延遲電路 641-643‧‧‧Time delay circuit

V_BE4X、V_BE1X‧‧‧電壓 V _BE4X , V _BE1X ‧‧‧ voltage

I_PTAT‧‧‧電流 I _PTAT ‧‧‧current

R1-R3‧‧‧電阻 R1-R3‧‧‧ resistance

V_i‧‧‧輸入信號 V _i ‧‧‧ input signal

V_o‧‧‧輸出信號 V _o ‧‧‧ output signal

V_r‧‧‧參考信號 V _r ‧‧‧ reference signal

V_ref‧‧‧參考電壓 V _ref ‧‧‧reference voltage

V_B‧‧‧偏壓電壓 V _B ‧‧‧ bias voltage

VDD‧‧‧操作電壓 VDD‧‧‧ operating voltage

VCC‧‧‧電壓源 VCC‧‧‧ voltage source

I_VDD‧‧‧驅動電流 I _VDD ‧‧‧ drive current

t1-t3‧‧‧時間 T1-t3‧‧‧ time

+、-‧‧‧輸入端 +, -‧‧‧ input

A、B、C‧‧‧節點 A, B, C‧‧‧ nodes

MN1-MN9‧‧‧N型電晶體 MN1-MN9‧‧‧N type transistor

MP1-MP10‧‧‧P型電晶體 MP1-MP10‧‧‧P type transistor

C₀、C₁‧‧‧電容 C ₀ , C ₁ ‧‧‧ capacitor

VEE‧‧‧輸入級電壓 VEE‧‧‧ input stage voltage

V_C‧‧‧控制信號 V _C ‧‧‧ control signal

第1圖係顯示依據本發明一實施例之驅動電路100的功能方塊圖。 1 is a functional block diagram showing a driving circuit 100 in accordance with an embodiment of the present invention.

第2A圖係顯示依據本發明一實施例之驅動電路100的詳細電路圖。 2A is a detailed circuit diagram showing a driving circuit 100 in accordance with an embodiment of the present invention.

第2B圖係顯示依據本發明一實施例之差動放大器120的一示意圖。 2B is a schematic diagram showing a differential amplifier 120 in accordance with an embodiment of the present invention.

第3圖係顯示依據本發明一實施例之帶差電壓參考電路的電路圖。 Figure 3 is a circuit diagram showing a differential voltage reference circuit in accordance with an embodiment of the present invention.

第4A~4D圖係顯示依據本發明第2B圖之實施例中的不同電壓位準及驅動電流與時間的關係圖。 4A to 4D are graphs showing different voltage levels and drive current versus time in an embodiment according to Fig. 2B of the present invention.

第5圖係顯示依據本發明另一實施例之驅動電路100的功能方塊圖。 Figure 5 is a functional block diagram showing a driving circuit 100 in accordance with another embodiment of the present invention.

第6A圖係顯示依據本發明一實施例中之切換式電容升壓器600的電路圖。 Figure 6A is a circuit diagram showing a switched capacitor booster 600 in accordance with an embodiment of the present invention.

第6B圖係顯示依據本發明一實施例中之切換式電容升壓器600A的電路圖。 Fig. 6B is a circuit diagram showing a switched capacitor booster 600A in accordance with an embodiment of the present invention.

第6C圖係顯示依據本發明一實施例中之主要邏輯閘的輸出及充電信號的波形圖。 Figure 6C is a waveform diagram showing the output and charging signals of the main logic gates in accordance with an embodiment of the present invention.

第7圖係顯示依據本發明第6A圖之實施例中操作電壓、輸入信號V_i、及輸出信號V_o隨著時間變化關係的波形圖。 Figure 7 is a waveform diagram showing the relationship of the operating voltage, the input signal V _i , and the output signal V _o as a function of time in the embodiment of Figure 6A of the present invention.

為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。 The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

在電子系統中往往會具有不同的操作電壓以提供至其類比電路(例如1.8V)及數位電路(例如1.0V)。不同的規格可能會需要使用不同於這些操作電壓的其他電壓位準。舉例來說，行動工業處理器介面(Mobile Industry Processor Interface，MIPI)之規格中需要產生具有0V及1.2V電壓位準的輸出信號。因此，需要一種驅動電路以產生具有驅動能力的這些電壓位準。第1圖係顯示依據本發明一實施例之驅動電路100的功能方塊圖。驅動電路100係包括一位準調節器(level shifter)110、一差動放大器120、及一輸出級(output stage)130。請參考第1圖，位準調節器110係耦接至一輸入信號V_i(其具有一第一電壓位準)以及一參考電壓V_ref(其具有一第二電壓位準)，並輸出一參考信號V_r至差動放大器120的一第一輸入端(例如第1圖中的+端)。該參考電壓V_ref之第二電壓位準係表示驅動電路100之輸出信號V_o所需要的電壓位準，且其可藉由不具有電流驅動能力之一帶差電壓參考電路(bandgap voltage reference circuit)所產生(其細節將詳述於後)。差動放大器120之輸出端及其第二輸入端係耦接至輸出級130。輸出級130亦耦接至輸入信號V_i以做為另一輸入，並提供一輸出信號V_o，其即為驅動電路100之輸出。差動放大器120及輸出級130均可接受具有一第三電壓位準之一操作電壓以進行操作。在一實施例中，該第三電壓位準係高於該第一電壓位準，且該第二電壓位準係介於該第一電壓位準及該第三電壓位準之間。當經由輸出級130形成一負回授迴路時，差動放大器120之第一輸入端及第二輸入端會形成虛擬短路(virtual short)。因此，差動放大器120之第二輸入端之信號(即V_o)係與差動放大器120之第一輸入端的參考信號V_r相同。 There are often different operating voltages in an electronic system to provide to analog circuits (eg, 1.8V) and digital circuits (eg, 1.0V). Different specifications may require the use of other voltage levels than these operating voltages. For example, the Mobile Industry Processor Interface (MIPI) specification requires an output signal with a voltage level of 0V and 1.2V. Therefore, there is a need for a drive circuit to generate these voltage levels with drive capability. 1 is a functional block diagram showing a driving circuit 100 in accordance with an embodiment of the present invention. The drive circuit 100 includes a level shifter 110, a differential amplifier 120, and an output stage 130. Referring to FIG. 1 , the level regulator 110 is coupled to an input signal V _i (having a first voltage level) and a reference voltage V _ref (which has a second voltage level), and outputs a The reference signal V _{r is} to a first input of the differential amplifier 120 (eg, the + terminal in FIG. 1). The reference voltage V _ref of the voltage level of the second line indicates the driving voltage level output signal V _o of the circuit 100 is required, and it may not have the area by voltage reference circuit current driving capability (bandgap voltage reference circuit) Produced (the details of which will be detailed later). The output of the differential amplifier 120 and its second input are coupled to the output stage 130. The output stage 130 is also coupled to the input signal V _i as another input and provides an output signal V _o , which is the output of the drive circuit 100. Both differential amplifier 120 and output stage 130 can accept an operating voltage having a third voltage level for operation. In an embodiment, the third voltage level is higher than the first voltage level, and the second voltage level is between the first voltage level and the third voltage level. When a negative feedback loop is formed via the output stage 130, a virtual short is formed at the first input and the second input of the differential amplifier 120. Therefore, the signal at the second input of the differential amplifier 120 (i.e., _Vo ) is the same as the reference signal _{Vr at} the first input of the differential amplifier 120.

第2A圖係顯示依據本發明一實施例之驅動電路100的詳細電路圖。以下將介紹驅動電路100中的各元件之運作。位準調節器110之運作係基於輸入信號V_i。該輸入信號V_i係耦接至P型場效電晶體(下述為P型電晶體)MP3之閘極以及N型場效電晶體(下述為N型電晶體)MN4之閘極。N型電晶體MN4之源極係耦接至地。P型電晶體MP3之源極係耦接至參考電壓V_ref。N型電晶體MN4及P型電晶體MP3之汲極均耦接於節點B，意即差動放大器120之第一輸入端。因此，可依據輸入信號V_i以在節點B獲得參考信號V_r。舉例來說，假設輸入信號V_i係處於0V的低邏輯位準且參考電壓V_ref係處於1.2V之固定電壓，P型電晶體MP3係被開啟且N型電晶體MN4係被關閉，使得參考信號V_r約略在1.2V之電壓位準。假設輸入信號V_i係處於1V之高邏輯位準，N型電晶體MN4會被開啟，使得在節點B的參考信號V_r會被下拉至0V。輸出級130之運作亦是基於輸入信號V_i。輸出級130係包括N型電晶體MN1、MN2及MN5。N型電晶體MN2及MN5之閘極均由輸入信號V_i所控制，且N型電晶體MN2及MN5之源極均耦接至地。N型電晶體MN5之汲極係耦接至差動放大器120之輸出端，且N型電晶體MN2之汲極係耦接至可提供輸出信號V_o之差動放大器120的第二輸入端。N型電晶體MN1其閘極係耦接至差動放大器120的輸出端，其源極係耦接至差動放大器120的第二輸入端，且其汲極係耦接至操作電壓VDD。因此，可依據輸入信號V_i在差動放大器120建立一負回授迴路。舉例來說，假設輸入信號係處於0V的低邏輯位準，N型電晶體MN2及MN5均被關閉，使得N型電晶體MN1由差動放大器120之輸出端至第二輸入端形成一負回授迴路。因此，差動放大器120之第一輸入端及第二輸入端會形成虛擬短路，故在差動放大器120之第二輸入端之輸出信號V_o係與在差動放大器120之第一輸入端的參考信號V_r(如上所述，約為1.2V)相同。假設輸入信號V_i係處於1.0V的高邏輯位準，N型電晶體MN2及MN5會被開啟，使得N型電晶體MN1被關閉且無回授迴路。輸出信號V_o會經由N型電晶體MN2而被下拉至0V。在此時，參考信號V_r亦如同前述為0V，然而，這並不是因為虛擬短路的緣故。在輸出級130中之上拉的N型電晶體MN1及下拉的N型電晶體MN2可提供驅動後續電路之驅動能力。除此之外，由於上拉及下拉的電晶體均是由N型電晶體所製成，因N型電晶體之驅動能力一般來說是P型電晶體的2~3倍，故其可節省晶片面積。差動放大器120亦可接受具有第三電壓位準(例如1.8V)之操作電壓VDD以進行運作。在另一實施例中，參考電壓V_ref可不經由位準調節器110而直接耦接至差動放大器120之第一輸入端。因為當輸入信號V_i處於高邏輯位準時在差動放大器120之第一輸入端及第二輸入端不會形成虛擬短路，無論差動放大器120之第一輸入端的信號位準為何，輸出信號V_o均會被下拉至0V。在另一實施例中，場效電晶體亦可替換為雙載子接面電晶體(bipolar junction transistor，BJT)。 2A is a detailed circuit diagram showing a driving circuit 100 in accordance with an embodiment of the present invention. The operation of each component in the drive circuit 100 will be described below. The operation of the level regulator 110 is based on the input signal V _i . The input signal V _i is coupled to a gate of a P-type field effect transistor (hereinafter referred to as a P-type transistor) MP3 and a gate of an N-type field effect transistor (hereinafter referred to as an N-type transistor) MN4. The source of the N-type transistor MN4 is coupled to ground. The source of the P-type transistor MP3 is coupled to the reference voltage V _ref . The drains of the N-type transistor MN4 and the P-type transistor MP3 are both coupled to the node B, that is, the first input terminal of the differential amplifier 120. Therefore, the reference signal V _r can be obtained at the node B in accordance with the input signal V _i . For example, suppose the input signal V _i is at a low logic level of 0V and the reference voltage V _ref is at a fixed voltage of 1.2V, the P-type transistor MP3 is turned on and the N-type transistor MN4 is turned off, so that the reference The signal V _r is approximately at a voltage level of 1.2V. Assuming that the input signal V _i is at a high logic level of 1V, the N-type transistor MN4 will be turned on, so that the reference signal V _r at the node B will be pulled down to 0V. The operation of the output stage 130 is also based on the input signal V _i. The output stage 130 includes N-type transistors MN1, MN2, and MN5. The gates of the N-type transistors MN2 and MN5 are both controlled by the input signal V _i , and the sources of the N-type transistors MN2 and MN5 are all coupled to ground. N-type transistor MN5 of drain lines coupled to the output terminal of the differential amplifier 120, the N-type transistor MN2 and a drain that is coupled to the system may provide a second input terminal of the differential output signal V _o of the amplifier 120. The N-type transistor MN1 has its gate coupled to the output of the differential amplifier 120, its source coupled to the second input of the differential amplifier 120, and its drain coupled to the operating voltage VDD. Therefore, a negative feedback loop can be established in the differential amplifier 120 in accordance with the input signal V _i . For example, assuming that the input signal is at a low logic level of 0V, the N-type transistors MN2 and MN5 are both turned off, so that the N-type transistor MN1 forms a negative return from the output of the differential amplifier 120 to the second input. Grant a loop. Therefore, the first input end and the second input end of the differential amplifier 120 form a virtual short circuit, so the output signal V _o at the second input end of the differential amplifier 120 and the reference at the first input end of the differential amplifier 120 The signal V _r (about 1.2 V as described above) is the same. Assuming that the input signal V _i is at a high logic level of 1.0V, the N-type transistors MN2 and MN5 are turned on, so that the N-type transistor MN1 is turned off and there is no feedback loop. The output signal _Vo will be pulled down to 0V via the N-type transistor MN2. At this time, the reference signal _{Vr is} also 0V as described above, however, this is not due to a virtual short circuit. The N-type transistor MN1 and the pull-down N-type transistor MN2 pulled up in the output stage 130 can provide driving capability for driving subsequent circuits. In addition, since the pull-up and pull-down transistors are made of N-type transistors, the driving ability of the N-type transistor is generally 2 to 3 times that of the P-type transistor, so it can save Wafer area. The differential amplifier 120 can also accept an operating voltage VDD having a third voltage level (e.g., 1.8V) to operate. In another embodiment, the reference voltage V _ref may be directly coupled to the first input of the differential amplifier 120 without via the level regulator 110. Because the virtual input is not formed at the first input end and the second input end of the differential amplifier 120 when the input signal V _{i is} at the high logic level, regardless of the signal level of the first input terminal of the differential amplifier 120, the output signal V is output. _o will be pulled down to 0V. In another embodiment, the field effect transistor can also be replaced by a bipolar junction transistor (BJT).

第2B圖係顯示依據本發明一實施例之差動放大器120的一示意圖。如第2B圖所示，一操作電壓VDD係提供至一示範性的差動放大器120，且該差動放大器120係在節點A(即差動放大器120之輸出端)提供一輸出電壓V_a。差動放大器120係透過P型電晶體對MP1及MP2耦接至操作電壓VDD，且透過N型電晶體MN3耦接至地。N型電晶體MN3之閘極係由一偏壓電壓V_B所控制，該偏壓電壓V_B係可開啟/關閉N型電晶體MN3以致能/禁能差動放大器120。在另一實施例中，差動放大器120係透過一電流源(即N型電晶體MN6及MN7之源極均耦接至已耦接至地的一電流源)以耦接至地。差動放大器120之第一輸入端(N型電晶體MN6之閘極)係耦接至具有參考信號V_r的節點B。差動放大器120之第二輸入端(N型電晶體MN7之閘極)係耦接至位於輸出級130的節點C，藉以提供驅動電路100之輸出信號V_o。需注意的是，對於熟習本發明領域之技藝者而言，當了解差動放大器120可用許多形式來實現。在一實施例中，差動放大器120係可由雙載子接面電晶體(BJT)來實現。 2B is a schematic diagram showing a differential amplifier 120 in accordance with an embodiment of the present invention. As shown in Figure 2B, an operation voltage VDD is provided to the differential amplifier a train exemplary 120, and line 120 of the differential amplifier provides an output voltage V _a at node A (i.e., the output terminal of the differential amplifier 120). The differential amplifier 120 is coupled to the operating voltage VDD through the P-type transistor pair MP1 and MP2, and coupled to the ground through the N-type transistor MN3. The N-type transistor MN3 gate line is controlled by a bias voltage V _B, the bias voltage V _B can be based on / off the N-type transistor MN3 so as to enable / disable the differential amplifier 120. In another embodiment, the differential amplifier 120 is coupled to ground through a current source (ie, the sources of the N-type transistors MN6 and MN7 are each coupled to a current source coupled to ground). The first input of the differential amplifier 120 (the gate of the N-type transistor MN6) is coupled to the node B having the reference signal _Vr . The second input of the differential amplifier 120 (the gate of the N-type transistor MN7) is coupled to the node C at the output stage 130 to provide an output signal V _{o of the} drive circuit 100. It should be noted that for those skilled in the art of the invention, it is understood that the differential amplifier 120 can be implemented in a number of forms. In an embodiment, the differential amplifier 120 can be implemented by a bi-carrier junction transistor (BJT).

數個輸入電壓位準係提供至輸出級130，例如VDD、V_a及V_i。舉例來說，操作電壓VDD係提供至N型電晶體 MN1之汲極。N型電晶體MN1之閘極及N型電晶體MN5之汲極均耦接至具有電壓位準V_a之節點A(即差動放大器120之輸出端)。N型電晶體MN5之閘極及N型電晶體MN2之閘極均耦接至輸入信號V_i。N型電晶體MN1之源極及N型電晶體MN2之汲極均耦接至差動放器120之第二輸入端(N型電晶體MN7之閘極)。N型電晶體MN2之源極及N型電晶體MN5之源極均耦接至地。舉例來說，假設輸入信號V_i處於0V之低邏輯位準，N型電晶體MN4、MN5及MN2均被關閉。意即差動放大器120之第一輸入端(具有參考信號V_r之N型電晶體MN6的閘極)的電壓位準即為參考電壓V_ref(例如1.2V)。同時，N型電晶體MN1會被開啟且輸出信號V_o會被上拉至與參考信號V_r相同的電壓位準(例如1.2V)。舉例來說，若操作電壓VDD為1.8V，電壓V_a約為1.6V。相反地，假設輸入信號V_i處於1V之高邏輯位準，N型電晶體MN4、MN5及MN2會被開啟。意即差動放大器120之第一輸入端的參考信號V_r及輸出信號V_o均會被下拉至0V(即接地)。 A plurality of input line voltage level to the output stage 130, e.g. VDD, V _a and V _i. For example, the operating voltage VDD is supplied to the drain of the N-type transistor MN1. The gate of the N-type transistor MN1 and the drain of the N-type transistor MN5 are both coupled to the node A having the voltage level V _a (ie, the output of the differential amplifier 120). The gate of the N-type transistor MN5 and the gate of the N-type transistor MN2 are both coupled to the input signal V _i . The source of the N-type transistor MN1 and the drain of the N-type transistor MN2 are both coupled to the second input terminal of the differential amplifier 120 (the gate of the N-type transistor MN7). The source of the N-type transistor MN2 and the source of the N-type transistor MN5 are both coupled to ground. For example, assuming that the input signal V _{i is} at a low logic level of 0V, the N-type transistors MN4, MN5, and MN2 are all turned off. That is, the voltage level of the first input terminal of the differential amplifier 120 (the gate of the N-type transistor MN6 having the reference signal V _r ) is the reference voltage V _ref (for example, 1.2 V). At the same time, the N-type transistor MN1 will be turned on and the output signal V _o will be pulled up to the same voltage level as the reference signal V _r (for example, 1.2V). For example, if the operating voltage VDD is 1.8V, the voltage V _a is approximately 1.6V. Conversely, assume that V _i is at a high logic level of 1V, N-type transistors MN4, MN5 and MN2 are turned on. That is, the reference signal V _r and the output signal V _o of the first input terminal of the differential amplifier 120 are both pulled down to 0V (ie, grounded).

第3圖係顯示依據本發明一實施例之帶差電壓參考電路的電路圖。帶差電壓參考電路可提供非常穩定的參考電壓而不受到溫度及電源變化之影響。在一實施例中，參考電壓V_ref可由帶差電壓參考電路300所產生，如第3圖所示。一電壓源VCC係提供至運算放大器(operational amplifier)310。運算放大器310之負輸入端係連接至數個相同的BJT(例如：BJT320~350)之集極，該些BJT 320~350係具有共同的集極及一共同的射極。BJT 320~350之基極係連接至其共同集極。運算放大器310之正輸入端係連接至BJT 360之集極。電阻R1、R2及R3，舉例來說，係分別為5K、5K及390Ω。因此，橫跨於BJT 320~350之共同集極及共同射極之電壓為V_BE4X，且橫跨於BJT 360之集極及地之間的電壓為V_BE1X。更進一步而言，通過電阻R3之電流I_PTAT為(V_BE1X-V_BE4X)/R3。因此，由帶差電壓參考電路300所產生的參考電壓V_ref可由下列公式計算而得：V_ref=V_BE1X+(V_BE1X-V_BE4X)*(5K/390) Figure 3 is a circuit diagram showing a differential voltage reference circuit in accordance with an embodiment of the present invention. The differential voltage reference circuit provides a very stable reference voltage without being affected by temperature and power supply variations. In an embodiment, the reference voltage V _ref may be generated by the difference voltage reference circuit 300 as shown in FIG. A voltage source VCC is provided to an operational amplifier 310. The negative input of operational amplifier 310 is coupled to the collectors of a plurality of identical BJTs (e.g., BJTs 320-350) having a common collector and a common emitter. The base of BJT 320~350 is connected to its common collector. The positive input of operational amplifier 310 is coupled to the collector of BJT 360. Resistors R1, R2, and R3 are, for example, 5K, 5K, and 390Ω, respectively. Therefore, the voltage across the common collector and common emitter of BJT _320-350 is V _BE4X , and the voltage across the collector and ground of BJT 360 is V _BE1X . Further, the current I _PTAT through the resistor R3 is (V _BE1X - V _BE4X ) / R3. Therefore, the reference voltage V _ref generated by the difference voltage reference circuit 300 can be calculated by the following formula: V _ref =V _BE1X +(V _BE1X -V _BE4X )*(5K/390)

需注意的是帶差電壓參考電路300之輸出電壓可為一固定值1.2V。更詳細而言，雖然電壓V_BE4X及V_BE1X會因為溫度改變而產生變化，但電壓V_BE4X及V_BE1X之間的差值可保持在一定值，使得電壓V_ref之位準可約略固定在1.2V。然而，因為帶差電壓參考電路300並不具有上拉及下拉電晶體以提供驅動能力，帶差電壓參考電路300並無法提供足夠的電流以驅動其他電路。因此，驅動電路100之驅動電流係主要來自輸出級130。第4A~4D圖係顯示依據本發明第2B圖之實施例中的不同電壓位準及驅動電流與時間的關係圖。在此實施例中，第一電壓位準為1V，第二電壓位準為1.2V，且第三電壓位準為1.8V。如第4B~4D圖所示，當輸入信號V_i處於0V之低邏輯位準時，參考信號V_r及輸出信號V_o均在1.2之電壓位準。當輸入信號V_i處於1V之高邏輯位準時，參考信號V_r及輸出信號V_o均會被快速地下拉至0V的電壓位準(意即接地)。由第4A圖，需注意到當輸出信號V_o轉換至高邏輯位準(即上拉)時，驅動電流I_VDD(即由操作電壓VDD所供應的電流，可包括流過P型電晶體對MP1及MP2之源極的一第一驅動電流以及流過N型電晶體MN1之汲極的一第二驅動電流)會產生一高峰值，且在包含當輸出信號由高邏輯位準轉換為低邏輯位準時之其他時間會維持約略為0A。因此，可在驅動電流I_VDD幾乎不消耗穩定功率的情況下提供驅動能力。 It should be noted that the output voltage of the differential voltage reference circuit 300 can be a fixed value of 1.2V. In more detail, although the voltages V _BE4X and V _BE1X will change due to temperature changes, the difference between the voltages V _BE4X and V _BE1X can be kept at a certain value, so that the level of the voltage V _ref can be approximately fixed at 1.2. V. However, because the differential voltage reference circuit 300 does not have pull-up and pull-down transistors to provide drive capability, the differential voltage reference circuit 300 does not provide sufficient current to drive other circuits. Therefore, the drive current of the drive circuit 100 is mainly from the output stage 130. 4A to 4D are graphs showing different voltage levels and drive current versus time in an embodiment according to Fig. 2B of the present invention. In this embodiment, the first voltage level is 1V, the second voltage level is 1.2V, and the third voltage level is 1.8V. As shown in Figures 4B to 4D, when the input signal V _{i is} at a low logic level of 0V, both the reference signal V _r and the output signal V _o are at a voltage level of 1.2. When the input signal V _{i is} at a logic level of 1V, both the reference signal V _r and the output signal V _o are quickly pulled down to a voltage level of 0V (ie, grounded). From Figure 4A, it should be noted that when the output signal _Vo transitions to a high logic level (ie, pull up), the drive current I _VDD (ie, the current supplied by the operating voltage VDD may include flowing through the P-type transistor pair MP1) And a first driving current of the source of the MP2 and a second driving current flowing through the drain of the N-type transistor MN1) generate a high peak value, and include when the output signal is converted from a high logic level to a low logic The other time of the quasi-time will be maintained at approximately 0A. Therefore, the driving ability can be provided with the driving current I _VDD hardly consuming stable power.

第5圖係顯示依據本發明另一實施例之驅動電路100的功能方塊圖。為了降低電路佈局(layout)面積並使用高速的應用，在驅動電路100會較傾向使用低電壓之裝置(由具有較低之電壓容忍度之先進CMOS製程所製造出的裝置)而不使用高電壓之裝置。舉例來說，這些低電壓裝置會需要其汲極-閘極電壓差小於1.2V，藉以防止汲極-閘極之「擊穿效應(punch through)」。在第5圖中之驅動電路100的輸出級130係與第2A圖類似，其差別在於額外的一個P型電晶體MP4耦接於N型電晶體MN1之源極及差動放大器120之第二輸入端，且額外的一個N型電晶體MN8耦接於N型電晶體MN5之汲極與差動放大器120之輸出端。在第5圖之實施例中，參考電壓V_ref可在沒有位準調節器110時直接耦接於差動放大器120之第一輸入端。在另一實施例中，可類似地與第2A圖同樣加入位準調節器110。差動放大器120可同樣地以上述的方式實現。P型電晶體MP4具有一閘極端耦接至輸入信號V_i、一源極端耦接至N型電晶體MN1之源極端、以及一汲極端耦接至差動放大器120的第二輸入端。N型電晶體MN8具有一閘極端及一汲極端，其均耦接至差動放大器120之輸出端，以及一源極端耦接至N型電晶體MN5之汲極。在第5圖中的驅動電路100之運作係類似於前述實施例。舉例來說，假設輸入信號V_i位於0V之低邏輯位準，N型電晶體MN2及MN5均會被關閉且P型電晶體MP4會被開啟，使得N型電晶體 MN1及P型電晶體MP4在由差動放大器120之輸出端至其第二輸入端形成一負回授迴路。假設輸入信號V_i位於1.0V之高邏輯位準，N型電晶體MN2及MN5均會被開啟且P型電晶體MP4會被關閉，使得N型電晶體MN1被關閉且沒有回授迴路。N型電晶體MN1之源極端的電壓可由P型電晶體MP4及N型電晶體MN1之一分壓所決定，此時P型電晶體MP4及N型電晶體MN1均被關閉。藉由設計N型電晶體MN1及P型電晶體MP4之長寬比，在N型電晶體MN1之源極端的電壓可設計為在操作電壓VDD(例如1.8V)及0V之間的一電壓位準，例如是1.2V。因此，N型電晶體MN1及P型電晶體MP4會具有小於1.2V之一汲極-源極電壓差V_ds。因為電壓V_a可能高至1.6V，以二極體方式連接之N型電晶體MN8可同樣地防止N型電晶體MN5之汲極-源極電壓差V_ds超過1.2V，如上述實施例所述。 Figure 5 is a functional block diagram showing a driving circuit 100 in accordance with another embodiment of the present invention. In order to reduce the layout area and use high-speed applications, the driver circuit 100 tends to use a low-voltage device (a device manufactured by an advanced CMOS process with lower voltage tolerance) without using a high voltage. Device. For example, these low voltage devices would require a drain-gate voltage difference of less than 1.2V to prevent the "punch through" of the drain-gate. The output stage 130 of the driving circuit 100 in FIG. 5 is similar to FIG. 2A except that an additional P-type transistor MP4 is coupled to the source of the N-type transistor MN1 and the second of the differential amplifier 120. The input terminal, and an additional N-type transistor MN8 is coupled to the drain of the N-type transistor MN5 and the output of the differential amplifier 120. In the embodiment of FIG. 5, the reference voltage V _ref can be directly coupled to the first input of the differential amplifier 120 when the level regulator 110 is absent. In another embodiment, level regulator 110 can be similarly added to Figure 2A. The differential amplifier 120 can be similarly implemented in the manner described above. The P-type transistor MP4 has a gate terminal coupled to the input signal V _i , a source terminal coupled to the source terminal of the N-type transistor MN1 , and a terminal coupled to the second input terminal of the differential amplifier 120 . The N-type transistor MN8 has a gate terminal and a gate terminal, both of which are coupled to the output terminal of the differential amplifier 120, and a source terminal is coupled to the drain of the N-type transistor MN5. The operation of the drive circuit 100 in Fig. 5 is similar to the previous embodiment. For example, assuming that the input signal V _i is at a low logic level of 0V, the N-type transistors MN2 and MN5 are both turned off and the P-type transistor MP4 is turned on, so that the N-type transistor MN1 and the P-type transistor MP4 A negative feedback loop is formed from the output of the differential amplifier 120 to its second input. Assuming that the input signal V _i is at a high logic level of 1.0 V, both N-type transistors MN2 and MN5 are turned on and the P-type transistor MP4 is turned off, so that the N-type transistor MN1 is turned off and there is no feedback loop. The voltage at the source terminal of the N-type transistor MN1 can be determined by dividing one of the P-type transistor MP4 and the N-type transistor MN1, and both the P-type transistor MP4 and the N-type transistor MN1 are turned off. By designing the aspect ratio of the N-type transistor MN1 and the P-type transistor MP4, the voltage at the source terminal of the N-type transistor MN1 can be designed to be a voltage level between the operating voltage VDD (for example, 1.8 V) and 0 V. Quasi, for example, 1.2V. Therefore, the N-type transistor MN1 and the P-type transistor MP4 will have a drain-source voltage difference V _{ds of} less than 1.2V. Since the voltage V _a may be as high as 1.6 V, the N-type transistor MN8 connected in a diode manner can similarly prevent the drain-source voltage difference V _{ds of the} N-type transistor MN5 from exceeding 1.2 V, as in the above embodiment. Said.

在第1圖至第5圖之實施例中，操作電壓VDD可具有由一電源供應器(例如1.8V的類比電源供應器)所提供之一第三電壓位準。在一些實施例中，依據一輸入級電壓VEE(例如一數位電源供應器)通過一切換式電容升壓器可產生操作電壓VDD，其中該輸入級電壓VEE提供了輸入信號V_i之該第一電壓位準，可去除額外的高電壓電源供應器及相關的PCB板繞線的需求。第6A圖係顯示依據本發明一實施例中之切換式電容升壓器600的電路圖。切換式電容升壓器(switched-capacitor booster)600係包括N型電晶體MN9、P型電晶體MP5及MP5、電容C₀、以及反相器601。N型電晶體MN9具有一閘極端耦接至輸入信號V_i、一源極端耦接至地、以及一汲極端。P型電晶體MP5 具有一閘極端耦接至N型電晶體MN9之汲極端、一汲極端耦接至輸入級電壓VEE、以及一源極端。P型電晶體MP6具有一閘極端耦接至輸入信號V_i、一汲極端耦接至N型電晶體MN9之汲極端、以及一源極端。P型電晶體MP5及MP6之源極端均耦接至電容C₀之一第一端，其亦提供了操作電壓VDD。反相器601之輸入係耦接於輸入信號V_i，且反相器601之輸出(產生輸入信號V_i之反相信號)係耦接至電容C₀的一第二端。舉例來說，假設輸入信號V_i具有1V的高邏輯位準，N型電晶體MN9會被開啟且P型電晶體MP6會被關閉。因此，P型電晶體MP5會被開啟且電容C₀之第一端會被充電至輸入級電壓VEE(例如1V)。電容C₀的第二端會被充電至高邏輯位準1V之反相邏輯位準，意即0V之低邏輯位準。因此，1V的電壓差會儲存於電容C₀。當輸入信號V_i具有0V的低邏輯位準，N型電晶體MN9會被關閉且P型電晶體MP6會被開啟，因此P型電晶體MP5會被關閉。提供操作電壓VDD之電容C₀的第一端在此情況下會浮接(floating)。電容C₀之第二端會被充電至0V之低邏輯位準的反相邏輯位準，意即1V的高邏輯位準，並將電容C₀之第一端的電壓位準升壓至接近2倍的輸入級電壓VEE。因為電荷由電容C₀流動至驅動電路100，操作電壓VDD之實際電壓位準約為1.6V至1.8V，其電壓位準已夠高讓驅動電路100正常運作。需注意的是，所產生的操作電壓VDD並不是固定的直流電壓，然而，因為操作電壓VDD僅用於當輸入信號為低邏輯位準時讓驅動電路100拉昇輸出電壓V_o，在當輸入信號V_i為高邏輯位準時之操作電壓VDD的變化是較不需要關心的。 In the embodiments of Figures 1 through 5, the operating voltage VDD can have a third voltage level provided by a power supply (e.g., an analog power supply of 1.8V). In some embodiments, the input stage according to a voltage VEE (e.g. a digital power supply) can be generated by a switching operation voltage VDD booster capacitor, wherein the input stage of the voltage VEE is provided a first input of V _i is The voltage level removes the need for additional high voltage power supplies and associated PCB board routing. Figure 6A is a circuit diagram showing a switched capacitor booster 600 in accordance with an embodiment of the present invention. The switched-capacitor booster 600 includes an N-type transistor MN9, P-type transistors MP5 and MP5, a capacitor C ₀ , and an inverter 601. The N-type transistor MN9 has a gate terminal coupled to the input signal V _i , a source terminal coupled to ground, and a drain terminal. The P-type transistor MP5 has a gate terminal coupled to the NMOS terminal of the N-type transistor MN9, an 汲 terminal coupled to the input stage voltage VEE, and a source terminal. The P-type transistor MP6 has a gate terminal coupled to the input signal V _i , a terminal coupled to the N-type transistor MN9 and a source terminal. The source terminals of the P-type transistors MP5 and MP6 are all coupled to the first terminal of the capacitor C ₀ , which also provides the operating voltage VDD . The input of the inverter 601 is coupled to the input signal V _i , and the output of the inverter 601 (the inverted signal of the input signal V _i ) is coupled to a second end of the capacitor C ₀ . For example, assuming that the input signal V _i has a high logic level of 1V, the N-type transistor MN9 will be turned on and the P-type transistor MP6 will be turned off. Therefore, the P-type transistor MP5 will be turned on and the first end of the capacitor C ₀ will be charged to the input stage voltage VEE (for example, 1V). The second end of capacitor C ₀ is charged to the inverted logic level of the high logic level 1V, which is the low logic level of 0V. Therefore, a voltage difference of 1V is stored in the capacitor C ₀ . When the input signal V _i has a low logic level of 0V, the N-type transistor MN9 is turned off and the P-type transistor MP6 is turned on, so the P-type transistor MP5 is turned off. Providing operation voltage VDD of the capacitor C ₀ of the first end in this case will be floating (floating). The second end of the capacitor C ₀ is charged to the inverted logic level of the low logic level of 0V, which means a high logic level of 1V, and the voltage level of the first terminal of the capacitor C ₀ is boosted to be close. 2 times the input stage voltage VEE. Since the charge flows from the capacitor C ₀ to the driving circuit 100, the actual voltage level of the operating voltage VDD is about 1.6V to 1.8V, and the voltage level is high enough for the driving circuit 100 to operate normally. It should be noted that the generated operating voltage VDD is not a fixed DC voltage, however, because the operating voltage VDD is only used to let the driving circuit 100 pull up the output voltage V _o when the input signal is at a low logic level, when the input signal is The change in operating voltage VDD when V _i is a high logic level is less of a concern.

第6B圖係顯示依據本發明一實施例中之切換式電容升壓器600A的電路圖。當使用切換式電容升壓器以產生操作電壓VDD時，若輸出電容負載相當大，因為電容C₀可能無法提供足夠的電荷至輸出電容負載，輸出信號V_o可能不會達到所需的參考電壓V_ref的第二電壓位準。相較於第6A圖中的切換式電容升壓器600，切換式電容升壓器600A更包括一電容調整電路610以及一充電控制器620。電容調整電路610包括一P型電晶體對MP7及MP8，其係依據耦接至P型電晶體MP7及MP8之第一充電信號V_GP7,8而將電容C₀之第一端及第二端(分別耦接至P型電晶體MP7及MP8的汲極)分別耦接至電容C₁之第一端及第二端(分別耦接至P型電晶體MP7及MP8的源極)。電容調整電路610更包括一P型電晶體對MP9及MP10，其係依據耦接至P型電晶體MP9及MP10之一第二充電信號V_GP9,10而分別將電容C₁之第一端及第二端耦接至輸入級電壓VEE及地。P型電晶體MP9具有一源極端耦接至輸入級電壓VEE、以及一汲極端耦接至電容C₁之第一端，且P型電晶體MP10具有一源極端耦接至電容C₁之第二端、以及一汲極端耦接至地。因此，當第一充電信號V_GP7,8為低邏輯位準時，P型電晶體對MP7及MP8係將電容C₁及電容C₀平行耦接(因此增加了在操作電壓VDD之總體的電容值及儲存的電荷)，且當第二充電信號V_GP9,10為低邏輯位準時，P型電晶體對MP9及MP10係將電容C₁充電至輸入級電壓VEE之一電壓差(即第一電壓位準)。第一充電信號V_GP7,8及第二充電信號V_GP9,10均由充電控制器620所產生。在一實施例中，第一充電信號V_GP7,8係為第二充電信號V_GP9,10之反相邏輯信號。在另一實施例中，僅在當第二充電信號V_GP9,10為高邏輯位準，且輸出信號V₀係低於參考電壓V_ref超過某一偏移值時，第一充電信號V_GP7,8方為低邏輯位準。這種設計僅當輸出電壓V₀顯著地低於參考電壓V_ref時(意即有大輸出電容負載)，才將電容C₁平行耦接於電容C₀以提供操作電壓VDD，因而降低了電容C₁之放電功耗。 Fig. 6B is a circuit diagram showing a switched capacitor booster 600A in accordance with an embodiment of the present invention. When a switched capacitor booster is used to generate the operating voltage VDD, if the output capacitive load is quite large, because the capacitor C ₀ may not provide sufficient charge to the output capacitive load, the output signal _Vo may not reach the desired reference voltage. The second voltage level of V _ref . Compared with the switched capacitor booster 600 in FIG. 6A, the switched capacitor booster 600A further includes a capacitor adjusting circuit 610 and a charging controller 620. The capacitance adjusting circuit 610 includes a P-type transistor pair MP7 and MP8, and the first end and the second end of the capacitor C _{0 are} coupled according to the first charging signal V _{GP7, 8} coupled to the P-type transistors MP7 and MP8. The drains of the P-type transistors MP7 and MP8 are respectively coupled to the first end and the second end of the capacitor C ₁ (coupled to the sources of the P-type transistors MP7 and MP8, respectively). The capacitance adjusting circuit 610 further includes a P-type transistor pair MP9 and MP10, which respectively connect the first end of the capacitor C _{1 according to} the second charging signal V _{GP9, 10} coupled to one of the P-type transistors MP9 and MP10. The second end is coupled to the input stage voltage VEE and ground. P-type transistor MP9 having a source terminal coupled to the input voltage level VEE, and a drain terminal coupled to a first terminal of the capacitor C _1, and the P-type transistor MP10 having a source terminal coupled to a first capacitance C ₁ of The two ends, and one turn, are extremely coupled to the ground. Therefore, when the first charging signal V _GP7,8 is at a low logic level, the P-type transistor pairs the capacitor C ₁ and the capacitor C _{0 in} parallel with the MP7 and MP8 (thus increasing the capacitance value of the overall operating voltage VDD) And the stored charge), and when the second charging signal V _{GP9, 10} is at a low logic level, the P-type transistor charges the capacitor C ₁ to a voltage difference of one of the input stage voltages VEE (ie, the first voltage) Level). The first charging signal V _GP7,8 and the second charging signal V _GP9,10 are both generated by the charge controller 620. In one embodiment, the first charging signal V _GP7,8 is an inverted logic signal of the second charging signal V _GP9,10 . In another embodiment, the first charging signal V _{GP7 is} only when the second charging signal V _{GP9, 10} is at a high logic level and the output signal V ₀ is lower than the reference voltage V _{ref by} more than a certain offset value. _{, 8} squares are low logic levels. This design only connects the capacitor C _{1 in} parallel with the capacitor C ₀ to provide the operating voltage VDD when the output voltage V _{0 is} significantly lower than the reference voltage V _ref (meaning that there is a large output capacitive load), thus reducing the capacitance. C ₁ discharge power consumption.

請參考第6B圖，在一實施例中，充電控制器620包括邏輯閘621、622、631及632、比較器623、以及時序延遲電路641、642及643。對於本發明領域之技術人員來說，當了解時序延遲電路641~643可用許多方式來實現，且可為可在其輸入端及輸出端的信號之間提供延遲的任何電路。時序延遲電路641~643係依序串聯耦接，且時序延遲電路641接收輸入信號V_i為其輸入。邏輯輯631可為一及閘(AND Gate)，其具有一輸出端、一第一輸入端以接收輸入信號V_i之反相信號、以及一第二輸入端以接收來自時序延遲電路641之輸出(即具有1單位時間延遲的輸入信號V_i)。邏輯閘632可為一及閘(AND Gate)，其具有一輸出端、一第一輸入端以接收來自時序延遲電路642之輸出(即具有2單位時間延遲的輸入信號V_i)、以及一第二輸入端以接收來自時序延遲參數643之輸出(具有3單位時間延遲的輸入信號V_i)。在一實施例中，邏輯閘632更包括一第三輸入端以接收一控制信號V_C，其中當該控制信號為低邏輯位準，在輸入信號V_i之各週期的期間，電容C₁會被充電/放電1次。當該控制信號V_C為高邏輯位準(或是當沒有第三輸入接收該控制信號V_C)，在輸入信號V_i之各週期的期間，電容C₁會被充電/放電2 次。邏輯閘622可為一或閘(OR Gate)，其具有一輸出端用以產生該第二充電信號V_GP9,10、一第一輸入耦接至邏輯閘631之輸出端、以及一第二輸入端耦接至邏輯閘632之輸出端。比較器623係具有一偏移值(例如0.05V)，並且包括一第一輸入端耦接至參考電壓V_ref(例如1.2V)、一第二輸入端耦接至輸出信號V_o、以及一輸出端。當輸出信號V_o係小於參考電壓超過該偏移值時(例如V_o<1.15V)，比較器623之輸出端可輸出高邏輯狀態，反之則輸出低邏輯狀態。邏輯閘621可為一反及閘(NAND Gate)，其具有一輸出端用以產生該第一充電信號V_GP7,8、一第一輸入端耦接至邏輯閘622之輸出端、以及一第二輸入端耦接至比較器623之輸出端。 Referring to FIG. 6B, in an embodiment, the charge controller 620 includes logic gates 621, 622, 631, and 632, a comparator 623, and timing delay circuits 641, 642, and 643. It will be apparent to those skilled in the art that the timing delay circuits 641-643 can be implemented in a number of ways and can be any circuit that provides a delay between the signals at its input and output. Timing delay lines 641 to 643 are sequentially coupled in series circuit, a delay circuit 641 receives the timing and V _i is its input. The logic set 631 can be an AND gate having an output, a first input for receiving an inverted signal of the input signal V _i , and a second input for receiving an output from the timing delay circuit 641 (ie, input signal V _i with 1 unit time delay). The logic gate 632 can be an AND gate having an output terminal, a first input terminal for receiving an output from the timing delay circuit 642 (ie, an input signal V _i having a delay of 2 units), and a first The two inputs receive the output from the timing delay parameter 643 (the input signal V _i having a 3 unit time delay). In an embodiment, the logic gate 632 further includes a third input terminal for receiving a control signal V _C , wherein when the control signal is a low logic level, during each period of the input signal V _i , the capacitor C ₁ It is charged/discharged once. When the control signal V _C to a high logic level (or when no input receiving the third control signal V _C), during each period V _i is the input of the capacitance C ₁ is charged / discharged twice. The logic gate 622 can be an OR gate having an output for generating the second charging signal V _GP9 , 10, a first input coupled to the output of the logic gate 631, and a second input The terminal is coupled to the output of the logic gate 632. The comparator 623 has an offset value (for example, 0.05 V), and includes a first input coupled to the reference voltage V _ref (eg, 1.2 V), a second input coupled to the output signal V _o , and a Output. When the output signal _Vo is less than the reference voltage exceeding the offset value (eg, V _o < 1.15V), the output of the comparator 623 can output a high logic state, and vice versa. The logic gate 621 can be a NAND gate having an output for generating the first charging signal V _GP7,8 , a first input coupled to the output of the logic gate 622, and a first The two inputs are coupled to the output of the comparator 623.

第6C圖係顯示依據本發明一實施例中當比較器623輸出高邏輯狀態時之主要邏輯閘的輸出及充電信號的波形圖。請參考第6C圖可得知當控制信號V_C為低邏輯狀態時，在輸入信號V_i之各週期的期間，電容C₁會被充電/放電1次，且當控制信號為高邏輯狀態時，在輸入信號V_i之各週期的期間，電容C₁會被充電/放電2次。當電容C₁在每個週期被充電/放電超過1次，電容C₁會提供更多的電荷至輸出電容負載，因此可大幅增加驅動能力。藉由同樣地增加串聯的時序延遲電路及邏輯閘(即邏輯閘632)的數量，在輸入信號V_i之各週期的期間，充電控制器620可用以充電/放電超過2次。在另一實施例中，若電容C₁在各週期中僅需要被充電/放電1次，時序延遲電路642及643、以及邏輯閘622及632則可被移除，且邏輯閘621之第一輸入端可耦接至邏輯閘631(其用以產生第二充電信號V_GP9,10)之輸出。在一些實施例中，比較器623可被移除，且邏輯閘621可為一反相器，其具有一輸入端耦接至邏輯閘622之輸出、以及一輸出端用以產生該第一充電信號V_GP7,8(即第一充電信號V_GP7,8為第二充電信號V_GP9,10之反相信號)。在此實施例中，不管輸出信號V_o及參考電壓V_ref之電壓位準為何，電容C₁皆係平行耦接於電容C₀以提供操作電壓VDD。 Figure 6C is a waveform diagram showing the output of the main logic gate and the charging signal when the comparator 623 outputs a high logic state in accordance with an embodiment of the present invention. Referring to FIG. 6C, it can be seen that when the control signal V _C is in a low logic state, the capacitor C ₁ is charged/discharged once during each period of the input signal V _i , and when the control signal is in a high logic state. During the periods of the input signal V _i , the capacitor C ₁ is charged/discharged twice. When the capacitor C ₁ is charged/discharged more than once per cycle, the capacitor C ₁ provides more charge to the output capacitive load, thus greatly increasing the driving capability. By increasing the number of the same timing delay circuits connected in series and a logic gate (i.e., logic gate 632), and during each period V _i is the input of the charge controller 620 may be used to charge / discharge more than 2 times. In another embodiment, if the capacitor C ₁ only needs to be charged/discharged once in each cycle, the timing delay circuits 642 and 643 and the logic gates 622 and 632 can be removed, and the first of the logic gates 621 The input can be coupled to an output of a logic gate 631 (which is used to generate a second charging signal V _{GP9, 10} ). In some embodiments, the comparator 623 can be removed, and the logic gate 621 can be an inverter having an input coupled to the output of the logic gate 622 and an output for generating the first charge. Signal V _GP7,8 (ie, the first charging signal V _GP7,8 is the inverted signal of the second charging signal V _GP9,10 ). In this embodiment, regardless of the voltage level of the output signal V _o and the reference voltage V _ref , the capacitor C ₁ is coupled in parallel to the capacitor C ₀ to provide the operating voltage VDD.

第7圖係顯示依據本發明第6A圖之實施例中操作電壓VDD、輸入信號V_i、及輸出信號V_o隨著時間變化關係的波形圖。在此實施例中，第一電壓位準為1V，且第二電壓位準為1.2V。如第7圖所示，當輸入信號V_i具有1V的高邏輯位準，操作電壓VDD會被充電至1V；然而，因為輸出信號V_o具有0V之低邏輯位準，故不會***作電壓VDD之實際電壓位準所影響。當輸入信號V_i具有0V之低邏輯位準時，操作電壓VDD會被升壓至接近1V的2倍(即2V)。因為電荷會由電容C₀流動至驅動電路100，操作電壓VDD之實際電壓位準約為1.6V至1.8V，其電壓位準已足夠高讓驅動電路100正常運作，可由輸出信號V_o之1.2V的高邏輯位準之波形得到確認。 Figure 7 is a waveform diagram showing the relationship of the operating voltage VDD, the input signal V _i , and the output signal V _o as a function of time in the embodiment of Figure 6A of the present invention. In this embodiment, the first voltage level is 1V and the second voltage level is 1.2V. As shown in Figure 7, when the input signal V _i has a high logic level of 1V, the operating voltage VDD will be charged to 1V; however, because the output signal _Vo has a low logic level of 0V, it will not be operated. The actual voltage level of VDD is affected. When the input signal V _i has a low logic level of 0V, the operating voltage VDD is boosted to approximately 2 times (ie, 2V). Since the charge flows from the capacitor C ₀ to the driving circuit 100, the actual voltage level of the operating voltage VDD is about 1.6V to 1.8V, and the voltage level is high enough for the driving circuit 100 to operate normally, which can be 1.2 by the output signal V _o . The waveform of the high logic level of V is confirmed.

綜上所述，本發明係揭露一種驅動電路，其可提供不同於複數操作電壓之電壓位準。因為本發明之驅動電路的電路設計已經簡化，與傳統的驅動電路相比，本發明之驅動電路可降低面積及功率消耗。 In summary, the present invention discloses a driving circuit that can provide a voltage level different from a complex operating voltage. Since the circuit design of the driving circuit of the present invention has been simplified, the driving circuit of the present invention can reduce the area and power consumption as compared with the conventional driving circuit.

本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. Retouching The scope of the present invention is defined by the scope of the appended claims.

100‧‧‧驅動電路 100‧‧‧ drive circuit

110‧‧‧位準調節器 110‧‧‧ level regulator

120‧‧‧差動放大器 120‧‧‧Differential Amplifier

130‧‧‧輸出級 130‧‧‧Output level

V_i‧‧‧輸入信號 V _i ‧‧‧ input signal

V_o‧‧‧輸出信號 V _o ‧‧‧ output signal

V_r‧‧‧參考信號 V _r ‧‧‧ reference signal

+、-‧‧‧輸入端 +, -‧‧‧ input

Claims

一種驅動電路，用以依據來自具有一第一電壓位準之一輸入級電壓所產生的一輸入信號及具有第二電壓位準之一參考電壓產生一輸出信號，該驅動電路包括：一差動放大器，具有一第一輸入端耦接至該參考電壓、一第二輸入端耦接至該輸出信號、以及一輸出端，其中該差動放大器係由具有一第三電壓位準之一操作電壓供電；一輸出級，耦接至該差動放大器之該第二輸入端及該輸出端，用以接收該輸入信號及該操作電壓以產生該輸出信號，其中該第二輸入端係依據該輸入信號耦接至該差動放大器之該輸出端，其中該第一電壓位準係低於該第三電壓位準，且該第二電壓位準係介於該第一電壓位準及該第三電壓位準之間。 a driving circuit for generating an output signal according to an input signal generated from an input stage voltage having a first voltage level and a reference voltage having a second voltage level, the driving circuit comprising: a differential An amplifier having a first input coupled to the reference voltage, a second input coupled to the output signal, and an output, wherein the differential amplifier is operated by a voltage having a third voltage level An output stage coupled to the second input end of the differential amplifier and the output end for receiving the input signal and the operating voltage to generate the output signal, wherein the second input is based on the input The signal is coupled to the output of the differential amplifier, wherein the first voltage level is lower than the third voltage level, and the second voltage level is between the first voltage level and the third Between voltage levels.

如申請專利範圍第1項所述之驅動電路，其中該輸出級包括：一第一N型電晶體，具有一閘極端耦接至該差動放大器之該輸出端、一汲極端耦接至該操作電壓、以及一源極端耦接至該差動放大器之該第二輸入端；一第二N型電晶體，具有一閘極端耦接至該輸入信號，一汲極端耦接至該差動放大器之該第二輸入端、以及一源極端耦接至地；以及一第五N型電晶體，具有一閘極端耦接至該輸入信號、一汲極端耦接至該差動放大器之該輸出端、以及一源極端耦接至地，其中該輸出信號係在該差動放大器之該第二輸入端所產生。 The driving circuit of claim 1, wherein the output stage comprises: a first N-type transistor having a gate terminal coupled to the output terminal of the differential amplifier, and a terminal coupled to the terminal An operating voltage and a source terminal are coupled to the second input end of the differential amplifier; a second N-type transistor having a gate terminal coupled to the input signal and a terminal coupled to the differential amplifier The second input terminal and the source terminal are coupled to the ground; and a fifth N-type transistor having a gate terminal coupled to the input signal and a terminal coupled to the output terminal of the differential amplifier And a source is extremely coupled to the ground, The output signal is generated at the second input of the differential amplifier.

如申請專利範圍第2項所述之驅動電路，其中該輸出級更包括：一第四P型電晶體，具有一閘極端耦接至該輸入信號、一汲極端耦接至該差動放大器之該第二輸入端、以及一源極端耦接至該第一N型電晶體之該源極端。 The driving circuit of claim 2, wherein the output stage further comprises: a fourth P-type transistor having a gate terminal coupled to the input signal and a terminal coupled to the differential amplifier The second input terminal and a source terminal are coupled to the source terminal of the first N-type transistor.

如申請專利範圍第2項所述之驅動電路，其中該輸出級更包括：一第八N型電晶體，具有一閘極端及一汲極端均耦接至該差動放大器之該輸出端、以及一源極端耦接至該第五N型電晶體之該汲極端。 The driving circuit of claim 2, wherein the output stage further comprises: an eighth N-type transistor having a gate terminal and a terminal coupled to the output of the differential amplifier, and A source is coupled to the 汲 terminal of the fifth N-type transistor.

如申請專利範圍第1項所述之驅動電路，其中該差動放大器包括：一第一P型電晶體，具有一閘極端耦接至該第一P型電晶體之一汲極端、以及一源極端耦接至該操作電壓；一第二P型電晶體，具有一閘極端耦接至該第一P型電晶體之該閘極端、一源極端耦接至該操作電壓、以及一汲極端；一第六N型電晶體，具有一汲極端耦接至該第一P型電晶體之該汲極端、一源極端、以及一閘極端；以及一第七N型電晶體，具有一汲極端耦接至該第二P型電晶體之該汲極端、一源極端耦接至該第六N型電晶體之該源極端、以及一閘極端，其中該第六N型電晶體之該閘極端為該差動放大器之該第一輸入端，該第七N型電晶體之該閘極端係該差動放大器之該第二輸入端，且該第二P型電晶體之該汲極端為該差動放大器之該輸出端。 The driving circuit of claim 1, wherein the differential amplifier comprises: a first P-type transistor having a gate terminal coupled to one of the first P-type transistors, and a source Extremely coupled to the operating voltage; a second P-type transistor having a gate terminal coupled to the gate terminal of the first P-type transistor, a source terminal coupled to the operating voltage, and a drain terminal; a sixth N-type transistor having a 汲 terminal coupled to the 汲 terminal, a source terminal, and a gate terminal of the first P-type transistor; and a seventh N-type transistor having a 汲 extreme coupling Connecting to the NMOS terminal of the second P-type transistor, a source terminal coupled to the source terminal of the sixth N-type transistor, and a gate terminal, wherein the gate terminal of the sixth N-type transistor is The difference of the differential amplifier An input terminal, the gate terminal of the seventh N-type transistor is the second input end of the differential amplifier, and the drain terminal of the second P-type transistor is the output terminal of the differential amplifier.

如申請專利範圍第5項所述之驅動電路，其中該差動放大器更包括：一第三N型電晶體，具有一閘極端耦接至一偏壓電壓、一汲極端耦接至該第六N型電晶體之該源極端、以及一源極端耦接至地，其中該第三N型電晶體之之開啟/關閉係依據該偏壓電壓，進而控制該差動放大器之開啟/關閉。 The driving circuit of claim 5, wherein the differential amplifier further comprises: a third N-type transistor having a gate terminal coupled to a bias voltage and a terminal coupled to the sixth The source terminal of the N-type transistor and the source terminal are coupled to the ground, wherein the opening/closing of the third N-type transistor is based on the bias voltage, thereby controlling the opening/closing of the differential amplifier.

如申請專利範圍第5項所述之驅動電路，其中該差動放大器更包括：一電流源，耦接於該第六N型電晶體之該源極端之地之間。 The driving circuit of claim 5, wherein the differential amplifier further comprises: a current source coupled between the ground of the source terminal of the sixth N-type transistor.

如申請專利範圍第1項所述之驅動電路，其中該參考電壓係由一帶差電壓參考電路所產生。 The driving circuit of claim 1, wherein the reference voltage is generated by a differential voltage reference circuit.

如申請專利範圍第1項所述之驅動電路，更包括：一位準調節器，耦接至該差動放大器，用以接收該參考電壓及該輸入信號以產生一參考信號，其中該差動放大器之該第一輸入端係耦接至該參考信號。 The driving circuit of claim 1, further comprising: a quasi-regulator coupled to the differential amplifier for receiving the reference voltage and the input signal to generate a reference signal, wherein the differential signal The first input of the amplifier is coupled to the reference signal.

如申請專利範圍第9項所述之驅動電路，其中該位準調節器包括：一第三P型電晶體，具有一源極端耦接至該參考電壓、一閘極端耦接至該輸入信號、以及一汲極端耦接至該參考信號；以及一第四N型電晶體，具有一源極端耦接至地、一閘極端耦接至該輸入信號、以及一汲極端耦接至該參考信號。 The driving circuit of claim 9, wherein the level regulator comprises: a third P-type transistor having a source terminal coupled to the reference voltage, a gate terminal coupled to the input signal, And an extreme coupling to the reference signal; A fourth N-type transistor has a source terminal coupled to the ground, a gate terminal coupled to the input signal, and a terminal coupled to the reference signal.

如申請專利範圍第1項所述之驅動電路，其中該操作電壓係依據該輸入信號及該輸入級電壓所產生。 The driving circuit of claim 1, wherein the operating voltage is generated according to the input signal and the input stage voltage.

如申請專利範圍第11項所述之驅動電路，其中該操作電壓係由一切換式電容升壓器所產生，且該切換式電容升壓器包括：一第九N型電晶體，具有一閘極端耦接至該輸入信號、一汲極端、以及一源極端耦接至地；一第五P型電晶體，具有一閘極端耦接至該第九N型電晶體之該汲極端、一源極端耦接至一第一電容之一第一端、以及一汲極端耦接至該輸入級電壓；以及一第六P型電晶體，具有一閘極端耦接至該輸入信號、一汲極端耦接至該第九N型電晶體之該汲極端、以及一源極端耦接至該第一電容之該第一端，其中該第一電容之該第二端係耦接至該輸入信號之一反相信號，且該操作電壓係在該第一電容之該第一端所產生。 The driving circuit of claim 11, wherein the operating voltage is generated by a switched capacitor booster, and the switched capacitor booster comprises: a ninth N-type transistor having a gate Extremely coupled to the input signal, a terminal, and a source terminal coupled to the ground; a fifth P-type transistor having a gate terminal coupled to the terminal of the ninth N-type transistor, a source An extreme coupling is coupled to a first end of a first capacitor, and a terminal is coupled to the input stage voltage; and a sixth P-type transistor having a gate terminal coupled to the input signal, and an extreme coupling Connecting to the first terminal of the ninth N-type transistor, and a source terminal coupled to the first end of the first capacitor, wherein the second end of the first capacitor is coupled to one of the input signals Inverting the signal, and the operating voltage is generated at the first end of the first capacitor.

如申請專利範圍第12項所述之驅動電路，其中該切換式電容升壓器更包括：一第七P型電晶體，具有一閘極端耦接至一第一充電信號、一汲極端耦接至該第一電容之該第一端、以及一源極端耦接至一第二電容之一第一端；一第八P型電晶體，具有一閘極端耦接至該第一充電信號、一汲極端耦接至該第一電容之該第二端、以及一源極端耦接至該第二電容之一第二端；一第九P型電晶體，具有一閘極端耦接至一第二充電信號、一汲極端耦接至該第二電容之該第一端、以及一源極端耦接至該輸入級電壓；以及一第十P型電晶體，具有一閘極端耦接至該第二充電信號、一汲極端耦接至地、以及一源極端耦接至該第二電容之該第二端。 The driving circuit of claim 12, wherein the switching capacitor booster further comprises: a seventh P-type transistor having a gate terminal coupled to a first charging signal and an extreme coupling The first end of the first capacitor and a source terminal are coupled to a first end of a second capacitor; an eighth P-type transistor having a gate terminal coupled to the first charging signal,汲 Extremely coupled to the second end of the first capacitor, and a source extreme coupling Connected to a second end of the second capacitor; a ninth P-type transistor having a gate terminal coupled to a second charging signal, a first terminal coupled to the second capacitor, and a source terminal is coupled to the input stage voltage; and a tenth P-type transistor having a gate terminal coupled to the second charging signal, a terminal coupled to the ground, and a source terminal coupled to the first The second end of the second capacitor.

如申請專利範圍第13項所述之驅動電路，其中該第一充電信號為該第二充電信號之一反相信號。 The driving circuit of claim 13, wherein the first charging signal is an inverted signal of the second charging signal.

如申請專利範圍第14項所述之驅動電路，其中該切換式電容升壓器更包括：一第一邏輯閘，具有一第一輸入端用以接收該輸入信號之該反相信號、一第二輸入端用以接收具有一單位時間延遲的該輸入信號、以及一輸出端用以產生該第二充電信號。 The driving circuit of claim 14, wherein the switching capacitor booster further comprises: a first logic gate having a first input terminal for receiving the inverted signal of the input signal, a first The two inputs are for receiving the input signal having a unit time delay, and an output for generating the second charging signal.

如申請專利範圍第14項所述之驅動電路，其中該切換式電容升壓器更包括：一第一邏輯閘，具有一第一輸入端用以接收該輸入信號之該反相信號、一第二輸入端用以接收具有1個單位時間延遲的該輸入信號、以及一輸出端；一第二邏輯閘、具有一第一輸入端用以接收具有2個單位時間延遲之該輸入信號的該反相信號、一第二輸入端用以接收具有3個單位時間延遲的該輸入信號、以及一輸出端；以及一第三邏輯閘，具有一第一輸入端耦接至該第一邏輯閘之該輸出端、一第二輸入端耦接收該第二邏輯閘之該輸出端、以及一輸出端用以產生該第二充電信號。 The driving circuit of claim 14, wherein the switching capacitor booster further comprises: a first logic gate having a first input terminal for receiving the inverted signal of the input signal, a first The second input terminal is configured to receive the input signal having a unit time delay, and an output terminal; a second logic gate having a first input terminal for receiving the inverse of the input signal having 2 unit time delays a phase signal, a second input terminal for receiving the input signal having a delay of 3 unit time, and an output terminal; and a third logic gate having a first input terminal coupled to the first logic gate The output terminal, a second input terminal coupled to receive the output of the second logic gate, and an output terminal for generating the second charging signal.

如申請專利範圍第16項所述之驅動電路，其中該第二邏輯閘更包括一第三輸入端用以接收一控制信號，其中當該控制信號為低邏輯狀態，在該輸入信號之各週期的期間該第二電容係被充電/放電1次，且當該控制信號為高邏輯狀態時，在該輸入信號之各週期的期間，該第二電容係被充電/放電2次。 The driving circuit of claim 16, wherein the second logic gate further comprises a third input terminal for receiving a control signal, wherein when the control signal is in a low logic state, in each cycle of the input signal The second capacitor is charged/discharged once during the period, and when the control signal is in the high logic state, the second capacitor is charged/discharged twice during each period of the input signal.

如申請專利範圍第13項所述之驅動電路，其中僅當該第二充電信號為高邏輯狀態且該輸出信號係低於該參考電壓超過一偏移值時，該第一充電信號為低邏輯狀態。 The driving circuit of claim 13, wherein the first charging signal is low logic only when the second charging signal is in a high logic state and the output signal is lower than the reference voltage by an offset value. status.

如申請專利範圍第18項所述之驅動電路，其中該切換式電容升壓器更包括：一第一邏輯閘，具有一第一輸入端用以接收該輸入信號之該反相信號、一第二輸入端用以接收具有1個單位時間延遲的該輸入信號、以及一輸出端用以產生該第二充電信號；一比較器，具有一第一輸入端耦接至該參考電壓、一第二輸入端耦接收該輸出信號、以及一輸出端；以及一第四邏輯閘，具有一第一輸入端耦接至該第一邏輯閘之該輸出端、一第二輸入端耦接至該比較器之該輸出端、以及一輸出端用以產生該第一充電信號，其中當該輸出信號低於該參考電壓超過該偏移值時，該比較器之該輸出端係輸出高邏輯狀態，其中當該輸出信號未低於該參考電壓超過該偏移值時，該比較器之該輸出端係輸出低邏輯狀態。 The driving circuit of claim 18, wherein the switching capacitor booster further comprises: a first logic gate having a first input terminal for receiving the inverted signal of the input signal, a first The second input terminal is configured to receive the input signal having a unit time delay, and an output terminal is configured to generate the second charging signal; a comparator having a first input end coupled to the reference voltage and a second The input terminal is coupled to receive the output signal, and an output terminal; and a fourth logic gate having a first input end coupled to the output end of the first logic gate and a second input end coupled to the comparator The output end and an output end are configured to generate the first charging signal, wherein when the output signal is lower than the reference voltage, the output of the comparator outputs a high logic state, wherein When the output signal is not lower than the reference voltage exceeds the offset value, the The output of the comparator outputs a low logic state.

如申請專利範圍第18項所述之驅動電路，其中該切換式電容升壓器更包括：一第一邏輯閘，具有一第一輸入端用以接收該輸入信號之該反相信號、一第二輸入端用以接收具有1個單位時間延遲的該輸入信號、以及一輸出端；一第二邏輯閘，具有一第一輸入端用以接收具有2個單位時間延遲的該輸入信號之該反相信號、一第二輸入端用以接收具有3個單位時間延遲的該輸入信號、以及一輸出端；一第三邏輯閘，具有一第一輸入端耦接至該第一邏輯閘之該輸出端、一第二輸入端耦接至該第二邏輯閘之該輸出端、以及一輸出端用以產生該第二充電信號；一比較器，具有一第一輸入端耦接至該參考電壓、一第二輸入端耦接至該輸出信號、以及一輸出端；以及一第四邏輯閘，具有一第一輸入端耦接至該第三邏輯閘之該輸出端，一第二輸入端耦接至該比較器之該輸出端、以及一輸出端用以產生該第一充電信號，其中當該輸出信號低於該參考電壓超過該偏移值時，該比較器之該輸出端係輸出高邏輯狀態，其中當該輸出信號未低於該參考電壓超過該偏移值時，該比較器之該輸出端係輸出低邏輯狀態。 The driving circuit of claim 18, wherein the switching capacitor booster further comprises: a first logic gate having a first input terminal for receiving the inverted signal of the input signal, a first The second input terminal is configured to receive the input signal having a unit time delay, and an output terminal; a second logic gate having a first input terminal for receiving the inverse of the input signal having 2 unit time delays a phase signal, a second input terminal for receiving the input signal having a delay of 3 unit time, and an output terminal; a third logic gate having a first input terminal coupled to the output of the first logic gate a second input end coupled to the output end of the second logic gate, and an output end for generating the second charging signal; a comparator having a first input coupled to the reference voltage, a second input terminal is coupled to the output signal and an output terminal; and a fourth logic gate having a first input end coupled to the output end of the third logic gate, and a second input end coupled To the comparator And the output end is configured to generate the first charging signal, wherein when the output signal is lower than the reference voltage, the output of the comparator outputs a high logic state, wherein the output signal When the reference voltage does not fall below the offset value, the output of the comparator outputs a low logic state.

如申請專利範圍第20項所述之驅動電路，其中該第二邏輯閘更包括一第三輸入端用以接收一控制信號，其中當該控制信號為低邏輯狀態，在該輸入信號之各週期的期間，該第二電容係被充電/放電1次，且當該控制信號為高邏輯狀態，在該輸入信號之各週期的期間，該第二電容係被充電/放電2次。 The driving circuit of claim 20, wherein the second logic gate further comprises a third input terminal for receiving a control signal, wherein when the control signal is in a low logic state, in each cycle of the input signal During the period The second capacitor is charged/discharged once, and when the control signal is in a high logic state, the second capacitor is charged/discharged twice during each period of the input signal.