TW201442231A - An integrated structure - Google Patents

Abstract

An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate.

Description

整合結構Integrated structure

本發明係關於一種整合結構，尤其係關於一種具有貫穿矽通孔的整合結構。The present invention relates to an integrated structure, and more particularly to an integrated structure having through-through holes.

為了節省寶貴的佈局空間或是增加內連線的效率，可將複數個積體電路(IC)晶片堆疊在一起成為一個IC封裝結構。為了達到此目的，可使用一種三維(3D)堆疊封裝技術來將複數積體電路晶片封裝在一起。此種三維(3D)堆疊封裝技術廣泛地使用到貫穿矽通孔(TSV)。貫穿矽通孔(TSV)是一種垂直導電通孔，其可以完全貫穿矽晶圓、矽板、任何材料所製成之基板或晶片。現今，3D積體電路(3D IC)被廣用至許多的領域如記憶體堆疊、影像感測晶片等。In order to save valuable layout space or increase the efficiency of interconnects, a plurality of integrated circuit (IC) chips can be stacked together to form an IC package structure. To achieve this, a three-dimensional (3D) stacked package technology can be used to package multiple integrated circuit chips together. Such three-dimensional (3D) stacked package technology is widely used to penetrate through vias (TSVs). A Through Through Hole (TSV) is a vertical conductive via that can extend completely through a wafer, a raft, or a substrate or wafer of any material. Today, 3D integrated circuits (3D ICs) are widely used in many fields such as memory stacking, image sensing wafers, and the like.

在製造具有貫穿矽通孔的積體電路時會遇到許多的整合問題，其中一個便是銅突出的問題。相較於單一的電晶體或是單一的內連線而言，貫穿矽通孔的體積是其一百倍或更大。這種尺寸的貫穿矽通孔所導致的機械應力、特性不匹配或是電性影響無法被忽視，因此需要建立一種較佳的整合技術來製造具有貫穿矽通孔的積體電路。There are many integration problems encountered in fabricating integrated circuits with through-holes, one of which is the problem of copper protrusion. The volume through the through hole is one hundred times or more compared to a single transistor or a single interconnect. The mechanical stress, characteristic mismatch or electrical influence caused by the through-hole through-hole of this size cannot be neglected, so it is necessary to establish a better integration technique to manufacture an integrated circuit having a through-hole.

提供一種整合結構，包含：基板，具有第一介電層與第二介電蓋層依序設置於其上；金屬閘極電晶體，具有設置於該基板上的高介電常數閘極介電層、嵌於該第一介電層之內的閘電極以及位於該基板內的源極/汲極；第一金屬接觸栓，貫穿該第一介電層且與該源極/汲極直接接觸；及貫穿矽通孔，貫穿該第二介電蓋層、該第一介電層與該基板。An integrated structure includes: a substrate having a first dielectric layer and a second dielectric cap layer disposed thereon; a metal gate transistor having a high dielectric constant gate dielectric disposed on the substrate a gate, a gate electrode embedded in the first dielectric layer, and a source/drain in the substrate; a first metal contact plug extending through the first dielectric layer and in direct contact with the source/drain And through the through hole, through the second dielectric cap layer, the first dielectric layer and the substrate.

100．．．基板100. . . Substrate

221．．．間隙壁221. . . Clearance wall

222．．．源極與汲極(S/D)222. . . Source and bungee (S/D)

231．．．緩衝層231. . . The buffer layer

232．．．高介電常數介電層232. . . High dielectric constant dielectric layer

233．．．功函數金屬層233. . . Work function metal layer

234．．．低電阻率填充金屬234. . . Low resistivity filler metal

250．．．電晶體250. . . Transistor

261．．．接觸洞蝕刻停止層261. . . Contact hole etch stop layer

262．．．第一層間介電層262. . . First interlayer dielectric layer

270．．．接觸栓270. . . Contact plug

272．．．第一蓋層272. . . First cover

273．．．接觸洞273. . . Contact hole

277．．．深溝渠277. . . Deep ditches

278．．．電絕緣層278. . . Electrical insulation

279．．．導電通孔279. . . Conductive through hole

280．．．過渡性貫穿矽通孔(TSV)280. . . Transitional through hole (TSV)

281．．．第三蓋層281. . . Third cover

282．．．第二蓋層282. . . Second cover

283、284．．．緩衝導電結構283, 284. . . Buffered conductive structure

283’、284’．．．緩衝導電結構283’, 284’. . . Buffered conductive structure

290_1、290_2．．．雙鑲嵌內連線結構290_1, 290_2. . . Double damascene interconnect structure

290’_1、290’_2、290’_3．．．雙鑲嵌內連線結構290’_1, 290’_2, 290’_3. . . Double damascene interconnect structure

292．．．第二層間介電層292. . . Second interlayer dielectric layer

295_1．．．導電通孔295_1. . . Conductive through hole

295’_1．．．導電通孔295’_1. . . Conductive through hole

295’_2．．．導電通孔295’_2. . . Conductive through hole

295’_3．．．導電通孔295’_3. . . Conductive through hole

295_2．．．導電通孔295_2. . . Conductive through hole

296_1．．．第一金屬(M1)層296_1. . . First metal (M1) layer

296’_1．．．第一金屬(M1)層296’_1. . . First metal (M1) layer

296’_2．．．第一金屬(M1)層296’_2. . . First metal (M1) layer

296’_3．．．第一金屬(M1)層296’_3. . . First metal (M1) layer

296_2．．．第一金屬(M1)層296_2. . . First metal (M1) layer

300．．．貫穿矽通孔300. . . Through the through hole

390_1、390_2．．．雙鑲嵌內連線結構390_1, 390_2. . . Double damascene interconnect structure

390’_1、390’_2、390’_3．．．雙鑲嵌內連線結構390’_1, 390’_2, 390’_3. . . Double damascene interconnect structure

395_1．．．導電通孔395_1. . . Conductive through hole

395’_1．．．導電通孔395’_1. . . Conductive through hole

395’_2．．．導電通孔395’_2. . . Conductive through hole

395’_3．．．導電通孔395’_3. . . Conductive through hole

395_2．．．導電通孔395_2. . . Conductive through hole

396_1．．．第一金屬(M1)層396_1. . . First metal (M1) layer

396’_1．．．第一金屬(M1)層396’_1. . . First metal (M1) layer

396’_2．．．第一金屬(M1)層396’_2. . . First metal (M1) layer

396’_3．．．第一金屬(M1)層396’_3. . . First metal (M1) layer

396_2．．．第一金屬(M1)層396_2. . . First metal (M1) layer

1000．．．較高層次之內連線層1000. . . Connection layer at a higher level

d1、d2、d3、d4、d4’、d5、d5’．．．高度/距離D1, d2, d3, d4, d4', d5, d5'. . . Height/distance

D1、D2、D1’、D2’、D1”、D1”．．．高度/距離D1, D2, D1', D2', D1", D1". . . Height/distance

熟知此項技藝者在參照附圖閱讀了下列詳細敘述後，當更瞭解本發明的上述目的與優點，其中：The above objects and advantages of the present invention will become more apparent from the written description of the appended claims.

圖1-4及5A顯示了根據本發明第一實施例之具有TSV之整合結構之製造方法的橫剖面示意圖；1-4 and 5A are cross-sectional views showing a manufacturing method of an integrated structure having a TSV according to a first embodiment of the present invention;

圖5B顯示了根據本發明第二實施例之具有TSV之整合結構的橫剖面示意圖；5B is a cross-sectional view showing an integrated structure having a TSV according to a second embodiment of the present invention;

圖6A顯示了根據本發明第三實施例之具有TSV之整合結構的橫剖面示意圖；6A is a cross-sectional view showing an integrated structure having a TSV according to a third embodiment of the present invention;

圖6B顯示了根據本發明第四實施例之具有TSV之整合結構的橫剖面示意圖；。6B is a cross-sectional view showing an integrated structure having a TSV according to a fourth embodiment of the present invention;

圖7顯示了根據本發明第一實施例之具有TSV之整合結構的最終結構示意圖。Fig. 7 is a view showing the final structure of an integrated structure having a TSV according to a first embodiment of the present invention.

下面將詳細地說明本發明的較佳實施例，舉凡本中所述的元件、元件子部、結構、材料、配置等皆可不依說明的順序或所屬的實施例而任意搭配成新的實施例，此些實施例當屬本發明之範疇。在閱讀了本發明後，熟知此項技藝者當能在不脫離本發明之精神和範圍內，對上述的元件、元件子部、結構、材料、配置等作些許之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準，且此些更動與潤飾當落在本發明之申請專利範圍內。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, the preferred embodiments of the present invention will be described in detail, and the components, components, structures, materials, configurations, and the like described herein may be arbitrarily combined into new embodiments without the order of the description or the embodiments. These embodiments are within the scope of the invention. After reading the present invention, it will be apparent to those skilled in the art that the above-described elements, components, structures, materials, configurations, etc. may be modified and retouched without departing from the spirit and scope of the invention. The scope of patent protection is subject to the definition of the scope of the patent application attached to the specification, and such modifications and refinements fall within the scope of the present invention.

本發明的實施例及圖示眾多，為了避免混淆，類似的元件係以相同或相似的標號示之。圖示意在傳達本發明的概念及精神，故圖中的所顯示的距離、大小、比例、形狀、連接關係….等皆為示意而非實況，所有能以相同方式達到相同功能或結果的距離、大小、比例、形狀、連接關係….等皆可視為等效物而採用之。The embodiments of the invention and the figures are numerous, and similar elements are denoted by the same or like numerals in order to avoid obscuring. The figures illustrate the concepts and spirit of the present invention, so that the distances, sizes, ratios, shapes, connection relationships, etc. shown in the figures are all illustrative and not actual, all of which can achieve the same function or result in the same manner. Distance, size, proportion, shape, connection relationship, etc. can be regarded as equivalents.

請參考圖1-4及5A，其顯示了根據本發明第一實施例之具有TSV之整合結構之製造方法的橫剖面概圖。如圖1中所示，提供半導體基板100。半導體基板100包含矽基板、含矽基板或絕緣層上覆矽(SOI)基板。接著，在半導體基板100上形成嵌於接觸洞蝕刻停止層261與第一層間介電層262中的高介電常數介電層金屬閘極電晶體250(此後簡稱為電晶體250)。此處的「高介電常數介電層金屬閘極電晶體」一詞係指具有金屬作為其閘電極及高介電常數(high-k)介電層作為其閘介電層的電晶體。雖然在圖1中，電晶體250似乎是由高介電常數後置及閘極後置製程所製造，但電晶體250可代表由任何製程如高介電常數前置與閘極前置製程、高介電常數前置與閘極後置製程所製造的電晶體，且電晶體250可以是P型導電電晶體或N型導電電晶體。Referring to Figures 1-4 and 5A, there are shown cross-sectional overviews of a method of fabricating an integrated structure having a TSV in accordance with a first embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a germanium substrate, a germanium-containing substrate, or an insulating layer overlying (SOI) substrate. Next, a high-k dielectric layer metal gate transistor 250 (hereinafter simply referred to as a transistor 250) embedded in the contact hole etch stop layer 261 and the first interlayer dielectric layer 262 is formed on the semiconductor substrate 100. The term "high-k dielectric layer metal gate transistor" as used herein refers to a transistor having a metal as its gate electrode and a high-k dielectric layer as its gate dielectric layer. Although transistor 250 appears to be fabricated from a high dielectric constant post and gate post process in FIG. 1, transistor 250 can represent any process such as a high dielectric constant pre- and gate pre-process, The high dielectric constant pre- and post-gate process produces a transistor, and the transistor 250 may be a P-type conductive transistor or an N-type conductive transistor.

如圖1中所示，電晶體250包含選擇性的緩衝層231、作為閘極介電層的U形高介電常數介電層232、一起作為閘電極的U形功函數金屬層233與低電阻率填充金屬234、間隙壁221及源極與汲極(S/D)222。在一較佳實施例中，選擇性的緩衝層231可以是傳統的氧化矽層以分離高介電常數介電層232與基板100。高介電常數介電層232係選自由下列者所構成的族群：氮化矽(SiN)、氮氧化矽(SiON)與金屬氧化物。金屬氧化物包含：氧化鉿(HfO₂)、氧化矽鉿(HfSiO)、氮氧化矽鉿(HfSiON)、氧化鋁(Al₂O₃)、氧化鑭 (La₂O₃)、氧化鋁鑭(LaAlO₃)、氧化鉭(Ta₂O₅)、氧化鋯(ZrO₂)、氧化矽鋯(ZrSiO₄)及氧化鉿鋯。U形功函數金屬層233可依據電晶體250的效能考量及導電類型考量而選自N型導電功函數材料(功函數介於約3.9 eV與約4.3 eV之間，如TiAl、TiAlN、ZrAl、WAl、TaAl、HfAl)、P型導電功函數材料(功函數介於約4.8 eV與約5.2 eV之間，如TiN、TaC)及中間型功函數材料(最常用的是含有雜質的TiN)。低電阻率填充金屬234可以是多層結構，其材料可選自由下列者所構成的族群：Al、Ti、Ta、W、Nb、Mo、Cu、TiN、TiC、TaN、Ti/W與Ti/TiN。在一較佳實施例中，若電晶體250為PMOS則U形功函數金屬層233包含TiN，若電晶體250為NMOS則U形功函數金屬層233包含TiAl；低電阻率填充金屬234包含鋁。間隙壁221可以是多層結構，可包含高溫氧化層(HTO)、氮化矽、氧化矽、碳化矽、氮氧化矽及/或六氯二矽烷所形成的氮化矽(HCD-SiN)。源極/汲極(S/D)222係由分佈於閘極兩側之基板中的摻質所形成。摻質的導電類型及物種則取決於電晶體250的導電類型及效能考量。此外，可使用選擇性磊晶成長(SEG)方法來形成舉升源極/汲極(未顯示於圖1中)。例如，當電晶體250為PMOS時，可使用具有鍺的磊晶矽層來形成源極/汲極222；當電晶體250為NMOS時，可使用具有碳或磷的磊晶矽層來形成源極/汲極(S/D)。應注意，為了要從電晶體250移除多餘的材料並形成全局平坦的表面，在完成圖1中所示的電晶體250之前可能會進行一或多道化學機械研磨製程。As shown in FIG. 1, the transistor 250 includes a selective buffer layer 231, a U-shaped high-k dielectric layer 232 as a gate dielectric layer, a U-shaped work function metal layer 233 as a gate electrode, and a low The resistivity fills the metal 234, the spacers 221, and the source and drain (S/D) 222. In a preferred embodiment, the selective buffer layer 231 can be a conventional hafnium oxide layer to separate the high-k dielectric layer 232 from the substrate 100. The high-k dielectric layer 232 is selected from the group consisting of tantalum nitride (SiN), niobium oxynitride (SiON), and metal oxides. Metal oxides include: hafnium oxide (HfO ₂ ), hafnium oxide (HfSiO), hafnium oxynitride (HfSiON), alumina (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), alumina lanthanum (LaAlO) ₃ ), lanthanum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), cerium zirconium oxide (ZrSiO ₄ ), and cerium zirconium oxide. The U-shaped work function metal layer 233 may be selected from an N-type conductive work function material according to the performance considerations of the transistor 250 and the conductivity type (the work function is between about 3.9 eV and about 4.3 eV, such as TiAl, TiAlN, ZrAl, WAl, TaAl, HfAl), P-type conductive work function materials (work function between about 4.8 eV and about 5.2 eV, such as TiN, TaC) and intermediate work function materials (most commonly TiN containing impurities). The low-resistivity filler metal 234 may be a multi-layered structure, and the material thereof may be selected from the group consisting of Al, Ti, Ta, W, Nb, Mo, Cu, TiN, TiC, TaN, Ti/W, and Ti/TiN. . In a preferred embodiment, if the transistor 250 is a PMOS, the U-shaped work function metal layer 233 includes TiN, and if the transistor 250 is an NMOS, the U-shaped work function metal layer 233 includes TiAl; and the low-resistivity filler metal 234 includes aluminum. . The spacer 221 may be a multi-layered structure and may include a high temperature oxide layer (HTO), tantalum nitride, hafnium oxide, tantalum carbide, niobium oxynitride, and/or hafnium nitride (HCD-SiN) formed of hexachlorodioxane. The source/drain (S/D) 222 is formed by dopants distributed in the substrates on both sides of the gate. The conductivity type and species of the dopant depend on the conductivity type and performance considerations of the transistor 250. Additionally, a selective epitaxial growth (SEG) method can be used to form the lift source/drain (not shown in Figure 1). For example, when the transistor 250 is a PMOS, an epitaxial layer having germanium may be used to form the source/drain 222; when the transistor 250 is an NMOS, an epitaxial layer having carbon or phosphorus may be used to form the source. Pole/bungee (S/D). It should be noted that in order to remove excess material from the transistor 250 and form a globally flat surface, one or more chemical mechanical polishing processes may be performed prior to completing the transistor 250 shown in FIG.

現在參考圖2，在平坦的表面上形成第一蓋層272。接著，在第一蓋層272、第一層間介電層262與接觸洞蝕刻停止層261中形成至少一接觸洞273。第一蓋層272包含一或多種選自下列者的介電材料：二氧化矽、氮化矽、以四乙氧基矽烷為前驅物所形成的氧化矽、碳化矽、氮氧化矽、碳氧化矽、氮碳氧化矽與聚合物。用以形成該至少一接觸洞273的製程包含至少一微影製程與至少一蝕刻製程。若第一蓋層272、第一層間介電層262與接觸洞蝕刻停止層261使用不同的材料，則可能需要用到一道以上的蝕刻製程。由於接觸洞(其他層也是)的尺寸與間距愈變愈小，若有必要可使用所謂的2P2E製程(即，兩道微影製程及兩道蝕刻製程)來形成接觸洞。雖然在圖2中只顯示了曝露源極/汲極222的一個接觸洞273，但此接觸洞273代表了形成在第一蓋層272、第一層間介電層262與接觸洞蝕刻停止層261中的所有接觸洞以及形成在第一蓋層272、第一層間介電層262與接觸洞蝕刻停止層261中之任一者中的任何接觸洞。例如，接觸洞可以落在電晶體250的金屬電極上並與低電阻率填充金屬234直接接觸。例如，接觸洞可以同時落在電晶體250之源極/汲極222與金屬電極兩者上並與兩者同時接觸。不只是接觸洞的位置，其形狀也不受限制。例如，接觸洞的側壁可以是筆直的或稍微傾斜。例如，為了同時接觸電晶體250之源極/汲極222與金屬電極兩者，接觸洞可以是卵形。又，在形成接觸洞273後，可以在接觸洞273的底部形成直接與源極/汲極222接觸的矽化物層(在圖2中未顯示)Referring now to Figure 2, a first cap layer 272 is formed on a flat surface. Next, at least one contact hole 273 is formed in the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer 261. The first cap layer 272 comprises one or more dielectric materials selected from the group consisting of cerium oxide, cerium nitride, cerium oxide formed by using tetraethoxy decane as a precursor, cerium carbide, cerium oxynitride, carbon oxidation. Niobium, niobium oxycarbide and polymers. The process for forming the at least one contact hole 273 includes at least one lithography process and at least one etching process. If the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer 261 use different materials, more than one etching process may be required. Since the size and spacing of the contact holes (other layers are also smaller) become smaller, if necessary, a so-called 2P2E process (i.e., two lithography processes and two etching processes) can be used to form the contact holes. Although only one contact hole 273 exposing the source/drain 222 is shown in FIG. 2, the contact hole 273 represents the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer. All of the contact holes in 261 and any contact holes formed in either of the first cap layer 272, the first interlayer dielectric layer 262, and the contact hole etch stop layer 261. For example, the contact hole can land on the metal electrode of the transistor 250 and be in direct contact with the low resistivity fill metal 234. For example, the contact holes can simultaneously land on both the source/drain 222 of the transistor 250 and the metal electrode and simultaneously contact the two. Not only the location of the contact hole, but also its shape is not limited. For example, the sidewall of the contact hole can be straight or slightly inclined. For example, to simultaneously contact both the source/drain 222 of the transistor 250 and the metal electrode, the contact hole may be oval. Further, after the contact hole 273 is formed, a vaporized layer directly contacting the source/drain 222 may be formed at the bottom of the contact hole 273 (not shown in FIG. 2).

現在參考圖3，在接觸洞273中形成一接觸栓270並在第一蓋層272上形成第二蓋層282。接著，在第二蓋層282、第一蓋層272、第一層間介電層262、接觸洞蝕刻停止層261與基板100中形成後貫穿矽通孔用的深溝渠277。接觸栓270可以下列方式形成：在基板上形成一或多種導電材料填入接觸洞273中；接著進行化學機械研磨製程以移除多餘的材料並形成全局平坦的表面。接觸栓270用的導電材料包含阻障/黏著材料與低電阻率填充材料。阻障/黏著材料可選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢、鉬、錳、銅，而其較佳地為鉭/氮化鉭或鈦/氮化鈦。低電阻率填充材料可選自鎢、銅、鋁、多晶矽，而其較佳地為鎢。第二蓋層282包含一或多種介電材料，此些介電材料可選自二氧化矽、氮化矽、以四乙氧基矽烷為前驅物所形成的氧化矽、碳化矽、氮氧化矽、碳氧化矽、氮碳氧化矽與聚合物。第二蓋層282較佳地為氮化矽或碳化矽。形成深溝渠277所用的製程包含至少一道微影製程與至少一道蝕刻製程。考慮到深溝渠277相較於尋常接觸栓(尋常接觸栓具有幾奈米至幾十奈米的直徑、幾十奈米的深度)的巨大尺寸(深溝渠277具有幾μm至幾十μm的直徑、幾μm至幾百μm 的深度)，可針對深溝渠277來客製化其微影製程所用的光阻、蝕刻製程所用的蝕刻物種與蝕刻配方。Referring now to FIG. 3, a contact plug 270 is formed in the contact hole 273 and a second cover layer 282 is formed on the first cover layer 272. Next, a deep trench 277 for the through hole is formed in the second cap layer 282, the first cap layer 272, the first interlayer dielectric layer 262, the contact hole etch stop layer 261, and the substrate 100. Contact plug 270 can be formed by forming one or more conductive materials on the substrate into contact holes 273; followed by a chemical mechanical polishing process to remove excess material and form a globally flat surface. The conductive material for the contact plug 270 comprises a barrier/adhesive material and a low resistivity filler material. The barrier/adhesive material may be selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese, copper, and is preferably tantalum/niobium nitride or titanium/titanium nitride. The low resistivity fill material may be selected from the group consisting of tungsten, copper, aluminum, polycrystalline germanium, and is preferably tungsten. The second cap layer 282 comprises one or more dielectric materials, and the dielectric materials may be selected from the group consisting of cerium oxide, cerium nitride, cerium oxide formed by using tetraethoxy decane as a precursor, cerium carbide, cerium oxynitride. , cerium oxyhydroxide, cerium oxynitride and polymers. The second cap layer 282 is preferably tantalum nitride or tantalum carbide. The process used to form the deep trenches 277 includes at least one lithography process and at least one etch process. Considering the large size of the deep trench 277 compared to the ordinary contact plug (the ordinary contact plug has a diameter of several nanometers to several tens of nanometers, a depth of several tens of nanometers) (the deep trench 277 has a diameter of several μm to several tens of μm) , a few μm to a few hundred μm depth), can be used for the deep trench 277 to customize the photoresist used in the lithography process, the etching species used in the etching process and the etching recipe.

現在參考圖4，將一電絕緣層(未顯示)形成於深溝渠277的側壁與底表面並將導電材料(未顯示)形成於深溝渠277中填滿深溝渠277。在形成電絕緣層與導電材料後，進行化學機械研磨製程以移除多餘的材料，以形成全局平坦的表面並完成包含電絕緣層278與導電通孔279的過渡性貫穿矽通孔(TSV)280。電絕緣層可藉由熱氧化製程所形成，則其不會形成在第二蓋層282、第一蓋層272、第一層間介電層262、接觸洞蝕刻停止層261的側壁及第二蓋層282的上表面上。或者，電絕緣層可藉由沈積製程如傳統的化學氣相沈積(CVD)製程、可流動化學氣相沈積(flowable CVD)、電漿增強化學氣相沈積(plasma-enhanced CVD)製程、高密度電漿化學氣相沈積(HDP CVD)製程所形成。電絕緣層可包含一或多種材料，此些材料可選自二氧化矽、氮化矽、氮氧化矽、碳化矽、碳氮化矽與聚合物。電絕緣層較佳地為單層二氧化矽層。導電通孔279所用的導電材料包含阻障/黏著材料、選擇性的晶種材料及低電阻率填充材料。阻障/黏著材料可選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢、鉬、錳與銅。選擇性的晶種材料通常與低電阻率填充材料相同，且其選自鎢、銅、鋁及多晶矽。低電阻率填充材料較佳地為電鍍製程所形成的銅而選擇性的晶種材料較佳地為物理濺鍍沈積所形成的銅。Referring now to Figure 4, an electrically insulating layer (not shown) is formed on the sidewalls and bottom surface of the deep trench 277 and a conductive material (not shown) is formed in the deep trench 277 to fill the deep trench 277. After forming the electrically insulating layer and the electrically conductive material, a chemical mechanical polishing process is performed to remove excess material to form a globally planar surface and complete a transitional through via (TSV) comprising an electrically insulating layer 278 and a conductive via 279. 280. The electrically insulating layer can be formed by a thermal oxidation process, and is not formed on the second cap layer 282, the first cap layer 272, the first interlayer dielectric layer 262, the sidewalls of the contact hole etch stop layer 261, and the second layer. On the upper surface of the cover layer 282. Alternatively, the electrically insulating layer can be formed by a deposition process such as a conventional chemical vapor deposition (CVD) process, a flowable CVD process, a plasma-enhanced CVD process, and a high density. Formed by a plasma chemical vapor deposition (HDP CVD) process. The electrically insulating layer may comprise one or more materials selected from the group consisting of cerium oxide, cerium nitride, cerium oxynitride, cerium carbide, cerium carbonitride and a polymer. The electrically insulating layer is preferably a single layer of hafnium oxide. The conductive material used for the conductive vias 279 comprises a barrier/adhesive material, a selective seed material, and a low resistivity fill material. The barrier/adhesive material may be selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese, and copper. The selective seed material is typically the same as the low resistivity fill material and is selected from the group consisting of tungsten, copper, aluminum, and polysilicon. The low resistivity fill material is preferably copper formed by an electroplating process and the selective seed material is preferably copper formed by physical sputter deposition.

在圖4中，很清楚地可以看到，由於第一蓋層272的厚度，所以電晶體250的高度d1(從基板100之上表面到低電阻率填充金屬234之上表面間的距離)係小於接觸栓270之高度d2 (從基板100之上表面到接觸栓270的上表面)。亦可以清楚的看到，由於第二蓋層282的厚度，所以接觸栓270之高度d2係小於過渡性貫穿矽通孔280在基板之上的高度d3(從基板100之上表面到過渡性貫穿矽通孔280之上表面間的距離)。In FIG. 4, it is clear that the height d1 of the transistor 250 (the distance from the upper surface of the substrate 100 to the upper surface of the low-resistivity filler metal 234) is due to the thickness of the first cap layer 272. It is smaller than the height d2 of the contact plug 270 (from the upper surface of the substrate 100 to the upper surface of the contact plug 270). It can also be clearly seen that due to the thickness of the second cap layer 282, the height d2 of the contact plug 270 is smaller than the height d3 of the transition through the via hole 280 above the substrate (from the upper surface of the substrate 100 to the transition through) The distance between the upper surfaces of the through holes 280).

現在參考圖5A，形成第二層間介電層292覆蓋第二蓋層282與過渡性貫穿矽通孔280，然後在第二層間介電層292之中形成雙鑲嵌內連線結構290_1與290_2。第二層間介電層292可以是多層結構，其可包含由四乙氧基矽烷為前驅物所形成的二氧化矽、碳化矽、氮化矽、氮氧化矽、碳氮化矽及/或低介電常數介電材料。低介電常數介電材料可選自摻雜氟的二氧化矽、摻雜碳的二氧化矽、多孔性二氧化矽、多孔性摻雜碳的二氧化矽、旋塗有機聚合物、矽氧樹脂系的有機聚合物。雙鑲嵌內連線結構290_1係由一體成形的導電通孔295_1與第一金屬(M1)層296_1所構成，並與接觸栓270直接接觸。雙鑲嵌內連線結構290_2係由一體成形的複數導電通孔295_2(在圖5A中顯示了四個)與第一金屬(M1)層296_2所構成，並與過渡性貫穿矽通孔280直接接觸。雙鑲嵌內連線結構所用的材料包含了阻障/黏著材料與低電阻率填充材料。阻障/黏著材料可選自鉭、氮化鉭、鈦、氮化鈦、鎢、氮化鎢、鉬、錳與銅，而其較佳的是鉭/氮化鉭或鈦/氮化鈦。低電阻率填充材料可選自鎢、銅、鋁及多晶矽，而其較佳的是銅。雙鑲嵌內連線結構290_1與290_2可藉由下列方式形成：在第二層間介電層292中形成通孔與溝渠；在基板上形成阻障/黏著材料與低電阻率填充材料而填充該通孔與溝渠；及進行化學機械研磨製程以移除多餘的材料並形成全局平坦的表面。Referring now to FIG. 5A, a second interlayer dielectric layer 292 is formed overlying the second cap layer 282 and the transition through vias 280, and then dual damascene interconnect structures 290_1 and 290_2 are formed in the second interlayer dielectric layer 292. The second interlayer dielectric layer 292 may be a multi-layer structure, which may include cerium oxide, tantalum carbide, tantalum nitride, hafnium oxynitride, niobium carbonitride, and/or low formed by tetraethoxy decane as a precursor. Dielectric constant dielectric material. The low-k dielectric material may be selected from fluorine-doped ceria, carbon-doped ceria, porous ceria, porous doped ceria, spin-on organic polymer, helium oxygen Resin-based organic polymer. The dual damascene interconnect structure 290_1 is composed of an integrally formed conductive via 295_1 and a first metal (M1) layer 296_1 and is in direct contact with the contact plug 270. The dual damascene interconnect structure 290_2 is formed by integrally forming a plurality of conductive vias 295_2 (four shown in FIG. 5A) and a first metal (M1) layer 296_2, and is in direct contact with the transition through vias 280. . The materials used in the dual damascene interconnect structure include barrier/adhesive materials and low resistivity fill materials. The barrier/adhesive material may be selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, molybdenum, manganese and copper, and preferably niobium/tantalum nitride or titanium/titanium nitride. The low resistivity filler material may be selected from the group consisting of tungsten, copper, aluminum, and polysilicon, and copper is preferred. The dual damascene interconnect structures 290_1 and 290_2 can be formed by forming vias and trenches in the second interlayer dielectric layer 292; forming a barrier/adhesive material and a low resistivity fill material on the substrate to fill the pass Holes and trenches; and chemical mechanical polishing processes to remove excess material and form a globally flat surface.

在圖5A中，可以很清楚地看到，由於雙鑲嵌內連線結構290_1不只是貫穿第二層間介電層292亦貫穿了第二蓋層282，所以雙鑲嵌內連線結構290_1之高度D1(從接觸栓270之上表面到雙鑲嵌內連線結構290_1之上表面間的距離)係大於雙鑲嵌內連線結構290_2之高度D2(從過渡性貫穿矽通孔280之上表面到雙鑲嵌內連線結構290_1之上表面間的距離)。In FIG. 5A, it can be clearly seen that since the dual damascene interconnect structure 290_1 penetrates the second cap layer 282 not only through the second interlayer dielectric layer 292, the height D1 of the dual damascene interconnect structure 290_1 (from the upper surface of the contact plug 270 to the distance between the upper surfaces of the dual damascene interconnect structure 290_1) is greater than the height D2 of the dual damascene interconnect structure 290_2 (from the transition through the upper surface of the through via 280 to the dual damascene The distance between the upper surfaces of the interconnect structure 290_1).

請參考圖1-4及5B，此些橫剖面概圖顯示了根據本發明第二實施例之具有TSV之整合結構的製造方法。圖1-4之製程、材料與結構係與前面段落所述相同，在此便不再重覆。在此實施例中，在形成接觸栓270與第二蓋層282之後，分別在電晶體250與接觸栓270上形成緩衝導電結構283與284。緩衝導電結構283與284可使用接觸栓270或雙鑲嵌內連線290所用的製程與材料，故便不再詳述其細節。應注意，可在過渡性貫穿矽通孔280完成之後形成緩衝導電結構283與284，或者可在形成深溝渠277之前形成緩衝導電結構283與284。在形成緩衝導電結構283與284後，依循圖5A之製程，形成覆蓋第二蓋層282、過渡性貫穿矽通孔280與緩衝導電結構283與284的第二層間介電層292，然後在第二層間介電層292中形成雙鑲嵌內連線結構290’_1、290’_2與 290’_3。雙鑲嵌內連線結構290’_1係由一體成形的導電通孔295’_1 與第一金屬(M1)層296’_1 所構成並與緩衝導電結構284直接接觸。雙鑲嵌內連線結構290’_2係由一體成形的複數導電通孔295’_2 (在圖5B中顯示了四個)與第一金屬(M1)層296’_2 所構成並與過渡性貫穿矽通孔280直接接觸。雙鑲嵌內連線結構290’_3係由一體成形的導電通孔295’_3與第一金屬(M1)層296’_3所構成並與緩衝導電結構283直接接觸。Referring to Figures 1-4 and 5B, such cross-sectional overviews illustrate a method of fabricating an integrated structure having a TSV in accordance with a second embodiment of the present invention. The process, materials and structure of Figures 1-4 are the same as described in the previous paragraph and will not be repeated here. In this embodiment, after forming the contact plug 270 and the second cap layer 282, the buffer conductive structures 283 and 284 are formed on the transistor 250 and the contact plug 270, respectively. The buffer conductive structures 283 and 284 may use the processes and materials used for the contact pins 270 or the dual damascene interconnects 290, so the details thereof will not be described in detail. It should be noted that the buffer conductive structures 283 and 284 may be formed after the completion of the transition through vias 280, or the buffer conductive structures 283 and 284 may be formed prior to forming the deep trenches 277. After forming the buffer conductive structures 283 and 284, following the process of FIG. 5A, a second interlayer dielectric layer 292 covering the second cap layer 282, the transition through vias 280 and the buffer conductive structures 283 and 284 is formed, and then Dual damascene interconnect structures 290'_1, 290'_2 and 290'_3 are formed in the two-layer dielectric layer 292. The dual damascene interconnect structure 290'_1 is composed of an integrally formed conductive via 295'_1 and a first metal (M1) layer 296'_1 and is in direct contact with the buffer conductive structure 284. The dual damascene interconnect structure 290'_2 is composed of a plurality of integrally formed conductive vias 295'_2 (four shown in FIG. 5B) and a first metal (M1) layer 296'_2. The through holes 280 are in direct contact. The dual damascene interconnect structure 290'_3 is formed by integrally formed conductive vias 295'_3 and first metal (M1) layers 296'_3 and in direct contact with the buffer conductive structures 283.

在圖5B中，可很清楚地看到，由於第一蓋層272的厚度，故緩衝導電結構283的高度d4(從電晶體250之上表面至緩衝導電結構283之上表面間的距離)係大於緩衝導電結構284的高度d5(從接觸栓270之上表面至緩衝導電結構284之上表面間的距離)。又，不若在圖5A所示的第一實施例中，在此實施例中的所有雙鑲嵌內連線結構290’_1、290’_2與290’_3皆具有相同的高度。In FIG. 5B, it can be clearly seen that due to the thickness of the first cap layer 272, the height d4 of the buffer conductive structure 283 (the distance from the upper surface of the transistor 250 to the upper surface of the buffer conductive structure 283) is Greater than the height d5 of the buffer conductive structure 284 (the distance from the upper surface of the contact plug 270 to the upper surface of the buffer conductive structure 284). Further, not in the first embodiment shown in Fig. 5A, all of the dual damascene interconnect structures 290'_1, 290'_2 and 290'_3 in this embodiment have the same height.

請參考圖1-4及6A，此些橫剖面概圖顯示了根據本發明第三實施例之具有TSV之整合結構的製造方法。圖1-4之製程、材料與結構係與前面段落所述相同，在此便不再重覆。在此實施例中，在完成過渡性貫穿矽通孔280之後，及形成第二層間介電層292之前形成第三蓋層281。第三蓋層281所用的材料係類似於第一與第二蓋層所用的材料。在形成了第三蓋層之後，依循圖6A之製程，形成覆蓋第三蓋層281的第二層間介電層292，然後在第二層間介電層292與第三蓋層281中形成雙鑲嵌內連線結構390_1與 390_2。雙鑲嵌內連線結構390_1係由一體成形的導電通孔395_1 與第一金屬(M1)層396_1 所構成並與接觸栓270直接接觸。雙鑲嵌內連線結構390_2係由一體成形的複數導電通孔395_2 (在圖6A中顯示了四個)與第一金屬(M1)層396_2 所構成並與過渡性貫穿矽通孔280直接接觸。Referring to Figures 1-4 and 6A, such cross-sectional overviews illustrate a method of fabricating an integrated structure having a TSV in accordance with a third embodiment of the present invention. The process, materials and structure of Figures 1-4 are the same as described in the previous paragraph and will not be repeated here. In this embodiment, the third cap layer 281 is formed after the completion of the transition through via 280 and before the formation of the second interlayer dielectric layer 292. The material used for the third cover layer 281 is similar to that used for the first and second cover layers. After the third cap layer is formed, a second interlayer dielectric layer 292 covering the third cap layer 281 is formed according to the process of FIG. 6A, and then a dual damascene is formed in the second interlayer dielectric layer 292 and the third cap layer 281. The interconnect structures 390_1 and 390_2. The dual damascene interconnect structure 390_1 is composed of an integrally formed conductive via 395_1 and a first metal (M1) layer 396_1 and is in direct contact with the contact plug 270. The dual damascene interconnect structure 390_2 is formed by integrally forming a plurality of conductive vias 395_2 (four shown in FIG. 6A) and a first metal (M1) layer 396_2 and in direct contact with the transition through vias 280.

類似於圖5A，在圖6A中由於雙鑲嵌內連線結構390_1不僅僅了貫穿第二層間介電層292與第三蓋層同時也貫穿了第二蓋層282，故雙鑲嵌內連線結構390_1的高度D1’(從接觸栓270之上表面至雙鑲嵌內連線結構390_1之上表面間的距離)係大於雙鑲嵌內連線結構390_2的高度D2’(從過渡性貫穿矽通孔280之上表面至雙鑲嵌內連線結構390_2之上表面間的距離)。Similar to FIG. 5A, in FIG. 6A, since the dual damascene interconnect structure 390_1 penetrates the second cap layer 282 not only through the second interlayer dielectric layer 292 and the third cap layer, the dual damascene interconnect structure The height D1' of 390_1 (from the upper surface of the contact plug 270 to the distance between the upper surfaces of the dual damascene interconnect structure 390_1) is greater than the height D2' of the dual damascene interconnect structure 390_2 (from the transition through the through hole 280) The distance from the upper surface to the surface above the dual damascene interconnect structure 390_2).

請參考圖1-4、6A與6B，此些橫剖面概圖顯示了根據本發明第四實施例之具有TSV之整合結構的製造方法。圖1-4之製程、材料與結構係與前面段落所述相同，在此便不再重覆。在此實施例中，在形成了第三蓋層281之後，分別於電晶體250與接觸栓270上形成緩衝導電結構283’與284’。緩衝導電結構283’與284’可使用接觸栓270或雙鑲嵌內連線290所用的製程與材料，故便不再詳述其細節。在形成緩衝導電結構283’與284’之後，依循圖6A的製程形成覆蓋第三蓋層281、緩衝導電結構283’與284’之第二層間介電層292，然後在第二層間介電層292中形成雙鑲嵌內連線結構390’_1、390’_2與390’_3。雙鑲嵌內連線結構390’_1係由一體成形的導電通孔395’_1 與第一金屬(M1)層396’_1 所構成並與緩衝導電結構284’直接接觸。雙鑲嵌內連線結構390’_2係由一體成形的複數導電通孔395’_2 (在圖6B中顯示了四個)與第一金屬(M1)層396’_2 所構成並與過渡性貫穿矽通孔280直接接觸。雙鑲嵌內連線結構390’_3係由一體成形的導電通孔395’_3與第一金屬(M1)層396’_3所構成並與緩衝導電結構283’直接接觸。Referring to Figures 1-4, 6A and 6B, these cross-sectional overviews illustrate a method of fabricating an integrated structure having a TSV in accordance with a fourth embodiment of the present invention. The process, materials and structure of Figures 1-4 are the same as described in the previous paragraph and will not be repeated here. In this embodiment, after the third cap layer 281 is formed, buffer conductive structures 283' and 284' are formed on the transistor 250 and the contact plug 270, respectively. The buffer conductive structures 283' and 284' can use the processes and materials used for the contact pins 270 or the dual damascene interconnects 290, so the details thereof will not be described in detail. After forming the buffer conductive structures 283' and 284', the second interlayer dielectric layer 292 covering the third cap layer 281, the buffer conductive structures 283' and 284' is formed in accordance with the process of FIG. 6A, and then the second interlayer dielectric layer is formed. Dual damascene interconnect structures 390'_1, 390'_2 and 390'_3 are formed in 292. The dual damascene interconnect structure 390'_1 is composed of an integrally formed conductive via 395'_1 and a first metal (M1) layer 396'_1 and is in direct contact with the buffer conductive structure 284'. The dual damascene interconnect structure 390'_2 is composed of a plurality of integrally formed conductive vias 395'_2 (four shown in FIG. 6B) and a first metal (M1) layer 396'_2. The through holes 280 are in direct contact. The dual damascene interconnect structure 390'_3 is formed by integrally formed conductive vias 395'_3 and first metal (M1) layers 396'_3 and in direct contact with the buffer conductive structures 283'.

極不同於前述的實施例，在圖6B中由於緩衝導電結構283’與284’，故雙鑲嵌內連線結構 390’_1 的高度D1”(從接觸栓270之上表面至雙鑲嵌內連線結構390’_1之上表面間的距離)係小於雙鑲嵌內連線結構390’_2的高度D2”(從過渡性貫穿矽通孔280之上表面至雙鑲嵌內連線結構390’_2之上表面間的距離)。又，由於第一蓋層272的厚度，緩衝導電結構283’的高度d4’(從電晶體250的上表面至緩衝導電結構283’之上表面間的距離)係大於緩衝導電結構284’之高度d5’(從接觸栓270之上表面至緩衝導電結構284’之上表面間的距離)。Much different from the previous embodiment, the height D1" of the dual damascene interconnect structure 390'_1 (from the upper surface of the contact plug 270 to the dual damascene interconnect) is due to the buffered conductive structures 283' and 284' in FIG. 6B. The distance between the top surfaces of the structures 390'_1) is less than the height D2" of the dual damascene interconnect structure 390'_2 (from the transition through the upper surface of the through via 280 to the dual damascene interconnect structure 390'_2 The distance between the surfaces). Moreover, due to the thickness of the first cap layer 272, the height d4' of the buffer conductive structure 283' (the distance from the upper surface of the transistor 250 to the upper surface of the buffer conductive structure 283') is greater than the height of the buffer conductive structure 284'. D5' (distance from the upper surface of the contact plug 270 to the upper surface of the buffer conductive structure 284').

現在參考圖7，其顯示根據本發明第一實施例(對應至圖5A)之具有貫穿矽通孔之整合結構的最終結構示意圖。在完成圖5A中所示的整合結構後，形成較高層次之內連線層1000。較高層次之內連線層1000可包含一或多層之金屬層間介電層、一或多層之雙鑲嵌內連線結構、一或多個被動元件如金屬-絕緣層-金屬(MIM)電容器、電感器、電阻、一或多種測試結構以及一或多個銲墊。在完成較高層次之內連線層1000後，翻轉基板100並對基板100的背側進行打磨、研磨及/或薄化製程以裸露導電通孔279並完成貫穿矽通孔300。雖然圖7只顯示了圖5A中所示之第一實施例的概略最終結構，但其他實施例(即圖5B、6A與6B)可依循相同的製程來製造較高層次之內連線層1000並完成貫穿矽通孔300。製造較高層次之內連線層1000並完成貫穿矽通孔300的此些製程並不會改變上述各個實施例的幾何特徵。Referring now to Figure 7, there is shown a final structural schematic of an integrated structure having through-through vias in accordance with a first embodiment of the present invention (corresponding to Figure 5A). After completing the integrated structure shown in FIG. 5A, a higher level inner interconnect layer 1000 is formed. The higher level interconnect layer 1000 can include one or more inter-metal dielectric layers, one or more dual damascene interconnect structures, one or more passive components such as metal-insulator-metal (MIM) capacitors, An inductor, a resistor, one or more test structures, and one or more pads. After completing the higher level interconnect layer 1000, the substrate 100 is flipped and the back side of the substrate 100 is ground, ground, and/or thinned to expose the conductive vias 279 and complete through the vias 300. Although FIG. 7 only shows the schematic final structure of the first embodiment shown in FIG. 5A, other embodiments (ie, FIGS. 5B, 6A, and 6B) can follow the same process to manufacture a higher level interconnect layer 1000. And the through hole 300 is completed. Manufacturing the higher level inner interconnect layer 1000 and completing such processes through the through via 300 does not alter the geometric features of the various embodiments described above.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100．．．基板100. . . Substrate

222．．．源極與汲極(S/D)222. . . Source and bungee (S/D)

250．．．電晶體250. . . Transistor

261．．．接觸洞蝕刻停止層261. . . Contact hole etch stop layer

262．．．第一層間介電層262. . . First interlayer dielectric layer

270．．．接觸栓270. . . Contact plug

272．．．第一蓋層272. . . First cover

278．．．電絕緣層278. . . Electrical insulation

279．．．導電通孔279. . . Conductive through hole

280．．．過渡性貫穿矽通孔280. . . Transitional through hole

282．．．第二蓋層282. . . Second cover

d1、d2、d3．．．高度/距離D1, d2, d3. . . Height/distance

Claims (10)

一種整合結構，包含：
基板，具有第一介電層與第二介電蓋層依序設置於其上；
金屬閘極電晶體，具有設置於該基板上的高介電常數閘極介電層、嵌於該第一介電層之內的金屬電極以及位於該基板內的源極/汲極；
第一金屬接觸栓，貫穿該第一介電層且與該源極/汲極直接接觸；及
貫穿矽通孔，貫穿該第二介電蓋層、該第一介電層與該基板。An integrated structure that includes:
a substrate having a first dielectric layer and a second dielectric cap layer disposed thereon in sequence;
a metal gate transistor having a high dielectric constant gate dielectric layer disposed on the substrate, a metal electrode embedded in the first dielectric layer, and a source/drain electrode located in the substrate;
a first metal contact plug penetrating the first dielectric layer and in direct contact with the source/drain; and a through-via via extending through the second dielectric cap layer, the first dielectric layer and the substrate. 如申請專利範圍第1項之整合結構，其中該第一金屬接觸栓的上表面係高於該金屬電極的上表面。The integrated structure of claim 1, wherein the upper surface of the first metal contact plug is higher than the upper surface of the metal electrode. 如申請專利範圍第1項之整合結構，其中該貫穿矽通孔的上表面係高於該第一金屬接觸栓的上表面。The integrated structure of claim 1, wherein the upper surface of the through hole is higher than the upper surface of the first metal contact plug. 如申請專利範圍第1項之整合結構，其中該第一介電層包含第一層間介電層與第一介電蓋層，該第一金屬接觸栓的上表面係與該第一介電蓋層共平面，該金屬閘極係與該第一層間介電層共平面。The integrated structure of claim 1, wherein the first dielectric layer comprises a first interlayer dielectric layer and a first dielectric cap layer, and an upper surface of the first metal contact plug is coupled to the first dielectric layer The cap layer is coplanar, and the metal gate is coplanar with the first interlayer dielectric layer. 如申請專利範圍第1項之整合結構，其中該金屬電極包含U形的功函數金屬層與低電阻率填充層。The integrated structure of claim 1, wherein the metal electrode comprises a U-shaped work function metal layer and a low resistivity fill layer. 如申請專利範圍第1項之整合結構，其中該金屬電極包含鋁、該第一金屬接觸栓包含鎢而該貫穿矽通孔包含銅。The integrated structure of claim 1, wherein the metal electrode comprises aluminum, the first metal contact plug comprises tungsten and the through hole comprises copper. 如申請專利範圍第1項之整合結構，更包含：
設置於該第二介電蓋層上並覆蓋該貫穿矽通孔的第二介電層；
第一內連線結構，貫穿該第二介電蓋層上並與該貫穿矽通孔相連接；及
第二內連線結構，貫穿該第二介電層與該第二介電蓋層並與該第一金屬接觸栓相連接。For example, the integrated structure of the first application scope of the patent scope includes:
a second dielectric layer disposed on the second dielectric cap layer and covering the through via hole;
a first interconnect structure extending through the second dielectric cap layer and connected to the through via hole; and a second interconnect structure extending through the second dielectric layer and the second dielectric cap layer Connected to the first metal contact plug. 如申請專利範圍第1項之整合結構，更包含：
第一緩衝導電結構，設置於該金屬電極上；及
第二緩衝導電結構，設置於該第一金屬接觸栓上。For example, the integrated structure of the first application scope of the patent scope includes:
The first buffer conductive structure is disposed on the metal electrode; and the second buffer conductive structure is disposed on the first metal contact plug. 如申請專利範圍第8項之整合結構，其中該第一緩衝導電結構的上表面與該第二緩衝導電結構的上表面係與該第二介電蓋層共平面。The integrated structure of claim 8 wherein the upper surface of the first buffered conductive structure and the upper surface of the second buffered conductive structure are coplanar with the second dielectric cap layer. 如申請專利範圍第1項之整合結構，更包含：
第二介電層，設置於該第二介電蓋層上並覆蓋該貫穿矽通孔、該第一緩衝導電結構與該第二緩衝導電結構；
第一內連線結構，貫穿該第二介電層而與該貫穿矽通孔相連接；
第二內連線結構，貫穿該第二介電層而與該第一緩衝導電結構相連接；及
第三內連線結構，貫穿該第二介電層而與該第二緩衝導電結構相連接。
For example, the integrated structure of the first application scope of the patent scope includes:
a second dielectric layer disposed on the second dielectric cap layer and covering the through via via, the first buffer conductive structure and the second buffer conductive structure;
a first interconnect structure connected to the through via via through the second dielectric layer;
a second interconnect structure connected to the first buffer conductive structure through the second dielectric layer; and a third interconnect structure connected to the second buffer conductive structure through the second dielectric layer .