TW201436229A - 積體電路裝置及其形成方法 - Google Patents

積體電路裝置及其形成方法 Download PDF

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TW201436229A
TW201436229A TW102148623A TW102148623A TW201436229A TW 201436229 A TW201436229 A TW 201436229A TW 102148623 A TW102148623 A TW 102148623A TW 102148623 A TW102148623 A TW 102148623A TW 201436229 A TW201436229 A TW 201436229A
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layer
region
channel region
integrated circuit
circuit device
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TW102148623A
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TWI528560B (zh
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Wei-Yuan Lu
Lilly Su
Chun-Hung Huang
Chii-Horng Li
Jyh-Huei Chen
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Taiwan Semiconductor Mfg
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Abstract

本發明提供一種積體電路裝置，包括：一半導體主體，其包括矽；一場效電晶體形成於前述半導體主體之上，前述場效電晶體包括一閘極、一源極區域、一汲極區域、以及一通道區域，前述通道區域具有一表面；前述源極區域以及前述汲極區域包括一第一層位於前述通道區域之前述表面下，前述第一層包括摻雜SiC，並具有一小於矽的晶格結構，以及一第二層位於前述第一層上方，前述第二層包括一磊晶生長之摻雜矽，其中前述第二層之一部分突出於前述通道區域之前述表面上；其中前述第二層具有一碳原子分數，其少於前述第一層之一半；以及其中前述第一層之一部分在前述通道區域之前述表面至少10 nm下。本發明另提供一種積體電路裝置的形成方法。

Description

積體電路裝置及其形成方法
本發明係有關於一種n型金氧半場效半導體及其製造方法。
隨著積體電路尺寸微縮化，設計者面臨短通道效應(short channel effect)與源/汲極電阻間的權衡。源/汲極摻雜愈多可降低電阻，但會加大接面深度(junction depth)以及相關的短通道效應。
本發明提供一種積體電路裝置，包括：一半導體主體，其包括矽晶；一場效電晶體，形成於前述半導體主體之上，前述場效電晶體包括一閘極、一源極區域、一汲極區域、以及一通道區域，前述通道區域具有一表面；前述源極區域以及前述汲極區域包括一第一層位於前述通道區域之前述表面下，前述第一層包括摻雜SiC，並具有一小於矽的晶格結構，以及一第二層位於前述第一層上方，前述第二層包括一磊晶生長之摻雜矽，其中前述第二層之一部分突出於前述通道區域之前述表面上；其中前述第二層具有一碳原子分數，其少於前述第一層之碳原子分數一半；以及其中前述第一層之一部分在前 述通道區域之前述表面至少10nm下。
本發明亦提供一種積體電路裝置之形成方法，包括；提供一半導體主體，形成一閘極疊層或一虛置閘極疊層於前述半導體主體之上；圖案化前述閘極疊層或前述虛置閘極疊層以從前述源極區域以及前述汲極區域移除前述閘極疊層或前述虛置閘極疊層而留下提供作為多個閘極之多個通道區域之圖案化疊層；形成間隔物環繞前述多個閘極之多個側壁；蝕刻多個溝槽於前述半導體主體之前述源極區域以及前述汲極區域中；藉由週期性的沉積與蝕刻形成一第一層於前述多個溝槽中，前述第一層包括Si、C、以及P；形成一第二層於前述第一層之上方，其係藉由磊晶生長，前述第二層包括Si以及P，前述第一層以及前述第二層提供前述源極區域以及前述汲極區域；以及熱退火以使P至少自前述第二層擴散，擴散之P界定前述源極區域與前述汲極區域以及前述多個通道區域間之p-n接面。
101、103、105、107、109、111、113‧‧‧步驟
100‧‧‧方法
200‧‧‧裝置
201‧‧‧半導體主體
203‧‧‧介電層
205‧‧‧電極層
207‧‧‧硬罩幕層
209‧‧‧光微影罩幕
210‧‧‧疊層
211‧‧‧閘極
213‧‧‧通道區域
214‧‧‧表面
215‧‧‧間隔物
216‧‧‧袋狀/暈狀區域
217‧‧‧溝槽
218‧‧‧尖端
219‧‧‧第一層
221‧‧‧第二層
223‧‧‧源極/汲極延伸區域
224‧‧‧擴散摻雜區域
第1圖為一製程實施例之流程圖；以及第2-8圖為一系列剖面圖，其顯示一裝置之各製程階段的實施例。
本發明提供積體電路裝置。裝置包括一半導體本體，一般包括矽晶。一場效電晶體形成於半導體本體上，其包括一通道區域形成於半導體本體中。電晶體之源極與汲極區域 包括第一層與第二層。第一層形成於通道區域上表面之平面下。第一層由一種含有晶格結構小於矽的摻雜SiC之材料所形成。第二層形成於第一層之上且超過通道區域上表面之平面。第二層由一種包括摻雜磊晶的矽材料所形成。第二層具有小於第一層一半的碳原子分數。在一實施例中，第一層係形成於通道區域下至少約10nm處。此種結構促進源極與汲極延伸區域的形成，其形成很淺的接面(junction)。此裝置提供低電阻的源極與汲極而同時較能抵抗短通道效應。
本發明亦提供形成積體電路裝置的方法。此方法包括提供一半導體本體並形成一疊層在此半導體本體之上。此方法包括提供先閘極製程與後閘極製程的實施例，因此疊層可為一閘極或一虛置閘極。疊層經圖案化以移除源極與汲極區域的疊層以便形成閘極，同時留下部分疊層於半導體本體上以形成閘極的通道區域。間隔物形成至閘極位置的側邊上。溝槽形成於半導體本體的源極與閘極區域中。在一實施例中，第一層藉由週期性的沉積與蝕刻形成。第一層包括Si、C以及P。在一實施例中，第二層係透過磊晶成長於第一層之上。第二層包括Si以及P。第一層以及第二層提供了電晶體之源極與汲極區域。熱退火造成磷從至少第二層擴散。擴散的磷決定p-n接面在源/汲極區域以及通道區域間的位置。
第1圖為一製造裝置200的方法100之流程圖。第2-8圖為一系列剖面圖，其顯示一裝置之各製程階段的實施例。要了解的是為了形成裝置200，在所示之方法100之各步驟之前、同時、之後可執行額外的製程。
方法100始於步驟101，其提供一疊層210於一半導體本體201之上。半導體本體可包括201可包括摻雜或未摻雜之矽晶以及絕緣體上半導體結構。一般而言，絕緣體上半導體結構包括一層半導體材料，如結晶矽，形成於一絕緣層上方。絕緣層可例如為埋入氧化物層(buried oxide layer)或氧化矽層。絕緣層係提供於一基板之上，一般為矽或玻璃基板。亦可使用其他半導體本體，如多層基板或梯度基板(gradient substrate)。半導體的晶體部分亦可以是Ge、SiGe、三五族材料等等。
疊層210係提供做為閘極疊層或虛置閘極疊層之一或多層。在第2-8圖所提供之實施例中，疊層210包括介電層203、電極層205以及硬罩幕層207。為使臨界尺寸縮減，裝置200可使用高介電常數的材料以及金屬電極取代傳統閘極金屬材料。用以形成源極以及汲極區域的製程對於適合的閘極材料有不利的影響。此種傷害可透過虛置閘極(後閘極製程)避免。
在一些實施例中，製程100為一虛置閘極製程。在一虛置閘極製程中，疊層係以犧牲材料形成，如以多晶矽取代電極金屬。介電層203亦可選擇使用犧牲材料。在虛置閘極製程中，會移除犧牲材料，並在步驟113之熱退火後沉積理想的閘極材料。
第1圖之方法100繼續於步驟103，疊層210之圖案化。圖案定義閘極211之位置並移除源極以及汲極區域的疊層210。圖案化一般包括提供一光微影罩幕，以光微影技術圖案化罩幕並以蝕刻將罩幕之圖案轉移至下方層。之後，移除光微影罩幕209而形成第3圖所示之結構。
方法100繼續於步驟105，間隔物215形成於鄰近閘極位置之處，如第4圖所示。間隔物215可透過沉積並圖案化介電層形成。在一些實施例中，間隔物215包括SiN層或SiO2層。在其他實施例中，間隔物包括一或多層合適之材料。合適之材料例如可包括SiO2、SiN、SiON。間隔物材料可使用合適之技術進行沉積。合適技術例如可包括電漿強化型化學氣相沉積(plasma enhanced CVD)、低壓化學氣相沉積(low pressure CVD)、次大氣化學氣相沉積(sub-atmospheric CVD)等等。間隙物215可利用任何合適的製程進行蝕刻，例如非等向性蝕刻(anisotropic etch)。
方法100繼續於步驟107，溝槽217形成於半導體本體中合適於源極以及汲極區域212之位置，如第5圖所示。在一些實施例中，步驟107為一非等向性濕蝕刻。非等向性濕蝕刻可為一種對晶面方向(crystal surface orientation)具有選擇性的濕蝕刻。蝕刻可使用，例如，15-50℃下體積濃度為1-10%之四甲基氫氧化銨(tetra-methyl ammonium hydroxide)溶液。非等向性蝕刻可製造具有尖端218的溝槽。在一些實施例中，尖端位於半導體本體201下離表面214小於6nm以下之位置，其會成為通道區域之表面。在一些實施例中，尖端218位於半導體本體201下離表面小於3nm以下之位置，例如2nm。尖端218的深度淺可促進淺接面(shallow junctions)的形成。
在一些方法100之實施例中，在如第5圖中所示之位置的袋狀/暈狀區域216係於步驟207之後植入。袋狀/暈狀區域216可例如以電中性摻質進行植入，其抑制電活性摻質之擴 散，如磷。可適用於此目的之摻質包括氮、氟。袋狀/暈狀區域216可以使用任何合適的離子植入製程形成。另一方面，對於方法100，袋狀/暈狀區域亦可為非必須的。亦可植入相反電性摻質(opposite conductivity dopant)以形成袋狀/暈狀區域216，例如以p型摻質植入n型電晶體。
第1圖之方法100繼續至步驟109，形成第一層219於溝槽217之中，如第6圖所示之結構。第一層219提供一源極/汲極區域212之導電性區域。在一些實施例中，第一層219對於半導體本體201之通道區域213造成拉伸應力。這係因使用晶格結構小於通道區域213之晶體材料形成第一層219所造成。例如，當通道區域為Si時，包括SiC之第一層219可提供需要之晶格結構。加入n型摻質，如P，可提供所需之導電性。
在一些實施例中，包括SiC：P之第一層219係以週期性的沉積與蝕刻(cyclical deposition and etching)製程所形成。週期性的沉積與蝕刻包括穿插進行的沉積步驟與回蝕刻步驟。回蝕刻步驟移除α-SiC以及缺陷的c-Si：C薄膜。蝕刻可使用氣體如HCl氣體。沉積可使用如Si2H6為主之混合氣體。沉積製程溫度可例如介於560-600℃間。沉積製程可為順應性或非順應性。由於非晶形沉積物較單晶相具有較高的蝕刻率，其淨效應可為一單相之第一層219的生長。
在一些實施例中，第一層219為SiC：P，具有相對較高之碳含量以及相對較低之磷含量。相對較高之碳含量為至少1%之碳分數(carbon fraction)。一般，碳原子分數不高於2.5%。相對較高的碳含量降低第一層219中之磷擴散率。相對較低之 磷含量為4.5e20原子/立方公分。磷含量一般至少為1.5e20原子/立方公分以提供所需之導電性。減少磷擴散穿過以及擴散出第一層219可促成淺接面的形成並減輕短通道效應。
第1圖之方法100繼續於步驟111，其形成第二層221於第一層219之上方，如第7圖所示。如第一層219，第二層221亦包括n型摻質，其一般為磷。相對於第一層219，第二層221藉由高擴散率釋放摻質係為理想的。在一些實施例中，第二層221之高擴散率一部分係藉由提供高於第一層219之摻質濃度所達成。一般而言，第二層包括濃度介於2.5e20-1e22原子/立方公分之間的摻質。在一些實施例中，第二層221具有少於第一層219一半之碳原子分數。一般而言，第二層幾乎不含碳，或僅少量。
第二層可以任何合適之製程形成。一合適製程例如可為磊晶生長。於利用週期性的沉積與蝕刻形成之第一層219處，可以相對較高的溫度執行磊晶生長。所謂較高的溫度可例如為650℃以上。相對較高的溫度改善製程的產能。第二層221之磊晶生長一般係以690℃以下的溫度進行。
第1圖之方法100繼續於步驟113，熱退火。熱退火步驟113造成摻質從第二層221擴散並形成源極與汲極延伸區域223，如第8圖所示。在熱退火步驟113之後，源極與汲極區域212包括第一層219、第二層221、以及源極與汲極延伸區域223。熱退火步驟113一般為毫秒退火(millisecond anneal)。在毫秒退火製程中，半導體本體係加熱至預先烘烤溫度。當半導體本體從下方維持預先烘烤溫度時，上表面係快速加熱至尖峰 溫度。
在一提供理想擴散範圍的實施例中，尖峰溫度係介於950-1250℃之間，而半導體本體的表面214係維持於950-1250℃之間2毫秒以上，但不超過15毫秒。在一實施例中，可使用介於600-780℃之間的預先烘烤溫度。將表面從預先烘烤溫度加熱至尖峰溫度的理想速率為700-900℃/秒。
在一些實施例中，係重複進行毫秒熱退火。摻質擴散輪廓更可透過一額外的退火改善，其係在毫秒退火前以較低的溫度進行。此額外退火步驟可包括一將半導體本體升溫至530-680℃之間的預烘烤，其間約維持5-15秒。表面214係加熱至尖峰溫度750-1000℃之間並維持1-5秒。
第一層219以及第二層221之幾何結構以及組成退火步驟113提供了淺源極與汲極延伸區域223。第二層221之摻質擴散形成餅狀楔型(pie-wedged shape)的擴散摻雜區域224鄰近於通道區域213。在一些實施例中，摻質自第二層221往通道區域之表面214(即半導體主體之表面214)擴散4-10nm。擴散摻雜區域224之窄端鄰近於第二層221，可具有一深度0-15nm(縱向範圍)。在一些實施例中，窄端之深度小於5nm。在一些實施例中，窄端之深度小於2nm。擴散摻雜區域224之窄端之淺深度促進淺源極與汲極延伸區域223之形成。在一些實施例中，源極與汲極延伸區域223在閘極之下的深度範圍為15nm以下。在一些實施例中，源極與汲極延伸區域223在閘極之下的深度範圍為5nm以下。
淺源極與汲極延伸區域223之形成係透過定位第 二層221使其下部範圍位在通道區域213之表面214下。在一些實施例中，第二層221之深度延伸至通道區域213之表面214下2-10nm處。在一些實施例中，第二層221延伸至通道區域213之表面214下之深度，相當於第一層219厚度之1/3-1/20。
第5圖之溝槽217形成一足夠深度以容納在通道區域213之表面214下的第二層221部分，此外亦包括全部的第一層219。一般而言，溝槽217形成至深度15-50nm處，例如25nm。
淺源極與汲極延伸區域223之形成更係透過定位第二層221使其上部範圍位在通道區域213之表面214以上。一般而言，第二層221之主體區域係在通道區域213之表面214之上。在一些實施例中，第二層221延伸至通道區域213之表面214之上10-30nm處。第二層221提供一摻質儲存槽以在步驟113形成源極與汲極延伸區域223。摻質從第二層221擴散進源極與汲極延伸區域223時，一般須通過一由間隔物215以及第二層219所形成之瓶頸(bottleneck)。透過第二層221在通道區域213之表面214以上以及其在表面214以下的厚度得維持退火步驟113時靠近瓶頸處之摻質濃度。
透過形成第一層，且使其覆蓋於溝槽217之側壁以縮減瓶頸的尺寸並形成淺源極與汲極延伸區域223。週期性的沉積與蝕刻的條件可設定為提供一沈積製程其至少對第一層219所形成之表面具部分選擇性。以此而言，選擇性沈積之沈積速率係與特定區域之表面具比例關係，而與表面位向無關。在一些實施例中，沈積之選擇性至少為對溝槽217之側壁相對於溝槽217之底部具有顯著之沈積速率。第一層219之一般厚度 為20nm時，而瓶頸尺寸可藉由僅3nm厚的側壁鍍層縮減至一理想厚度。第一層219一般於側壁217上覆蓋一厚度為3-10nm之鍍層。
步驟113完成後，一般接續額外的前段製程(front end of line processing)，然後再進行後段製程(back end of line processing)。額外的製程可提供裝置200多種特徵，如接點或導孔、內連線金屬層、介電層、鈍化層等等。源極與汲極區域212可經矽化，然而在一實施例中，其未經矽化：本發明之結構可提供夠低的源極與汲極電阻而不需經矽化。
隔離區域(未繪出)，可在步驟101前形成於半導體本體之上。隔離區域可使用隔離技術，如局部矽化或淺溝槽隔離(STI)，以定義並電性隔離裝置200之各個主動區域。
介電層203可使用任何合適的介電質。可使用SiO2或任何合適的介電層。介電層203可為一高介電常數材料層，不論係使用前閘極製程或後閘極製程。一高介電常數材料具有相較於SiO2之5倍之導電性。高介電常數材料之例子包括鉿為主的材料，如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO以及HfO2-Al2O3合金。其他高介電常數材料可例如包括但不限於ZrO2、Ta2O5、Al2O3、Y2O3、La2O3以及SrTiO3。
電極層205亦可為由各種材料所組成之一或多層。在一些實施例中，尤其係使用高介電常數材料之實施例中，電極層205為一或多層。一電極層205一般包括至少一層之Ti、TiN、TaN、Ta、TaC、TaSiN、W、WN、MoN以及MoON其他電極層所使用之材料可包括Ru、Pa、Pt、Co、Ni、Ha、 Zr、Ti、Ta、Al、導電碳化物、導電氧化物、以及前述之合金。
本發明提供一種積體電路裝置，包括：一半導體主體，其包括矽晶。一場效電晶體，形成於前述半導體主體之上。前述場效電晶體包括一閘極、一源極區域、一汲極區域、以及一通道區域，前述通道區域具有一表面。前述源極區域以及前述汲極區域包括一第一層位於前述通道區域之前述表面下。前述第一層包括摻雜SiC，並具有一小於矽的晶格結構，以及前述源極區域以及前述汲極區域更包括一第二層位於前述第一層上方並突出於前述通道區域之前述表面上，以及前述第二層包括一磊晶生長之摻雜矽。前述第二層具有一碳原子分數，其少於前述第一層之碳原子分數一半。前述第一層形成在前述通道區域之前述表面至少10nm下。
本發明另提供一種積體電路裝置之形成方法。前述形成方法提供一半導體主體，形成一閘極疊層或一虛置閘極疊層於前述半導體主體之上，以及圖案化前述閘極疊層或前述虛置閘極疊層以移除從前述源極區域以及前述汲極區域移除前述閘極疊層或前述虛置閘極疊層而留下提供作為多個閘極之多個通道區域之圖案化疊層。前述形成方法更包括形成間隔物環繞前述多個閘極之多個側壁，蝕刻多個溝槽於前述半導體主體之前述源極區域以及前述汲極區域中，以及藉由週期性的沉積與蝕刻形成一第一層於前述多個溝槽中，前述第一層包括Si、C、以及P。前述方法另更包括形成一第二層於前述第一層之上方，其係藉由磊晶生長，其中前述第二層包括Si以及P，以及前述第一層以及前述第二層提供前述源極區域以及前述 汲極區域。前述方法亦包括熱退火以形成P至少自前述第二層擴散，擴散之P界定前述源極區域與前述汲極區域以及前述多個通道區域間之p-n接面。
以上敘述許多實施例的特徵，使所屬技術領域中具有通常知識者能夠清楚理解以下的說明。所屬技術領域中具有通常知識者能夠理解其可利用本發明揭示內容作為基礎，以設計或更動其他製程及結構而完成相同於上述實施例的目的及/或達到相同於上述實施例的優點。所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。
100‧‧‧方法
101、103、105、107、109、111、113‧‧‧步驟

Claims (10)

  1. 一種積體電路裝置，包括：一半導體主體，其包括矽晶；一場效電晶體，形成於該半導體主體之上，該場效電晶體包括一閘極、一源極區域、一汲極區域、以及一通道區域，該通道區域具有一表面；該源極區域以及該汲極區域包括一第一層位於該通道區域之該表面下，該第一層包括摻雜SiC，並具有一小於矽的晶格結構，以及一第二層位於該第一層上方，該第二層包括一磊晶生長之摻雜矽，其中該第二層之一部分突出於該通道區域之該表面上；其中該第二層具有一碳原子分數，其少於該第一層之碳原子分數一半；以及其中該第一層之一部分在該通道區域之該表面至少10nm下。
  2. 如申請專利範圍第1項所述之積體電路裝置，其中該第一層具有一碳原子分數介於1-2.5%；以及其中該第二層具有一磷濃度介於2.5e20-1e22原子/立方公分，該第一層之磷濃度少於2.5e20原子/立方公分。
  3. 如申請專利範圍第1項所述之積體電路裝置，其中該第二層超過該通道區域之該表面至少10nm，其中該第二層延伸至該通道區域之該表面下至少2nm，以及其中該第二層延伸至該通道區域之該表面下的厚度為該第一層厚度之1/3-1/20。
  4. 如申請專利範圍第1項所述之積體電路裝置，其中該第一 層覆於該通道區域之多個側壁，而使該第一層將該第二層與該多個側壁隔開至少3nm。
  5. 如申請專利範圍第1項所述之積體電路裝置，其中該源極區域以及該汲極區域包括多個擴散摻雜延伸區域，其具有該閘極下不大於5nm的深度。
  6. 一種積體電路裝置之形成方法，包括；提供一半導體主體，形成一閘極疊層或一虛置閘極疊層於該半導體主體之上；圖案化該閘極疊層或該虛置閘極疊層以從該源極區域以及該汲極區域移除該閘極疊層或該虛置閘極疊層而留下提供作為多個閘極之多個通道區域之圖案化疊層；形成間隔物環繞該多個閘極之多個側壁；蝕刻多個溝槽於該半導體主體之該源極區域以及該汲極區域中；藉由週期性的沉積與蝕刻形成一第一層於該多個溝槽中，該第一層包括Si、C、以及P；形成一第二層於該第一層之上方，其係藉由磊晶生長，該第二層包括Si以及P，該第一層以及該第二層提供該源極區域以及該汲極區域；以及熱退火以造成P至少自該第二層擴散，擴散之P界定該源極區域與該汲極區域以及該多個通道區域間之p-n接面。
  7. 如申請專利範圍第6項所述之積體電路裝置的形成方法，其中P自該第二層擴散之速率大於自該第一層擴散 之速率。
  8. 如申請專利範圍第6項所述之積體電路裝置的形成方法，其中該第一層具有一碳原子分數介於1-2.5%，以及該第二層之碳原子分數少於該第一層之一半；以及其中該第二層具有一磷濃度介於2.5e20-1e22原子/立方公分，以及該第一層之磷濃度少於2.5e20原子/立方公分。
  9. 如申請專利範圍第6項所述之積體電路裝置的形成方法，其中該第二層超過該通道區域之該表面至少10nm，其中該第二層延伸至該通道區域之該表面下至少2nm，以及其中該第二層延伸至該通道區域之該表面下的厚度為該第一層厚度之1/3-1/20。
  10. 如申請專利範圍第6項所述之積體電路裝置的形成方法，其中該第一層之沈積至少部分順應於該多個溝槽，而使該第二層覆於該多個側壁至少3nm。
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Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6503783B1 (en) * 2000-08-31 2003-01-07 Micron Technology, Inc. SOI CMOS device with reduced DIBL
JP4369359B2 (ja) * 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7429775B1 (en) * 2005-03-31 2008-09-30 Xilinx, Inc. Method of fabricating strain-silicon CMOS
US7737468B2 (en) * 2007-05-21 2010-06-15 Infineon Technologies Ag Semiconductor devices having recesses filled with semiconductor materials
US7892932B2 (en) * 2008-03-25 2011-02-22 International Business Machines Corporation Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
US20100012988A1 (en) * 2008-07-21 2010-01-21 Advanced Micro Devices, Inc. Metal oxide semiconductor devices having implanted carbon diffusion retardation layers and methods for fabricating the same
US7951657B2 (en) * 2009-05-21 2011-05-31 International Business Machines Corporation Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
US8022488B2 (en) * 2009-09-24 2011-09-20 International Business Machines Corporation High-performance FETs with embedded stressors
US8598003B2 (en) * 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US8368147B2 (en) 2010-04-16 2013-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained semiconductor device with recessed channel
US9698054B2 (en) 2010-10-19 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of a p-type field effect transistor
US20120100686A1 (en) 2010-10-20 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming ultra-shallow junctions in semiconductor devices
DE102011080438B3 (de) * 2011-08-04 2013-01-31 Globalfoundries Inc. Herstellverfahren für einen N-Kanaltransistor mit einer Metallgateelektrodenstruktur mit großem ε und einem reduzierten Reihenwiderstand durch epitaktisch hergestelltes Halbleitermaterial in den Drain- und Sourcebereichen und N-Kanaltransistor
US8659059B2 (en) * 2011-12-30 2014-02-25 Stmicroelectronics, Inc. Strained transistor structure
US9142643B2 (en) * 2012-11-15 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming epitaxial feature

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