TW201432692A - De-duplication system and techniques using NAND flash based content addressable memory - Google Patents

Abstract

A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. This arrangement can be applied to de-duplication: for data sets stored in a primary data storage section, corresponding data keys can be generated and store in search NAND. A received key, rather from external to the system or internally generated, can then be compared against the search NAND. The system can be applied to both in-line and off-line de-duplication.

Description

利用反及快閃為基的內容可定址記憶體之重複刪除系統及技術 Deduplication system and technology for addressable memory using reverse flash-based content

本發明大致係關於非揮發性記憶體且更具體言之係關於使用基於反及快閃記憶體之內容可定址記憶體或儲存器(CAM或CAS)以對資料執行重複刪除操作之此等磁碟機。 The present invention relates generally to non-volatile memory and, more particularly, to the use of anti-flash memory-based content addressable memory or memory (CAM or CAS) to perform such de-duplication operations on data. Disc player.

內容可定址記憶體(亦被稱作關聯記憶體)在資料被定址及擷取之方式上與標準記憶體不同。在習用記憶體中，位址被供應且位於此指定位址上之資料被擷取。相比之下，在內容可定址記憶體(CAM)中，資料被寫入為索引鍵-資料對。為了擷取資料，供應搜尋索引鍵且搜尋記憶體中之所有索引鍵進行一匹配。若找到一匹配，則擷取相應資料。 Content addressable memory (also known as associative memory) differs from standard memory in the manner in which data is addressed and retrieved. In the conventional memory, the address is supplied and the data located at the specified address is retrieved. In contrast, in content addressable memory (CAM), data is written as an index key-data pair. In order to retrieve the data, the search index key is supplied and all index keys in the memory are searched for a match. If a match is found, the corresponding data is retrieved.

內容可定址記憶體或CAM可以數種方式實施。在一種實施例中，一CAM使用一習用記憶體及搜尋記憶體以查找一匹配索引鍵之相關CPU實施。記憶體中之索引鍵可被分類，在此情況中，可使用二進制搜尋；或其等可被不分類，在此情況中，其等通常被雜湊至桶中且各桶被線性搜尋。一CAM亦可實施為半導體記憶體，其中每個記憶體位置含有一n位元比較器。當提供一n位元索引鍵時，CAM中之各項目將比較搜尋索引鍵與項目之索引鍵並且在兩者相等的情況下用信號發出一匹配。 Content addressable memory or CAM can be implemented in several ways. In one embodiment, a CAM uses a conventional memory and search memory to find an associated CPU implementation that matches an index key. The index keys in the memory can be classified, in which case a binary search can be used; or the like can be unclassified, in which case they are typically hashed into the bucket and the buckets are searched linearly. A CAM can also be implemented as a semiconductor memory in which each memory location contains an n-bit comparator. When an n-bit index key is provided, each item in the CAM will compare the search index key with the index key of the item and signal a match if the two are equal.

第一組態樣係關於一種操作非揮發性記憶體系統之方法。複數個資料集儲存在系統之一第一非揮發性記憶體區段中。對於資料集之各者，一相應簽章儲存在一搜尋陣列中，其中對於資料集之各者，簽章導出自相應資料集且為一較小大小，其中搜尋陣列為反及型架構且簽章儲存在搜尋陣列中，沿著搜尋陣列之位元線定向。記憶體系統維持資料集儲存在第一非揮發性記憶體區段中之位置及相應簽章儲存在搜尋陣列中之位置之間之一對應關係。該方法進一步包含：接收一第一簽章；根據第一簽章加偏壓於搜尋陣列之字線；及判定搜尋陣列之位元線之任意者是否回應於字線之該加偏壓而傳導。 The first configuration is a method of operating a non-volatile memory system. A plurality of data sets are stored in one of the first non-volatile memory segments of the system. For each of the data sets, a corresponding signature is stored in a search array, wherein for each of the data sets, the signature is derived from the corresponding data set and is a smaller size, wherein the search array is an inverse type architecture and The chapters are stored in the search array and oriented along the bit line of the search array. The memory system maintains a correspondence between the location of the data set stored in the first non-volatile memory segment and the location of the corresponding signature stored in the search array. The method further includes: receiving a first signature; biasing the word line of the search array according to the first signature; and determining whether any of the bit lines of the search array are transmitted in response to the bias of the word line .

其他態樣係關於一種非揮發性記憶體系統。該系統包含儲存複數個資料集之一第一非揮發性記憶體區段。系統亦包含具有一搜尋陣列之一種搜尋區段、偏壓電路及感測電路。搜尋陣列儲存針對資料集之各者之一相應簽章，其中針對資料集之各者，簽章導出自相應資料集且為一較小大小。搜尋陣列為反及型架構且簽章被儲存為沿著搜尋陣列之位元線定向。偏壓電路連接至搜尋陣列之字線。感測電路連接至搜尋陣列之位元線。基於一所接收之第一簽章，偏壓電路根據第一簽章加偏壓於搜尋陣列之字線且感測電路判定搜尋陣列之位元線之任意者是否回應於字線之該加偏壓而傳導。記憶體系統維持資料集儲存在第一非揮發性記憶體區段中之位置與相應簽章儲存在搜尋陣列中之位置之間之一對應關係。 Other aspects relate to a non-volatile memory system. The system includes a first non-volatile memory segment that stores one of a plurality of data sets. The system also includes a search section, a biasing circuit, and a sensing circuit having a search array. The search array stores a corresponding signature for each of the data sets, wherein for each of the data sets, the signature is derived from the corresponding data set and is a smaller size. The search array is a reverse architecture and the signatures are stored as oriented along the bit line of the search array. A bias circuit is coupled to the word line of the search array. The sense circuit is connected to the bit line of the search array. Based on a received first signature, the bias circuit biases the word line of the search array according to the first signature and the sensing circuit determines whether any of the bit lines of the search array respond to the word line Conducted by bias. The memory system maintains a correspondence between the location of the data set stored in the first non-volatile memory segment and the location of the corresponding signature stored in the search array.

本發明之各種態樣、優點、特徵及實施例包含在其例示性實例之下文描述中，該描述應結合附圖理解。針對所有目的，本文參考之所有專利、專利申請案、文章、其他公開案、檔案及事項之全文以參考的方式併入本文中。在所併入公開案、檔案或事項與本申請案之任意者之間在定義上或術語使用上存在任意不一致或衝突的範圍內，應 以本申請案之定義或術語使用為準。 The various aspects, advantages, features, and embodiments of the invention are included in the following description of the exemplary embodiments. The entire contents of all patents, patent applications, articles, other publications, files, and the disclosures herein are hereby incorporated by reference in its entirety for all purposes. In the event of any inconsistency or conflict between the definitions or the use of the terms in any of the incorporated publications, files or matters and any of the applications, Use of the definition or terminology of this application.

201‧‧‧單元陣列 201‧‧‧Unit array

203‧‧‧區塊 203‧‧‧ Block

205‧‧‧區塊 205‧‧‧ Block

207‧‧‧感測放大區段(S/A) 207‧‧‧Sensing amplification section (S/A)

213‧‧‧字線選擇閘極(WLSW) 213‧‧‧Word line selection gate (WLSW)

217‧‧‧選擇電路 217‧‧‧Selection circuit

223‧‧‧開關 223‧‧‧Switch

225‧‧‧開關 225‧‧‧ switch

231‧‧‧CG驅動器 231‧‧‧CG driver

233‧‧‧UCG驅動器 233‧‧‧UCG drive

235‧‧‧UCG驅動器 235‧‧‧UCG drive

301‧‧‧陣列 301‧‧‧Array

303‧‧‧區塊 303‧‧‧ Block

305‧‧‧區塊 305‧‧‧ Block

307‧‧‧感測電路(S/A) 307‧‧‧Sensor circuit (S/A)

313‧‧‧開關 313‧‧‧Switch

315‧‧‧開關 315‧‧‧ switch

317‧‧‧選擇電路 317‧‧‧Selection circuit

331‧‧‧CG驅動器 331‧‧‧CG driver

343‧‧‧字線驅動器 343‧‧‧Word line driver

345‧‧‧字線驅動器 345‧‧‧Word line driver

353‧‧‧開關 353‧‧‧ switch

355‧‧‧開關 355‧‧‧ switch

901‧‧‧記憶體陣列 901‧‧‧ memory array

903‧‧‧緩衝器 903‧‧‧buffer

905‧‧‧暫存器 905‧‧‧ register

1301‧‧‧主機 1301‧‧‧Host

1303‧‧‧緩衝記憶體 1303‧‧‧Buffered memory

1305‧‧‧反及內容可定址記憶體(CAM)記憶體 1305‧‧‧Reverse Content Addressable Memory (CAM) Memory

1503‧‧‧隨機存取記憶體(RAM) 1503‧‧‧ Random Access Memory (RAM)

1507‧‧‧匯流排 1507‧‧ ‧ busbar

1509‧‧‧小陣列 1509‧‧‧Small array

1601‧‧‧記憶體系統 1601‧‧‧ memory system

1611‧‧‧主機 1611‧‧‧Host

1603‧‧‧主儲存器固態磁碟機(SSD)區段 1603‧‧‧Main storage solid state disk drive (SSD) section

1605‧‧‧反及部分 1605‧‧‧Reverse part

2301‧‧‧區塊M 2301‧‧‧ Block M

2305‧‧‧SUM區塊 2305‧‧‧SUM block

2307‧‧‧鎖存器 2307‧‧‧Latch

3701‧‧‧儲存區塊 3701‧‧‧Storage block

3703‧‧‧資料比較區段 3703‧‧‧Data comparison section

3705‧‧‧雜湊索引鍵區塊 3705‧‧‧Hatch index key block

3707‧‧‧後設資料 3707‧‧‧Subsequent information

3801‧‧‧主儲存器區段 3801‧‧‧Main storage section

3803‧‧‧搜尋反及(sNAND)區段 3803‧‧‧Search reverse (sNAND) section

3805‧‧‧快閃後設資料圖 3805‧‧‧After flashing data

3809‧‧‧DRAM 3809‧‧‧DRAM

3811‧‧‧雜湊產生器 3811‧‧‧Cruciator

3813‧‧‧布隆濾波器區段 3813‧‧‧Bron filter section

3815‧‧‧壓縮引擎 3815‧‧‧Compression engine

4001‧‧‧重複刪除子系統 4001‧‧‧Delete Subsystem

4003‧‧‧主儲存器系統 4003‧‧‧Main storage system

4101‧‧‧重複刪除子系統 4101‧‧‧Repeat deletion subsystem

4103‧‧‧固態磁碟機(SSD)系統 4103‧‧‧Solid Disk Drive (SSD) System

4111‧‧‧中央處理單元(CPU) 4111‧‧‧Central Processing Unit (CPU)

4113‧‧‧布隆濾波器刀鋒(BF) 4113‧‧‧Bron filter blade (BF)

4115‧‧‧重複刪除刀鋒(DD) 4115‧‧‧Repeat the blade (DD)

4121-1‧‧‧中央處理單元(CPU) 4121-1‧‧‧Central Processing Unit (CPU)

4121-N‧‧‧中央處理單元(CPU) 4121-N‧‧‧Central Processing Unit (CPU)

4123‧‧‧北橋接器NB 4123‧‧‧North Bridge NB

4131-2‧‧‧儲存刀鋒(SB) 4131-2‧‧‧Storage Blade (SB)

4131-(N-1)‧‧‧儲存刀鋒(SB) 4131-(N-1)‧‧‧Storage Blade (SB)

4133‧‧‧傳輸刀鋒(TB) 4133‧‧‧Transportation Blade (TB)

4151‧‧‧SAN/NAS 4151‧‧‧SAN/NAS

BL0‧‧‧位元線 BL0‧‧‧ bit line

BL1‧‧‧位元線 BL1‧‧‧ bit line

BL2‧‧‧位元線 BL2‧‧‧ bit line

BLB‧‧‧反轉值版本 BLB‧‧‧ inverted version

BLN‧‧‧位元線 BLN‧‧‧ bit line

bln‧‧‧位元線 Bln‧‧‧ bit line

blm‧‧‧位元線 Blm‧‧‧ bit line

CELSRC‧‧‧共用源極線 CELSRC‧‧‧Shared source line

DFF(0/1)‧‧‧數位值 DFF (0/1)‧‧‧ digit value

HVLSHIFT‧‧‧位準移位器 HVLSHIFT‧‧‧ position shifter

SGD‧‧‧汲極選擇閘極 SGD‧‧‧Bungee selection gate

SGS‧‧‧源極選擇閘極 SGS‧‧‧Source selection gate

V0‧‧‧低感測值 V0‧‧‧ low sensing value

VREAD‧‧‧字線接收電壓 VREAD‧‧‧ word line receiving voltage

圖1係被用作一CAM記憶體之一反及陣列之一示意展現。 Figure 1 is a schematic representation of one of the arrays used as a CAM memory.

圖2係在一反及陣列中供應字線用於習用操作之一些元件之網路之一示意圖。 Figure 2 is a schematic illustration of one of the networks that supply word lines for some of the components of the conventional operation in an array.

圖3係在一反及陣列中供應字線用於CAM操作之一些元件之網路之一示意圖。 Figure 3 is a schematic illustration of one of the networks that supply word lines for some of the components of the CAM operation in an array.

圖4展示索引鍵可如何沿著一反及陣列之字線被寫入並被搜尋之一實施例。 Figure 4 shows one embodiment of how an index key can be written and searched along a word line opposite the array.

圖5給出有關來自圖4之一索引鍵/反轉值對如何被程式化至一對反及串中之一些細節。 Figure 5 gives some details about how the index key/inverted value pairs from one of Figure 4 are stylized into a pair of inverses and strings.

圖6A至圖6C展示索引鍵可如何沿著一反及陣列之位元線被寫入並被搜尋之另一實施例。 Figures 6A-6C show another embodiment of how an index key can be written and searched along a bit line that is opposite the array.

圖7展示用於四狀態記憶體單元操作之每個單元2位元之一例示性編碼。 Figure 7 shows an exemplary encoding of one of the two bits per cell for four state memory cell operations.

圖8展示在每個單元2位元實例中，資料狀態與用作反轉值索引鍵之互補資料如何對應。 Figure 8 shows how the data state corresponds to the complementary material used as the inverted value index key in each cell 2-bit instance.

圖9展示一索引鍵將如何編碼至位元線BL上之一4單元反及串上及其反轉值如何編碼至位元線BLB上之一實例。 Figure 9 shows an example of how an index key will be encoded onto one of the four elements on the bit line BL and on the string and how its inverted value is encoded onto the bit line BLB.

圖10繪示在字線方向上之內容之匹配之過程。 Figure 10 illustrates the process of matching the content in the direction of the word line.

圖11繪示一傳導位元線之位置可如何用作至可用於擷取與目標索引鍵相關之資料之另一表格之索引。 Figure 11 illustrates how the location of a conductive bit line can be used as an index to another table that can be used to retrieve data associated with a target index key.

圖12示意繪示一索引鍵-值對(key-value pair)如何儲存在一基於反及之CAM中且如何使用索引鍵存取值。 Figure 12 is a schematic illustration of how an index key-value pair is stored in an inverse CAM based and how the index key is used to access the value.

圖13繪示用於轉置資料索引鍵之一記憶體配置。 FIG. 13 illustrates a memory configuration for a transposed data index key.

圖14展現使用一FIFO型結構轉置資料之一第一硬體實施例。 Figure 14 illustrates a first hardware embodiment using one of the FIFO type transposed data.

圖15展現用於轉置資料之另一硬體實施例。 Figure 15 shows another hardware embodiment for transposing data.

圖16展示一記憶體系統將一CAM型反及併入至一固態磁碟機(SSD)中用於在記憶體系統內執行資料分析之記憶體系統之一實施例。 16 shows an embodiment of a memory system in which a memory system incorporates a CAM type into a solid state disk drive (SSD) for performing data analysis in a memory system.

圖17繪示如何藉由利用一陣列之反及結構執行結合數值範圍偵測之資料分析。 Figure 17 illustrates how data analysis for combined numerical range detection can be performed by utilizing an array of inverse structures.

圖18係針對圖17所示之過程之資料鎖存器指派之一實例。 Figure 18 is an example of a data latch assignment for the process illustrated in Figure 17.

圖19及圖20繪示兩個搜尋過程之一些步驟。 Figures 19 and 20 illustrate some of the steps of the two search processes.

圖21及圖22繪示一最大值及一最小值搜尋操作。 21 and 22 illustrate a maximum value and a minimum value search operation.

圖23及圖24分別給出一晶片上算術運算及一相應鎖存器利用之一示意展現。 Figures 23 and 24 show a schematic representation of an arithmetic operation on a wafer and the use of a corresponding latch, respectively.

圖25A至圖25C繪示可如何執行算術運算之一些細節。 25A-25C illustrate some details of how arithmetic operations can be performed.

圖26A及圖26B繪示更多鎖存器可如何用於執行涉及更多n之算術運算。 26A and 26B illustrate how more latches can be used to perform arithmetic operations involving more n.

圖27及圖28繪示至金融資料分析之一應用。 Figures 27 and 28 illustrate one application to financial data analysis.

圖29至圖31展示一資料集可如何被放置在超過一個反及串及相應鎖存器結構上之一些實例。 Figures 29 through 31 show some examples of how a data set can be placed over more than one inverted string and corresponding latch structure.

圖32及圖33分別繪示針對分析結果之數位及類比計數技術。 32 and 33 respectively illustrate the digital and analog counting techniques for the analysis results.

圖34給出用於對大型檔案系統執行分析之檔案映射之一實例。 Figure 34 shows an example of a file map for performing analysis on a large file system.

圖35係重複刪除過程之一闡釋。 Figure 35 is an illustration of one of the deduplication processes.

圖36示意繪示雜湊值用作資料集之一索引。 Figure 36 is a schematic illustration of the hash value used as an index into a data set.

圖37再次繪示雜湊值用作資料集之一索引，其中資料厚塊本身亦可被比較。 Figure 37 again shows that the hash value is used as an index for the data set, where the data chunks themselves can also be compared.

圖38係一重複刪除系統之一例示性架構。 Figure 38 is an exemplary architecture of an iterative deletion system.

圖39展示過時旗標位元可如何併入至反及串中。 Figure 39 shows how the obsolete flag bit can be incorporated into the inverse string.

圖40係將一重複刪除子系統併入至一SSD中之一簡化展現。 Figure 40 is a simplified representation of the incorporation of a deduplication subsystem into an SSD.

圖41係將一重複刪除子系統併入至一SSD中之一更詳細展現。 Figure 41 is a more detailed representation of incorporating a deduplication subsystem into an SSD.

基於反及快閃記憶體之內容可定址記憶體Addressable memory based on the content of the flash memory

下文提出一種使將一基於快閃之反及記憶體陣列用作可實現為二進制及三進制實施例之一內容可定址記憶體(CAM)之方法。如下文更詳細描述，索引鍵可沿著一區塊之位元線被程式化。搜尋索引鍵隨後沿著區塊之字線輸入，使得其上已程式化相應索引鍵之位元線將傳導。此允許一區塊之所有索引鍵同時被檢查。 A method of using a flash-based inverse memory array as a content addressable memory (CAM) that can be implemented as one of binary and ternary embodiments is presented below. As described in more detail below, the index keys can be stylized along a bit line of a block. The search index key is then entered along the word line of the block such that the bit line on which the corresponding index key has been programmed will be transmitted. This allows all index keys of a block to be checked at the same time.

讀取一反及記憶體陣列之典型方式在於每次一單條字線(或一字線之一部分)地讀出資料，其中沿著反及串之未選中字線被加偏壓使得其等完全接通而不管資料狀態如何，使未選中記憶體不影響讀取操作。以此方式，記憶體之資料內容每次一頁(讀取單位)地被讀出。相比之下，為了將一反及快閃記憶體用作一內容可定址記憶體，所有字線被設定為一特定資料相依值，其中資料係索引鍵，且記憶體判定哪些位元線隨後傳導，藉此判定特定位元線對應於輸入索引鍵，而非個別單元之資料。其中在一增強寫入後讀取操作之背景下感測電壓被施加至多條字線之一操作在2011年12月21日申請之美國專利申請案第13/332,780號中給出(且其亦大致提出有關反及快閃記憶體之更多細節)；但是，即使在此情況下，僅一些字線接收到一感測電壓。此外，在先前技術反及記憶體中，資料沿著字線對準，其中資料頁(針對讀取及寫入兩者)沿著字線對準。本文中，資料沿著位元線對準且沿著位元線之許多或甚至所有字線可接收足以在一程式化狀態中接通一單元之一高電壓或足以在擦除狀態中接通一單元之一低電壓。下文討論將使用基於EEPROM之快閃記憶體作為例示性實施例，但是舉例而言，亦可使用具有一反及型架構之其他記憶體裝置，包含3D反及(諸如T.Maeda等人，「Multi-stacked 1G cell/layer Pipe-shaped BiCS flash memory」，2009 Symposium on VLSI Circuits，第22頁至第23頁)。 A typical way of reading a reverse memory array is to read the data each time a single word line (or a portion of a word line), wherein the unselected word lines along the inverted string are biased such that they are completely equal Turn on regardless of the data status, so that unselected memory does not affect the read operation. In this way, the data content of the memory is read out one page (read unit). In contrast, in order to use a reverse flash memory as a content addressable memory, all word lines are set to a specific data dependent value, where the data is an index key and the memory determines which bit lines are subsequently followed. Conduction, thereby determining that a particular bit line corresponds to an input index key, rather than an individual unit. One of the sensing voltages being applied to one of the plurality of word lines in the context of an enhanced post-write read operation is given in U.S. Patent Application Serial No. 13/332,780, filed on Dec. 21, 2011 (and also More details about the inverse flash memory are presented; however, even in this case, only some of the word lines receive a sense voltage. Moreover, in prior art anti-memory, the data is aligned along the word line, with the data pages (for both read and write) aligned along the word line. Herein, the data is aligned along the bit line and many or even all of the word lines along the bit line are receivable to be high enough to turn on one of the cells in a stylized state or to be turned on in the erased state. One of the units is low voltage. The following discussion will use EEPROM-based flash memory as an illustrative embodiment, but for example, other memory devices with a reverse architecture may also be used, including 3D inverses (such as T. Maeda et al., Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash memory", 2009 Symposium on VLSI Circuits, pages 22 to 23).

在二進制、基於EEPROM之快閃記憶體中，在一寫入操作中，各單元被留在一擦除狀態或電荷被放置在單元之浮動閘極上以將單元置於一程式化狀態，其在本文中被視作1及0狀態。當讀取電壓之一低值被施加至其控制閘極時，僅處於擦除狀態或1狀態之一單元將傳導。對於程式化或0狀態中之單元，讀取電壓之一高值需被施加至一單元之控制閘極以傳導。索引鍵將沿著記憶體陣列之一區塊之位元線配置。由於1狀態中之一單元將針對任一讀取電壓傳導，故各索引鍵需以反轉值或非反轉值形式被寫入兩次。如下文討論，此可藉由沿著一位元線寫入目標索引鍵及沿著另一位元線寫入其反轉值，或向半條位元線寫入(非反轉值)目標索引鍵及向位元線之另一半寫入反轉值的目標索引鍵而完成。可使用多位元程式化將更多索引鍵資訊壓縮至反及鏈中。舉例而言，在一每個單元2至3位元情況中，索引鍵可在控制器RAM中分類且位元將被程式化為下(中)或上頁。下文討論將多數參考二進制實施例給出，下文討論多狀態情況之一些詳情。 In binary, EEPROM-based flash memory, in a write operation, each cell is left in an erased state or charge is placed on the floating gate of the cell to place the cell in a stylized state, This article is considered as a 1 and 0 state. When a low value of the read voltage is applied to its control gate, only one of the cells in the erased state or the 1 state will conduct. For a unit in a stylized or 0 state, one of the read voltages is applied to the control gate of a cell for conduction. The index key will be configured along the bit line of one of the blocks of the memory array. Since one of the 1 states will conduct for any of the read voltages, each index key needs to be written twice in the form of an inverted or non-inverted value. As discussed below, this can be done by writing a target index key along one bit line and writing its inverted value along another bit line, or writing a (non-inverted value) target to a half bit line. The index key is completed by writing the target index key of the inverted value to the other half of the bit line. Multi-bit stylization can be used to compress more index key information into the reverse chain. For example, in the case of 2 to 3 bits per cell, the index keys can be sorted in the controller RAM and the bits will be programmed into the lower (middle) or upper page. The discussion below is given in most of the reference binary embodiments, some of which are discussed below.

一般概念可由圖1繪示。目標索引鍵索引鍵0、索引鍵1、…沿著一反及區塊之位元線BL0、BL1、…程式化。資料被程式化在可藉由目標索引鍵之行位址編號索引之一單獨位置中。為了針對一索引鍵搜尋區塊，藉由根據高讀取電壓或低讀取電壓(其根據搜尋索引鍵)設定所有字線而在區塊之字線上廣播搜尋索引鍵。(除根據索引鍵設定字線電壓外，反及串末端上之選擇閘極亦需被接通)。各BL有效地同時比較其自身與區塊中之所有位元線之WL索引鍵型樣。若位元線索引鍵匹配搜尋索引鍵，則位元線之整體將傳導且「1」將被讀出。(注意，如進一步討論，此討論出於最後一段中討論之原因而稍加簡化)。一旦找到索引鍵之行索引，其即可用於從一「資料」區塊中找 取相應資料。索引鍵可為資料頁之雜湊碼，其將藉由匹配的反及鏈之行位址引至右資料頁。對於內容匹配應用程式，諸如資料壓縮或重複刪除，比如說，各16KB之內容可產生一相應雜湊碼，其可沿著反及鏈儲存。若沿著反及鏈之索引鍵匹配，則將比較資料頁與沿著字線之比較資料以避免雜湊衝突情況。在其他情況中，沿著字線之內容可能並非係一雜湊值，而是可被搜尋為資料之一索引鍵之資源元素之特性；或位元線本身可為資料本身之元素，而非至資料庫之一指標。 The general concept can be illustrated by Figure 1. The target index key index key 0, the index key 1, ... are stylized along the bit lines BL0, BL1, ... of the opposite block. The data is stylized in a separate location that can be indexed by the row index number of the target index key. To search for a block for an index key, the search index key is broadcast on the word line of the block by setting all word lines according to a high read voltage or a low read voltage (which is based on the search index key). (In addition to setting the word line voltage according to the index key, the selection gate on the end of the string must also be turned on). Each BL effectively compares its own WL index key pattern with all bit lines in the block at the same time. If the bit line index key matches the search index key, the entire bit line will be conducted and "1" will be read. (Note that as discussed further, this discussion is somewhat simplified for the reasons discussed in the last paragraph). Once the index of the index key is found, it can be used to find it from a "data" block. Take the appropriate information. The index key can be a hash code of the data page, which will be directed to the right data page by the matching reverse chain address. For content matching applications, such as data compression or deduplication, for example, each 16 KB of content can produce a corresponding hash code that can be stored along the inverse chain. If the index key is matched along the inverse chain, the data page will be compared with the data along the word line to avoid the hash conflict. In other cases, the content along the word line may not be a hash value, but a property of a resource element that can be searched for as an index key of the data; or the bit line itself can be an element of the data itself, rather than One indicator of the database.

在圖1所示之配置下，陣列之所有位元線及因此所有索引鍵同時被搜尋。在不使用所有位元線型之架構之陣列中，同時被搜尋之索引鍵數將為被並行感測之位元線數，諸如一奇偶配置中總數之一半。索引鍵之大小係字線數。在實務中，索引鍵之此等最大值通常將稍小，此係因為舉例而言，一些行通常為缺陷預留。 In the configuration shown in Figure 1, all of the bit lines of the array and thus all of the index keys are simultaneously searched. In an array that does not use all of the bit line architectures, the number of index keys being simultaneously searched will be the number of bit lines being sensed in parallel, such as one-half the total number in a parity configuration. The size of the index key is the number of word lines. In practice, these maximum values of index keys will usually be slightly smaller, because for example, some rows are usually reserved for defects.

如上所述，由於處於0狀態或1狀態之一記憶體單元將針對高讀取電壓傳導，故索引鍵將需以非反轉值及反轉值兩者之形式被輸入兩次。此可藉由在兩條位元線上程式化目標索引鍵、將索引鍵數減半或在相同位元線上程式化索引鍵之兩個版本，將索引鍵大小減半而完成。但是，假定可用反及區塊之大小，即使在此等減小之情況下，可並行檢查之索引鍵數仍非常大。相對於一些其他記憶體技術，反及快閃記憶體在其操作上具有相對大的延時，但是在許多應用中，此將被可並行檢查之索引鍵(位元線)數(舉例而言，128K)更多地抵消。過程可皆在晶片上完成，且由於僅滿足匹配情況之位元線以相對低的功率消耗傳導電流，使得與將所有資料從記憶體中切換出來及在控制器中進行比較相比，其係一相對低功率及更高速度之過程。 As described above, since one of the memory cells in the 0 state or the 1 state will conduct for the high read voltage, the index key will need to be input twice in the form of both the non-inverted value and the inverted value. This can be done by styling the target index key on two bit lines, halving the index key number, or staging the two versions of the index key on the same bit line, halving the index key size. However, assuming that the size of the block can be reversed, even in the case of such a decrease, the number of index keys that can be checked in parallel is still very large. In contrast to some other memory technologies, the flash memory has a relatively large delay in its operation, but in many applications, this will be the number of index keys (bit lines) that can be checked in parallel (for example, 128K) more offset. The process can all be done on the wafer, and because only the bit line that satisfies the matching condition conducts current with relatively low power consumption, compared to switching all the data out of the memory and comparing it in the controller. A relatively low power and higher speed process.

關注一些實施方案細節，一例示性實施例可基於一快閃記憶體，其中索引被保存在128Gb反及鏈上。使用一全位元線(ABL)架構，其中一感測操作將同時對一區塊上之所有索引執行一匹配操作。 包含額外行冗餘以避免任意壞行(有關此冗餘及行存取以及一般而言快閃記憶體之更多細節可見於下列美國專利公開案/申請案號：US-2005-0141387-A1；US-2008-0266957-A1；US-2011-0002169-A1；US-2010-0329007-A1；13/463,422；及13/420,961)。相同資料之兩個複本資料(Data)及資料條(Data Bar)被寫入至反及鏈中。在本實例中，此允許具有128位元索引鍵之16KB/2/2=32000組資訊。 Concerning some implementation details, an exemplary embodiment may be based on a flash memory in which the index is stored on a 128Gb inverse chain. Using an all-bit line (ABL) architecture, one sensing operation will perform a matching operation on all indexes on a block at the same time. Include extra row redundancy to avoid any bad lines (more details on this redundancy and row access and in general flash memory can be found in the following US Patent Publication/Application No.: US-2005-0141387-A1 ; US-2008-0266957-A1; US-2011-0002169-A1; US-2010-0329007-A1; 13/463,422; and 13/420,961). Two copies of the same data (Data) and data bars (Data Bar) are written into the reverse chain. In this example, this allows 16KB/2/2=32000 sets of information with a 128-bit index key.

在寫入索引鍵時，此等通常將被逐頁寫入，但是在允許逐頁寫入之記憶體中，部分頁程式化可用於寫入索引鍵之部分，隨後添加更多。對於多狀態實施方案，此部分頁程式化通常比在二進制區塊中更受限。作為一實例，資料可被移位至記憶體上且反轉值資料可在記憶體上產生以省去控制器對此等資料操縱之努力，其中資料及資料條可在資料不移位的情況下寫入兩次，資料首先被寫入，且所產生之反轉值接下來被寫入。索引鍵及資料兩者可被輸入至記憶體系統中，或在一些情況中，可藉由控制器在記憶體系統上從資料中產生索引鍵，諸如藉由從資料中產生雜湊值以用作索引鍵。若索引鍵將在沿著位元線寫入前分類，則此歸因於所涉及之資料數量(諸如多個區塊量之資料)而通常將在控制器上完成。舉例而言，資料可最初被寫入一特定區域中，比如說晶粒0、平面0、區塊0至15，且隨後被分類及寫入至已被分類為區塊級之區塊中。另一選擇係，索引鍵在將其分類為所要粒度級並將其等寫入至一組區塊中之前可在RAM中(在控制器上或一單獨晶片上)或快取反及記憶體(諸如美國臨時申請案第61/713,038號中描述)中組合。 When writing index keys, these are usually written page by page, but in memory that allows page-by-page writes, partial page stylization can be used to write the portion of the index key, and then add more. For multi-state implementations, this partial page stylization is usually more limited than in binary blocks. As an example, the data can be shifted to the memory and the inverted value data can be generated on the memory to save the controller from trying to manipulate the data, wherein the data and the data strip can be shifted without data. Write twice, the data is first written, and the resulting inverted value is written next. Both the index key and the data can be input to the memory system, or in some cases, the controller can generate an index key from the material on the memory system, such as by generating a hash value from the data to serve as Index key. If the index key will be sorted prior to writing along the bit line, this is typically done on the controller due to the amount of data involved, such as data for multiple block sizes. For example, data can be initially written into a particular area, such as die 0, plane 0, blocks 0 through 15, and then sorted and written into blocks that have been classified as block level. Alternatively, the index key can be in RAM (on the controller or on a separate wafer) or cached and memory before sorting it into the desired level of granularity and writing it to a set of blocks. A combination (such as described in US Provisional Application No. 61/713,038).

如下文進一步討論，資料/資料條對可被寫入在兩條位元線或一單條位元線上。當資料/資料條對被寫入兩條位元線上時(諸如參考圖4討論)，該等對可緊隨彼此地被寫入或以其他型樣被寫入，諸如在一區域中寫入資料位元線，且在另一區中寫入反轉值的資料位元線。當 對之兩個部分被寫入在相同位元線上時(如下文參考圖6A討論)，其等可以一頂部/底部格式或交錯寫入。舉例而言，當資料及反轉值資料經交錯以沿著字線交替時，此具有一列中最多兩個元素沿著位元線係相同的優點；此外，交錯可導致至記憶體上之高效資料轉移，此係因為首先，資料之一頁被轉移至記憶體上且下一頁可能剛好藉由反轉值所有位元而產生在鎖存器中，此係因為下一頁係第一頁之反轉值資料。 As discussed further below, the data/data strip pairs can be written on two bit lines or a single bit line. When a data/item pair is written on two bit lines (such as discussed with reference to Figure 4), the pairs can be written next to each other or written in other patterns, such as writing in an area. The data bit line is written, and the data bit line of the inverted value is written in another area. when When two parts are written on the same bit line (as discussed below with reference to Figure 6A), they can be written in a top/bottom format or interleaved. For example, when data and inverted value data are interleaved to alternate along a word line, this has the advantage that up to two elements in a column are the same along the bit line; in addition, interleaving can result in high efficiency on the memory. Data transfer, because first, one page of the data is transferred to the memory and the next page may be generated in the latch by simply inverting all the bits. This is because the next page is the first page. Inversion value data.

匹配的索引隨後可被連結至對應於所判定行位址之其他資料；舉例而言，索引鍵可為諸如來自一安全雜湊演算法(SHA)之一雜湊值，其用於指向亦可儲存在記憶體本身上之其他位置之實際資料。所有匹配可在反及晶片內完成且當找到匹配時，若需要，行位址亦可被轉移出來或若亦儲存在反及晶片上，則僅資料可被轉移出來。 The matching index can then be linked to other data corresponding to the determined row address; for example, the index key can be a hash value such as from a Secure Hash Algorithm (SHA), which can also be used to point to Actual information on other locations on the memory itself. All matches can be done in the opposite direction and when a match is found, the row address can be transferred if necessary or if it is also stored on the opposite wafer, only the data can be transferred.

為了高效實施將一反及陣列用作一CAM記憶體，可對字線驅動電路進行變化。為了沿著一區塊之字線廣播一搜尋索引鍵，除接通反及串之任一端上之選擇閘極外，區塊之各字線亦需根據搜尋索引鍵設定為高讀取電壓或低讀取電壓。此與典型反及操作形成對比，其中針對一讀取電壓一次僅選擇一單條字線，所有其他字線接收足以使其等不影響感測而不管其等之資料狀態如何之一通過電壓。 In order to efficiently implement an inverted array as a CAM memory, the word line driver circuit can be varied. In order to broadcast a search index key along the word line of a block, in addition to the selection gate on either end of the reverse and the string, the word lines of the block also need to be set to a high read voltage according to the search index key or Low read voltage. This is in contrast to a typical inverse operation in which only a single word line is selected at a time for a read voltage, all other word lines receiving a voltage sufficient to cause it to not affect the sensing regardless of the state of the data.

圖2係在一反及陣列中供應字線用於習用操作之一些元件之網路之一示意圖。201係一反及晶片之一平面之單元陣列，其中兩個區塊明確標註為203及205。各區塊之字線由一字線選擇閘極WLSW 213或215根據來自選擇電路217之控制而饋送。位元線未被指示，但將向下延伸至感測放大區塊S/A 207。隨後分別經由開關223及225從驅動器CG驅動器231及UCG驅動器233及235供應不同的控制閘極電壓CGI至選擇閘極213及215。在本文所示之例示性實施例中，一區塊被視作具有132條字線，其中一對虛設字線包含在反及串之汲極側及源極側 上。UCG驅動器233及235用於供應程式化、(標準、非CAM)讀取或驗證操作期間用在未選中字線上之通過電壓。由於此位準用在大多數字線上，故此等可針對一單個驅動器集總在一起。所選控制閘極在程式化時被加偏壓至VPGM，在讀取或驗證時被加偏壓至CGR電壓。在圖2中，CGI<126：1>係經解碼之全域CG線。CGI<0>及CGI<127>，其等在本文中歸因於邊緣字線效應而不同於其他126條字線被加偏壓。虛設字線偏壓CGD0/1係針對汲極側虛設字線且CGDS0/1係針對源極側虛設字線。 Figure 2 is a schematic illustration of one of the networks that supply word lines for some of the components of the conventional operation in an array. 201 is an array of cells in one plane opposite to the wafer, two of which are clearly labeled 203 and 205. The word lines of the respective blocks are fed by a word line selection gate WLSW 213 or 215 in accordance with control from the selection circuit 217. The bit line is not indicated but will extend down to the sense amplification block S/A 207. Different control gate voltages CGI are then supplied from the driver CG driver 231 and the UCG drivers 233 and 235 via the switches 223 and 225 to the selection gates 213 and 215, respectively. In the exemplary embodiment shown herein, a block is considered to have 132 word lines, with a pair of dummy word lines being included on the drain side and the source side of the inverted string on. UCG drivers 233 and 235 are used to supply the pass voltages used on unselected word lines during stylized, (standard, non-CAM) read or verify operations. Since this bit is used on most word lines, this can be aggregated together for a single drive. The selected control gate is biased to VPGM during programming and is biased to the CGR voltage during reading or verification. In Figure 2, CGI < 126: 1> is the decoded global CG line. CGI<0> and CGI<127>, which are differently biased from the other 126 word lines due to the edge word line effect herein. The dummy word line bias CGD0/1 is for the drain side dummy word line and the CGDS0/1 is for the source side dummy word line.

針對一典型的反及記憶體操作，一次僅個別加偏壓於一些字線。除一所選字線外，毗鄰或邊緣字線亦可接收特殊偏壓位準以改良操作。因此，現有字線驅動器經配置使得其等可僅關注少數字線。在邏輯變化的情況下，可能可驅動高達可能二十四條左右之字線。但是，驅動一區塊之所有字線(本文中128個，忽略虛設字線)將需要額外類比驅動器。圖3繪示一些此等變化。 For a typical inverse memory operation, only a few word lines are biased at a time. In addition to a selected word line, adjacent or edge word lines can also receive special bias levels to improve operation. Thus, existing word line drivers are configured such that they can focus on only a few digit lines. In the case of a logical change, it is possible to drive up to twenty-four possible word lines. However, driving all of the word lines of a block (128 in this case, ignoring the dummy word lines) will require an additional analog driver. Figure 3 illustrates some of these changes.

陣列301、區塊303及305、選擇電路317、CG驅動器331及開關313及315可與圖2中相同。額外字線驅動器展示於343及345且可透過各自開關353及355供應字線。在343及345之各者中，位準移位器HVLSHIFT針對各字線接收電壓VREAD及一數位值DFF(0/1)。位準移位器隨後將廣播索引鍵之數位值0、1轉換為類比高字線位準及類比低字線位準。由於記憶體單元仍將需被寫入(程式化或程式驗證兩者)，故圖2中概略繪出之另一電路仍將存在，但未展示在圖3中以簡化討論。亦可能較佳對感測電路S/A 307進行一些變化以在保持一索引鍵及其反轉值之位元線對之間更高效地執行下文所述之「互斥或」運算。 The array 301, the blocks 303 and 305, the selection circuit 317, the CG driver 331, and the switches 313 and 315 can be the same as in FIG. Additional word line drivers are shown at 343 and 345 and word lines can be supplied through respective switches 353 and 355. In each of 343 and 345, the level shifter HVLSHIFT receives a voltage VREAD and a digital value DFF (0/1) for each word line. The level shifter then converts the digital value 0, 1 of the broadcast index key to an analog high word line level and an analog low word line level. Since the memory cells will still need to be written (both programmed or programmed), another circuit outlined in Figure 2 will still exist, but is not shown in Figure 3 to simplify the discussion. It may also be preferable to make some changes to the sensing circuit S/A 307 to perform the "mutual exclusion" operation described below more efficiently between bit pairs that maintain an index key and its inverted value.

圖4展示沿著位元線之索引鍵之編碼，其中索引鍵以非反轉值形式及反轉值形式被輸入兩次。本文中，位元線針對非反轉值索引鍵被 標註為BL且針對反轉值版本被標註為BLB。本文中，該等對被展示為毗鄰，但是不一定如此，而是通常將使「互斥或」運算及跟蹤資料更容易。此外，此配置易適於使用一奇/偶BL配置之反及陣列。如圖4的一半所展示，作為參考，全部1之一索引鍵沿著BL1被寫入且全部0之一索引鍵沿著BLn被寫入，其中相應反轉值索引鍵在BLB1及BLBn上。對於有缺陷位元線，位元線黏著為「0」或黏著為「1」，而不管字線電壓偏壓如何。兩個讀取結果之間之「互斥或」結果將總是產生「1」。BL及BLB資料型樣將使缺陷位元線免於錯誤地產生匹配結果。在本實例中，僅使用七條字線。如亦繪示在圖5中，一更有趣的索引鍵(1001101)被輸入在BLn+1上，其反轉值版本在BLBn+1上。 Figure 4 shows the encoding of the index key along the bit line, where the index key is entered twice in the form of a non-inverted value and an inverted value. In this paper, the bit line is indexed for the non-inverted value index key. Labeled as BL and labeled as BLB for the inverted value version. In this article, the pairs are shown as being contiguous, but not necessarily so, but will generally make "mutual exclusion" operations and tracking data easier. In addition, this configuration is easily adapted to use an inverse of an odd/even BL configuration. As shown in half of FIG. 4, for reference, one of the index keys of all 1 is written along BL1 and one of the index keys of all 0 is written along BLn, where the corresponding inverted value index keys are on BLB1 and BLBn. For defective bit lines, the bit line is glued to "0" or glued to "1" regardless of the word line voltage bias. The "mutually exclusive" result between the two readings will always produce a "1". The BL and BLB data patterns will protect the defective bit lines from erroneously producing matching results. In this example, only seven word lines are used. As also shown in Figure 5, a more interesting index key (1001101) is entered on BLn+1 with its inverted version at BLBn+1.

圖5展示兩個相應反及串，其中0係一程式化單元，1係保留在其擦除狀態之一單元，單元沿著反及串串聯連接至共用源極線CELSRC。為了搜尋此索引鍵，其被針對0項目被編碼為低讀取電壓且針對1被編碼為高讀取電壓。搜尋索引鍵被展示在圖5左上方。如感測1列中之「c」(及「nc」)所示，在被置於字線上時，此相應地發現BLn+1在傳導(且BLBn+1不傳導)。但是，BL1及BLBn兩者亦傳導，此係因為1狀態中之一單元將針對任意讀取值傳導。 Figure 5 shows two corresponding inverse strings, where 0 is a stylized unit, 1 is reserved in one of its erased states, and the cells are connected in series along the reverse and serial to the common source line CELSRC. In order to search for this index key, it is encoded as a low read voltage for a 0 item and as a high read voltage for 1 . The search index key is shown at the top left of Figure 5. As shown by "c" (and "nc") in the sense 1 column, when placed on the word line, this correspondingly finds that BLn+1 is conducting (and BLBn+1 is not conducting). However, both BL1 and BLBn are also conducted, since one of the 1 states will conduct for any read value.

隨後以反轉值搜尋進行第二感測(此等可以任意順序執行)。雖然BL1及BLBn仍傳導，但是來自實際上找到的索引鍵之結果已改變：BLn+1現未傳導且BLBn+1傳導。藉由取得兩個讀取之結果並對其等進行「互斥或」運算，所找到的索引鍵將在相應位元線上及亦在其反轉值版本上給出一0。因此，藉由搜尋「互斥或」資料中之00型樣，輸入行位址可被找到且相應資料區塊可被存取。在圖4中所使用之類型之實施例下，需要兩次讀取用於型樣匹配且反及裝置上之內部型樣偵測可判斷是否存在一匹配。BL/BLB對之冗餘提供冗餘以幫助防止壞位元線的影響，但是一第二對亦可被保留用於進一步保護。索引鍵 之一複本亦可與任意相關資料保留在一起且用於檢查匹配，此複本可為受ECC保護的。為了錯誤偵測及校正目的，亦可藉由各位元線包含數個(舉例而言，8個)同位位元而提供額外保護，其中冗餘位元較佳沿著針對所有索引鍵之相同位元線，使得如下所述，此等同位位元可藉由使用施加至此等字線之一「隨意(don't care)」值而被讀取或取出用於比較。舉例而言，資料可在檢查資料時被讀取，作為一寫入後讀取或另一資料完整性檢查之部分，但在CAM型操作期間被忽略。 A second sensing is then performed with an inverted value search (this can be performed in any order). Although BL1 and BLBn are still conducting, the result from the actually found index key has changed: BLn+1 is now not conducting and BLBn+1 is conducting. By taking the results of the two reads and performing a "mutually exclusive" operation on them, the found index key will give a zero on the corresponding bit line and also on its inverted version. Therefore, by searching for the 00 type in the "mutually exclusive" data, the input row address can be found and the corresponding data block can be accessed. In the embodiment of the type used in Figure 4, two reads are required for pattern matching and the internal pattern detection on the device can be used to determine if there is a match. The BL/BLB provides redundancy for redundancy to help prevent the effects of bad bit lines, but a second pair can also be reserved for further protection. Index key A copy may also be kept with any relevant material and used to check for matches, which may be ECC protected. For error detection and correction purposes, additional protection may be provided by the inclusion of a number of (for example, 8) co-located bits, where the redundant bits are preferably along the same bit for all index keys. The meta-line is such that, as described below, the equivalent bit can be read or fetched for comparison by using a "don't care" value applied to one of the word lines. For example, data can be read as part of a post-write read or another data integrity check, but is ignored during CAM-type operations.

通常，對於本文所述之此實施例及其他實施例，一寫入後讀取可用於確保索引鍵已被成功寫入至反及記憶體中，此係因為任意錯誤位元可能阻止一反及串傳導且將在匹配時產生「假陰性」。若找到一錯誤，則壞資料可被重寫。在例示性反及快閃實例中，錯誤寫入之資料可被重寫至另一資料區塊且任意索引鍵-資料對應關係相應地更新。有關寫入後讀取操作之更多細節可見於美國專利申請案第13/332,780號及其中所引用之參考。 In general, for this and other embodiments described herein, a post-write read can be used to ensure that the index key has been successfully written to the memory, since any error bit may prevent a reversal. Strings are transmitted and will produce a "false negative" when matched. If an error is found, the bad data can be rewritten. In the exemplary inverse flashing example, the erroneously written material can be rewritten to another data block and the arbitrary index key-data correspondence is updated accordingly. Further details regarding the post-write read operation can be found in U.S. Patent Application Serial No. 13/332,780, the disclosure of which is incorporated herein by reference.

有關效能，在一16KB頁之128位元索引鍵之情況中，若資料及其反轉值兩者之兩個複本被儲存，則對應於4KB之索引鍵或32000個索引鍵。(由於所有字線立刻被感測，因此本文中，一「頁」涉及感測一區塊之所有字線而非一單條字線)。若此頁32000個索引鍵在50us內被感測，則此係每秒每平面0.64GC(十億比較)之一速率。若四個平面被並行感測，此可在大約200mW之一消耗下導致2.56GC/s。 Regarding performance, in the case of a 128-bit index key of a 16 KB page, if two copies of the data and its inverted value are stored, it corresponds to an index key of 4 KB or 32,000 index keys. (Since all word lines are sensed immediately, a "page" in this article involves sensing all word lines of a block rather than a single word line). If 32,000 index keys on this page are sensed within 50us, this is a rate of 0.64 GC per second per plane (billion comparison). If the four planes are sensed in parallel, this can result in 2.56 GC/s at one of approximately 200 mW.

圖6A繪示索引鍵可如何沿著一位元線儲存之一第二實施例。在此情況中，索引鍵及其反轉值被寫入至相同位元線上。針對一給定區塊，此意味著最大索引鍵大小僅係字線數的一半，但此允許搜尋索引鍵及反轉值索引鍵同時被廣播。因此，搜尋可在一單次讀取中完成。 Figure 6A illustrates a second embodiment of how an index key can be stored along a single bit line. In this case, the index key and its inverted value are written to the same bit line. For a given block, this means that the maximum index key size is only half the number of word lines, but this allows the search index key and the inverted value index key to be broadcast simultaneously. Therefore, the search can be done in a single read.

參考圖6A，此展示14條不同字線，其中索引鍵在位元線之頂半部輸入且此等相同索引鍵之反轉值版本在相同位元線之底半部中以反 轉值形式輸入。因此，取D7上之位元線，列1至7保持一7位元索引鍵且列8至14保持相同索引鍵之反轉值版本。(雖然類似於圖4配置，但是在圖6A中，頂半部及底半部展現14條不同的字線，其中頂部-底部分割區係索引鍵/反轉值索引鍵邊界，而在圖4中，頂部及底部係相同七條字線針對兩個不同感測操作重複兩次)。為了比較目的，圖6A中展示之索引鍵與圖4中相同，其中位元線D7在頂半部中保持找到的索引鍵且在底半部中保持其反轉值，且D8保持反轉值索引鍵使得此兩個半部被切換。 Referring to FIG. 6A, there are shown 14 different word lines, wherein the index key is input at the top half of the bit line and the inverted value versions of the same index keys are in the bottom half of the same bit line. Input form input. Thus, taking the bit line on D7, columns 1 through 7 hold a 7-bit index key and columns 8 through 14 maintain the inverted version of the same index key. (Although similar to the configuration of FIG. 4, in FIG. 6A, the top half and the bottom half exhibit 14 different word lines, wherein the top-bottom partition is an index key/inverted value index key boundary, and in FIG. 4 In the middle, the top and bottom are the same seven word lines repeated twice for two different sensing operations). For comparison purposes, the index key shown in Figure 6A is the same as in Figure 4, where bit line D7 holds the found index key in the top half and maintains its inverted value in the bottom half, and D8 maintains the inverted value The index key causes the two halves to be switched.

為了搜尋一索引鍵，搜尋型樣隨後在頂半部字線上廣播且其反轉值在底半部字線上廣播。在此情況D7中，具有一匹配索引鍵之任意位元線隨後將傳導，如底部所示，其中「nc」係非傳導且「c」係傳導。若需要冗餘，則非反轉值版本亦可如在D8上被程式化且隨後藉由廣播非反轉值搜尋索引鍵而被偵測，且位元線讀取搜尋一11型樣，其隨後可被輸出為一資料指標。若想要進一步冗餘，則索引鍵或索引鍵對/反轉值對可第二次被寫入至陣列中且亦可包含同位位元，其幾乎與針對基於圖4之實施例討論一樣。缺陷位元線應與隔離鎖存器隔離且不使用。若一些缺陷出現為黏著為「0」，則其可潛在地產生「假」匹配。在此情況中，應比較資料內容以確認此係一真匹配還是一假匹配。另一最常見的可靠性問題在於一些單元在一段時間後可能已經丟失一些電荷，其亦將產生一「假」匹配。隨後，一內容匹配檢查將消除「假」匹配錯誤。字線電壓偏壓可被預算為更高一點以避免「遺漏」一匹配，其係非常有害的錯誤。一「假」匹配可用內容檢查進行雙重檢查。 To search for an index key, the search pattern is then broadcast on the top half of the word line and its inverted value is broadcast on the bottom half of the word line. In this case D7, any bit line with a matching index key will then be conducted, as shown at the bottom, where "nc" is non-conducting and "c" is conducting. If redundancy is required, the non-inverted version can also be detected as programmed on D8 and then detected by broadcasting a non-inverted value search index key, and the bit line read searches for an 11 pattern, It can then be output as a data indicator. If further redundancy is desired, the index key or index key pair/inverted value pair can be written to the array a second time and can also contain co-located bits, almost as discussed for the embodiment based on FIG. The defective bit line should be isolated from the isolation latch and not used. If some defects appear to be "0", they can potentially produce a "false" match. In this case, the data content should be compared to confirm whether the system is a true match or a false match. Another most common reliability issue is that some cells may have lost some charge after a while, which will also produce a "false" match. Subsequently, a content match check will eliminate the "false" match error. The word line voltage bias can be budgeted a bit higher to avoid a "missing" match, which is a very harmful error. A "fake" match allows for a double check of the content check.

圖6B示意繪示沿著反及串的索引鍵/反轉值對。兩個串被展示為(針對位元線BLn及BLm)在任一端上各具有一汲極及源極選擇閘極(SGD、SGS)，其中源極端隨後沿著源極線CELSRC連接。其間係串 聯連接之串上之記憶體單元。在本實例中，串具有保持一48位元索引鍵、48位元反轉值及一些同位位元之單元容量。雖然本文中繪示為索引鍵沿著前48條字線，之後是反轉值沿著接下來48條字線，更一般地，其等可以不同方式交錯；舉例而言，索引鍵位元之各者之後可在下一字線中跟隨其反轉值，此係因為在程式化時，此允許一頁載入並寫入，在此之後，程式化資料可在鎖存器中反轉值並寫入至下一字線中。同位位元亦可沿著反及串不同地定位，但是使其等分組可導致在搜尋索引鍵時更容易的解碼。 Figure 6B schematically illustrates an index key/inverted value pair along the inverse string. The two strings are shown (for bit lines BLn and BLm) each having a drain and source select gate (SGD, SGS) on either end, with the source terminals subsequently connected along the source line CELSRC. String in between A memory unit connected to the string. In this example, the string has a cell capacity that maintains a 48-bit index key, a 48-bit inverted value, and some parity bits. Although shown herein as index keys along the first 48 word lines, followed by inverted values along the next 48 word lines, more generally, they may be interleaved in different ways; for example, index key bits Each can then follow its inverted value in the next word line, because this allows a page to be loaded and written during programmaticization, after which the stylized data can be inverted in the latch and Write to the next word line. The parity bits can also be positioned differently along the inverse string, but grouping them can result in easier decoding when searching for index keys.

位元線BLn及BLm之各者展示沿著四條毗鄰字線及保持反轉值之相應四條毗鄰字線之一索引鍵之一部分。為了搜尋區塊之索引鍵，字線隨後根據搜尋索引鍵被加偏壓，其中高感測電壓用於檢查「0」值且低感測電壓用於檢查「1」值。高值在本文中被視作VREAD且可與未選中字線之一典型反及記憶體中使用的相同，且低感測值被標註為V0。選擇閘極亦需接通且VREAD亦應施加至保持同位位元之字線，如此等用於資料完整性檢查且並非作為索引鍵搜尋操作中之因素。 Each of the bit lines BLn and BLm exhibits a portion of the index key along one of the four adjacent word lines and the corresponding four adjacent word lines that hold the inverted value. To search for the index key of the block, the word line is then biased according to the search index key, where the high sense voltage is used to check the "0" value and the low sense voltage is used to check the "1" value. The high value is considered herein as VREAD and can be the same as that used in one of the unselected word lines, and the low sensed value is labeled as V0. The selection gate also needs to be turned on and VREAD should also be applied to the word line holding the parity bit, so that it is used for data integrity checking and is not a factor in the index key search operation.

為了使所儲存的索引鍵更穩健，記憶體可移位感測邊際以利於「假」匹配而非遺漏。(類似地，程式化參數可相對於通常所使用之參數移位)。隨後可藉由資料檢查檢驗「假」匹配以幫助移除任意假陽性。一重複索引鍵可用於檢查以防止錯誤，其中此等重複索引鍵可連同相關資料儲存在其他反及串上，或系統上之其他位置上。如參考圖2及圖3所述，有關一標準反及記憶體，此配置將需添加額外電路。 In order to make the stored index keys more robust, the memory can shift the sensing margin to facilitate "false" matching rather than missing. (Similarly, the stylized parameters can be shifted relative to the parameters that are typically used). A "fake" match can then be verified by a data check to help remove any false positives. A repeat index key can be used to check for errors, where such duplicate index keys can be stored along with related data on other reverse strings, or other locations on the system. As described with reference to Figures 2 and 3, for a standard inverse memory, this configuration will require the addition of additional circuitry.

取代在一單次感測中感測全索引鍵(或索引鍵/反轉值)搜尋，可搜尋一部分索引鍵，其允許全索引鍵/反轉值匹配遞增地完成。此可允許較無法獨立設定之字線位準，導致相對於一標準反及記憶體之較小電路變化，但其可需要一些邏輯變化。全索引鍵/反轉值可依序被搜尋，其中各後續感測將基於先前感測結果判斷。對於圖6B之實 例，取代一次性檢查索引鍵/反轉值之所有24+24字線，一次可完成(比如說)24位元之一部分索引鍵檢查：若未找到匹配，則過程可移至保持索引鍵之任意其他區塊；若找到一匹配，則可檢查第二部分索引鍵，及等等。後續檢查可再次針對所有反及串及比較部分搜尋之結果，或僅檢查在先前部分索引鍵匹配中進行之搜尋。圖6C繪示此一部分索引鍵比較，其中索引鍵中僅48位元中之24位元被檢查。索引鍵之其他位元及其反轉值隨後被設定為「隨意」值，如設定在VREAD上之反轉值之相應位元上所示。 Instead of sensing a full index key (or index key/inverted value) search in a single sense, a portion of the index key can be searched, which allows the full index key/inverted value match to be done incrementally. This may allow for word line levels that are less than independently configurable, resulting in smaller circuit variations relative to a standard inverse memory, but which may require some logic variation. The full index key/inverted value can be searched sequentially, with each subsequent sense being judged based on the previous sensed result. For Figure 6B For example, instead of checking all the 24+24 word lines of the index key/inverted value at one time, one part of the 24-bit index key check can be done at one time (for example): if no match is found, the process can be moved to the hold index key. Any other block; if a match is found, the second part of the index key can be checked, and so on. Subsequent checks can again search for results for all reverse and compare partial searches, or only for searches made in previous partial index key matches. Figure 6C illustrates this partial index key comparison where only 24 of the 48 bits in the index key are checked. The other bits of the index key and their inverted values are then set to a "random" value, as indicated by the corresponding bit set to the inverted value on VREAD.

當各索引鍵在一位元線上寫入兩次(以非反轉值、反轉值形式)時，具有128條字線之一區塊可保持64位元索引鍵，而128位元索引鍵將需要256條字線之區塊。此外，應注意，雖然索引鍵/反轉值索引鍵在此處被展示為分別寫入至字線之頂半部/底半部中。更一般而言，索引鍵及反轉值對可以任意所要方式交錯，只要其對於區塊中之所有索引鍵係一致的；但是，此將需要追蹤配置。沿著反及鏈之交錯型樣可能較佳，此係因為資料可在另一WL中反轉值程式化而無需再次載入資料。存在亦可得益於在毗鄰字線上使反轉值及非反轉值資料交錯之一些其他耦合效應。有關此類型之實施例之效能，對於一16KB頁之64位元索引鍵，若保留一重複索引鍵/反轉值索引鍵對，則此係8KB或64,000個索引鍵。在每次感測35us下，此給出1.82C/s/平面。若4個平面被並行操作，則此係大約200mW下之7.3CG/s。 When each index key is written twice on a bit line (in the form of non-inverted value, inverted value), one block with 128 word lines can hold the 64-bit index key, and the 128-bit index key A block of 256 word lines will be required. In addition, it should be noted that although the index key/inverted value index key is shown here to be written into the top half/bottom half of the word line, respectively. More generally, the index key and the inverted value pair can be interleaved in any desired manner as long as it is consistent for all index keys in the block; however, this would require a trace configuration. It may be preferable to interleave the pattern along the reverse chain because the data can be inverted in another WL without having to reload the data. The presence may also benefit from some other coupling effects that interleave the inverted and non-inverted values on adjacent word lines. Regarding the performance of this type of embodiment, for a 64-bit index key of a 16 KB page, if a duplicate index key/inverted value index key pair is retained, this is 8 KB or 64,000 index keys. This gives a 1.82 C/s/plane at each sensing of 35 us. If the four planes are operated in parallel, this is 7.3 CG/s at approximately 200 mW.

對於圖4或圖6A之實施例之任一者，方法使用一反及快閃記憶體中可得之固有「及」功能性以在一單個感測操作中比較數千個索引鍵。此方法具有優於傳統基於CPU或半導體之CAM記憶體之數個主要優點。其一，由於比較在「晶粒上」完成，故無需將資料移出記憶體。此節省時間及IO功率兩者。此外，實際比較操作使用比習用記憶體小的功率。由於所有位元線同時被感測，其中僅匹配的反及鏈傳導 電流，故基於反及之CAM高度並行；舉例而言，在具有4×8KB平面之一反及快閃記憶體中，在每個晶粒的一次感測中可檢查(32K×8位元/位元組)/2=128K索引鍵。若一感測可在35us內完成，則如上文參考圖4所述之一偶/奇感測將花費50us。此係50us中之128K索引鍵，使得一整個8GB晶粒(2000個區塊)可在~100ms內被感測。相應能量消耗為200mW之數量級。為了增大效能，多個晶粒可並行操作。 For either of the embodiments of FIG. 4 or FIG. 6A, the method uses an inherent "and" functionality available in flash memory to compare thousands of index keys in a single sensing operation. This approach has several major advantages over traditional CPU or semiconductor based CAM memory. First, since the comparison is done on the "die", there is no need to move the data out of the memory. This saves both time and IO power. In addition, the actual comparison operation uses less power than the conventional memory. Since all bit lines are sensed at the same time, only matching anti-chain conduction Current, so the CAM height is parallel based on the inverse; for example, in one of the 4×8KB planes and the flash memory, it can be checked in one sense of each die (32K×8 bits/ Bytes) / 2 = 128K index key. If a sensing can be done within 35 us, then an even/odd sensing as described above with reference to Figure 4 would cost 50 us. This is a 128K index key in 50us, so that an entire 8GB die (2000 blocks) can be sensed within ~100ms. The corresponding energy consumption is on the order of 200 mW. To increase performance, multiple dies can be operated in parallel.

如先前技術部分中所述，索引鍵可在CAM中儲存為分類，在此情況中可使用二進制搜尋；或未分類，其此情況中使用線性搜尋。一基於反及之CAM之情況亦如此，除由於基於反及之CAM可按區塊級搜尋，故在一分類CAM中，索引鍵僅需被分類至區塊之粒度或並行感測之區塊之數量外。CAM允許二進制搜尋，但歸因於此並行性而在區塊級上。甚至對於線性搜尋，此並行性可使線性搜尋相當於或甚至快於相對較大資料集之二進制搜尋。再次，對於此等配置之任意者，亦可藉由並行運行多個晶粒而改良本文中之效能。 As described in the prior art section, the index keys can be stored as a classification in the CAM, in which case a binary search can be used; or unclassified, in which case a linear search is used. The same is true for the CAM based on the inverse, except that the CAM can be searched by block level based on the inverse CAM, so in a class CAM, the index key only needs to be classified into the granularity of the block or the block of parallel sensing. The number is outside. CAM allows binary searching, but at the block level due to this parallelism. Even for linear searches, this parallelism allows a linear search to be equivalent or even faster than a binary search of a relatively large data set. Again, for any of these configurations, the performance herein can be improved by running multiple dies in parallel.

索引鍵可基於給定數量的最高(或最低)有效位元分類。基於有效位元的一分類通常在所搜尋的索引鍵或內容並非一雜湊值而是一組特定或資料本身時最有用。在此情況中，各區塊中的分類資料將皆針對其等索引鍵共用特定數量之最高有效位元。 The index key can be classified based on a given number of highest (or lowest) valid bits. A classification based on valid bits is usually most useful when the index key or content being searched for is not a hash value but a set of specific or material itself. In this case, the categorical data in each block will share a certain number of most significant bits for its index keys.

內容可定址記憶體以二進制(其中搜尋索引鍵由如上所述的0及1組成)形式及三進制形式(其中搜尋索引鍵亦可包含「隨意」值)兩者存在。如上所討論，當一高讀取值沿著一字線被廣播時，沿著該字線的所有單元將傳導而不管其狀態如何。此性質允許藉由針對索引鍵及其反轉值將相應字線設定為高讀取電壓而實施一「隨意」值；即，當用索引鍵及其反轉值(在圖4之第二次讀取或在字線之下半部中)感測時，隨意值針對索引鍵及其反轉值被設定為高讀取值，而索引鍵之其他值如前反轉值。 The content addressable memory exists in the form of a binary (where the search index key consists of 0 and 1 as described above) and a ternary form (where the search index key may also contain a "random" value). As discussed above, when a high read value is broadcast along a word line, all cells along the word line will conduct regardless of their state. This property allows a "random" value to be implemented by setting the corresponding word line to a high read voltage for the index key and its inverted value; that is, when using the index key and its inverted value (in the second time in Figure 4) When reading or in the lower half of the word line), the random value is set to a high read value for the index key and its inverted value, and the other values of the index key are as before the inverted value.

一基於反及之CAM之此等性質亦使其尤其適於若干其他使用。 舉例而言，由於大量索引鍵可被並行搜尋，故此允許被搜尋區塊中的相同索引鍵的所有複本在該過程中被判定，其改良在清理資料庫方面有價值的類型的重複刪除操作的效率。反及結構亦使一CAM可用作一布隆(Bloom)濾波器，此係因為可藉由在組合搜尋索引鍵中將索引鍵之間不同的任意值設定為高讀取電壓而形成多個搜尋索引鍵的一交集，其隨後可用於並行搜尋一或多個區塊之水平儲存索引鍵。 This property based on the inverse CAM also makes it particularly suitable for several other uses. For example, since a large number of index keys can be searched in parallel, all replicas of the same index key in the searched block are allowed to be determined in the process, which improves the type of deduplication operation that is valuable in cleaning up the database. effectiveness. The inverse structure also enables a CAM to be used as a Bloom filter because it can be formed by setting any value different between the index keys to a high read voltage in the combined search index key. Searching for an intersection of index keys, which can then be used to search for horizontal storage index keys for one or more blocks in parallel.

「隨意」值的使用亦可用於執行一種類型之「迭代」搜尋。此可用作索引鍵可具有或可能具有一些數量之位元錯誤。一或一系列簡化索引鍵(其中值的一些子集針對不同項目被設定為「隨意」)被用於搜尋。數個不同的此等索引鍵(其中值的一不同子集在各者中被遮罩)隨後被迭代用於檢查寫入索引鍵之間的匹配。 The use of "free" values can also be used to perform a type of "iteration" search. This can be used as an index key to have or may have some number of bit errors. One or a series of simplified index keys (where some subsets of values are set to "casual" for different items) are used for the search. A number of different such index keys (where a different subset of values are masked in each) are then iterated to check for matches between the write index keys.

其中可採用一系列簡化搜尋索引鍵之另一實例係內容本身係一資料集而非一雜湊值的情況。舉例而言，其可為來自影像處理之值。在此一情況中，藉由將較低有效位元設定為「隨意」，區塊之內容可被搜尋至所要數量之有效位元。類似配置亦可用於內容型樣匹配或用於索引鍵係主資料內容之性質的情況。 Another example in which a series of simplified search index keys can be used is that the content itself is a data set rather than a hash value. For example, it can be a value from image processing. In this case, by setting the lower significant bit to "arbitrary", the contents of the block can be searched for the desired number of significant bits. Similar configurations can also be used for content pattern matching or for indexing the nature of key data content.

因此，歸因於其並行性、相對較低功率消耗或兩者，基於反及之CAM可用於許多應用中，諸如資料庫搜尋、語音識別、DNA匹配/基因組搜尋、加密及等等。其可便於基於CAM之索引且可併入至舉例而言CAM索引之SSD系統中。 Thus, based on its parallelism, relatively low power consumption, or both, the inverse-based CAM can be used in many applications, such as database search, speech recognition, DNA matching/genome search, encryption, and the like. It can facilitate CAM-based indexing and can be incorporated into an SSD system such as a CAM index.

至此，討論已主要考量二進制反及記憶體用於CAM的情況。更一般而言，亦可使用多狀態(MLC)記憶體；舉例而言，在一混合的二進制MLC記憶體中，索引鍵可儲存在二進制記憶體中作為CAM使用，而索引鍵指向之資料可儲存在MLC區域中。亦可將MLC反及記憶體用於CAM，其使用每個單元2至3位元，舉例而言，用在索引鍵 匹配中。使用每個單元2至3位元，反及鏈可儲存更長索引鍵。在參考圖6A描述之類型之實施例中，其中一索引鍵及其反轉值被寫入至相同字線中，二進制運算中之一128單元反及鏈可儲存64位元索引鍵，而具有每個單元2位元之一128反及鏈可儲存128位元索引鍵。類似地，每個單元3位元運算可儲存192位元索引鍵。 So far, the discussion has mainly considered the case of binary inverse memory and memory for CAM. More generally, multi-state (MLC) memory can also be used; for example, in a mixed binary MLC memory, the index key can be stored in binary memory for use as a CAM, and the information pointed to by the index key can be Stored in the MLC area. MLC can also be used for CAM, which uses 2 to 3 bits per unit, for example, for index keys. Matching. Using 2 to 3 bits per unit, the reverse chain can store longer index keys. In an embodiment of the type described with reference to FIG. 6A, wherein an index key and its inverted value are written into the same word line, one of the 128 operations in the binary operation can store the 64-bit index key, but has One of the 2 bits of each unit 128 and the chain can store 128-bit index keys. Similarly, each unit 3-bit operation can store a 192-bit index key.

圖7展示針對四狀態記憶體單元操作之每個單元2位元之一例示性編碼。如所示，擦除狀態被編碼為11，向上的第一狀態(或「a」狀態)係10，之後係00(針對「b」)及01(或「c」狀態)。亦展示不同感測級。圖8展示資料狀態與用作反轉值索引鍵之互補資料如何對應。 圖9展示一索引鍵({00111001})將如何編碼至位元線BL上之一4單元反及串及其在位元線BLB上之補數上之一實例。在MLC CAM實施例中，系統可使用沿著反及鏈的一條或兩條字線以儲存各反及鏈之同位位元以檢查反及鏈之完整性。如二進制之情況，製造缺陷行可被獨立出來且沿著字線之更多冗餘(重複資料)可進一步保護索引鍵的完整性。此外，互補資料如圖中所示移位以提供更大感測邊際。 Figure 7 shows an exemplary encoding of one of the two bits per cell for a four state memory cell operation. As shown, the erased state is encoded as 11, the upward first state (or "a" state) is 10, followed by 00 (for "b") and 01 (or "c" state). Different sensing levels are also shown. Figure 8 shows how the data state corresponds to the complementary data used as the inverted value index key. Figure 9 shows an example of how an index key ({00111001}) will be encoded onto a 4-cell inverse of the bit line BL and its complement on the bit line BLB. In an MLC CAM embodiment, the system can use one or two word lines along the inverse chain to store the anti-bits of each anti-chain to check the integrity of the anti-chain. In the case of binary, manufacturing defect rows can be isolated and more redundant (duplicate data) along the word line to further protect the integrity of the index key. In addition, the complementary data is shifted as shown in the figure to provide a larger sensing margin.

在上文中，索引鍵沿著陣列之位元線被寫入，其中搜尋索引鍵沿著字線廣播，允許沿著一區塊位元線之索引鍵被並行搜尋。配置亦可被反轉值，其中反及陣列亦可***作，使得內容或索引鍵匹配在字線方向上。在此配置下，一或更多索引鍵將沿著各字線(其可為非常長的索引鍵)被寫入，一種在數個不同環境中有用的一配置。多個短索引鍵亦可沿著字線方向儲存。若索引鍵被編碼為具有如值之一2D陣列之有效性，則此將允許位元線及字線方向兩者上之內容搜尋，但是更典型情況將僅針對字線方向上的內容匹配。舉例而言，由於字線比位元線長得多，故一基於字線之CAM允許使用更長索引鍵。此外，當字線沿著字線按頁被寫入時，其可更方便地(至少在最初)沿著字線寫入輸入索引鍵資料。此隨後將允許索引鍵根據沿著字線寫入被 搜尋。若需要，索引鍵隨後可沿著位元線被重寫，其中其等隨後可如上所述被搜尋。歸因於涉及之資料數量，為了將索引鍵從一字線定向移動至一位元線定向上，一旦一區塊量的索引鍵被組合，其等可從反及記憶體被讀出至控制器且隨後沿著位元線再配置及寫入；另一選擇係，索引鍵之此旋轉可在反及裝置上執行，但是此通常將需要修改記憶體晶片結構以完成此。最初沿著字線寫入索引鍵，將索引鍵轉移至控制器，及將其等再配置以重寫至位元線上之此過程亦可包含在將其等重寫回一位元線定向之前之如上所述之類型的分類過程。 In the above, the index keys are written along the bit lines of the array, with the search index keys being broadcast along the word lines, allowing index keys along a block bit line to be searched in parallel. The configuration can also be inverted, where the array can also be manipulated such that the content or index key matches in the wordline direction. In this configuration, one or more index keys will be written along each word line (which can be a very long index key), a configuration that is useful in several different environments. Multiple short index keys can also be stored along the word line direction. If the index key is encoded as having a 2D array of values, this would allow for content search on both the bit line and word line directions, but more typically would only match for content in the word line direction. For example, a word line based CAM allows for longer index keys because the word lines are much longer than the bit lines. In addition, when a word line is written in a page along a word line, it is more convenient (at least initially) to write the input index key material along the word line. This will then allow the index key to be written according to the word line along the search. If desired, the index key can then be overwritten along the bit line, where it can then be searched as described above. Due to the amount of data involved, in order to move the index key from a word line orientation to a bit line orientation, once the index key of a block quantity is combined, it can be read from the inverse memory to the control. The device is then reconfigured and written along the bit line; another option is that the rotation of the index key can be performed on the opposite device, but this would typically require modifying the memory die structure to accomplish this. The process of initially writing an index key along a word line, transferring the index key to the controller, and reconfiguring it to rewrite onto the bit line may also be included before rewriting it back to a bit line orientation. A classification process of the type described above.

參考圖10繪示在字線方向上匹配內容之過程。當系統接收索引鍵時，此等可形成為一或更多索引鍵之頁並沿著字線被寫入至記憶體陣列901中。為了匹配內容，系統將一或多個搜尋索引鍵之匹配內容輸入至一匹配緩衝器或暫存器905中，其隨後可用於沿著字線查找重複內容。將沿著一字線之資料從記憶體陣列901讀取至一緩衝器或暫存器903中。記憶體隨後可執行緩衝器903中的讀取資料與緩衝器905中的搜尋資料之間的內部匹配操作，其中若需要，忽略一定數量的位元。忽略的位元或可成為「隨意」值，此係因為讀取時可能發生一些讀取錯誤。當找到一匹配時，可用控制器中之錯誤校正校正此等忽略位元。通常，可比較之沿著字線之最小長度之索引鍵/內容為1KB，而在一平面中可比較之最長長度之索引鍵/內容係16KB。若索引鍵長度小於1KB，則索引鍵可以厚塊型樣重複從而以更大並行性進行型樣匹配。隨後，匹配情況將產生一組「1」且未匹配情況將產生50%「1」。電路可偵測一字是否均為「1」以判斷匹配或遺漏。若在一字中存在一些「0」，則此字可作為一漏失摒棄。為了防止一些讀取錯誤在其應為一匹配時產生一漏失，大多數投票電路可用於選擇具有多數「1」之字進行匹配。可藉由將隔離鎖存器標記為「忽略」而遮罩一些字。為了簡化操作，通常較佳寫入檔案之開端以與特定行對準。在 完成一條字線上之一比較後，可以一類似序列比較下一字線內容。 Referring to Figure 10, the process of matching content in the direction of the word line is illustrated. When the system receives the index key, these may be formed into pages of one or more index keys and written into the memory array 901 along the word lines. To match the content, the system inputs the matching content of one or more search index keys into a match buffer or register 905, which can then be used to find duplicate content along the word line. The data along a word line is read from the memory array 901 into a buffer or buffer 903. The memory can then perform an internal matching operation between the read data in buffer 903 and the search data in buffer 905, with a certain number of bits being ignored if desired. Ignored bits can be "free" values because some read errors can occur when reading. When a match is found, these ignore bits can be corrected with error corrections in the controller. In general, the index key/content that can be compared along the minimum length of the word line is 1 KB, and the index key/content of the longest length that can be compared in one plane is 16 KB. If the index key length is less than 1 KB, the index key can be repeated in a thick block pattern to perform pattern matching with greater parallelism. Subsequently, the match will result in a set of "1"s and the unmatched case will result in a 50% "1". The circuit can detect if a word is "1" to determine a match or omission. If there is some "0" in a word, the word can be discarded as a miss. In order to prevent some read errors from generating a miss when it should be a match, most voting circuits can be used to select a word with a majority of "1" for matching. Some words can be masked by marking the isolation latch as "ignore". In order to simplify the operation, it is generally preferred to write the beginning of the file to align with a particular line. in After completing one of the word lines, the next word line content can be compared in a similar sequence.

使用基於反及快閃之CAM之索引鍵-值定址儲存磁碟機Use the index-value-based address storage drive based on the inverse flash and CAM

此部分考量將上述類型之反及快閃內容可定址記憶體(CAM)或內容可定址儲存器(CAS)併入一儲存磁碟機中。習用儲存磁碟機(諸如固態磁碟機或硬碟機(SSD或HDD))藉由一邏輯區塊位址(LBA)定址以讀取及寫入儲存在其等實體媒體上之資料。此等採用邏輯至實體位址轉譯表以定位資料，其中位址轉譯表儲存在快閃上、DRAM中或磁性媒體上且依據磁區、位元組或頁更新。此等位址之典型大小係32、48或64位元。在一些應用中，諸如在資料庫中，需具有大型索引鍵(數百或數千位元)，其可定位比資料庫中之元素數大得多之一空間。在此等情況中，利用索引鍵-值對之一內容可定址記憶體用於索引儲存在裝置中之元素。 This section considers incorporating the above-described type of anti-flash content addressable memory (CAM) or content addressable storage (CAS) into a storage drive. A conventional storage disk drive (such as a solid state disk drive or hard disk drive (SSD or HDD)) is addressed by a logical block address (LBA) to read and write data stored on its physical media. These use logical to physical address translation tables to locate data, where the address translation table is stored on flash, in DRAM, or on magnetic media and updated based on magnetic regions, bytes, or pages. The typical size of such addresses is 32, 48 or 64 bits. In some applications, such as in a repository, there is a need for large index keys (hundreds or thousands of bits) that can locate a space that is much larger than the number of elements in the repository. In such cases, one of the index key-value pairs can be used to address the memory used to index the elements stored in the device.

在一內容可定址記憶體中，資料作為一索引鍵-資料對被寫入。 為了擷取資料，供應一搜尋索引鍵；搜尋記憶體中之所有索引鍵進行一匹配。若找到一匹配，則擷取相應資料。此部分提供一種儲存磁碟機，其將如先前部分中描述之一基於快閃之反及陣列用作使用索引鍵-值對而非一邏輯區塊位址定址之一內容可定址記憶體。此磁碟機可提供二進制及三進制搜尋能力，意味著索引鍵中之位元型樣可具有1或0值以及「隨意」項目。此類型之基於反及之CAS磁碟機隨後可用於取代CAM或CAS功能性之其他實施方案，諸如採用一資料庫之實施方案，其通常將包含一主機CPU、DRAM及儲存媒體。 In a content addressable memory, the data is written as an index key-data pair. In order to retrieve the data, a search index key is supplied; all index keys in the search memory are searched for a match. If a match is found, the corresponding data is retrieved. This section provides a storage disk drive that will address the memory based on one of the content described in the previous section based on the flash and the array being used to address one of the logical key block addresses instead of a logical block address. This disk drive provides binary and ternary search capabilities, meaning that the bit pattern in the index key can have a 1 or 0 value and a "random" item. This type of reverse-based CAS disk drive can then be used to replace other implementations of CAM or CAS functionality, such as with a database implementation, which would typically include a host CPU, DRAM, and storage media.

因此，此部分將作為來自前一部分之一型樣匹配引擎之一反及快閃記憶體之操作應用於使用索引鍵-值對而非習用邏輯區塊位置索引之儲存裝置。裝置可使用一標準傳輸協定，諸如PCI-E、SAS、SATA、eMMC、SCSI及等等。在用於一型樣匹配模式中時，反及單元不僅儲存值，而且亦可用於比較其等之儲存值與一輸入值。在本部 分之實例中，目標型樣沿著位元線儲存，但是亦可使用上文討論之基於字線之儲存。在位元線實例中，將匹配之型樣沿著字線廣播。若反及鏈中之所有元素匹配其等之目標型樣，則反及鏈(位元線)將傳導。 傳導位元線之位置可被用作至另一表格之一索引，其可用於擷取與目標索引鍵相關之資料。此展示在圖11中，該圖11詳解圖1。 Therefore, this section will be applied to the storage device using index key-value pairs instead of the conventional logical block position index as an operation from one of the former part matching engines and flash memory. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and the like. When used in a pattern matching mode, the inverse unit not only stores the value, but also can be used to compare the stored value with an input value. In this department In the example, the target pattern is stored along the bit line, but the word line based storage discussed above can also be used. In the bit line instance, the matching pattern is broadcast along the word line. If all elements in the chain match their target type, then the inverse chain (bit line) will be transmitted. The position of the conductive bit line can be used as an index to one of the other tables, which can be used to retrieve information related to the target index key. This is shown in Figure 11, which is detailed in Figure 1.

在圖11中，如前所述，位元線BL0、BL1、…沿著陣列之行延伸且用相應索引鍵索引鍵0、索引鍵1、…寫入。隨後根據搜尋索引鍵(本文中索引鍵2)加偏壓於字線，使得其擴及被字線橫跨之所有位元線。當找到一匹配索引鍵或諸匹配索引鍵時，隨後將位元線之行位址作為一索引輸入以查找資料集，其亦儲存在磁碟機上。許多配置係可行的，其中舉例而言，索引鍵可儲存在經最佳化用於CAM之二進制或MLC陣列中，而資料儲存在更標準的MLC陣列中。 In Fig. 11, as described above, the bit lines BL0, BL1, ... extend along the row of the array and are written with the corresponding index key index key 0, index key 1, .... The word line is then biased according to the search index key (index key 2 herein) such that it extends across all bit lines spanned by the word line. When a matching index key or matching index key is found, the row address of the bit line is then used as an index input to find the data set, which is also stored on the disk drive. Many configurations are possible, where, for example, index keys can be stored in binary or MLC arrays optimized for CAM, while data is stored in more standard MLC arrays.

使用此一機制之一磁碟機隨後可用於搜尋一大的搜尋空間中之索引鍵-值對，執行一般型樣匹配(使用布隆濾波器)或可用於判定集合成員資格。使用此一方案之一磁碟機之一些優點包含低功率使用及高頻寬。由於資料無需從反及陣列移動至一單獨計算模組以進行比較，故IO運算上消耗之功率減小。此外，由於僅匹配一給定搜尋型樣之位元線將傳導，故反及比較運算亦係低功率的。有關頻寬，一單個反及晶粒能夠在50us內進行(比如說)256K 64位元比較，算出為每個比較低於200ps。此外，多個晶粒可並行操作以增大頻寬或增大有效索引鍵長度。潛在地，可基於電流設計在一單個晶粒中在~100ms內搜尋8Gb(約8G索引鍵)之64位元索引鍵。 Using one of these mechanisms, the drive can then be used to search for index key-value pairs in a large search space, perform general pattern matching (using Bloom filters) or can be used to determine set membership. Some of the advantages of using a disk drive in this solution include low power usage and high frequency bandwidth. Since the data does not need to be moved from the inverse array to a separate computing module for comparison, the power consumed by the IO operation is reduced. In addition, since the bit lines that only match a given search pattern will conduct, the inverse operation is also low power. Regarding the bandwidth, a single inverse and the die can be compared within 50us (say) 256K 64 bits, which is calculated to be less than 200ps for each comparison. In addition, multiple dies can be operated in parallel to increase the bandwidth or increase the effective index key length. Potentially, a 64-bit index key of 8 Gb (about 8 G index key) can be searched for ~100 ms in a single die based on the current design.

進一步參考圖12考量使用具有一共同介面(諸如SAS、PCI-E、SATA及等等)之一儲存磁碟機之理念，但其使用索引鍵-值對而非一習用邏輯定址寫入。在寫入方法中，主機將寫入索引鍵-值對(K,V)至磁碟機。磁碟機將在圖12之資料表中之一些位址上將值V儲存在一資料 儲存器中，如(1)所示。磁碟機將在磁碟機之一陣列之一區塊中將索引鍵值K儲存在一位元線「i」上，如圖12之(2)所示。磁碟機將在區塊表中的位址i上輸入一項目，具有指向值V之一指標，如(3)所示。 具有匹配索引鍵之行位址可從反及記憶體中從狀態位元輸出。 Referring further to Figure 12, the concept of storing a disk drive with one of a common interface (such as SAS, PCI-E, SATA, etc.) is used, but it uses an index key-value pair instead of a conventional logical address write. In the write method, the host will write the index key-value pair (K, V) to the disk drive. The disk drive will store the value V in a data at some of the addresses in the data sheet of Figure 12. In the memory, as shown in (1). The disk drive will store the index key K on one bit line "i" in one of the arrays of one of the disk drives, as shown in (2) of FIG. The drive will enter an entry in the address i in the block table with an indicator pointing to the value V, as shown in (3). A row address with a matching index key can be output from the status bit from the inverse memory.

在反及快閃記憶體中，資料被寫入基於字線之頁中。鑑於此，如上討論，索引鍵最初可沿著字線寫入，隨後再配置以沿著位元線寫入，或首先儲存在RAM中且隨後被分類為位元線定向之索引鍵。(主機亦可能已關注針對索引鍵之此基於位元線之定向，但是此操作通常較佳如從磁碟機外所見為透明，其中一主機僅提供基本索引鍵-值對且無需進行此資料操縱)。控制器將關注將索引鍵及值指派至實體位址及判定所需定址結構以將索引鍵轉譯為相應資料位置。索引鍵至值映射表在儲存其等及更新其等方面，可以與常見邏輯至實體映射表大致相同之方式維持，諸如使用查找表或基於一對應公式之映射。舉例而言，可將行位址映射至主儲存快閃管理層中之後設資料。 In the reverse flash memory, data is written into the page based on the word line. In view of this, as discussed above, the index key can initially be written along the word line, then reconfigured to be written along the bit line, or first stored in RAM and then classified as an index key oriented by the bit line. (The host may also have focused on this bit line-based orientation for the index key, but this operation is usually better as seen from outside the disk drive, where a host only provides basic index key-value pairs and does not need to do this. Manipulation). The controller will focus on assigning index keys and values to the physical address and determining the desired addressing structure to translate the index keys into corresponding data locations. The index key-to-value mapping table can be maintained in much the same way as a common logic-to-entity mapping table, such as using a lookup table or a mapping based on a corresponding formula, in terms of storing it, updating it, and the like. For example, the row address can be mapped to the data stored in the main storage flash management layer.

在一變型中，若磁碟機本身具有一索引鍵產生能力，諸如由控制器使用之一雜湊演算法，則僅資料集本身會被發送至磁碟機及磁碟機上產生之相應索引鍵。此將亦允許無索引鍵產生能力之一不同主機發送資料至隨後產生並儲存索引鍵-值之磁碟機。在此類型之配置下，為了使一主機使用一索引鍵存取一值，主機將需使用如磁碟機所使用之相同索引鍵產生演算法(舉例而言，諸如來自一安全雜湊演算法(SHA))。 In a variant, if the drive itself has an index key generation capability, such as a hash algorithm used by the controller, only the data set itself will be sent to the corresponding index key generated on the disk drive and the disk drive. . This will also allow one of the unindexed key generation capabilities to send data to the disk drive that subsequently generates and stores the index key-value. In this type of configuration, in order for a host to access a value using an index key, the host will need to generate an algorithm using the same index key as used by the disk drive (for example, such as from a secure hash algorithm ( SHA)).

現在關注讀取過程，主機將向磁碟機發送一索引鍵(K)，其隨後用於搜尋索引鍵區塊。如先前部分中討論，索引鍵區塊可被分類，在此情況中，可使用二進制搜尋；或其等可能未被分類，在此情況中使用一線性搜尋。對於各索引鍵區塊，磁碟機將施加索引鍵K至字線。若一匹配索引鍵沿著區塊中之一位元線存在，則反及快閃將在與匹配 索引鍵相關之位元位置「j」上暫存一「1」。如圖12中(4)所示，值「j」隨後可用作至相關區塊表之一索引，以擷取至資料表中之相關值V之一指標(3)。若搜尋所有索引鍵區塊而未找到一匹配，則磁碟機可返回一「元素未找到狀態」或出錯。 Now focusing on the reading process, the host will send an index key (K) to the disk drive, which is then used to search the index key block. As discussed in the previous section, the index key blocks can be classified, in which case a binary search can be used; or the like may not be classified, in which case a linear search is used. For each index key block, the drive will apply the index key K to the word line. If a matching index key exists along one of the bit lines in the block, then the inverse flash will match A "1" is temporarily stored in the bit position "j" associated with the index key. As shown in (4) of FIG. 12, the value "j" can then be used as an index to one of the related block tables to retrieve one of the correlation values V in the data table (3). If all index key blocks are searched and a match is not found, the drive can return an "element not found" or an error.

CAM反及可被併入至與相關資料所儲存之相同記憶體系統中，諸如一SSD，在此情況中，對應於搜尋索引鍵之資料可被直接提供至主機。在其他實施例中，CAM反及可為用於提供本文所述之類型之基於CAM之操作之一單獨裝置，而相關資料可被單獨儲存，在此情況中，提供至分開裝置上之相應資料之位址或其他指標。 The CAM can be incorporated into the same memory system as the associated material, such as an SSD, in which case the data corresponding to the search index key can be provided directly to the host. In other embodiments, the CAM can be a separate device for providing one of the types of CAM-based operations described herein, and the related material can be stored separately, in which case the corresponding data is provided to the separate device. Address or other indicator.

因此，儲存磁碟機可受益於使用一反及快閃記憶體中可得之固有「及」功能性以在單個感測操作中比較數千個索引鍵。此類型之一儲存磁碟機具有優於傳統基於CPU或半導體之CAM記憶體之數個主要優點。其一，由於索引鍵比較在「晶粒上」完成，故無需將資料移出記憶體。此節省時間及IO功率兩者。此外，實際比較操作使用比習用記憶體小的功率。 Thus, a storage disk drive can benefit from the use of an inherent "and" functionality available in flash memory to compare thousands of index keys in a single sensing operation. One of the types of storage drives has several major advantages over traditional CPU or semiconductor based CAM memory. First, since the index key comparison is done on the "die", there is no need to move the data out of the memory. This saves both time and IO power. In addition, the actual comparison operation uses less power than the conventional memory.

除上文更詳細討論之低功率及高頻寬優點外，此方案亦具有優點，即若按一線性模式搜尋資料，則寫入時間可較短。多數資料庫花費時間及能量分類及維持表以在讀取資料時實現快速、二進制類型之搜尋能力。在本發明之一實施例中，資料及索引鍵之寫入可以一隨機方式完成，使得寫入為O(1)複雜性之數倍。搜尋將使用一線性搜尋機制，其高度並行化但仍係O(N)複雜性。此不如多數二進制搜尋之O(LogN)高效，且係***時間對查找時間之一取捨。此外，應注意即使當資料以分類方式被儲存時，搜尋之高度並行化意味著分類僅需完成至搜尋完成之程度，即至可並行搜尋之區塊粒度或區塊數。 In addition to the low power and high frequency advantages discussed in more detail above, this approach also has the advantage that if the data is searched in a linear mode, the write time can be shorter. Most databases spend time and energy classification and maintenance tables to enable fast, binary type search capabilities when reading data. In one embodiment of the invention, the writing of data and index keys can be done in a random manner such that the write is a multiple of the O(1) complexity. The search will use a linear search mechanism that is highly parallelized but still O(N) complex. This is not as efficient as O(LogN) for most binary searches, and the insertion time is a trade-off for one of the lookup times. In addition, it should be noted that even when the data is stored in a classified manner, the highly parallelization of the search means that the classification only needs to be completed to the extent that the search is completed, that is, the block size or the number of blocks that can be searched in parallel.

該類型之基於反及快閃之CAS磁碟機可應用於若干應用中，包含先前部分中描述之應用。此等例示性應用之一組實例係針對使用型樣 匹配(CAM)反及進行重複刪除以儲存雜湊索引鍵。輸入資料可透過雜湊函數發送以產生內容相關指紋。隨後可用現有雜湊索引鍵搜尋指紋以看資料是否已存在於資料儲存器中。若其確實已存在，則不採取寫入行動；但若資料並未存在，則新資料將被寫入至儲存器中。重複刪除可在資料備份時，在主儲存器之記憶體回收(garbage collection)操作期間或在資料從主機進入時線內完成。另一應用係用於虛擬記憶體管理，其可類似於重複刪除完成。磁碟機亦可應用於人類基因組，其中磁碟機在CAM反及中儲存簽章，使得DNA序列之任意段可被搜尋。磁碟機亦便於並行計算，其中可在反及記憶體內完成一數學反及函數。 This type of anti-flash-based CAS disk drive can be used in several applications, including the applications described in the previous section. One of the example applications of this exemplary application is for the use pattern The match (CAM) is reversed to store the hash index key. Input data can be sent via a hash function to generate a content-related fingerprint. The fingerprint can then be searched using the existing hash index key to see if the data already exists in the data store. If it does exist, no write action is taken; but if the data does not exist, the new data will be written to the storage. Deduplication can be done during data backup, during the garbage collection operation of the primary storage or when the data is accessed from the host. Another application is for virtual memory management, which can be done similar to deduplication. The disk drive can also be applied to the human genome, where the disk drive stores the signature in the CAM reverse, allowing any segment of the DNA sequence to be searched. The disk drive is also convenient for parallel computing, in which a mathematical inverse function can be implemented in the opposite memory.

如上所述，CAM反及運算具有沿著位元線定向之索引鍵，而反及記憶體沿著字線寫入。因此，當索引鍵從一主機進入時，其等需累積在某一類型之一緩衝記憶體中，轉置至一位元線定向，形成為頁(包含根據需要添加任意反轉值索引鍵)且轉移至反及裝置用於寫入。 此示意繪示在圖13中。 As described above, the CAM inverse operation has an index key oriented along the bit line, and the memory is written along the word line. Therefore, when the index key enters from a host, it needs to be accumulated in one of the buffer memories of a certain type, and is transposed to a bit line orientation to form a page (including adding any inverted value index key as needed) And transferred to the reverse device for writing. This schematic is shown in Figure 13.

如圖13中所示，一主機1301(舉例而言，一PC)可取得資料檔案並產生相應索引鍵(諸如使用一安全雜湊演算法(SHA)以產生一64位元雜湊索引鍵)，其隨後可被轉移至記憶體系統上之一緩衝記憶體1303，其中索引鍵可累積。轉置緩衝記憶體1303用於對準用於寫入反及CAM記憶體1305之索引鍵。一旦索引鍵數量足夠，比如說針對具有4MB區塊之一反及記憶體1305之4MB索引鍵，資料可被轉移用於程式化為沿著字線之頁。圖14及圖15給出用於轉置緩衝記憶體之硬體實施方案之一些實例，但此可以各種其他方式實施，諸如藉由使用一場可程式化閘陣列(FPGA)。舉例而言，區塊量之索引鍵可累積在一FPGA中且隨後每次一條字線地被讀出並被轉移至CAM反及用於寫入。 As shown in FIG. 13, a host 1301 (for example, a PC) can retrieve a profile and generate a corresponding index key (such as using a Secure Hash Algorithm (SHA) to generate a 64-bit hash index key). It can then be transferred to one of the buffer memories 1303 on the memory system where the index keys can be accumulated. The transposition buffer memory 1303 is used to align the index keys for writing the inverse CAM memory 1305. Once the number of index keys is sufficient, for example, for a 4MB index key with one of the 4MB blocks and the memory 1305, the data can be transferred for stylization as a page along the word line. Figures 14 and 15 present some examples of hardware implementations for transposing buffer memory, but this can be implemented in a variety of other ways, such as by using a field programmable gate array (FPGA). For example, the index key for the block amount can be accumulated in an FPGA and then read out one word line at a time and transferred to the CAM for writing.

圖14係FIFO型之轉置記憶體之一硬體實施方案之一示意圖。資料可以(比如說)64位元索引鍵或索引進入並保存在行定向之64位元暫存器中。暫存器被鏈接為一FIFO配置，使得當一新索引鍵進入時，先前索引鍵向右移位一行。一旦針對將被程式化至CAM反及記憶體中之一頁(即，對於一典型設計之8KB至16KB)存在足夠索引鍵(或更早，若將使用較少數量之索引鍵)，頁移位至反及用於程式化為其中之陣列。在此配置下，若需要，可在被程式化之前在仍處於FIFO的同時搜尋索引鍵，此係因為索引鍵可按每次一個移位出來用於比較。 Figure 14 is a schematic diagram of one of the hardware implementations of the FIFO type transposed memory. The data can, for example, be a 64-bit index key or index entered and stored in the row-oriented 64-bit scratchpad. The scratchpad is linked into a FIFO configuration such that when a new index key is entered, the previous index key is shifted one line to the right. Once there is enough index key for a page that will be programmed into CAM and memory (ie, 8KB to 16KB for a typical design) (or earlier, if a smaller number of index keys will be used), page shift The bit is reversed and used to program the array into it. In this configuration, if necessary, the index key can be searched while still in the FIFO before being programmed, because the index key can be shifted out one at a time for comparison.

圖15係用於使用超過一RAM型配置轉置資料索引鍵之另一硬體實施方案之一示意圖。資料可以舉例而言，64位元索引鍵或索引之形式進入並保存在64位元暫存器中，其累積在鎖存器中之一相對較小的16×64陣列1509中。16×64位元之小陣列1509隨後可在一匯流排1507上每次一個字(16位元)地移位至RAM 1503中。在將64個字移位至RAM中後，小陣列1509可累積下一16×64位元。此過程可繼續直至RAM 1503係滿的或另外需要寫入索引鍵，此時被程式化在CAM反及記憶體中。在圖15之配置下，若需在索引鍵被寫入至CAM反及中之前搜尋索引鍵，則在無轉置的情況下儲存之索引鍵之另一RAM緩衝器可保留用於此搜尋目的。 Figure 15 is a schematic illustration of another hardware embodiment for using a transposed data index key in more than one RAM type configuration. For example, the 64-bit index key or index form enters and is stored in a 64-bit scratchpad that is accumulated in a relatively small 16x64 array 1509 in the latch. The small array 1509 of 16 x 64 bits can then be shifted into RAM 1503 one word at a time (16 bits) on a bus 1507. After shifting 64 words into RAM, the small array 1509 can accumulate the next 16 x 64 bits. This process can continue until the RAM 1503 is full or otherwise requires an index key to be written, which is then stylized in the CAM and memory. In the configuration of Figure 15, if the index key needs to be searched before the index key is written to the CAM reverse, another RAM buffer of the index key stored without the transposition can be reserved for this search purpose. .

應用於資料分析Applied to data analysis

先前部分中描述之將一反及結構之一記憶體裝置用作一內容可定址記憶體之類型之高度並行操作亦可應用於執行資料分析。此允許大規模並行計算應用於不同分析應用，其中計算在儲存器內部執行且遠端於伺服器執行。此配置亦可允許處理即時完成，使用並行處理且亦允許分析在無輸入/輸出傳輸限制的情況下執行。因此，此等技術及結構可應用於許多應用，從處理資料倉儲應用中之大量資料、金融資料之數量分析及其他資料分析密集型使用。 The highly parallel operation of the type described in the previous section, which uses a memory device as a content addressable memory, can also be applied to perform data analysis. This allows massively parallel computing to be applied to different analysis applications where the computation is performed inside the memory and remotely at the server. This configuration also allows processing to be done on-the-fly, using parallel processing and also allowing analysis to be performed without input/output transfer restrictions. Therefore, these technologies and structures can be applied to many applications, from processing large amounts of data in data warehousing applications, quantitative analysis of financial data, and other data analysis intensive use.

可使用若干拓撲，一實例展示在圖16中。在本實例中，一記憶體系統1601係一計算固態磁碟機(SSD)，其包含一主儲存器SSD區段1603，所使用之反及裝置可為正常反及裝置以及CAM型反及。在例示性實施例中，當需要一特定具體實例時，反及部分1605再次被視作基於EEPROM之快閃記憶體。一主機1611(諸如一PC或甚至一網路連接)，將資料及對資料執行分析之任意指令提供至記憶體系統1601。 可將資料供應至反及區段1605以儲存用於分析且隨後供應至主儲存器區段1603，允許線內分析(若需要)或直接儲存在主儲存區段1603中及在請求分析時被擷取至反及模組1605。在一些情況中，諸如當資料係索引鍵/相關資料對時，索引鍵可儲存在反及1605及進入主儲存器區段1603之相關資料上，其中系統可維持如先前部分中描述之一索引鍵-資料對應關係。在回應於來自主機之一請求，將資料從主儲存器區段1603轉移至反及區段1605以執行分析之情況中，可根據需要在將資料寫入至反及結構1605中之前將CPU或GPU或SSD控制器用於執行一些初步操縱(選擇資料子集、產生雜湊值及等等)。 Several topologies may be used, an example being shown in FIG. In this example, a memory system 1601 is a computing solid state disk drive (SSD) that includes a primary storage SSD segment 1603, and the inverse device used can be a normal reverse device and a CAM type. In an exemplary embodiment, when a particular embodiment is desired, the inverse portion 1605 is again considered to be an EEPROM-based flash memory. A host 1611 (such as a PC or even a network connection) provides data and any instructions for performing analysis of the data to the memory system 1601. The data may be supplied to the reverse section 1605 for storage for analysis and then supplied to the primary storage section 1603, allowing inline analysis (if needed) or stored directly in the primary storage section 1603 and when requested for analysis. Capture to the inverse module 1605. In some cases, such as when the data is an index key/related data pair, the index key can be stored on the opposite data 1605 and into the primary storage section 1603, wherein the system can maintain an index as described in the previous section. Key-data correspondence. In response to a request from one of the hosts to transfer data from the primary storage section 1603 to the reverse section 1605 to perform the analysis, the CPU or the CPU or the data may be written to the inverse structure 1605 as needed. A GPU or SSD controller is used to perform some preliminary manipulations (selecting a subset of data, generating hash values, and the like).

圖16之配置將在下文中被用作例示性實施例，但是可使用若干變型或其他拓撲。舉例而言，主資料儲存器區段1603不一定為一SSD，而可為硬碟機或其他資料儲存器。此外，反及部分1605不一定被併入至與主儲存器1603相同之系統中，而是作為針對結合一大量資料儲存系統使用之此部分之一單獨系統。在其他情況中，在資料數量可由基於CAM之反及系統本身管理的情況下，反及系統可直接結合主機用於執行資料分析。舉例而言，併入CAM反及及一些額外快閃儲存器之一可攜式裝置可能係足夠的。 The configuration of Figure 16 will be used hereinafter as an illustrative embodiment, although several variations or other topologies may be used. For example, the primary data storage section 1603 is not necessarily an SSD, but may be a hard disk drive or other data storage. Moreover, the inverse portion 1605 is not necessarily incorporated into the same system as the primary storage 1603, but rather as a separate system for use in conjunction with a portion of a mass data storage system. In other cases, in the case where the amount of data can be managed by the CAM-based and the system itself, the system can be directly combined with the host for performing data analysis. For example, a portable device incorporating one of the CAM and some additional flash memory may be sufficient.

圖17至圖20繪示當資料包含分類(即，可適於多個類型，諸如(紅、藍、綠)或(是、否)之資料)資料以及數值範圍偵測兩者時，反及陣列可如何用於針對陣列之所有行並行執行分析。歸因於本文描述之 記憶體之CAM本質，可處理多個類型。在本實例中，分類資料及數值資料可沿著相同反及串儲存，但分類資料保存為二進制格式，而數值資料可被保存為二進制(D1)、每個單元2位元(D2)、每個單元3位元(D3)或其他多狀態格式。亦應注意，分類/數值區別不一定係嚴格的，此係因為本文描述之技術允許處理數值資料以使其成為分類資料用於分析，在一些情況中，此可能比執行數值比較快。每個單元之位元越大，將用於儲存資料之字線數越少，但此等多狀態操作中涉及之複雜性增大。分析將產生特定查詢之一匹配且匹配結果可在反及內或反及外計數。如下文參考圖30及圖31進一步討論，計數可在反及內數位完成，其係精確的；或以一類比形式完成，其更快但較不準確。當在反及外計數時，匹配結果將被轉移至控制器且「1」或「0」數將在此計數。 17 to 20 illustrate that when the data includes classification (ie, data that can be applied to multiple types such as (red, blue, green) or (yes, no)) and numerical range detection, How an array can be used to perform analysis in parallel for all rows of an array. Due to the description of this article The CAM nature of memory can handle multiple types. In this example, the classified data and the numerical data can be stored along the same reverse and string, but the classified data is saved in binary format, and the numerical data can be saved as binary (D1), 2 bits per unit (D2), each Units are 3 bits (D3) or other multi-state format. It should also be noted that the classification/value distinctions are not necessarily strict, as the techniques described herein allow for the processing of numerical data to be used as classification data for analysis, which in some cases may be faster than the execution of values. The larger the bit per cell, the less the number of word lines that will be used to store the data, but the complexity involved in such multi-state operations increases. The analysis will produce a match for one of the specific queries and the match results can be counted in or out of the opposite. As discussed further below with respect to Figures 30 and 31, the counting can be done in the inverse and internal digits, which is accurate; or done in an analogous form, which is faster but less accurate. When counting back and out, the match result will be transferred to the controller and the number of "1" or "0" will be counted here.

圖17左側展示一區塊之兩個資料集如何沿著位元線BLn及BLm被寫入反及串上。各串之上部分上被輸入二進制形式之分類資料，更下方被輸入一些數值資料，其中展示一每個單元3位元格式，位元從上至下配置為最低有效位元至最高有效位元。本文中，可首先搜尋所展示之分類資料字線，隨後針對匹配「類型」對數值資料執行分析。分類資料可為「隨意」或不在相同記憶體區塊上寫入數值資料。隨後可藉由每次讀取一條字線，將適當讀取位準(CGRV)置於MSB字線上而依序分析數值資料，本文中從最高有效位元開始。右側係可如何按一查詢序列比較數值資料之一示意圖。位元線之各者具有可用於追蹤分析操作之序列之結果之一組關聯鎖存器，其中結果如何被指派至鎖存器之一實例展示在圖18中。(資料鎖存器在本文中標註為XDL、UDL且在更下方標註為LDL分別作為轉移資料鎖存器、上資料鎖存器及下資料鎖存器以對應於諸如美國專利第7,206,230號及第8,102,705號中描述之配置，其中可見此等鎖存器結構之更多細節且亦見下文圖28及 圖29)。 The left side of Figure 17 shows how two data sets of a block are written onto the inverse of the string along bit lines BLn and BLm. The upper part of each string is input into the binary type of classification data, and the lower part is input with some numerical data, which shows a 3-bit format per unit, and the bit is configured from the top to the bottom to the most significant bit to the most significant bit. . In this article, you can first search for the classified data word lines displayed, and then perform an analysis on the matching "type" logarithmic data. The categorical data can be "arbitrary" or not written on the same memory block. The data can then be analyzed sequentially by placing a suitable read level (CGRV) on the MSB word line each time a word line is read, starting with the most significant bit in this paper. The right side can compare one of the numerical data in a query sequence. Each of the bit lines has a set of associated latches that can be used to track the results of the sequence of analysis operations, and an example of how the results are assigned to the latches is shown in FIG. (The data latches are labeled XDL, UDL, and labeled LDL as the transfer data latch, the upper data latch, and the lower data latch, respectively, to correspond to, for example, U.S. Patent No. 7,206,230, and Configurations described in 8,102,705, in which more details of such latch structures can be seen and also see Figure 28 below. Figure 29).

圖19之表格展示針對四個資料值看一數字是否大於010011001之一比較之一實例。本文中搜尋從最高有效位元向下朝最低有效位元完成。當搜尋到最高有效位元(MSB9)時，發現最高值大於搜尋數，相應地設定鎖存器，忽略後續讀取且不進行更新。對於其他三個值，結果係不確定的。當檢查到下一位元MSB8時，第二資料仍係不確定的，但發現較低兩個值小於搜尋值，因此相應地設定鎖存器且之後不再需要更新。繼續第二資料值，MSB7結果將再次不確定且不展示，但MSB值確定其大於搜尋值且相應地設定鎖存器。此時，此資料集之最終搜尋值被確定，如最右側行中所示。若存在仍不確定的資料，則過程將朝最低有效位元繼續直至最終搜尋結果皆確定。最終結果將展示在資料鎖存器之一者上，在本實例中諸如XDL=1。適於查詢之匹配可隨後被計數或被保存至另一字線用於結合其他查詢準則進一步分析。 The table of Figure 19 shows an example of comparing one of the four data values to see if a number is greater than 010011001. The search in this article is done from the most significant bit down to the least significant bit. When the most significant bit (MSB9) is found, the highest value is found to be greater than the number of searches, the latch is set accordingly, subsequent reads are ignored and no updates are made. For the other three values, the results are uncertain. When the next meta-MSB8 is checked, the second data is still indeterminate, but the lower two values are found to be less than the search value, so the latches are set accordingly and no longer need to be updated. Continuing with the second data value, the MSB7 result will again be undefined and not displayed, but the MSB value determines that it is greater than the search value and sets the latch accordingly. At this point, the final search value for this dataset is determined, as shown in the far right row. If there is still uncertainty, the process will continue towards the least significant bit until the final search results are determined. The final result will be shown on one of the data latches, such as XDL=1 in this example. Matches suitable for querying can then be counted or saved to another word line for further analysis in conjunction with other query criteria.

圖20係看哪些資料值介於123與231之間之另一搜尋之一實例。 對於第一讀取，對照上限檢查資料值之第一位(對於第一數字，發現已超過該上限)，將其置於範圍外，使得可忽略任意後續讀取。發現第二數字與MSB上限相等，其中底部資料在MSB上限之下。在第二讀取時，第二數字之第二位被發現超過上限，因此鎖存器被設定且無需進一步更新。對於第四資料，第二讀取發現此低於MSB下限值，且因此在範圍外，使得鎖存器再次被設定且無需進一步更新。第三列資料之第二讀取發現其等於下限之MSB，使得對照第三讀取中之搜尋之上限值之第二位及第四讀取中之搜尋之下限值之第二位檢查下一位。最終搜尋結果隨後展示在最右行中。 Figure 20 is an example of another search for which data values are between 123 and 231. For the first read, the first bit of the data value is checked against the upper limit (for the first number, the upper limit has been found to have been exceeded), and is placed out of range so that any subsequent reads can be ignored. The second number is found to be equal to the MSB upper limit, with the bottom data below the MSB upper limit. At the second read, the second bit of the second number is found to exceed the upper limit, so the latch is set and no further updates are required. For the fourth data, the second read finds this below the MSB lower limit, and is therefore out of range, causing the latch to be set again and no further updates are required. The second reading of the third column of data finds that it is equal to the MSB of the lower limit, so that the second bit of the upper limit of the search in the third reading and the second bit of the lower limit of the search in the fourth reading are checked. Next person. The final search results are then displayed in the far right row.

圖21及圖22繪示如何執行最大值及最小值搜尋。在針對最大值搜尋之圖21中，針對5個反及串繪示之過程，各從上到下配置LSB至 MSB之9個位元。在左側，MSB列被搜尋且被載入至UDL鎖存器中。 在此實例中，最左側兩個反及串針對最高有效位元具有一「1」。對於其餘搜尋，其他行可被忽略。過程繼續沿著列向上，其中下兩個最大MSB係不確定的。從第四列向上，左側兩行不同，其中如載入至LDL中之結果表明第二行具有最大值。(本文中，為闡釋目的展示兩個鎖存器，但可藉由在每次一個地讀取行時重寫而按每條位元線單個鎖存器完成此過程)。圖22類似繪示一最小值搜尋，再次從MSB向上開始。左側展示向上至第五最高有效位元後的情況，其中最外行皆具有零值直至所述點，如UDL中反映。圖22的右側展示隨後載入至LDL中之兩個讀取之結果，其將最左行展示為最小值。 21 and 22 illustrate how to perform maximum and minimum search. In Figure 21 for the maximum search, the LSB is configured from top to bottom for the process of five reverse and string descriptions. 9 bits of MSB. On the left side, the MSB column is searched and loaded into the UDL latch. In this example, the leftmost two reverse strings have a "1" for the most significant bit. For the rest of the search, other lines can be ignored. The process continues along the column up, where the next two largest MSBs are uncertain. Up from the fourth column, the two rows on the left are different, and the result as loaded into the LDL indicates that the second row has the maximum value. (In this article, two latches are shown for illustrative purposes, but this can be done by a single latch per bit line by rewriting each time the row is read one at a time). Figure 22 similarly depicts a minimum search, starting again from the MSB. The left side shows the situation up to the fifth most significant bit, where the outermost row has a value of zero until the point, as reflected in the UDL. The right side of Figure 22 shows the results of two reads that are subsequently loaded into the LDL, which shows the leftmost row as the minimum.

可對檔案大小執行最大值及最小值搜尋。對於一最大值，記憶體可查找沿著反及鏈具有最大位數之檔案大小，隨後藉由消除小數而查找下一最大檔案。對於一最小值，記憶體可查找沿著反及鏈具有最小位數之檔案大小，且隨後藉由消除較大數而搜尋下一最小檔案。一檔案系統之部分可以此方式儲存。 Maximum and minimum search can be performed on the file size. For a maximum value, the memory can look up the file size with the largest number of digits along the reverse chain, and then find the next largest file by eliminating the decimal. For a minimum value, the memory can look up the file size with the smallest number of bits along the reverse chain, and then search for the next smallest file by eliminating the larger number. Portions of a file system can be stored in this manner.

陣列結構允許每次一列地完成資料分析，此係因為其等可藉由每次讀取一條字線而完成。舉例而言，陣列結構亦可用於對沿著反及串之數字資料執行算術運算，諸如加法、減法及乘法。針對加法運算在圖23中示意繪示該過程。本文中，可針對各位元線將區塊N 2301之資料集逐行與區塊M 2301之相應資料集相加。結果隨後可被寫入至一SUM區塊2305中。本文中，區塊N具有反及串N1至N128K，區塊M具有反及串M1至M128K且SUM區塊類似地具有反及串SUM1至SUM128K。所選數值資料值可藉由每次一字線地從區塊M 2301及N 2303之反及串i讀取各字線之值至相關鎖存器2307而相加，在其中相加之後，從鎖存器中寫回至SUM區塊，SUMi=Ni+Mi。若反及具有更多資料鎖存器，則在寫入至SUM區塊之前可累積更多位元。在3個資 料鎖存器之情況中，存在在寫入至SUM區塊之前可相加之4個數字。 在5個資料鎖存器之情況中，在寫入至SUM區塊之前16個數字可相加。 The array structure allows data analysis to be completed one column at a time because it can be done by reading one word line at a time. For example, the array structure can also be used to perform arithmetic operations on digital data along the inverse string, such as addition, subtraction, and multiplication. This process is schematically illustrated in Figure 23 for the addition operation. In this paper, the data set of the block N 2301 can be added row by row to the corresponding data set of the block M 2301 for each element line. The result can then be written to a SUM block 2305. Herein, the block N has the inverse of the strings N1 to N128K, the block M has the inverse of the strings M1 to M128K, and the SUM block similarly has the inverse strings SUM1 to SUM128K. The selected value data can be added by reading the value of each word line from the inverse of the blocks M 2301 and N 2303 and the string i to the associated latch 2307 one word line at a time, after adding them, Write back from the latch to the SUM block, SUMi=Ni+Mi. If there are more data latches, then more bits can be accumulated before being written to the SUM block. In 3 capitals In the case of a material latch, there are 4 numbers that can be added before being written to the SUM block. In the case of five data latches, the 16 numbers can be added before being written to the SUM block.

在圖23之實例中，且亦在下文討論之實例中，反及陣列被組織為具有一區塊結構，諸如快閃記憶體所有的區塊結構。更一般而言，字線可為陣列之字線之任意者；且當記憶體具有一區塊結構時，此等不一定來自不同區塊，如舉例而言，在將來自相同資料集之數值資料之兩條不同字線相加時。此外，在將結果寫入一新字線之前，超過兩個資料可被處理並保存至資料鎖存器。舉例而言，在具有3個資料鎖存器的情況下，在寫入一字線之前，記憶體可將4頁相加，將進位保存在資料鎖存器中用於下次位元相加。對於5個資料鎖存器，其可將16頁相加且隨後馬上寫入不同字線，及等等。 In the example of Figure 23, and also in the examples discussed below, the inverse array is organized to have a block structure, such as a block structure of all flash memory. More generally, the word line can be any of the word lines of the array; and when the memory has a block structure, the pieces do not necessarily come from different blocks, as for example, values from the same data set When the two different word lines of the data are added. In addition, more than two data can be processed and saved to the data latch before the result is written to a new word line. For example, in the case of three data latches, the memory can add 4 pages before writing a word line, and store the carry in the data latch for the next bit addition. . For five data latches, it is possible to add 16 pages and then immediately write to different word lines, and so on.

圖24繪示鎖存器可如何在此過程中用於相加之一實例。與各位元線相關之鎖存器在本文中被標註為UDL、LDL及XDL。圖24繪示具有讀取自保持不同值之不同字線之值之此等鎖存器之各者之單一者，此係因為此等針對從LSB至MSB之一13位數依序被讀取。(即，箭頭以時間表示讀取序列或等效地針對與一單條字線相關之鎖存器之一單個UDL、LDL、XDL集合沿著字線向下。UDL含有時間A處從一第一區塊(諸如圖23之區塊N)收集之資料集且LDL含有在時間B處從一第二區塊(諸如區塊M)收集之資料集。XDL鎖存器可保持任意進位位元。兩個資料集可被相加且儲存回LDL中，和隨後被程式化回至另一區塊中。其他運算(乘法、減法、除法等)可類似地執行：舉例而言，可在將一資料與另一資料之補數相加時完成加法。此外，可藉由適當地對準數位資訊使得點針對運算元對準而類似地執行浮點運算。 Figure 24 illustrates how the latch can be used to add one instance in this process. The latches associated with each of the meta-lines are labeled UDL, LDL, and XDL in this document. Figure 24 illustrates a single of each of these latches having values read from different word lines holding different values, since these are sequentially read for 13 bits from one of the LSB to the MSB. . (ie, the arrow represents the read sequence in time or equivalently for a single UDL, LDL, XDL set of latches associated with a single word line down the word line. UDL contains time A from a first The data set collected by the block (such as block N of Figure 23) and the LDL contain a data set collected from a second block, such as block M, at time B. The XDL latch can hold any carry bit. Two data sets can be added and stored back into the LDL, and then programmed back into another block. Other operations (multiplication, subtraction, division, etc.) can be performed similarly: for example, one would Addition is done when the data is added to the complement of another data. In addition, floating point operations can be similarly performed by aligning the bits with respect to the operands by appropriately aligning the digit information.

圖25A至圖25C給出有關一些算術運算在其等在鎖存器中執行時之機制之更多細節。圖25A關注加法，具體地10+3，如頂部所述。此 處「10」或二進制之1010係讀取自區塊A且「3」(0011二進制)係讀取自一區塊B。此等數字針對左行中之區塊A及B展示列出，從上到下寫入MSB至LSB。在時間T0、T1、T2及T3處，此等被讀取至鎖存器UDL及LDL中，進位保持在XDL鎖存器中，如下方所示。結果從其中鎖存之值被寫回至區塊C中。 Figures 25A through 25C show more details regarding the mechanism of some arithmetic operations as they are executed in the latches. Figure 25A focuses on addition, specifically 10+3, as described at the top. this The "10" or binary 1010 is read from block A and "3" (0011 binary) is read from a block B. These numbers are listed for blocks A and B in the left row, and MSB to LSB are written from top to bottom. At times T0, T1, T2, and T3, these are read into latches UDL and LDL, and the carry is held in the XDL latch, as shown below. The value from which the result is latched is written back to block C.

圖25B繪示如何執行兩個數字N1及N2之減法以形成差N1-N2。此可藉由將N1與2的補數N2+1而完成。展示此處再次使用10及3以在鎖存器結構中確定10-3之一特定實例：在頂列中係二進制形式之10，在第二列中係2的補數3+1(3c+1)且結果展示在底部。任意溢位位元需被摒棄，結果為二進制形式的7。圖25C展示可如何使用位元位移及加法完成乘法，其中10及3再次被用作輸入。 Figure 25B illustrates how the subtraction of two numbers N1 and N2 is performed to form the difference N1-N2. This can be done by adding N1 and 2's complement N2+1. It is shown here that 10 and 3 are used again to determine a specific instance of 10-3 in the latch structure: 10 in binary form in the top column and 3+1 in 3 in the second column (3c+ 1) and the results are shown at the bottom. Any overflow bit needs to be discarded and the result is 7 in binary form. Figure 25C shows how multiplication can be done using bit shifting and addition, where 10 and 3 are again used as inputs.

圖26A及圖26B關注除XDL鎖存器外亦存在超過UDL及LDL之各位元線上可得之額外鎖存器，諸如一多狀態記憶體裝置中所見。圖26A關注3個資料鎖存器之情況。如所示，來自四個區塊(或更一般而言，四頁)之資料被寫入。此允許四個數字在一單次寫入中被相加或相減。圖26B展示一5鎖存器情況，其允許在一次寫入中將多達16個數字相加或相減。 26A and 26B focus on additional latches available on the individual lines of UDL and LDL in addition to the XDL latch, as seen in a multi-state memory device. Figure 26A focuses on the case of three data latches. As shown, data from four blocks (or more generally, four pages) is written. This allows four numbers to be added or subtracted in a single write. Figure 26B shows a 5-latch case that allows up to 16 numbers to be added or subtracted in a single write.

參考圖27及圖28繪示應用於金融資料分析之一些實例。圖27繪示載入股票資料用於一單個股票歷史資料分析之一實例，其中對於128k(在本實例中)，位元線可各被指派至給定股票或其他金融工具，每天之日期被寫入至一不同區塊。各股票之資料可沿著反及串排列。 在各股票佔用一條位元線的情況下，對於128K位元線之一陣列，可同時評估總共128,000隻股票。每日價格隨後可佔用反及鏈之不同區塊或不同位置。針對不同天使用區塊，運算(諸如平均值、線性迴歸及等等)可使用來自相應區塊之資料執行，其中經分析資料可被保存在一新的區塊中。 Some examples of application to financial data analysis are illustrated with reference to FIGS. 27 and 28. Figure 27 illustrates an example of loading stock data for analysis of a single stock historical data, where for a 128k (in this example), the bit lines can each be assigned to a given stock or other financial instrument, and the daily date is Write to a different block. The information of each stock can be arranged along the reverse. In the case where each stock occupies one bit line, for an array of 128K bit lines, a total of 128,000 stocks can be evaluated simultaneously. The daily price can then occupy different blocks or different locations in the opposite chain. For different days of use of blocks, operations (such as averages, linear regression, and the like) can be performed using data from corresponding blocks, where the analyzed data can be saved in a new block.

為了執行其他類型之分析，資料可不同地配置在陣列上。一實例展示在圖28中，其中資料集經配置以執行相關研究。在一第一區塊中，輸入一給定天之多達128K股票之資料。在第二區塊中，來自從相同晶片或不同晶片預處理之不同股票B之資料將與相同位元線上針對股票A之經預處理資料對準。隨後，可相應地計算股票A與股票B之間之相關性。取決於所要運算之複雜性及賦予反及裝置之晶片上能力，此等運算可在晶片上執行或在控制器的幫助下執行。舉例而言，若對於特定應用需要，反及可包含相當複雜但具體的運算。 In order to perform other types of analysis, the data can be configured differently on the array. An example is shown in Figure 28, where the data set is configured to perform related research. In a first block, enter the data for up to 128K stocks for a given day. In the second block, data from different stocks B pre-processed from the same wafer or different wafers will be aligned with the pre-processed data for stock A on the same bit line. Subsequently, the correlation between stock A and stock B can be calculated accordingly. Depending on the complexity of the operation to be performed and the on-wafer capability imparted to the device, such operations can be performed on the wafer or with the help of a controller. For example, if it is needed for a particular application, it can include quite complex but specific operations.

圖29至圖31更詳細地考量用於分析之資料配置。目前為止，此部分及先前部分之討論已主要將在反及陣列上分析之資料集或索引鍵視作在單個反及串上。但是，更一般而言，由於各位元線可具有沿著其形成之可連接至相同資料鎖存器之許多反及串，故此允許資料(一結構描述)沿著相同反及位元線配置在一些單獨區塊中。此示意繪示在圖29中，其中從最高有效位元配置至最低有效位元之一資料集之一些數值資料儲存在相同位元線上，但儲存在來自單獨區塊之反及串中。(本文中此等被展示為毗鄰，但在更一般情況中不一定如此)。位元線隨後可連接至轉移資料鎖存器XDL且透過XS W(電晶體開關)連接至相應感測放大器(SA)及資料鎖存器UDL、LDL，其中在一更典型的多狀態操作中此等可對應於上頁資料鎖存器及下頁資料鎖存器。 (有關圖30中及下一段中圖31中描述之鎖存器結構之更多細節可見於美國專利第7,206,230號及第8,102,705號)。 Figures 29 through 31 consider the configuration of the data for analysis in more detail. So far, the discussion of this and previous sections has focused on the data set or index key analyzed on the inverse array as a single inverse. However, more generally, since each bit line can have a number of inverses formed along it that can be connected to the same data latch, the data (a structural description) is allowed to be placed along the same inverse bit line. In some separate blocks. This schematic is illustrated in Figure 29, where some of the data from the most significant bit configuration to the least significant bit data set is stored on the same bit line, but stored in the inverse of the separate block. (This is shown as being adjacent in this article, but not necessarily in the more general case). The bit line can then be connected to the transfer data latch XDL and connected to the respective sense amplifier (SA) and data latches UDL, LDL via XS W (transistor switch), where in a more typical multi-state operation These can correspond to the data latch on the previous page and the data latch on the next page. (More details regarding the latch structure depicted in Figure 31 in the middle and lower sections of Figure 30 can be found in U.S. Patent Nos. 7,206,230 and 8,102,705).

資料亦可配置在一組(通常毗鄰)位元線內，其等共用相同資料匯流排以與一組資料鎖存器通信。舉例而言，具有此共用結構之一組8條或16條毗鄰位元線可在此等位元線組之多者上儲存各資料集。圖31示意繪示鎖存器結構，其中8條反及位元線可透過來自YBOX電路之邏輯運算處理具有共用SBUS及DBUS之資料，使得一結構描述可儲存 在共用相同資料鎖存器組之8條相關位元線中。 The data can also be configured in a set of (usually adjacent) bit lines that share the same data bus to communicate with a set of data latches. For example, a group of 8 or 16 adjacent bit lines having one of the shared structures can store each data set on the plurality of bit line groups. Figure 31 is a schematic diagram showing the structure of the latch, wherein the eight reverse bit lines can process the data having the shared SBUS and DBUS through the logical operation from the YBOX circuit, so that a structure description can be stored. In the 8 related bit lines sharing the same data latch group.

可根據不同資料計數方法計算分析運算之結果。如圖32中示意繪示，計數可在CPU內數位地完成，將資料從RAM切換出來用於計數。數位計數亦可在反及裝置內執行，諸如藉由二進制搜尋或射擊鏈。類比計數亦可在反及內完成，其雖然較不準確但可更快速完成。圖33展示用於使用類比「線或」電路快速計數之此電路之一些元件：本文中，資料被施加至並聯連接之一組電晶體之閘極，各與由一類比偏壓控制之一電晶體串聯連接。電晶體由一電流鏡之一支線饋送，其另一支線透過充當作用以設定一數位化電流位準之一電晶體而接地。 The result of the analysis operation can be calculated according to different data counting methods. As schematically illustrated in Figure 32, the counting can be done digitally within the CPU, switching the data out of the RAM for counting. The digit count can also be performed within the inverse device, such as by a binary search or shot chain. The analog count can also be done in the opposite direction, which is less accurate but can be completed more quickly. Figure 33 shows some of the components of this circuit for fast counting using an analog-to-wire OR circuit: In this paper, data is applied to the gates of a group of transistors connected in parallel, each electrically controlled by an analog bias. The crystals are connected in series. The transistor is fed by one of the legs of a current mirror, the other of which is grounded through a transistor that acts to set a digitized current level.

圖34繪示分析可如何應用於大型檔案系統。當檔案系統增大時，存在執行複雜查詢之一增大需求，諸如「10天來多少檔案已被更新？」及「哪些是屬於John的前五大檔案？」。第一個係提供檔案系統之所有或部分之一高階概括之彚總查詢之一實例，而第二個係定位根據一計分函數具有最高分數的k個檔案及/或目錄之前k個查詢。如參考圖16描述之反及區段之併入提供執行此等查詢之一簡單解決方案。 Figure 34 illustrates how the analysis can be applied to a large file system. As the file system grows, there is an increase in the need to perform complex queries, such as "How many files have been updated in 10 days?" and "Which are the top five files belonging to John?". The first system provides an example of one or more of the high-level summaries of all or part of the file system, while the second system locates the k queries and/or the first k queries of the directory based on a score function with the highest score. The incorporation of the segments as described with reference to Figure 16 provides a simple solution to perform such queries.

在左側，圖34展示一檔案系統。基本檔案資料(所有人、時戳、檔案大小等)如圖34右側所示保存至垂直反及鏈中之反及中。藉由反及SSD以此方式執行分析節省建立如左側檔案結構中所示之資料樹結構所需之麻煩。隨後，舉例而言，可對針對特定日期對位於一些字線中之時戳搜尋彚總查詢。前k個查詢可舉例而言藉由識別「John」及檔案大小而完成。(如上所示，可針對檔案大小完成最小值及最大值搜尋，其允許檔案系統之部分依此儲存)。 On the left side, Figure 34 shows a file system. The basic file data (owner, time stamp, file size, etc.) is saved to the reverse of the vertical and reverse chain as shown on the right side of Figure 34. Performing the analysis in this way by countering the SSD saves the trouble of creating a data tree structure as shown in the left file structure. Then, for example, a timestamp located in some wordlines for a particular date can be searched for a total query. The first k queries can be completed by, for example, identifying "John" and the file size. (As shown above, the minimum and maximum search can be done for the file size, which allows portions of the file system to be stored accordingly).

應用於重複刪除Applied to deduplication

如上所示，基於反及之CAM或CAS裝置並行搜尋大量索引鍵之能力可用於改良在清理資料庫方面有價值之類型之重複刪除操作之效 率。此部分針對線內或處理後重複刪除操作兩者更詳細考量重複刪除操作。雖然判定一資料型樣是否已沿著反及陣列之位元線存在之能力可用於檢查資料型樣本身是否重複，但是其尤其可用於基於大資料集之相應簽章之重複，諸如藉由一雜湊演算法從資料集產生之一索引鍵，其儲存在CAM反及陣列中。 As indicated above, the ability to search a large number of index keys in parallel based on the inverse CAM or CAS device can be used to improve the effectiveness of deduplication operations of the type that are valuable in cleaning up the database. rate. This section considers deduplication in more detail for both inline and post-processing deduplication operations. Although the ability to determine whether a data pattern has been present along the bit line opposite the array can be used to check whether the data sample body is duplicated, it can be used in particular for repetition of a corresponding signature based on a large data set, such as by a The hash algorithm generates an index key from the data set, which is stored in the CAM inverse array.

可參考圖35繪示基本理念。頂部展示(比如說)由各100GB之10組形成之1,000GB之原始資料。在本實例中，10個資料集之3個係重複，使得此等之兩個可被消除以移除冗餘，作為一類型之粗粒資料壓縮技術。隨後在下文展示重複刪除，其減小至800GB，其中重複被移除且映射相應地更新。若一使用者在查找冗餘資料集，則可透過相關後設資料定位資料，如在下方映射所示，3至1映射至重複資料集之剩餘一者。 The basic concept can be illustrated with reference to FIG. The top shows (for example) 1,000 GB of raw material formed by 10 groups of 100 GB each. In this example, three of the ten data sets are repeated such that two of these can be eliminated to remove redundancy as a type of coarse-grained data compression technique. Deduplication is then shown below, which is reduced to 800 GB, with the repetition being removed and the mapping updated accordingly. If a user is looking for a redundant data set, the data can be located through the associated data, as shown in the mapping below, and 3 to 1 are mapped to the remaining one of the duplicate data sets.

一典型攝取資料路徑包含組塊、雜湊及索引及映射。組塊判定資料中之邊界，藉由檔案邊界、一固定大小組塊、一可變組塊(諸如藉由使用Rabin指紋)或藉由更智慧的方式(諸如一內容型感知)。雜湊可基於可易計算得到的厚塊識別符，其具有高度耐衝突性，諸如密碼型(例如，SHA-1、SHA-2、MD5)。雜湊值隨後可充當資料集之一索引，其中在相應項目之間形成一映射，其允許搜尋較小索引之重複，而非完整資料集。圖36對此進行示意繪示。 A typical ingest data path contains chunks, hashes, and indexes and maps. The chunks determine the boundaries in the data, by file boundaries, a fixed size chunk, a variable chunk (such as by using a Rabin fingerprint), or by a smarter approach (such as a content-based perception). The hash can be based on an easily calculated thick block identifier that is highly conflict resistant, such as a cryptographic type (eg, SHA-1, SHA-2, MD5). The hash value can then serve as an index to one of the data sets, with a mapping formed between the corresponding items that allows searching for duplicates of smaller indexes rather than a complete data set. This is schematically illustrated in Figure 36.

將CAM反及結構應用於此，可針對一組索引鍵使用一些區塊而將雜湊索引鍵或其他簽章儲存在反及鏈中。若輸入資料匹配雜湊索引鍵之任意者，則可能係重複資料。匹配的雜湊索引鍵行位址可指向相應後設資料之位置，其中雜湊索引鍵將被再次確認且資料位置可被識別。為了防止一雜湊衝突(其中相同索引鍵對應於多個資料集)，資料厚塊本身可被比較，但是對於一適當選擇之雜湊算法，此等撞擊之可能性極小。此示意繪示在圖37中。CAM反及之一雜湊索引鍵區塊 3705保持簽章。隨後藉由將後設資料3707映射至儲存區塊3701中之相應資料集而關聯反及串位址。在本文之例示性實施例中，此主儲存器被視作一固態磁碟機(諸如上文針對分析應用所描述)，但亦可為一硬碟機或其他非揮發性儲存器。圖式繪示映射至相同資料集之多個後設資料指標：舉例而言，一檔案1將調用指標x1且一檔案3將調用x3。即使3701上之內容重複，上級檔案系統仍需要後設資料指標。資料比較區段3703允許資料比較在反及快閃記憶體3701內完成，一些位元被忽略或在控制器內比較。 Applying the CAM inverse structure to this, a hashed index key or other signature can be stored in the reverse chain using a number of blocks for a set of index keys. If the input data matches any of the hash index keys, the data may be duplicated. The matched hash index key row address can point to the location of the corresponding post-data, where the hash index key will be reconfirmed and the data location can be identified. To prevent a hash collision (where the same index key corresponds to multiple data sets), the data chunks themselves can be compared, but for a properly chosen hash algorithm, the likelihood of such impacts is minimal. This schematic is shown in Figure 37. CAM reverses one of the hash index key blocks 3705 keeps the signature. The inverse and serial addresses are then associated by mapping the post material 3707 to the corresponding data set in the storage block 3701. In the exemplary embodiment herein, the primary storage is considered a solid state disk drive (such as described above for analytical applications), but can also be a hard disk drive or other non-volatile storage. The figure shows multiple post-data indicators mapped to the same data set: for example, one file 1 will call indicator x1 and one file 3 will call x3. Even if the content on the 3701 is duplicated, the superior file system still needs to set the data indicator. The data comparison section 3703 allows data comparison to be done in the inverse flash memory 3701, with some bits being ignored or compared within the controller.

圖38係此一系統之一架構之一示意展現。主儲存器區段3801在本文中係一快閃磁碟機，諸如具有一32TB容量之一SSD。若需要，可包含一選用壓縮引擎3815以壓縮此資料。(當資料以壓縮形式儲存時，在產生一簽章之前，資料將被解壓縮，使得雜湊索引鍵或其他指紋係基於非壓縮資料，而壓縮形式仍可維持在主儲存區域中)。在一些情況中，壓縮資料可直接用於產生雜湊索引鍵作為內容簽章。對應於資料集之雜湊索引鍵隨後保持在一CAM或搜尋反及(sNAND)區段3803中。本文中，sNAND由具有總共24GB容量之4MB區塊形成，對應於各6B之10⁹個簽章。系統將維持資料集與其等之相應索引鍵之間之一對應關係。此類似於快閃記憶體系統中之常見邏輯至實體位址轉譯，除現在其介於sNAND 3803之位元線定向之索引鍵位置與主儲存器3801中之相應資料集之間，且可相應地管理。本文中，在快閃後設資料圖3805之快閃記憶體中維持對應關係：在本實例中，此係256GB之後設資料，其由4×10⁹個64B段形成。(雖然本文中繪示為單獨的，但是sNAND 3803及快閃後設資料圖3805可在相同的快閃反及記憶體上)。除映射外，後設資料區段亦可保存索引鍵之複本，使得sNAND中之任意匹配可對照複本驗證，該複本可為受ECC保護的。藉由在後設資料區段或其他位置保存索引鍵之複本，此允許使用有利於一「匹 配」而非一「遺漏」之一讀取邊際檢查搜尋陣列：若匹配係真，則後設資料將確認此，而若假，則後設資料將無一匹配索引鍵。此甚至在無需搜尋陣列上之ECC的情況下幫助減小錯誤率。 Figure 38 is a schematic representation of one of the architectures of this system. The main storage section 3801 is herein a flash drive, such as one having a 32 TB capacity SSD. If desired, an optional compression engine 3815 can be included to compress the data. (When the data is stored in compressed form, the data will be decompressed before a signature is generated, so that the hash index key or other fingerprint is based on uncompressed data, and the compressed form can still be maintained in the main storage area). In some cases, the compressed material can be used directly to generate a hash index key as a content signature. The hash index key corresponding to the data set is then held in a CAM or search reverse (sNAND) section 3803. Herein, sNAND is formed by a 4 MB block having a total of 24 GB capacity, corresponding to 10 ⁹ signatures of each 6B. The system will maintain a correspondence between the data set and its corresponding index key. This is similar to the common logic-to-physical address translation in flash memory systems, except that it is now between the index key position of the bit line orientation of sNAND 3803 and the corresponding data set in the main memory 3801, and can be corresponding Management. In this paper, the correspondence is maintained in the flash memory of the data map 3805 after the flashing: in this example, the data is set after 256 GB, which is formed by 4 × 10 ⁹ 64B segments. (Although it is shown here as separate, sNAND 3803 and flash map data 3805 can be on the same flash and memory). In addition to the mapping, the subsequent data section can also save a copy of the index key, so that any match in the sNAND can be verified against the duplicate, which can be protected by the ECC. By saving a copy of the index key in the post data section or other location, this allows the use of a marginal search search array that facilitates a "match" rather than a "missing": if the match is true, then the data is set This will be confirmed, and if it is false, then there will be no matching index key in the post data. This helps reduce the error rate even without the need to search for ECC on the array.

在3811上從資料集產生雜湊索引鍵。此可線內完成，在資料進入時產生或從已在主儲存區段中之資料後處理得到。在任一情況中，在將索引鍵寫入至sNAND 3803中之前，其等可如上文參考圖13至15描述累積。本文中，DRAM 3809累積雜湊索引鍵，其在4MB資料可得時清除至sNAND 3803。亦可包含一選用布隆濾波器區段3813，其更可用於較大儲存情況。 A hash index key is generated from the data set on 3811. This can be done in-line, generated when the data is entered or post-processed from the data already in the main storage section. In either case, before the index key is written into the sNAND 3803, it can be accumulated as described above with reference to FIGS. 13 to 15. Herein, DRAM 3809 accumulates a hash index key that is cleared to sNAND 3803 when 4 MB of data is available. An optional Bloom filter section 3813 can also be included, which can be used for larger storage conditions.

在一線內重複刪除過程中，當資料進入時，雜湊產生器3811可產生相應索引鍵。可首先檢查RAM區段3809中之索引鍵，且若未找到匹配(或即使找到匹配，如需要)，可搜尋sNAND 3803；另一選擇係，可並行檢查sNAND及RAM區段。若未找到匹配，則當RAM清除時，索引鍵可被寫入至RAM區段3809中且隨後被寫入至sNAND 3803上，相應資料集被寫入至主儲存器3801中且對應關係示於後設資料3805中。(映射亦可最初維持在RAM中，隨後開始記錄在3805中，諸如在映射被移至區段3805之後)。若找到一匹配，則資料可取決於所需以若干方式處理。其可簡單不被寫入。若存在一雜湊衝突的問題，則可對照匹配簽章之實際資料檢查實際資料(相對於簽章)：雖然更耗時，但是此應為少有情況，此係因為即使對於具有一相對較高衝突機率之索引鍵，可能性仍非常小。另一選擇係，若存在一匹配，則新資料集將不被寫入主儲存器，且其後設資料將指向匹配的資料位置。在此等情況之任意者中，若需要，當找到一匹配時，可藉由索引鍵之一複本驗證索引鍵，諸如可保存在後設資料3805中。此雙重檢查將不耗費額外時間，此係因為後設資料需被檢查及修改以指向重複索引鍵所指向之實體位置。若新索引鍵無一匹配，則資料將被寫入至3801。新 索引鍵可暫時儲存在RAM 3809中。具有新指標之新後設資料可儲存在3805中。 During the one-line deduplication process, when the data enters, the hash generator 3811 can generate a corresponding index key. The index key in RAM section 3809 can be checked first, and if no match is found (or even if a match is found, if needed), sNAND 3803 can be searched; another option is to check the sNAND and RAM sections in parallel. If no match is found, when the RAM is cleared, the index key can be written to the RAM section 3809 and then written to the sNAND 3803, the corresponding data set is written to the main memory 3801 and the correspondence is shown in After the information is 3805. (The mapping may also be initially maintained in RAM, and then recorded in 3805, such as after the mapping is moved to section 3805). If a match is found, the data can be processed in several ways depending on the needs. It can be simply not written. If there is a problem of hash collision, the actual data (relative to the signature) can be checked against the actual data of the matching signature: although it is more time consuming, this should be rare, because even if it has a relatively high The index key of the conflict probability is still very small. Another option is that if there is a match, the new data set will not be written to the main memory, and the subsequent data will point to the matching data location. In any of these cases, if a match is found, the index key can be verified by a copy of one of the index keys, such as in the post material 3805. This double check will not take extra time, because the post data needs to be checked and modified to point to the physical location pointed to by the duplicate index key. If there is no match for the new index key, the data will be written to 3801. new The index key can be temporarily stored in the RAM 3809. New post-data with new indicators can be stored in the 3805.

可回應於來自一主機之一特定請求或作為如使用備用儲存器之重複刪除之週期性壓縮之一內部資料維持操作之部分可對主記憶體3801中已存在的資料完成後處理或線外重複刪除。主記憶體新資料區段3801中之資料可被讀回且檢查索引鍵進行重複刪除，但在此情況中，索引鍵通常皆已在sNAND 3803中且RAM區段3801無需檢查。來自新資料區段之索引鍵可與來自舊資料區段之儲存索引鍵比較看一些資料是否重複。若找到一匹配，則來自新資料區段之索引鍵可被標記刪除。3801中之資料可被移除。3805中之後設資料將被修改以指向新的實體位置。在重複刪除後，資料通常被分段。記憶體回收可被觸發以合併資料及移除所刪除之資料及索引鍵。無論線內或線外完成，sNAND 3803歸因於先前部分中所討論程度的並行性而提供大的記憶體空間及良好的索引鍵匹配速度。通常，由於線外重複刪除可在記憶體回收期間完成，故其無效能代價；而雖然線內過程確實具有一效能代價之取捨，但其可節省主磁碟機容量，減小導致快閃磁碟機耐用性增大之寫入放大及藉由執行較少寫入操作而減小功率消耗。線外重複刪除亦可提供更多空閒容量用於「過度佈建」及改良效能，其中過度佈建係可用於壓縮資料及其他功能之額外儲存器之部分。具有額外容量，記憶體回收將不經常被觸發。 The post-processing or out-of-line repetition may be performed on the data already existing in the main memory 3801 in response to a portion of the internal data maintenance operation from a particular request from one of the hosts or as a periodic compression of the deduplication using the alternate storage. delete. The data in the main memory new data section 3801 can be read back and the index key checked for deduplication, but in this case, the index keys are typically already in sNAND 3803 and the RAM section 3801 does not need to be checked. The index key from the new data section can be compared with the storage index key from the old data section to see if some data is duplicated. If a match is found, the index key from the new data section can be marked for deletion. The data in 3801 can be removed. After 3805, the data will be modified to point to the new physical location. After deduplication, the data is usually segmented. Memory reclamation can be triggered to merge data and remove deleted data and index keys. Whether completed in-line or off-line, sNAND 3803 provides large memory space and good index key matching speed due to the degree of parallelism discussed in the previous section. Generally, since the off-line deduplication can be completed during the memory recovery period, it can be ineffective. Although the in-line process does have a cost-off, it can save the main disk drive capacity and reduce the flash magnetism. The disk drive has increased durability for write amplification and reduces power consumption by performing fewer write operations. Off-line deduplication can also provide more free capacity for "over-deployment" and improved performance, where over-provisioning is part of the extra storage that can be used to compress data and other functions. With extra capacity, memory reclamation will not be triggered often.

sNAND記憶體3803之例示性實施例再次基於一快閃型記憶體，其中記憶體單元按區塊單位擦除。因此，可能存在一區塊之一些索引鍵已變成過時之情況，但其中其在將當前索引鍵重寫至另一區塊中時可能不需要，因此相同區塊將包含當前索引鍵及過時索引鍵。鑑於此，較佳存在一些將索引鍵標記為過時之方式。這樣做之一方式係藉由將此指示為後設資料之部分。另一方式係此可藉由具有針對各索引 鍵之一或多個旗標位元，使得過時索引鍵可被程式化使得其等將停止反及鏈傳導而完成。如圖39中示意繪示，此等位元可以類似於用於上文參考圖6B描述之同位位元之一配置沿著相應反及串中之一或多條字線。(可使用一類似配置，其中索引鍵及反轉值儲存在相同位元線上，如圖5中，其中雖然僅將索引鍵-索引鍵反轉值對之一者標記為過時係足夠，但是通常標記兩者更佳)。為了將相應索引鍵標記為過時，沿著過時資料字線之相應單元隨後可被程式化，其中進一步更新可在另一專用字線上完成，或若允許部分頁程式化，則藉由進一步程式化相同字線完成。在進行索引鍵搜尋時，過時旗標字線隨後被設定為低讀取值，使得任意過時索引鍵(反及串)將不傳導且因此未被發現匹配搜尋索引鍵。(此類似於同位位元情況，但其中相應字線皆被設定為高「隨意」值)。在記憶體回收期間，一區塊中之所有索引鍵可被轉移至RAM區塊並在此再組織，此時任意過時索引鍵可被完全移除且仍有效的索引鍵可被寫回，此時亦可被添加新索引鍵。 The exemplary embodiment of sNAND memory 3803 is again based on a flash memory in which the memory cells are erased in block units. Therefore, there may be cases where some of the index keys of a block have become obsolete, but it may not be needed when rewriting the current index key into another block, so the same block will contain the current index key and the obsolete index. key. In view of this, it is preferable to have some way of marking the index key as obsolete. One way to do this is by indicating this as part of the post-set data. Another way is by having an index for each One or more flag bits of the key, such that the obsolete index key can be programmed such that it will stop performing reverse chain conduction. As schematically illustrated in FIG. 39, the bits may be arranged along one or more of the word lines in the corresponding inverse string, similar to one of the parity bits described above with respect to FIG. 6B. (A similar configuration can be used where the index key and the inverted value are stored on the same bit line, as in Figure 5, although it is usually sufficient to mark one of the index key-index key inversion values as obsolete, but usually Mark both better). In order to mark the corresponding index key as obsolete, the corresponding unit along the obsolete data word line can then be programmed, where further updates can be done on another dedicated word line, or if partial page programming is allowed, by further stylization The same word line is completed. When index key search is performed, the obsolete flag word line is then set to a low read value such that any outdated index keys (reverse and string) will not be transmitted and thus are not found to match the search index key. (This is similar to the parity bit case, but the corresponding word line is set to a high "casual" value). During memory reclamation, all index keys in a block can be transferred to the RAM block and reorganized here, at which point any outdated index key can be completely removed and the still valid index key can be written back. A new index key can also be added.

圖38之架構可以若干方式實現。舉例而言，主儲存器可為一或多個硬碟機或其他類型之非揮發性記憶體。此處，例示性實施例再次被視作一固態磁碟機(SSD)。重複刪除結構可被併入SSD結構或作為一單獨的子系統，其具有索引鍵且其等至相關資料之對應關係。圖40對此進行示意繪示。如上所討論，重複刪除子系統4001可用於對主儲存器系統4003中之資料之線內或線外操作。在任一情況中，配置允許組合系統利用重複刪除子系統4001之sNAND結構之快速搜尋、低功率操作。 The architecture of Figure 38 can be implemented in a number of ways. For example, the primary storage can be one or more hard drives or other types of non-volatile memory. Here, the illustrative embodiment is again considered a solid state disk drive (SSD). The deduplication structure can be incorporated into the SSD structure or as a separate subsystem with index keys and waiting for correspondence to related material. This is schematically illustrated in Figure 40. As discussed above, the deduplication subsystem 4001 can be used for in-line or out-of-line operation of data in the primary storage system 4003. In either case, the configuration allows the combined system to utilize the fast seek, low power operation of the sNAND structure of the deduplication subsystem 4001.

圖41係一更詳細展現，其將一重複刪除子系統4101添加至一SSD系統4103中，使得重複刪除功能性可整合至儲存產品中。一實施方案可基於具有許多PCI-Express插槽之成品刀鋒式伺服器，定製刀鋒可***其中。建立圖41之例示性系統所需之刀鋒將為： 傳輸刀鋒(TB)4133--此係呈現至其他伺服器之儲存介面。其可為Fiberchannel、乙太網路等。傳輸刀鋒隨後可在系統外在SAN/NAS 4151上連接至一網路。 Figure 41 is a more detailed presentation showing the addition of a deduplication subsystem 4101 to an SSD system 4103 such that the deduplication functionality can be integrated into the storage product. An implementation can be based on a finished blade server with many PCI-Express slots into which a custom blade can be inserted. The blade required to create the exemplary system of Figure 41 would be: Transport Blade (TB) 4313 - This is presented to the storage interface of other servers. It can be Fiberchannel, Ethernet, etc. The transport blade can then be connected to a network on the SAN/NAS 4151 outside the system.

儲存刀鋒(SB)4131-i--此等等效於目前的ESS企業磁碟機，具有其等選擇使用之任意快閃儲存媒體(X3、BIC、改型X2等)。此等刀鋒包含本端DRAM及快閃轉譯表，其用於製作邏輯至實體映射。 Storage Blade (SB) 4131-i--This is equivalent to the current ESS Enterprise Disk Drive, with any flash storage media (X3, BIC, Modified X2, etc.) that it chooses to use. These blades include local DRAM and flash translation tables for making logical-to-entity mappings.

布隆濾波器刀鋒(BF)4113--提供布隆濾波函數用於判定一物件是否存在於儲存刀鋒中。此可實施在DRAM或快閃中。大致上每太位元組之主儲存器可使用512MB之布隆濾波儲存器。此刀鋒將具有專門硬體用於進行雜湊函數及位元操縱之高效計算。 Bloom Filter Blade (BF) 4113-- provides a Bloom filter function to determine if an object is present in the storage blade. This can be implemented in DRAM or flash. In general, the main memory of each terabyte can use a 512 MB Bloom filter memory. This blade will have specialized hardware for efficient calculation of hash functions and bit manipulation.

重複刪除刀鋒(DD)4115--執行重複刪除功能。此刀鋒將具有定製硬體以執行列至行變換。刀鋒亦可用DRAM擴充以進行預分類以實施淺的二進制樹搜尋。大約358個元區塊(假設每個裝置4個平面)可用於各太位元組之主儲存器。 Repeat Delete Blade (DD) 4115--Perform the deduplication function. This blade will have custom hardware to perform column-to-row transformations. The blade can also be expanded with DRAM for pre-classification to implement a shallow binary tree search. Approximately 358 metablocks (assuming 4 planes per device) are available for the main memory of each terabyte.

CPU 4111、4121-i--CPU可針對主儲存器及重複刪除功能運行管理軟體。CPU可內建於伺服器母板或添加作為額外刀鋒功能。不同刀鋒藉由匯流排結構連接至其他插槽及透過北橋接器NB 4123連接至CPU。 The CPU 4111, 4121-i--CPU can run the management software for the main memory and the deduplication function. The CPU can be built into the server motherboard or added as an additional blade feature. The different blades are connected to the other slots by the bus bar structure and to the CPU through the north bridge NB 4123.

在重複刪除CPU(DD CPU)4111上運行之重複刪除系統軟體可用「此叢集是否已存在於濾波器中？」之一查詢將一4K叢集轉移至布隆濾波器(BF)刀鋒4113。BF刀鋒4113將計算必要的雜湊函數並查詢布隆濾波器儲存器以判定叢集是否存在。若不存在，則4K叢集將被添加至布隆濾波器且將返回值「不存在」。若4K叢集存在，則布隆濾波器將返回「存在」至重複刪除系統軟體。當重複刪除系統軟體接收到「不存在」回應時，其將發送一「添加叢集」命令至重複刪除刀鋒4115。重複刪除刀鋒4115將計算一雜湊指紋，將其添加至sNAND陣列 (經由列-行轉置區塊)及用4K叢集之邏輯位址更新關聯位元線位址表。 The deduplication system software running on the deduplication CPU (DD CPU) 4111 can transfer a 4K cluster to the Bron filter (BF) blade 4113 using one of the queries "Is this cluster already present in the filter?" The BF Blade 4113 will calculate the necessary hash function and query the Bloom filter memory to determine if the cluster is present. If it does not exist, the 4K cluster will be added to the Bloom filter and the return value will be "not present". If a 4K cluster exists, the Bloom filter will return "present" to the deduplication system software. When the deduplication system software receives a "nothing" response, it will send an "add cluster" command to the deduplication blade 4115. Repeatedly remove blade 4115 will calculate a hash fingerprint and add it to the sNAND array The associated bit line address table is updated (via the column-row transpose block) and with the logical address of the 4K cluster.

當重複刪除系統軟體接收到「存在」回應時，其隨後將發出一查詢至重複刪除刀鋒4115。重複刪除刀鋒4115將產生雜湊指紋並將其用於針對匹配指紋之叢集之位置而查詢搜尋反及(sNAND)區塊。一旦找到匹配，位元線位址將被用於索引至一表格中以擷取重複叢集之邏輯位址「Y」。位址「Y」被返回至重複刪除管理軟體。 When the deduplication system software receives a "presence" response, it will then issue a query to the deduplication blade 4115. The deduplication blade 4115 will generate a hash fingerprint and use it to query the search reverse (sNAND) block for the location of the cluster of matching fingerprints. Once a match is found, the bit line address will be used to index into a table to retrieve the logical address "Y" of the repeating cluster. The address "Y" is returned to the deduplication management software.

在已定位到重複命中後，重複刪除管理軟體告知儲存管理軟體位於「X」及「Y」上之叢集係重複。儲存管理軟體隨後可發出一「重複刪除Y->X」命令至儲存刀鋒之一者。假設邏輯位址「X」指向實體位置「Z」，儲存刀鋒隨後將更新其內部邏輯至實體轉譯表，使得邏輯位址「Y」現指向實體位置「Z」。「Z」之參考計數器將遞增。 After the repeated hits have been located, the deduplication management software informs the storage management software that the clusters on "X" and "Y" are duplicated. The storage management software can then issue a "Repeat Y->X" command to one of the storage blades. Assuming the logical address "X" points to the physical location "Z", the storage blade will then update its internal logic to the entity translation table so that the logical address "Y" now points to the physical location "Z". The reference counter for "Z" will be incremented.

結論in conclusion

已為闡釋及描述之目的提出上文詳細描述。其不旨在為詳盡的或限於所揭示之精確形式。有關上述教示之許多修改及變化係可能的。選擇所述實施例以最好地說明所揭示技術之原理及其實踐應用，以藉此使其他熟習此項技術者能在不同實施例中及結合如對於設想之特定使用適合之不同修改最佳地利用技術。 The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations to the above teachings are possible. The embodiments were chosen to best illustrate the principles of the disclosed technology and its practical applications, in order to enable others skilled in the art to make various modifications in various embodiments and combinations as appropriate for the particular use contemplated. Land use technology.

4101‧‧‧重複刪除子系統 4101‧‧‧Repeat deletion subsystem

4103‧‧‧固態磁碟機(SSD)系統 4103‧‧‧Solid Disk Drive (SSD) System

4111‧‧‧中央處理單元(CPU) 4111‧‧‧Central Processing Unit (CPU)

4113‧‧‧布隆濾波器刀鋒(BF) 4113‧‧‧Bron filter blade (BF)

4115‧‧‧重複刪除刀鋒(DD) 4115‧‧‧Repeat the blade (DD)

4121-1‧‧‧中央處理單元(CPU) 4121-1‧‧‧Central Processing Unit (CPU)

4121-N‧‧‧中央處理單元(CPU) 4121-N‧‧‧Central Processing Unit (CPU)

4123‧‧‧北橋接器NB 4123‧‧‧North Bridge NB

4131-2‧‧‧儲存刀鋒(SB) 4131-2‧‧‧Storage Blade (SB)

4131-(N-1)‧‧‧儲存刀鋒(SB) 4131-(N-1)‧‧‧Storage Blade (SB)

4133‧‧‧傳輸刀鋒(TB) 4133‧‧‧Transportation Blade (TB)

4151‧‧‧SAN/NAS 4151‧‧‧SAN/NAS

Claims (70)

一種操作一非揮發性記憶體系統之方法，其包括：將複數個資料集儲存在該系統之一第一非揮發性記憶體區段中；針對該等資料集之各者，將一相應簽章儲存在一搜尋陣列中，其中對於該等資料集之各者，該簽章導出自該相應資料集且為一較小大小，其中該搜尋陣列為反及型架構且該等簽章儲存在該搜尋陣列中，沿著該搜尋陣列之位元線定向；藉由該記憶體系統維持該等資料集儲存在該第一非揮發性記憶體區段中之位置與該等相應簽章儲存在該搜尋陣列中之位置之間之一對應關係；接收一第一簽章；根據該第一簽章加偏壓於該搜尋陣列之字線；及判定該搜尋陣列之該等位元線之任意者是否回應於該等字線之該加偏壓而傳導。 A method of operating a non-volatile memory system, comprising: storing a plurality of data sets in a first non-volatile memory segment of the system; for each of the data sets, a corresponding sign The chapters are stored in a search array, wherein for each of the data sets, the signature is derived from the corresponding data set and is a smaller size, wherein the search array is a reverse architecture and the signatures are stored in The search array is oriented along a bit line of the search array; the memory system maintains the location of the data set stored in the first non-volatile memory segment and the corresponding signature is stored in the Corresponding to one of the locations in the search array; receiving a first signature; biasing the word line of the search array according to the first signature; and determining any of the bit lines of the search array Whether or not the conduction is conducted in response to the biasing of the word lines. 如請求項1之方法，其進一步包括：回應於判定該搜尋陣列之該等位元線皆不回應於該等字線之偏壓而傳導，將該第一簽章所對應之一第一資料集寫入至該第一非揮發性記憶體區段中。 The method of claim 1, further comprising: in response to determining that the bit lines of the search array are not responsive to the bias of the word lines, the first data corresponding to the first signature The set is written into the first non-volatile memory segment. 如請求項2之方法，其進一步包括：將該第一簽章寫入至搜尋陣列中。 The method of claim 2, further comprising: writing the first signature to the search array. 如請求項3之方法，其進一步包括：在將該第一簽章寫入至該搜尋陣列中之前，將該第一簽章寫入至RAM記憶體中。 The method of claim 3, further comprising: writing the first signature to the RAM memory before writing the first signature to the search array. 如請求項1之方法，其進一步包括： 回應於判定該搜尋陣列之一位元線回應於該等字線之偏壓而傳導，不將該第一簽章所對應之一第一資料集寫入至該第一非揮發性記憶體區段中。 The method of claim 1, further comprising: Responding to determining that one of the bit lines of the search array is transmitted in response to the bias of the word lines, and not writing the first data set corresponding to the first signature to the first non-volatile memory area In the paragraph. 如請求項5之方法，其進一步包括：在該對應關係中使該第一資料集與對應於在該判定中傳導之該位元線之該簽章相關聯。 The method of claim 5, further comprising: associating the first data set with the signature corresponding to the bit line that is conducted in the determination in the correspondence. 如請求項1之方法，其中該加偏壓包含將一或多條字線設定為一「隨意」值，該方法進一步包括：回應於判定該搜尋陣列之該等位元線之一者以上回應於該等字線之該加偏壓而傳導，隨後根據該第一簽章但不同於該先前加偏壓而加偏壓於該搜尋陣列之該等字線；及判定該搜尋陣列之該等位元線之任意者是否回應於該等字線之該等加偏壓兩者而傳導。 The method of claim 1, wherein the biasing comprises setting one or more word lines to a "random" value, the method further comprising: responding to determining one of the bit lines of the search array to respond Conducting the biasing of the word lines, then biasing the word lines of the search array according to the first signature but different from the previous bias; and determining the search array Whether any of the bit lines are conducted in response to both of the biasing of the word lines. 如請求項1之方法，其中該第一簽章之該接收包含：從一相應第一資料集中產生該第一簽章。 The method of claim 1, wherein the receiving of the first signature comprises: generating the first signature from a corresponding first data set. 如請求項8之方法，其中該等資料集以壓縮形式儲存在該第一記憶體區段中且該相應第一資料集在從其中產生該第一簽章之前被解壓縮。 The method of claim 8, wherein the data sets are stored in the first memory segment in a compressed form and the corresponding first data set is decompressed prior to generating the first signature therefrom. 如請求項8之方法，其中該等簽章係從該相應資料集產生之雜湊值。 The method of claim 8, wherein the signatures are hash values generated from the corresponding data set. 如請求項8之方法，其中自該記憶體系統之外接收該第一資料集。 The method of claim 8, wherein the first data set is received from outside the memory system. 如請求項8之方法，其中該第一資料集讀取自該第一非揮發性記憶體區段。 The method of claim 8, wherein the first data set is read from the first non-volatile memory segment. 如請求項12之方法，其中該第一資料集被讀取作為一系統上資料維持操作之部分。 The method of claim 12, wherein the first data set is read as part of a data maintenance operation on a system. 如請求項12之方法，其中該第一資料集回應於來自該記憶體系統之輸出之一請求而被讀取。 The method of claim 12, wherein the first data set is read in response to a request from an output of the memory system. 如請求項1之方法，其進一步包括：比較該第一簽章與儲存在該記憶體系統之一第二區段中之一或多個簽章。 The method of claim 1, further comprising: comparing the first signature with one or more signatures stored in a second section of the one of the memory systems. 如請求項15之方法，其中該第二區段係揮發性RAM記憶體。 The method of claim 15, wherein the second segment is a volatile RAM memory. 如請求項16之方法，其中該記憶體系統在該加偏壓及判定的同時針對該第一簽章搜尋該RAM記憶體。 The method of claim 16, wherein the memory system searches for the RAM memory for the first signature while the biasing and determining. 如請求項15之方法，其中該第二區段係一快閃記憶體陣列，其中該一或多個簽章儲存為沿著其字線定向。 The method of claim 15, wherein the second segment is a flash memory array, wherein the one or more signatures are stored as being oriented along their word lines. 如請求項1之方法，其中維持一對應關係包含：維持該對應關係之一複本作為該記憶體系統之非揮發性記憶體中之後設資料。 The method of claim 1, wherein maintaining a correspondence comprises: maintaining a copy of the correspondence as a post-data in the non-volatile memory of the memory system. 如請求項19之方法，其進一步包括維持該簽章之複本作為該後設資料之部分。 The method of claim 19, further comprising maintaining a copy of the signature as part of the post material. 如請求項20之方法，其中該等簽章之該等複本係受ECC保護的。 The method of claim 20, wherein the copies of the signatures are protected by the ECC. 如請求項1之方法，其中該第一記憶體區段係一固態磁碟機。 The method of claim 1, wherein the first memory segment is a solid state disk drive. 如請求項1之方法，其中搜尋陣列係該固態磁碟機之部分。 The method of claim 1, wherein the search array is part of the solid state drive. 如請求項1之方法，其中搜尋陣列係單獨於該固態磁碟機之單元。 The method of claim 1, wherein the search array is separate from the unit of the solid state drive. 如請求項24之方法，其中該等單獨單元儲存該等簽章及該對應關係。 The method of claim 24, wherein the individual units store the signatures and the correspondence. 如請求項1之方法，其中該等資料集以壓縮形式儲存在該第一記憶體區段中。 The method of claim 1, wherein the data sets are stored in the first memory segment in a compressed form. 如請求項1之方法，其進一步包括：將經更新之複數個簽章寫入至該搜尋陣列中；及根據該等簽章之該更新而更新該對應關係。 The method of claim 1, further comprising: writing the updated plurality of signatures to the search array; and updating the correspondence according to the update of the signatures. 如請求項27之方法，其進一步包括：將該等未更新簽章之一或多者標記為過時。 The method of claim 27, further comprising: marking one or more of the unupdated signatures as obsolete. 如請求項28之方法，其中該搜尋陣列具有一區塊結構且其中該等區塊包含保留用於將簽章標記為過時之一或多條字線。 The method of claim 28, wherein the search array has a block structure and wherein the blocks include one or more word lines reserved for marking the signature as obsolete. 如請求項28之方法，其中該搜尋陣列具有一區塊結構，該方法進一步包括：對該搜尋陣列中之該等簽章執行一記憶體回收操作，其包含：針對一或多個區塊，將未被標記為過時之該等簽章複製至揮發性記憶體中；及將未被標記為過時之該等簽章重寫至該搜尋陣列之一不同區塊中。 The method of claim 28, wherein the search array has a block structure, the method further comprising: performing a memory reclamation operation on the signatures in the search array, comprising: for one or more blocks, The signatures that are not marked as obsolete are copied into the volatile memory; and the signatures that are not marked as obsolete are rewritten into different blocks of the search array. 如請求項30之方法，其中該記憶體回收操作進一步包含：將一或多個額外簽章添加至寫入至該不同區塊中之該簽章。 The method of claim 30, wherein the memory reclamation operation further comprises: adding one or more additional signatures to the signature written to the different block. 如請求項1之方法，其中該等第一資料集為一固定大小。 The method of claim 1, wherein the first data set is a fixed size. 如請求項1之方法，其中該等第一資料集為一可變大小。 The method of claim 1, wherein the first data set is a variable size. 如請求項1之方法，其中使用相對於標準值偏移達正邊際之該等字線之讀取電壓執行該加偏壓。 The method of claim 1, wherein the biasing is performed using a read voltage of the word lines offset to a positive margin with respect to a standard value. 如請求項1之方法，其進一步包括：回應於判定該搜尋陣列之一位元線回應於該等字線之偏壓而傳導，判定該第一簽章所對應之一第一資料集是否與對應於傳導之該位元線之該資料集相同。 The method of claim 1, further comprising: in response to determining that a bit line of the search array is transmitted in response to a bias of the word lines, determining whether a first data set corresponding to the first signature is The data set corresponding to the bit line of conduction is the same. 一種非揮發性記憶體系統，其包括：一第一非揮發性記憶體區段，其儲存複數個資料集；一搜尋區段，其包含：一搜尋陣列，其儲存該等資料集之各者之一相應簽章，其 中對於該等資料集之各者，該簽章導出自該相應資料集且為一較小大小，其中該搜尋陣列為反及型架構且該等簽章儲存在該搜尋陣列中，沿著該搜尋陣列之位元線定向；偏壓電路，其連接至該搜尋陣列之該等字線；及感測電路，其連接至該搜尋陣列之該等位元線，其中基於一所接收之第一簽章，該偏壓電路根據該第一簽章加偏壓於該搜尋陣列之該等字線且該感測電路判定該搜尋陣列之該等位元線之任意者是否回應於該等字線之該加偏壓而傳導，其中該記憶體系統維持該等資料集儲存在該第一非揮發性記憶體區段中之位置與該等相應簽章儲存在該搜尋陣列中之位置之間之一對應關係。 A non-volatile memory system comprising: a first non-volatile memory segment storing a plurality of data sets; a search segment comprising: a search array storing each of the data sets One of the corresponding signatures, For each of the data sets, the signature is derived from the corresponding data set and is a smaller size, wherein the search array is a reverse architecture and the signatures are stored in the search array along the Locating a bit line orientation of the array; a bias circuit coupled to the word lines of the search array; and a sensing circuit coupled to the bit line of the search array, wherein based on a received a signature, the bias circuit biasing the word lines of the search array according to the first signature and the sensing circuit determines whether any of the bit lines of the search array are responsive to the The biasing of the word line is conducted, wherein the memory system maintains the location of the data set stored in the first non-volatile memory segment and the location of the corresponding signature stored in the search array One of the correspondences. 如請求項36之非揮發性記憶體系統，其中回應於判定該搜尋陣列之該等位元線皆不回應於該等字線之偏壓而傳導，該系統將該第一簽章所對應之一第一資料集寫入至該第一非揮發性記憶體區段中。 The non-volatile memory system of claim 36, wherein the system is responsive to determining that the bit lines of the search array are not responsive to the bias of the word lines, the system corresponding to the first signature A first data set is written into the first non-volatile memory segment. 如請求項37之非揮發性記憶體系統，其中此外，該搜尋區段進一步包含連接至該搜尋陣列之寫入電路其且該記憶體系統將該第一簽章寫入至搜尋陣列中。 The non-volatile memory system of claim 37, wherein the search segment further comprises a write circuit coupled to the search array and the memory system writes the first signature into the search array. 如請求項38之非揮發性記憶體系統，其中該搜尋區段進一步包含一RAM記憶體，且在將該第一簽章寫入至該搜尋陣列中之前，該搜尋區段將該第一簽章寫入至RAM記憶體中。 The non-volatile memory system of claim 38, wherein the search segment further comprises a RAM memory, and the search segment prioritizes the first signature before writing the first signature to the search array The chapter is written to the RAM memory. 如請求項36之非揮發性記憶體系統，其中回應於判定該搜尋陣列之一位元線回應於該等字線之偏壓而傳導，該記憶體系統不將該第一簽章所對應之一所接收之第一資料集寫入至該第一非揮發性記憶體區段中。 The non-volatile memory system of claim 36, wherein the memory system does not correspond to the first signature in response to determining that a bit line of the search array is transmitted in response to a bias voltage of the word lines A received first data set is written into the first non-volatile memory segment. 如請求項40之非揮發性記憶體系統，其中該記憶體系統在該對 應關係中使該第一資料集與對應於在該判定中傳導之該位元線之該簽章相關聯。 The non-volatile memory system of claim 40, wherein the memory system is in the pair The first data set is associated with the signature corresponding to the bit line that is conducted in the determination. 如請求項36之非揮發性記憶體系統，其中該加偏壓包含將一或多條字線設定為一「隨意」值，其中：回應於判定該搜尋陣列之該等位元線之一者以上回應於該等字線之該加偏壓而傳導，該搜尋陣列隨後根據該第一簽章但不同於該先前加偏壓而加偏壓於該搜尋陣列之該等字線；及判定該搜尋陣列之該等位元線之任意者是否回應於該等字線之該等加偏壓兩者而傳導。 The non-volatile memory system of claim 36, wherein the biasing comprises setting one or more word lines to a "random" value, wherein: responsive to determining one of the bit lines of the search array The above is responsive to the biasing of the word lines, the search array then biasing the word lines of the search array according to the first signature but different from the previous bias; and determining Whether any of the bit lines of the search array are responsive to both of the biasing of the word lines. 如請求項36之非揮發性記憶體系統，其中該記憶體系統進一步包含簽章產生電路，其中該系統從一相應第一資料集產生該第一簽章。 The non-volatile memory system of claim 36, wherein the memory system further comprises a signature generation circuit, wherein the system generates the first signature from a respective first data set. 如請求項43之非揮發性記憶體系統，其中該記憶體系統包含壓縮電路且該等資料集以壓縮形式儲存在該第一記憶體區段中且該相應第一資料集在從其中產生該第一簽章之前被解壓縮。 The non-volatile memory system of claim 43, wherein the memory system includes a compression circuit and the data sets are stored in the first memory segment in a compressed form and the corresponding first data set is generated therefrom The first signature was unzipped before. 如請求項43之非揮發性記憶體系統，其中該等簽章係從該相應資料集產生之雜湊值。 The non-volatile memory system of claim 43, wherein the signatures are hash values generated from the corresponding data set. 如請求項43之非揮發性記憶體系統，其中自該記憶體系統之外接收該第一資料集。 The non-volatile memory system of claim 43, wherein the first data set is received from outside the memory system. 如請求項43之非揮發性記憶體系統，其中該第一資料集讀取自該第一非揮發性記憶體區段。 The non-volatile memory system of claim 43, wherein the first data set is read from the first non-volatile memory segment. 如請求項47之非揮發性記憶體系統，其中該第一資料集被讀取作為一系統上資料維持操作之部分。 The non-volatile memory system of claim 47, wherein the first data set is read as part of a data maintenance operation on a system. 如請求項47之非揮發性記憶體系統，其中該第一資料集回應於來自該記憶體系統之輸出之一請求而被讀取。 The non-volatile memory system of claim 47, wherein the first data set is read in response to a request from an output of the memory system. 如請求項36之非揮發性記憶體系統，其中該記憶體系統進一步 包含一第二記憶體區段且該記憶體系統比較該第一簽章與儲存在該第二區段中之一或多個簽章。 The non-volatile memory system of claim 36, wherein the memory system further A second memory segment is included and the memory system compares the first signature with one or more signatures stored in the second segment. 如請求項50之非揮發性記憶體系統，其中該第二區段係揮發性RAM記憶體。 The non-volatile memory system of claim 50, wherein the second segment is a volatile RAM memory. 如請求項51之非揮發性記憶體系統，其中該記憶體系統在該加偏壓及判定的同時針對該第一簽章搜尋該RAM記憶體。 The non-volatile memory system of claim 51, wherein the memory system searches for the RAM memory for the first signature while the biasing and determining. 如請求項50之非揮發性記憶體系統，其中該第二區段係一快閃記憶體陣列，其中該一或多個簽章儲存為沿著其字線定向。 The non-volatile memory system of claim 50, wherein the second segment is a flash memory array, wherein the one or more signatures are stored as being oriented along their word lines. 如請求項36之非揮發性記憶體系統，其中維持一對應關係包含：維持該對應關係之一複本作為該記憶體系統之非揮發性記憶體中之後設資料。 The non-volatile memory system of claim 36, wherein maintaining a correspondence comprises maintaining a copy of the correspondence as a post-data in the non-volatile memory of the memory system. 如請求項54之非揮發性記憶體系統，其進一步包括維持該簽章之複本作為該後設資料之部分。 The non-volatile memory system of claim 54, further comprising maintaining a copy of the signature as part of the post-data. 如請求項55之非揮發性記憶體系統，其中該等簽章之該等複本係受ECC保護的。 The non-volatile memory system of claim 55, wherein the copies of the signatures are protected by the ECC. 如請求項36之非揮發性記憶體系統，其中該第一記憶體區段係一固態磁碟機。 The non-volatile memory system of claim 36, wherein the first memory segment is a solid state disk drive. 如請求項36之非揮發性記憶體系統，其中搜尋區段係該固態磁碟機之部分。 The non-volatile memory system of claim 36, wherein the search segment is part of the solid state drive. 如請求項36之非揮發性記憶體系統，其中搜尋區段係單獨於該固態磁碟機之單元。 The non-volatile memory system of claim 36, wherein the search segment is separate from the unit of the solid state drive. 如請求項59之非揮發性記憶體系統，其中該等單獨單元儲存該等簽章及該對應關係。 The non-volatile memory system of claim 59, wherein the individual units store the signatures and the correspondence. 如請求項36之非揮發性記憶體系統，其中該記憶體系統包含壓縮電路且在儲存在該第一記憶體區段之前壓縮該等資料集。 The non-volatile memory system of claim 36, wherein the memory system includes a compression circuit and compresses the data sets prior to being stored in the first memory segment. 如請求項36之非揮發性記憶體系統，其中在將經更新複數個簽 章寫入至該搜尋陣列中時，該記憶體系統根據該等簽章之該更新而更新該對應關係。 The non-volatile memory system of claim 36, wherein the plurality of signatures are to be updated When the chapter is written into the search array, the memory system updates the correspondence according to the update of the signatures. 如請求項62之非揮發性記憶體系統，其中在寫入該經更新複數個簽章時，該記憶體系統將該等未更新簽章之一或多者標記為過時。 The non-volatile memory system of claim 62, wherein the memory system marks one or more of the unupdated signatures as obsolete when the updated plurality of signatures are written. 如請求項63之非揮發性記憶體系統，其中該搜尋陣列具有一區塊結構且其中該等區塊包含保留用於將簽章標記為過時之一或多條字線。 A non-volatile memory system as in claim 63, wherein the search array has a block structure and wherein the blocks contain one or more word lines reserved for marking the signature as obsolete. 如請求項63之非揮發性記憶體系統，其中該搜尋陣列具有一區塊結構，該非揮發性記憶體系統對該搜尋陣列中之該等簽章執行記憶體回收操作，一記憶體回收操作包含：針對一或多個區塊，將未被標記為過時之該等簽章複製至揮發性記憶體中；及將未被標記為過時之該等簽章重寫至該搜尋陣列之一不同區塊中。 The non-volatile memory system of claim 63, wherein the search array has a block structure, the non-volatile memory system performs a memory reclamation operation on the signatures in the search array, and a memory reclamation operation includes : copying the signatures that are not marked as obsolete to the volatile memory for one or more of the blocks; and rewriting the signatures that are not marked as obsolete to one of the different regions of the search array In the block. 如請求項65之非揮發性記憶體系統，其中該記憶體回收操作進一步包含：將一或多個額外簽章添加至寫入該不同區塊中之該簽章。 The non-volatile memory system of claim 65, wherein the memory reclamation operation further comprises: adding one or more additional signatures to the signature written in the different block. 如請求項36之非揮發性記憶體系統，其中該等第一資料集為一固定大小。 The non-volatile memory system of claim 36, wherein the first data set is a fixed size. 如請求項36之非揮發性記憶體系統，其中該等第一資料集為一可變大小。 The non-volatile memory system of claim 36, wherein the first data set is a variable size. 如請求項36之非揮發性記憶體系統，其中使用相對於標準值偏移達正邊際之該等字線之讀取電壓執行該加偏壓。 The non-volatile memory system of claim 36, wherein the biasing is performed using a read voltage of the word lines offset to a positive margin relative to a standard value. 如請求項36之非揮發性記憶體系統，其中回應於判定該搜尋陣列之一位元線回應於該等字線之偏壓而傳導，判定該第一簽章 所對應之一第一資料集是否與對應於傳導之該位元線之該資料集相同。 The non-volatile memory system of claim 36, wherein the first signature is determined in response to determining that a bit line of the search array is transmitted in response to a bias voltage of the word lines Corresponding to one of the first data sets is the same as the data set corresponding to the bit line of the conduction.