TW201430853A - Non-volatile memory storage apparatus, memory controller and data storage method - Google Patents
Non-volatile memory storage apparatus, memory controller and data storage method Download PDFInfo
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本發明是有關於一種非揮發性記憶體儲存裝置、記憶體控制器與資料儲存方法,且特別是有關於一種能夠在非揮發性記憶體儲存裝置斷電時將緩衝記憶體中之資料寫入至非揮發性記憶體模組的非揮發性記憶體儲存裝置、記憶體控制器與資料儲存方法。 The present invention relates to a non-volatile memory storage device, a memory controller and a data storage method, and more particularly to a method for writing data in a buffer memory when a non-volatile memory storage device is powered off. Non-volatile memory storage device, memory controller and data storage method to non-volatile memory modules.
數位相機、手機與MP3在這幾年來的成長十分迅速,使得消費者對儲存媒體的需求也急速增加。由於非揮發性記憶體具有資料非揮發性、省電、體積小與無機械結構等的特性,適合可攜式應用,最適合使用於這類可攜式由電池供電的產品上。隨身碟就是一種以NAND快閃記憶體(Flash Memory)作為儲存媒體的儲存裝置。例如,透過通用序列匯流排(Universal Serial Bus,USB),使用者輕易地將隨身碟插拔於主機,以進行數位資料的傳遞。 Digital cameras, mobile phones and MP3s have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Because non-volatile memory has the characteristics of non-volatile data, power saving, small size and no mechanical structure, it is suitable for portable applications and is most suitable for use in such portable battery-powered products. A flash drive is a storage device that uses NAND flash memory as a storage medium. For example, through the Universal Serial Bus (USB), the user can easily plug and drop the USB flash drive to the host to transfer digital data.
由於寫入資料至快閃記憶體的速度遠低於與主機連接之USB的傳輸速度,因此,一般來說,緩衝記憶體會被配置在非揮發性記憶體儲存裝置中,以暫存來自於主機的資料。特別是,當主機下達寫入指令與欲寫入的資料給非揮發性記憶體儲存裝置時,記憶體控制電路(亦稱為記憶體控制器)會在將資料暫存於緩衝記憶體後即將指示已完成寫入指令的訊息回覆給主機,以使主機能夠繼續執行下一個運作,由此提升運作效率。 Since the speed of writing data to the flash memory is much lower than the speed of the USB connected to the host, in general, the buffer memory is configured in the non-volatile memory storage device to temporarily store the memory from the host. data of. In particular, when the host issues a write command and a data to be written to the non-volatile memory storage device, the memory control circuit (also referred to as a memory controller) will temporarily store the data in the buffer memory. A message indicating that the write command has been completed is replied to the host, so that the host can continue to perform the next operation, thereby improving operational efficiency.
然而,由於隨身碟是透過USB操作於主機所提供的電源,因此,倘若在緩衝記憶體中仍存有資料的情況下使用者將隨身碟從主機中拔除時,暫存於緩衝記憶體中的資料將會遺失。基此,如何在非揮發性記憶體儲存裝置斷電時將暫存於緩衝記憶體中的資料寫入至快閃記憶體中,是此領域技術人員所致力的課題。 However, since the flash drive is operated by the host computer through the USB power supply, if the user removes the flash drive from the host computer while still storing data in the buffer memory, it is temporarily stored in the buffer memory. The information will be lost. Therefore, how to write the data temporarily stored in the buffer memory to the flash memory when the non-volatile memory storage device is powered off is a problem that a person skilled in the art is working on.
本發明提供一種記憶體儲存系統、記憶體控制器與資料儲存方法,其能夠在斷電時將暫存於緩衝記憶體中的資料寫入至非揮發性記憶體模組中。 The invention provides a memory storage system, a memory controller and a data storage method, which can write data temporarily stored in a buffer memory to a non-volatile memory module when the power is off.
本發明範例實施例提出一種非揮發性記憶體儲存裝置,其包括連接器、儲能電路、電源轉換與供應電路、非揮發性記憶體模組、記憶體控制器與緩衝記憶體。連接器用以耦接至主機系統。儲能電路用以接收輸入電壓並且提供輸出電壓。電源轉換與供應電路耦接儲能電路並且用以將輸出電壓轉換成第一電壓與第 二電壓。非揮發性記憶體模組耦接電源轉換與供應電路並且操作於第一電壓。記憶體控制器耦接連接器、儲能電路與電源轉換與供應電路並且操作於第二電壓。緩衝記憶體用以暫存資料。記憶體控制器用以在接收到訊號時將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組,其中此訊號為用以指示上述輸入電壓在一段預設時間內持續小於預設電壓的偵測訊號或為用以指示連接器的非作動狀態的偵測訊號或為從主機系統中所接收的暫停模式訊號、暖重置訊號或熱重置訊號。 Exemplary embodiments of the present invention provide a non-volatile memory storage device including a connector, a storage circuit, a power conversion and supply circuit, a non-volatile memory module, a memory controller, and a buffer memory. The connector is for coupling to the host system. The tank circuit is configured to receive an input voltage and provide an output voltage. The power conversion and supply circuit is coupled to the energy storage circuit and is configured to convert the output voltage into the first voltage and the Two voltages. The non-volatile memory module is coupled to the power conversion and supply circuit and operates at the first voltage. The memory controller is coupled to the connector, the tank circuit and the power conversion and supply circuit and operates at the second voltage. Buffer memory is used to temporarily store data. The memory controller is configured to write the data temporarily stored in the buffer memory to the non-volatile memory module when the signal is received, wherein the signal is used to indicate that the input voltage continues to be less than a preset time for a preset period of time. The voltage detection signal is a detection signal for indicating the non-actuated state of the connector or a pause mode signal, a warm reset signal or a hot reset signal received from the host system.
在本發明之一實施例中,上述之儲能電路包括二極體、第一電阻、第二電阻、開關與電容組。二極體具有陽極與陰極,陽極用以接收上述輸入電壓,陰極用以提供上述輸出電壓。第一電阻的第一端耦接至二極體的陰極並且第二電阻的第一端耦接至二極體的陰極。開關的第一端耦接至第二電阻的第二端並且開關的控制端耦接至記憶體控制器。電容組的第一端耦接至第一電阻的第二端與開關的第二端並且電容組的第二端耦接至接地端。 In an embodiment of the invention, the energy storage circuit includes a diode, a first resistor, a second resistor, a switch and a capacitor group. The diode has an anode and a cathode, the anode is for receiving the input voltage, and the cathode is for providing the output voltage. The first end of the first resistor is coupled to the cathode of the diode and the first end of the second resistor is coupled to the cathode of the diode. The first end of the switch is coupled to the second end of the second resistor and the control end of the switch is coupled to the memory controller. The first end of the capacitor group is coupled to the second end of the first resistor and the second end of the switch, and the second end of the capacitor group is coupled to the ground.
在本發明之一實施例中,上述之記憶體控制器更用以在被致能後第一次接收到來自於主機系統的小型電腦標準界面(Small Computer Standard Interface,SCSI)指令時,開啟(turn on)上述開關。 In an embodiment of the invention, the memory controller is further configured to be turned on when the Small Computer Standard Interface (SCSI) command from the host system is received for the first time after being enabled ( Turn on) The above switch.
在本發明之一實施例中,上述之記憶體控制器更用以在被致能後第一次接收到來自於主機系統的寫入指令時,開啟上述開關。 In an embodiment of the invention, the memory controller is further configured to turn on the switch when receiving a write command from the host system for the first time after being enabled.
在本發明之一實施例中,上述之記憶體控制器更用以在被致能且等待一延遲時間之後,開啟上述開關。 In an embodiment of the invention, the memory controller is further configured to turn on the switch after being enabled and waiting for a delay time.
在本發明之一實施例中,上述之非揮發性記憶體模組包括多個實體區塊並且此些實體區塊至少被分組為一資料區與一備用區,其中上述之記憶體控制器在接收到訊號時從備用區中提取一實體區塊並且將暫存於緩衝記憶體中的資料寫入至此實體區塊中。 In an embodiment of the present invention, the non-volatile memory module includes a plurality of physical blocks and the physical blocks are at least grouped into a data area and a spare area, wherein the memory controller is When receiving the signal, a physical block is extracted from the spare area and the data temporarily stored in the buffer memory is written into the physical block.
在本發明之一實施例中,上述之記憶體控制器在接收到該訊號時僅使用從備用區中所提取的實體區塊的實體頁面之中屬於下頁面的實體頁面來寫入暫存於緩衝記憶體中的資料。 In an embodiment of the present invention, when the memory controller receives the signal, only the physical page belonging to the next page among the physical pages of the physical block extracted from the spare area is used to write the temporary storage. Buffer data in memory.
在本發明之一實施例中,上述之記憶體控制器更用以在接收到訊號時在實體區塊的冗餘位元區中記錄對應所寫入之資料的映射資訊。 In an embodiment of the invention, the memory controller is further configured to record mapping information corresponding to the written data in the redundant bit area of the physical block when the signal is received.
在本發明之一實施例中,上述之記憶體控制器更用以在接收到訊號時從備用區中提取另一實體區塊並且在所提取的另一實體區塊中記錄對應所寫入之資料的映射資訊。 In an embodiment of the present invention, the memory controller is further configured to extract another physical block from the spare area when the signal is received, and record the corresponding written in the extracted another physical block. Mapping information of the data.
在本發明之一實施例中,上述之非揮發性記憶體儲存裝置更包括存取指示燈,其中上述之記憶體控制器更用以在接收到訊號時關閉此存取指示燈。 In an embodiment of the invention, the non-volatile memory storage device further includes an access indicator, wherein the memory controller is further configured to turn off the access indicator when receiving the signal.
本發明範例實施例提出一種記憶體控制器,其包括主機介面、記憶體介面、記憶體管理電路與緩衝記憶體。主機介面用以耦接至主機系統。記憶體介面用以耦接至非揮發性記憶體模 組。記憶體管理電路耦接主機介面與記憶體介面。緩衝記憶體耦接記憶體管理電路並且用以暫存來自於主機系統的資料。記憶體管理電路用以在接收到訊號時將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組。此外,其中記憶體管理電路更用以開啟包括在儲能電路中的開關。 An exemplary embodiment of the present invention provides a memory controller including a host interface, a memory interface, a memory management circuit, and a buffer memory. The host interface is coupled to the host system. The memory interface is coupled to the non-volatile memory model group. The memory management circuit is coupled to the host interface and the memory interface. The buffer memory is coupled to the memory management circuit and is used to temporarily store data from the host system. The memory management circuit is configured to write the data temporarily stored in the buffer memory to the non-volatile memory module when the signal is received. In addition, the memory management circuit is further configured to turn on a switch included in the energy storage circuit.
在本發明之一實施例中,上述之記憶體管理電路更用以在被致能後第一次接收到來自於主機系統的寫入指令時,開啟上述開關。 In an embodiment of the invention, the memory management circuit is further configured to turn on the switch when receiving a write command from the host system for the first time after being enabled.
在本發明之一實施例中,上述之記憶體管理電路更用以在被致能且等待一延遲時間之後,開啟上述開關。 In an embodiment of the invention, the memory management circuit is further configured to turn on the switch after being enabled and waiting for a delay time.
在本發明之一實施例中,上述之非揮發性記憶體模組包括多個實體區塊並且此些實體區塊至少被分組為一資料區與一備用區,其中上述之記憶體管理電路在接收到訊號時從備用區中提取一實體區塊並且將暫存於緩衝記憶體中的資料寫入至此實體區塊中。 In an embodiment of the present invention, the non-volatile memory module includes a plurality of physical blocks and the physical blocks are at least grouped into a data area and a spare area, wherein the memory management circuit is When receiving the signal, a physical block is extracted from the spare area and the data temporarily stored in the buffer memory is written into the physical block.
在本發明之一實施例中,上述之記憶體管理電路在接收到該訊號時僅使用從備用區中所提取的實體區塊的實體頁面之中屬於下頁面的實體頁面來寫入暫存於緩衝記憶體中的資料。 In an embodiment of the present invention, when the memory management circuit receives the signal, only the physical page belonging to the next page among the physical pages of the physical block extracted from the spare area is used to write the temporary storage. Buffer data in memory.
在本發明之一實施例中,上述之記憶體管理電路更用以在接收到訊號時在實體區塊的冗餘位元區中記錄對應所寫入之資料的映射資訊。 In an embodiment of the invention, the memory management circuit is further configured to record mapping information corresponding to the written data in the redundant bit area of the physical block when the signal is received.
在本發明之一實施例中,上述之記憶體管理電路更用以 在接收到訊號時從備用區中提取另一實體區塊並且在所提取的另一實體區塊中記錄對應所寫入之資料的映射資訊。 In an embodiment of the invention, the memory management circuit is further used to Another physical block is extracted from the spare area when the signal is received and the mapping information corresponding to the written data is recorded in the extracted another physical block.
在本發明之一實施例中,上述之記憶體管理電路更包括存取指示燈,其中上述之記憶體控制器更用以在接收到訊號時關閉此存取指示燈。 In an embodiment of the invention, the memory management circuit further includes an access indicator, wherein the memory controller is further configured to turn off the access indicator when the signal is received.
本發明範例實施例提出一種資料儲存方法,用於一非揮發性記憶體模組中。此資料儲存方法包括判斷來自於主機系統的輸入電壓是否在預設時間內持續小於預設電壓;以及當來自於主機系統的輸入電壓在預設時間內持續小於預設電壓時,將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組。 An exemplary embodiment of the present invention provides a data storage method for use in a non-volatile memory module. The data storage method includes determining whether an input voltage from the host system continues to be less than a preset voltage within a preset time; and when the input voltage from the host system continues to be less than a preset voltage for a preset time, the buffer is temporarily buffered. The data in the memory is written to the non-volatile memory module.
在本發明之一實施例中,上述之將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組的步驟包括:從備用區中提取實體區塊;以及將暫存於緩衝記憶體中的資料寫入至實體區塊中。 In an embodiment of the present invention, the step of writing the data temporarily stored in the buffer memory to the non-volatile memory module includes: extracting the physical block from the spare area; and temporarily storing the data in the buffer memory The data in the volume is written to the physical block.
在本發明之一實施例中,上述之實體區塊分別地包括多個下頁面與多個上頁面並且寫入資料至此些下頁面的速度快於寫入資料至此些上頁面的速度。 In an embodiment of the present invention, the physical block includes a plurality of lower pages and a plurality of upper pages, respectively, and the data is written to the lower pages faster than the data is written to the upper pages.
在本發明之一實施例中,其中每一實體區塊包括多個實體頁面並且此些實體頁面分別地屬於下頁面與上頁面並且寫入資料至屬於下頁面之實體頁面的速度快於寫入資料至屬於上頁面之實體頁面的速度。並且,上述之將暫存於緩衝記憶體中的資料寫入至實體區塊中的步驟包括:僅使用從備用區中所提取的實體區塊的實體頁面之中屬於的下頁面的實體頁面來寫入暫存於緩衝記 憶體中的資料。 In an embodiment of the present invention, each physical block includes a plurality of physical pages and the physical pages belong to the lower page and the upper page, respectively, and the data is written to the physical page belonging to the lower page faster than writing. The speed of the data to the physical page belonging to the previous page. Moreover, the step of writing the data temporarily stored in the buffer memory into the physical block includes: using only the entity page of the next page belonging to the physical page of the physical block extracted from the spare area. Write temporarily stored in the buffer Recall the information in the body.
在本發明之一實施例中,上述之將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組的步驟更包括:在實體區塊的冗餘位元區中記錄對應所寫入之資料的映射資訊。 In an embodiment of the present invention, the step of writing the data temporarily stored in the buffer memory to the non-volatile memory module further includes: recording corresponding writes in the redundant bit area of the physical block Mapping information of incoming data.
在本發明之一實施例中,上述之將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組的步驟更包括:從備用區中提取另一實體區塊並且在所提取的另一實體區塊中記錄對應所寫入資料的映射資訊。 In an embodiment of the invention, the step of writing the data temporarily stored in the buffer memory to the non-volatile memory module further comprises: extracting another physical block from the spare area and extracting the The mapping information corresponding to the written data is recorded in another physical block.
在本發明之一實施例中,上述之將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組的步驟更包括:關閉存取指示燈。 In an embodiment of the invention, the step of writing the data temporarily stored in the buffer memory to the non-volatile memory module further comprises: turning off the access indicator.
本發明範例實施例提出一種資料儲存方法,用於一非揮發性記憶體模組中。此資料儲存方法包括:判斷是否偵測到連接器的非作動狀態;以及當偵測到連接器的非作動狀態時,將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組。 An exemplary embodiment of the present invention provides a data storage method for use in a non-volatile memory module. The data storage method includes: determining whether the non-actuated state of the connector is detected; and writing the data temporarily stored in the buffer memory to the non-volatile memory module when the non-actuated state of the connector is detected; .
本發明範例實施例提出一種資料儲存方法,用於一非揮發性記憶體模組中。此資料儲存方法包括:判斷是否從主機系統中接收到暫停模式訊號、暖重置訊號或熱重置訊號;以及當從主機系統中接收到暫停模式訊號、暖重置訊號或熱重置訊號時,將暫存在緩衝記憶體中的資料寫入至非揮發性記憶體模組。 An exemplary embodiment of the present invention provides a data storage method for use in a non-volatile memory module. The data storage method includes: determining whether a pause mode signal, a warm reset signal or a hot reset signal is received from the host system; and when receiving a pause mode signal, a warm reset signal or a warm reset signal from the host system Write data temporarily stored in the buffer memory to the non-volatile memory module.
基於上述,本發明範例實施例的記憶體儲存系統、記憶體控制器與資料儲存方法能夠在非揮發性記憶體儲存裝置斷電時 將暫存於緩衝記憶體中的資料寫入至快閃記憶體中。 Based on the above, the memory storage system, the memory controller, and the data storage method of the exemplary embodiments of the present invention can be used when the non-volatile memory storage device is powered off. Write data temporarily stored in the buffer memory to the flash memory.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
1000‧‧‧主機系統 1000‧‧‧Host system
1100‧‧‧電腦 1100‧‧‧ computer
1102‧‧‧微處理器 1102‧‧‧Microprocessor
1104‧‧‧隨機存取記憶體 1104‧‧‧ Random access memory
1106‧‧‧輸入/輸出裝置 1106‧‧‧Input/output devices
1108‧‧‧系統匯流排 1108‧‧‧System Bus
1110‧‧‧資料傳輸介面 1110‧‧‧Data transmission interface
1202‧‧‧滑鼠 1202‧‧‧ Mouse
1204‧‧‧鍵盤 1204‧‧‧ keyboard
1206‧‧‧顯示器 1206‧‧‧ display
1208‧‧‧印表機 1208‧‧‧Printer
1212‧‧‧隨身碟 1212‧‧‧USB flash drive
1214‧‧‧記憶卡 1214‧‧‧ memory card
1216‧‧‧固態硬碟 1216‧‧‧ Solid State Drive
1310‧‧‧數位相機 1310‧‧‧ digital camera
1312‧‧‧SD卡 1312‧‧‧SD card
1314‧‧‧MMC卡 1314‧‧‧MMC card
1316‧‧‧記憶棒 1316‧‧‧ Memory Stick
1318‧‧‧CF卡 1318‧‧‧CF card
1320‧‧‧嵌入式儲存裝置 1320‧‧‧Embedded storage device
100‧‧‧非揮發性記憶體儲存裝置 100‧‧‧Non-volatile memory storage device
102‧‧‧連接器 102‧‧‧Connector
104‧‧‧記憶體控制器 104‧‧‧ memory controller
106‧‧‧非揮發性記憶體模組 106‧‧‧Non-volatile memory module
108‧‧‧儲能電路 108‧‧‧ Energy storage circuit
110‧‧‧電源轉換與供應電路 110‧‧‧Power conversion and supply circuit
202‧‧‧記憶體管理電路 202‧‧‧Memory Management Circuit
204‧‧‧主機介面 204‧‧‧Host interface
206‧‧‧記憶體介面 206‧‧‧ memory interface
208‧‧‧緩衝記憶體 208‧‧‧buffer memory
210‧‧‧錯誤檢查與校正電路 210‧‧‧Error checking and correction circuit
304(0)~304(R)‧‧‧實體區塊 304(0)~304(R)‧‧‧ physical block
402‧‧‧資料區 402‧‧‧Information area
404‧‧‧備用區 404‧‧‧ spare area
406‧‧‧系統區 406‧‧‧System Area
408‧‧‧取代區 408‧‧‧Replaced area
510(0)~510(H)‧‧‧邏輯區塊 510(0)~510(H)‧‧‧ logical block
Vin‧‧‧輸入電壓 Vin‧‧‧Input voltage
Vout‧‧‧輸出電壓 Vout‧‧‧ output voltage
D‧‧‧二極體 D‧‧‧ diode
R1‧‧‧第一電阻 R1‧‧‧first resistance
R2‧‧‧第二電阻 R2‧‧‧second resistance
S‧‧‧開關 S‧‧ switch
C‧‧‧電容組 C‧‧‧capacitor group
GND‧‧‧接地端 GND‧‧‧ ground terminal
圖1A是根據本發明範例實施例繪示的主機系統與非揮發性記憶體儲存裝置。 FIG. 1A illustrates a host system and a non-volatile memory storage device according to an exemplary embodiment of the invention.
圖1B是根據本發明範例實施例所繪示的電腦、輸入/輸出裝置與非揮發性記憶體儲存裝置的示意圖。 FIG. 1B is a schematic diagram of a computer, an input/output device, and a non-volatile memory storage device according to an exemplary embodiment of the invention.
圖1C是根據本發明另一範例實施例所繪示的主機系統與非揮發性記憶體儲存裝置的示意圖。 FIG. 1C is a schematic diagram of a host system and a non-volatile memory storage device according to another exemplary embodiment of the invention.
圖2是繪示圖1A所示的非揮發性記憶體儲存裝置的概要方塊圖。 FIG. 2 is a schematic block diagram showing the non-volatile memory storage device shown in FIG. 1A.
圖3是根據本發明範例實施例所繪示的記憶體控制器的概要方塊圖。 FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.
圖4與圖5是根據本發明範例實施例所繪示之管理記憶體模組的範例示意圖。 4 and FIG. 5 are schematic diagrams showing an example of a management memory module according to an exemplary embodiment of the invention.
圖6~圖8是根據本發明範例實施例所繪示的寫入資料至非揮發性記憶體模組的範例。 6-8 are examples of writing data to a non-volatile memory module according to an exemplary embodiment of the invention.
圖9是根據本發明範例實施例所繪示的儲能電路的示意圖。 FIG. 9 is a schematic diagram of an energy storage circuit according to an exemplary embodiment of the invention.
圖10是根據本發明範例實施例所繪示的資料儲存方法的流 程圖。 FIG. 10 is a flow of a data storage method according to an exemplary embodiment of the present invention. Cheng Tu.
圖11是根據本發明另一範例實施例所繪示的資料儲存方法的流程圖。 FIG. 11 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.
圖12是根據本發明另一範例實施例所繪示的資料儲存方法的流程圖。 FIG. 12 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.
一般而言,非揮發性記憶體儲存裝置(亦稱,非揮發性記憶體儲存系統)包括非揮發性記憶體模組與記憶體控制器(亦稱,記憶體控制電路)。通常非揮發性記憶體儲存裝置是與主機系統一起使用,以使主機系統可將資料寫入至非揮發性記憶體儲存裝置或從非揮發性記憶體儲存裝置中讀取資料。 In general, a non-volatile memory storage device (also referred to as a non-volatile memory storage system) includes a non-volatile memory module and a memory controller (also referred to as a memory control circuit). Typically, non-volatile memory storage devices are used with host systems to enable the host system to write data to or read data from non-volatile memory storage devices.
圖1A是根據本發明範例實施例所繪示之主機系統與非揮發性記憶體儲存裝置。 FIG. 1A illustrates a host system and a non-volatile memory storage device according to an exemplary embodiment of the invention.
請參照圖1A,主機系統1000一般包括電腦1100與輸入/輸出(input/output,I/O)裝置1106。電腦1100包括微處理器1102、隨機存取記憶體(random access memory,RAM)1104、系統匯流排1108與資料傳輸介面1110。輸入/輸出裝置1106包括如圖1B的滑鼠1202、鍵盤1204、顯示器1206與印表機1208。必須瞭解的是,圖1B所示的裝置非限制輸入/輸出裝置1106,輸入/輸出裝置1106可更包括其他裝置。 Referring to FIG. 1A, the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106. The computer 1100 includes a microprocessor 1102, a random access memory (RAM) 1104, a system bus 1108, and a data transmission interface 1110. The input/output device 1106 includes a mouse 1202, a keyboard 1204, a display 1206, and a printer 1208 as in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the input/output device 1106, and the input/output device 1106 may further include other devices.
在本發明實施例中,非揮發性記憶體儲存裝置100是透 過資料傳輸介面1110與主機系統1000的其他元件耦接。藉由微處理器1102、隨機存取記憶體1104與輸入/輸出裝置1106的運作可將資料寫入至非揮發性記憶體儲存裝置100或從非揮發性記憶體儲存裝置100中讀取資料。例如,非揮發性記憶體儲存裝置100可以是如圖1B所示的隨身碟1212、記憶卡1214或固態硬碟(Solid State Drive,SSD)1216等的非揮發性記憶體儲存裝置。 In the embodiment of the present invention, the non-volatile memory storage device 100 is transparent. The data transmission interface 1110 is coupled to other components of the host system 1000. The data can be written to or read from the non-volatile memory storage device 100 by the operation of the microprocessor 1102, the random access memory 1104, and the input/output device 1106. For example, the non-volatile memory storage device 100 may be a non-volatile memory storage device such as a flash drive 1212, a memory card 1214, or a solid state drive (SSD) 1216 as shown in FIG. 1B.
一般而言,主機系統1000可實質地為可儲存資料的任意系統。雖然在本範例實施例中,主機系統1000是以電腦系統來作說明,然而,在本發明另一範例實施例中主機系統1000可以是數位相機、攝影機、通信裝置、音訊播放器或視訊播放器等系統。例如,在主機系統為數位相機(攝影機)1310時,非揮發性記憶體儲存裝置100則為其所使用的SD卡1312、MMC卡1314、記憶棒(memory stick)1316、CF卡1318或嵌入式儲存裝置1320(如圖1C所示)。嵌入式儲存裝置1320包括嵌入式多媒體卡(Embedded MMC,eMMC)。值得一提的是,嵌入式多媒體卡是直接耦接於主機系統的基板上。 In general, host system 1000 can be substantially any system that can store data. Although in the present exemplary embodiment, the host system 1000 is illustrated by a computer system, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, a video camera, a communication device, an audio player, or a video player. And other systems. For example, when the host system is a digital camera (camera) 1310, the non-volatile memory storage device 100 is used for its SD card 1312, MMC card 1314, memory stick 1316, CF card 1318 or embedded. Storage device 1320 (shown in Figure 1C). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system.
圖2是繪示圖1A所示的非揮發性記憶體儲存裝置的概要方塊圖。 FIG. 2 is a schematic block diagram showing the non-volatile memory storage device shown in FIG. 1A.
請參照圖2,非揮發性記憶體儲存裝置100包括連接器102、記憶體控制器104、非揮發性記憶體模組106、儲能電路108以及電源轉換與供應電路110。 Referring to FIG. 2, the non-volatile memory storage device 100 includes a connector 102, a memory controller 104, a non-volatile memory module 106, a tank circuit 108, and a power conversion and supply circuit 110.
連接器102耦接至記憶體控制器104,並且用以耦接至主 機系統1000。也就是說,非揮發性記憶體儲存裝置100是透過連接器102與主機系統1000上的對應連接埠相連。 The connector 102 is coupled to the memory controller 104 and coupled to the main Machine system 1000. That is, the non-volatile memory storage device 100 is connected to the corresponding port on the host system 1000 through the connector 102.
在本範例實施例中,連接器102為通用序列匯流排(Universal Serial Bus,USB)連接器。然而,必須瞭解的是,本發明不限於此,在本發明另一範例實施例中,連接器102亦可以是電氣和電子工程師協會(Institute of Electrical and Electronic Engineers,IEEE)1394連接器、高速周邊零件連接介面(Peripheral Component Interconnect Express,PCI Express)連接器、序列先進附件(Serial Advanced Technology Attachment,SATA)連接器、安全數位(Secure Digital,SD)介面連接器、記憶棒(Memory Stick,MS)介面連接器、多媒體儲存卡(Multi Media Card,MMC)介面連接器、小型快閃(Compact Flash,CF)介面連接器、整合式驅動電子介面(Integrated Device Electronics,IDE)連接器或其他適合的連接器。 In the present exemplary embodiment, the connector 102 is a Universal Serial Bus (USB) connector. However, it should be understood that the present invention is not limited thereto. In another exemplary embodiment of the present invention, the connector 102 may also be an Institute of Electrical and Electronic Engineers (IEEE) 1394 connector, a high-speed peripheral. Peripheral Component Interconnect Express (PCI Express) connector, Serial Advanced Technology Attachment (SATA) connector, Secure Digital (SD) interface connector, Memory Stick (MS) interface Connector, Multi Media Card (MMC) interface connector, Compact Flash (CF) interface connector, Integrated Device Electronics (IDE) connector or other suitable connector .
記憶體控制器104用以執行以硬體型式或韌體型式實作的多個邏輯閘或控制指令,並且根據主機系統1000的指令在非揮發性記憶體模組106中進行資料的寫入、讀取與抹除等運作。特別是,記憶體控制器104會執行本範例實施例的資料儲存方法與記憶體管理方法來對非揮發性記憶體模組106中進行資料的寫入、讀取、抹除以及區塊管理等運作。根據本發明範例實施例的資料儲存方法與記憶體管理方法將於以下配合圖式作詳細說明。 The memory controller 104 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type, and write data in the non-volatile memory module 106 according to an instruction of the host system 1000. Read and erase operations. In particular, the memory controller 104 performs the data storage method and the memory management method of the present exemplary embodiment to write, read, erase, and manage the data in the non-volatile memory module 106. Operation. The data storage method and the memory management method according to an exemplary embodiment of the present invention will be described in detail below with reference to the drawings.
非揮發性記憶體模組106是耦接至記憶體控制器104,並 且用以儲存主機系統1000所寫入之資料。非揮發性記憶體模組106包括多個實體區塊。各實體區塊分別具有複數個頁面,其中屬於於同一個實體區塊之實體頁面可被獨立地寫入且被同時地抹除。更詳細來說,實體區塊為抹除之最小單位。亦即,每一實體區塊含有最小數目之一併被抹除之記憶胞。實體頁面為程式化的最小單元。即,實體頁面為寫入資料的最小單元。每一實體頁面通常包括資料位元區與冗餘位元區。資料位元區用以儲存使用者的資料,而冗餘位元區用以儲存系統的資料(例如,錯誤檢查與校正碼)。資料位元區與冗餘位元區的配置為此領域技術人員所知的一般知識,在此不詳細描述。在本範例實施中,非揮發性記憶體模組106為多層記憶胞(Multi Level Cell,MLC)NAND快閃記憶體模組。然而,本發明不限於此,非揮發性記憶體模組106亦可是單層記憶胞(Single Level Cell,SLC)NAND快閃記憶體模組、其他快閃記憶體模組或其他具有相同特性的記憶體模組。 The non-volatile memory module 106 is coupled to the memory controller 104, and And used to store the data written by the host system 1000. The non-volatile memory module 106 includes a plurality of physical blocks. Each physical block has a plurality of pages, respectively, wherein physical pages belonging to the same physical block can be independently written and erased simultaneously. In more detail, the physical block is the smallest unit of erasure. That is, each physical block contains one of the smallest number of erased memory cells. The entity page is the smallest unit that is stylized. That is, the physical page is the smallest unit for writing data. Each physical page typically includes a data bit area and a redundant bit area. The data bit area is used to store the user's data, and the redundant bit area is used to store system data (eg, error checking and correction codes). The configuration of the data bit area and the redundant bit area is a general knowledge known to those skilled in the art and will not be described in detail herein. In this example implementation, the non-volatile memory module 106 is a multi-level cell (MLC) NAND flash memory module. However, the present invention is not limited thereto, and the non-volatile memory module 106 may also be a single level cell (SLC) NAND flash memory module, other flash memory modules, or other components having the same characteristics. Memory module.
儲能電路108耦接至記憶體控制器104。在本範例實施例中,非揮發性記憶體儲存裝置100運作所需之電源是透過連接器102由主機系統1000所提供。在此,儲能電路108用以透過連接器102從主機系統1000中接收輸入電壓並且提供輸出電壓,以供應給非揮發性記憶體儲存裝置100的記憶體控制器104與非揮發性記憶體模組106。特別是,在本範例實施例中,儲能電路108更用以儲存一備用電能,並且當主機系統1000中斷供電時,儲能電路108會提供此備用電能作為輸出電壓,以供應給記憶體控制 器104與非揮發性記憶體模組106作為短暫運作之用。 The tank circuit 108 is coupled to the memory controller 104. In the present exemplary embodiment, the power required for the operation of the non-volatile memory storage device 100 is provided by the host system 1000 through the connector 102. Here, the tank circuit 108 is configured to receive an input voltage from the host system 1000 through the connector 102 and provide an output voltage for supply to the memory controller 104 of the non-volatile memory storage device 100 and the non-volatile memory model. Group 106. In particular, in the present exemplary embodiment, the energy storage circuit 108 is further configured to store a backup power, and when the host system 1000 interrupts the power supply, the energy storage circuit 108 provides the backup power as an output voltage for supply to the memory control. The device 104 and the non-volatile memory module 106 serve as a short-term operation.
電源轉換與供應電路110耦接至儲能電路108並且用以控制非揮發性記憶體儲存裝置100的電源。具體來說,電源轉換與供應電路110會將所接收到的電壓(即,儲能電路108所提供的輸出電壓)轉換為第一電壓與第二電壓,將第一電壓提供給非揮發性記憶體模組106,並且將第二電壓提供給記憶體控制器104。 The power conversion and supply circuit 110 is coupled to the energy storage circuit 108 and is used to control the power of the non-volatile memory storage device 100. Specifically, the power conversion and supply circuit 110 converts the received voltage (ie, the output voltage provided by the tank circuit 108) into a first voltage and a second voltage, and supplies the first voltage to the non-volatile memory. The body module 106 and provides a second voltage to the memory controller 104.
圖3是根據本發明範例實施例所繪示的記憶體控制器的概要方塊圖。 FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.
請參照圖3,記憶體控制器104包括記憶體管理電路202、主機介面204、記憶體介面206與緩衝記憶體208。 Referring to FIG. 3, the memory controller 104 includes a memory management circuit 202, a host interface 204, a memory interface 206, and a buffer memory 208.
記憶體管理電路202用以控制記憶體控制器104的整體運作,以進行資料的寫入、讀取、抹除等運作。例如,記憶體管理電路202具有多個控制指令,並且在可攜式非揮發性記憶體儲存裝置100運作時,此些控制指令會被執行以根據本範例實施例的資料儲存方法與記憶體管理方法。 The memory management circuit 202 is configured to control the overall operation of the memory controller 104 to perform operations such as writing, reading, and erasing data. For example, the memory management circuit 202 has a plurality of control commands, and when the portable non-volatile memory storage device 100 operates, such control commands are executed to perform data storage method and memory management according to the present exemplary embodiment. method.
例如,在本範例實施例中,記憶體管理電路202的控制指令是以韌體型式來實作。例如,記憶體管理電路202具有微處理器單元(未繪示)與唯讀記憶體(未繪示),並且此些控制指令是被燒錄至此唯讀記憶體中。當可攜式非揮發性記憶體儲存裝置100運作時,此些控制指令會由微處理器單元來執行以完成根據本發明實施例的資料儲存方法與記憶體管理方法。 For example, in the present exemplary embodiment, the control instructions of the memory management circuit 202 are implemented in a firmware version. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and such control instructions are programmed into the read-only memory. When the portable non-volatile memory storage device 100 operates, such control commands are executed by the microprocessor unit to complete the data storage method and the memory management method according to the embodiments of the present invention.
在本發明另一範例實施例中,記憶體管理電路202的控 制指令亦可以程式碼型式儲存於非揮發性記憶體模組106的特定區域(例如,記憶體模組中專用於存放系統資料的系統區)中。此外,記憶體管理電路202具有微處理器單元(未繪示)、唯讀記憶體(未繪示)及隨機存取記憶體(未繪示)。特別是,此唯讀記憶體具有驅動碼段,並且當記憶體控制器104被致能時,微處理器單元會先執行此驅動碼段來將儲存於非揮發性記憶體模組106中之控制指令載入至記憶體管理電路202的隨機存取記憶體中。之後,微處理器單元會運轉此些控制指令以執行本發明範例實施例的資料儲存方法與記憶體管理方法。此外,在本發明另一範例實施例中,記憶體管理電路202的控制指令亦可以一硬體型式來實作。 In another exemplary embodiment of the present invention, the memory management circuit 202 controls The programming instructions may also be stored in a particular area of the non-volatile memory module 106 (eg, a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a drive code segment, and when the memory controller 104 is enabled, the microprocessor unit first executes the drive code segment to be stored in the non-volatile memory module 106. The control command is loaded into the random access memory of the memory management circuit 202. Thereafter, the microprocessor unit operates the control commands to perform the data storage method and the memory management method of the exemplary embodiments of the present invention. In addition, in another exemplary embodiment of the present invention, the control command of the memory management circuit 202 can also be implemented in a hardware format.
主機介面204是耦接至記憶體管理電路202並且用以接收與識別主機系統1000所傳送的指令與資料。也就是說,主機系統1000所傳送的指令與資料會透過主機介面204來傳送至記憶體管理電路202。在本範例實施例中,主機介面204是對應連接器102為USB介面。然而,必須瞭解的是本發明不限於此,主機介面204亦可以是PATA介面、IEEE 1394介面、PCI Express介面、SD介面、MS介面、MMC介面、CF介面、SATA介面、IDE介面或其他適合的資料傳輸介面。 The host interface 204 is coupled to the memory management circuit 202 and is configured to receive and identify instructions and data transmitted by the host system 1000. That is to say, the instructions and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204. In the exemplary embodiment, the host interface 204 is a USB interface of the corresponding connector 102. However, it should be understood that the present invention is not limited thereto, and the host interface 204 may also be a PATA interface, an IEEE 1394 interface, a PCI Express interface, an SD interface, an MS interface, an MMC interface, a CF interface, a SATA interface, an IDE interface, or other suitable. Data transmission interface.
記憶體介面206是耦接至記憶體管理電路202並且用以存取非揮發性記憶體模組106。也就是說,欲寫入至非揮發性記憶體模組106的資料會經由記憶體介面206轉換為非揮發性記憶體模組106所能接受的格式。 The memory interface 206 is coupled to the memory management circuit 202 and is used to access the non-volatile memory module 106. That is, the data to be written to the non-volatile memory module 106 is converted to a format acceptable to the non-volatile memory module 106 via the memory interface 206.
緩衝記憶體208是耦接至記憶體管理電路202並且用以暫存來自於主機系統1000的資料與指令或來自於非揮發性記憶體模組106的資料。在此,緩衝記憶體208為靜態隨機存取記憶體(Static Random-Access Memory,SRAM)。然而,必須瞭解的是,本發明不限於此,在另一範例實施例中,緩衝記憶體208亦可是動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)或其他適合的記憶體。此外,在本範例另一實施例中,緩衝記憶體208亦可獨立於記憶體控制器104來配置。也就是說,緩衝記憶體208可配置在記憶體控制器104的外部,並且透過匯流排與記憶體控制器104耦接。 The buffer memory 208 is coupled to the memory management circuit 202 and is used to temporarily store data and instructions from the host system 1000 or data from the non-volatile memory module 106. Here, the buffer memory 208 is a static random access memory (SRAM). However, it should be understood that the present invention is not limited thereto. In another exemplary embodiment, the buffer memory 208 may also be a Dynamic Random Access Memory (DRAM) or other suitable memory. Moreover, in another embodiment of the present example, the buffer memory 208 can also be configured independently of the memory controller 104. That is, the buffer memory 208 can be disposed outside the memory controller 104 and coupled to the memory controller 104 through the bus bar.
在本發明一範例實施例中,記憶體控制器104還包括錯誤檢查與校正電路210。錯誤檢查與校正電路210是耦接至記憶體管理電路202並且用以執行錯誤檢查與校正程序以確保資料的正確性。例如,當記憶體管理電路202從主機系統1000中接收到寫入指令時,錯誤檢查與校正電路210會為對應此寫入指令的資料產生對應的錯誤檢查與校正碼(Error Checking and Correcting Code,ECC Code),並且記憶體管理電路202會將對應此寫入指令的資料與對應的錯誤檢查與校正碼寫入至非揮發性記憶體模組106中。之後,當記憶體管理電路202從非揮發性記憶體模組106中讀取資料時會同時讀取此資料對應的錯誤檢查與校正碼,並且錯誤檢查與校正電路210會依據此錯誤檢查與校正碼對所讀取的資料執行錯誤檢查與校正程序。 In an exemplary embodiment of the invention, the memory controller 104 further includes an error checking and correction circuit 210. The error checking and correction circuit 210 is coupled to the memory management circuit 202 and is used to perform error checking and correction procedures to ensure the correctness of the data. For example, when the memory management circuit 202 receives a write command from the host system 1000, the error check and correction circuit 210 generates a corresponding error check and correction code (Error Checking and Correcting Code) for the data corresponding to the write command. ECC Code), and the memory management circuit 202 writes the data corresponding to the write command and the corresponding error check and correction code to the non-volatile memory module 106. Then, when the memory management circuit 202 reads the data from the non-volatile memory module 106, the error check and correction code corresponding to the data is simultaneously read, and the error check and correction circuit 210 checks and corrects according to the error. The code performs an error check and correction procedure on the data read.
圖4與圖5是根據本發明範例實施例所繪示之管理記憶體模組的範例示意圖。 4 and FIG. 5 are schematic diagrams showing an example of a management memory module according to an exemplary embodiment of the invention.
必須瞭解的是,在此描述非揮發性記憶體模組106之實體區塊的運作時,以“提取”、“交換”、“分組”、“輪替”等詞來操作實體區塊是邏輯上的概念。也就是說,記憶體模組106之實體區塊的實際位置並未更動,而是邏輯上對非揮發性記憶體模組106的實體區塊進行操作。 It should be understood that when the operation of the physical block of the non-volatile memory module 106 is described herein, it is logical to operate the physical block with words such as "extract", "exchange", "group", and "rotation". On the concept. That is to say, the actual location of the physical block of the memory module 106 is not changed, but the physical block of the non-volatile memory module 106 is logically operated.
請參照圖4,記憶體管理電路202會將非揮發性記憶體模組106的實體區塊304(0)~304(R)邏輯地分組為資料區402、備用區404、系統區406與取代區408。 Referring to FIG. 4, the memory management circuit 202 logically groups the physical blocks 304(0)-304(R) of the non-volatile memory module 106 into a data area 402, a spare area 404, a system area 406, and a replacement. Area 408.
資料區402與備用區404的實體區塊是用以儲存來自於主機系統1000的資料。具體來說,資料區402是已儲存資料的實體區塊,而備用區404的實體區塊是用以替換資料區402的實體區塊。因此,備用區404的實體區塊為空或可使用的實體區塊,即無記錄資料或標記為已沒用的無效資料。也就是說,在備用區中的實體區塊已被執行抹除運作,或者當備用區中的實體區塊被提取用於儲存資料之前所提取之實體區塊會被執行抹除運作。因此,備用區的實體區塊為可被使用的實體區塊。 The physical blocks of the data area 402 and the spare area 404 are used to store data from the host system 1000. Specifically, the data area 402 is a physical block in which data is stored, and the physical block of the spare area 404 is a physical block used to replace the data area 402. Therefore, the physical block of the spare area 404 is empty or usable physical block, that is, no recorded data or invalid data marked as useless. That is to say, the physical block in the spare area has been erased, or the physical block extracted before the physical block in the spare area is extracted for storing data is subjected to the erase operation. Therefore, the physical block of the spare area is a physical block that can be used.
邏輯上屬於系統區406的實體區塊是用以記錄系統資料,其中此系統資料包括關於記憶體晶片的製造商與型號、記憶體晶片的實體區塊數、每一實體區塊的實體頁面數等。 The physical block logically belonging to the system area 406 is used to record system data, wherein the system data includes the manufacturer and model of the memory chip, the number of physical blocks of the memory chip, and the number of physical pages of each physical block. Wait.
邏輯上屬於取代區408中的實體區塊是替代實體區塊。 例如,非揮發性記憶體模組106於出廠時會預留4%的實體區塊作為更換使用。也就是說,當資料區402、備用區404與系統區406中的實體區塊損毀時,預留於取代區408中的實體區塊是用以取代損壞的實體區塊(即,壞實體區塊(bad block))。因此,倘若取代區408中仍存有正常之實體區塊且發生實體區塊損毀時,記憶體管理電路202會從取代區408中提取正常的實體區塊來更換損毀的實體區塊。倘若取代區408中無正常之實體區塊且發生實體區塊損毀時,則記憶體管理電路202會將整個非揮發性記憶體儲存裝置100宣告為寫入保護(write protect)狀態,而無法再寫入資料。 The physical block logically belonging to the replacement area 408 is a substitute physical block. For example, the non-volatile memory module 106 will reserve 4% of the physical block for replacement when it leaves the factory. That is, when the physical block 402, the spare area 404, and the physical block in the system area 406 are damaged, the physical block reserved in the replacement area 408 is used to replace the damaged physical block (ie, the bad physical area). Block (bad block). Therefore, if the normal physical block still exists in the replacement area 408 and the physical block is damaged, the memory management circuit 202 extracts the normal physical block from the replacement area 408 to replace the damaged physical block. If there is no normal physical block in the replacement area 408 and the physical block is damaged, the memory management circuit 202 declares the entire non-volatile memory storage device 100 as a write protect state, and cannot Write data.
特別是,資料區402、備用區404、系統區406與取代區408之實體區塊的數量會依據不同的記憶體規格而有所不同。此外,必須瞭解的是,在非揮發性記憶體儲存裝置100的運作中,實體區塊關聯至資料區402、備用區404、系統區406與取代區408的分組關係會動態地變動。例如,當備用區中的實體區塊損壞而被取代區的實體區塊取代時,則原本取代區的實體區塊會被關聯至備用區。 In particular, the number of physical blocks of data area 402, spare area 404, system area 406, and replacement area 408 may vary depending on different memory specifications. In addition, it must be understood that in the operation of the non-volatile memory storage device 100, the grouping relationship of the physical block association to the data area 402, the spare area 404, the system area 406, and the replacement area 408 may dynamically change. For example, when a physical block in a spare area is damaged and replaced by a physical block of the replaced area, the physical block of the originally replaced area is associated with the spare area.
請參照圖5,如上所述,資料區402與備用區404的實體區塊是以輪替方式來儲存主機系統1000所寫入之資料。在本範例實施例中,記憶體管理電路202會配置邏輯位址給主機系統1000以利於在以上述輪替方式來儲存資料之實體區塊中進行資料存取。特別是,記憶體管理電路202會將所提供的邏輯位址分組為邏輯區塊510(0)~510(H),並且將邏輯區塊510(0)~510(H)映射至資 料區402的實體區塊。例如,當非揮發性記憶體儲存裝置100被主機系統1000的作業系統以檔案系統(例如,FAT 32)格式化時,邏輯區塊510(0)~510(H)分別地映射至資料區402的實體區塊304(0)~304(D)。也就是說,一個邏輯區塊會映射資料區402中的一個實體區塊。在此,記憶體管理電路202會建立邏輯區塊-實體區塊映射表(logical block-physical block mapping table),以記錄邏輯區塊與實體區塊之間的映射關係。 Referring to FIG. 5, as described above, the physical block of the data area 402 and the spare area 404 stores the data written by the host system 1000 in a rotating manner. In the present exemplary embodiment, the memory management circuit 202 configures the logical address to the host system 1000 to facilitate data access in the physical block in which the data is stored in the above-described alternate manner. In particular, the memory management circuit 202 groups the provided logical addresses into logical blocks 510(0)-510(H) and maps logical blocks 510(0)~510(H) to the resources. The physical block of the material area 402. For example, when the non-volatile memory storage device 100 is formatted by the operating system of the host system 1000 in a file system (eg, FAT 32), logical blocks 510(0)-510(H) are mapped to the data area 402, respectively. Physical blocks 304(0)~304(D). That is, one logical block maps one physical block in the data area 402. Here, the memory management circuit 202 establishes a logical block-physical block mapping table to record the mapping relationship between the logical block and the physical block.
圖6~圖8是根據本發明範例實施例所繪示的寫入資料至非揮發性記憶體模組的範例。 6-8 are examples of writing data to a non-volatile memory module according to an exemplary embodiment of the invention.
請同時參照圖6~圖8,例如,在邏輯區塊510(0)是映射至實體區塊304(0)的映射狀態下,當記憶體控制器104從主機系統1000中接收到寫入指令而欲寫入資料至屬於邏輯區塊510(0)的邏輯位址時,記憶體管理電路202會依據邏輯區塊-實體區塊映射表識別邏輯區塊510(0)目前是映射至實體區塊304(0)並且從備用區404中提取實體區塊304(D+1)作為替換實體區塊來輪替實體區塊304(0)。然而,當記憶體管理電路202將新資料寫入至實體區塊304(D+1)的同時,記憶體管理電路202不會立刻將實體區塊304(0)中的所有有效資料搬移至實體區塊304(D+1)而抹除實體區塊304(0)。具體來說,記憶體管理電路202會將實體區塊304(0)中欲寫入實體頁面之前的有效資料(即,實體區塊304(0)的第0實體頁面與第1實體頁面中的資料)複製至實體區塊304(D+1)的第0實體頁面與第1實體頁面中(如圖6所示),並且將新資料寫入至實 體區塊304(D+1)的第2實體頁面與第3實體頁面中(如圖7所示)。此時,記憶體管理電路202即完成寫入的運作。因為實體區塊304(0)中的有效資料有可能在下個操作(例如,寫入指令)中變成無效,因此立刻將實體區塊304(0)中的有效資料搬移至實體區塊304(D+1)可能會造成無謂的搬移。此外,資料必須依序地寫入至實體區塊內的實體頁面,因此,記憶體管理電路202僅會先搬移欲寫入實體頁面之前的有效資料。 Referring to FIG. 6 to FIG. 8 simultaneously, for example, when the logical block 510(0) is mapped to the physical block 304(0), the memory controller 104 receives the write command from the host system 1000. When the data is to be written to the logical address belonging to the logical block 510(0), the memory management circuit 202 identifies that the logical block 510(0) is currently mapped to the physical area according to the logical block-physical block mapping table. Block 304(0) and extracts the physical block 304 (D+1) from the spare area 404 as a replacement physical block to rotate the physical block 304(0). However, when the memory management circuit 202 writes new data to the physical block 304 (D+1), the memory management circuit 202 does not immediately move all valid data in the physical block 304(0) to the entity. Block 304 (D+1) erases physical block 304(0). Specifically, the memory management circuit 202 will store the valid data before the entity page in the physical block 304(0) (ie, the 0th entity page of the physical block 304(0) and the 1st entity page. Data) is copied to the 0th entity page of the physical block 304 (D+1) and the 1st entity page (as shown in FIG. 6), and the new data is written to the real The second entity page of the body block 304 (D+1) is in the third entity page (as shown in FIG. 7). At this time, the memory management circuit 202 completes the operation of writing. Since the valid data in the physical block 304(0) may become invalid in the next operation (for example, a write command), the valid data in the physical block 304(0) is immediately moved to the physical block 304 (D). +1) may cause unnecessary moves. In addition, the data must be sequentially written to the physical page within the physical block. Therefore, the memory management circuit 202 only moves the valid data before the physical page is written.
在本範例實施例中,暫時地維持此等母子暫態關係(即,實體區塊304(0)與實體區塊304(D+1))的運作稱為開啟(open)母子區塊,並且原實體區塊稱為母實體區塊而替換實體區塊稱為子實體區塊。 In the present exemplary embodiment, temporarily maintaining the operation of the parent-child transient relationship (ie, the physical block 304(0) and the physical block 304(D+1)) is referred to as opening the parent and child blocks, and The original physical block is called the parent physical block and the replacement physical block is called the child physical block.
之後,當需要將實體區塊304(0)與實體區塊304(D+1)的內容真正合併時,記憶體管理電路202才會將實體區塊304(0)與實體區塊304(D+1)的資料整併至一個實體區塊,由此提升實體區塊的使用效率。在此,合併母子區塊的運作稱為關閉(close)母子區塊。例如,如圖8所示,當進行關閉母子區塊時,記憶體管理電路202會將實體區塊304(0)中剩餘的有效資料(即,實體區塊304(0)的第4實體頁面~第(K)實體頁面中的資料)複製至替換實體區塊304(D+1)的的第4實體頁面~第(K)實體頁面中,然後將實體區塊304(0)抹除並關聯至備用區404,同時,將實體區塊304(D+1)關聯至資料區402。也就是說,記憶體管理電路202會在邏輯區塊-實體區塊映射表中將邏輯區塊510(0)重新映射至304(D+1)。此外, 在本範例實施例中,記憶體管理電路202會建立備用區實體區塊表(未繪示)來記錄目前被關聯至備用區的實體區塊。值得一提的是,在開啟母子區塊時記憶體管理電路202需使用更多緩衝記憶體252的儲存空間來儲存管理變數,以記錄更詳細的儲存狀態。例如,此些管理變數會記錄屬於邏輯區塊510(0)的有效資料被分散地儲存在實體區塊304(0)與實體區塊304(D+1)的哪些實體頁面中(如圖7所示)。基此,在可攜式非揮發性記憶體儲存裝置100運作期間,母子區塊的組數是有限的。因此,當可攜式非揮發性記憶體儲存裝置100接收到來自於主機系統1000的寫入指令時,倘若已開啟母子區塊的組數達到上限時,記憶體管理電路202需關閉至少一組目前已開啟之母子區塊(即,執行關閉母子區塊運作)以執行此寫入指令。在此,圖6~圖8所示的寫入運作稱為一般寫入模式。 Thereafter, when it is necessary to actually merge the contents of the physical block 304(0) with the physical block 304(D+1), the memory management circuit 202 will place the physical block 304(0) with the physical block 304(D). The +1) data is merged into one physical block, thereby improving the efficiency of the use of the physical block. Here, the operation of merging the parent and child blocks is called closing the mother and child blocks. For example, as shown in FIG. 8, when the parent and child blocks are closed, the memory management circuit 202 will store the remaining valid material in the physical block 304(0) (ie, the fourth entity page of the physical block 304(0). ~ The material in the (K) entity page) is copied to the 4th entity page to the (K) entity page of the replacement entity block 304 (D+1), and then the physical block 304(0) is erased and Associated to spare area 404, while physical block 304 (D+1) is associated to data area 402. That is, the memory management circuit 202 will remap the logical block 510(0) to 304(D+1) in the logical block-physical block mapping table. In addition, In the present exemplary embodiment, the memory management circuit 202 creates a spare area physical block table (not shown) to record the physical blocks currently associated with the spare area. It is worth mentioning that the memory management circuit 202 needs to use more storage space of the buffer memory 252 to store management variables when the mother and child blocks are turned on to record a more detailed storage state. For example, such management variables record which physical pages of the physical block 304(0) and the physical block 304(D+1) are randomly stored in the physical block of the logical block 510(0) (FIG. 7). Shown). Accordingly, during operation of the portable non-volatile memory storage device 100, the number of groups of mother and child blocks is limited. Therefore, when the portable non-volatile memory storage device 100 receives the write command from the host system 1000, the memory management circuit 202 needs to close at least one group if the number of groups of the mother and child blocks has been reached to the upper limit. The parent and child blocks that are currently open (ie, performing the shutdown parent and child block operations) execute this write command. Here, the write operation shown in FIGS. 6 to 8 is referred to as a general write mode.
圖9是根據本發明範例實施例所繪示的儲能電路的示意圖。 FIG. 9 is a schematic diagram of an energy storage circuit according to an exemplary embodiment of the invention.
請參照圖9,儲能電路1110包括二極體D、第一電阻R1、第二電阻R2、開關S與電容組C。二極體D的陽極用以接收來自於主機系統1000的輸入電壓Vin,並且二極體D的陰極用以提供輸出電壓Vout。第一電阻R1的第一端和第二電阻R2的第一端耦接至二極體D的陰極。開關S的第一端耦接至第二電阻R2的第二端,並且開關S的控制端耦接至記憶體控制器104。電容組C的第一端耦接至開關S的第二端且耦接至第一電阻R1的第二端, 並且電容組C的第二端耦接至接地端。在本範例實施例中,電容組C可包括併聯的多個電容。 Referring to FIG. 9 , the tank circuit 1110 includes a diode D, a first resistor R1, a second resistor R2, a switch S, and a capacitor group C. The anode of the diode D is for receiving the input voltage Vin from the host system 1000, and the cathode of the diode D is for providing the output voltage Vout. The first end of the first resistor R1 and the first end of the second resistor R2 are coupled to the cathode of the diode D. The first end of the switch S is coupled to the second end of the second resistor R2, and the control end of the switch S is coupled to the memory controller 104. The first end of the capacitor group C is coupled to the second end of the switch S and coupled to the second end of the first resistor R1. And the second end of the capacitor group C is coupled to the ground. In the present exemplary embodiment, the capacitor bank C may include a plurality of capacitors in parallel.
在本範例實施例中,當非揮發性記憶體儲存裝置100耦接至主機系統1000時,電容組C會儲存備用電能。電容組C所儲存的備用電能是於主機系統1000所提供之輸入電壓不足時用以維持記憶體控制器104與非揮發性記憶體模組106的短暫運作。在本範例實施例中,例如,電容組的容量為470~2200微法拉(uF)。值得一提的是,在本範例實施例中,第一電阻R1是為了避免當非揮發性記憶體儲存裝置100耦接至主機系統1000時電容組C所造成的大量吸入電流(inrush current)。例如,第一電阻R1的電阻值為200歐母。特別是,第一電阻R1會造成輸出電壓Vout偏低而使記憶體控制器104與非揮發性記憶體模組106無法正常地運作。基此,在本範例實施例中,在第一次接收到來自於主機系統1000的小型電腦標準界面(Small Computer Standard Interface,SCSI)時,記憶體控制器104(或記憶體控制器104的記憶體管理電路202)會開啟(turn on)開關S,以使開關S閉合來併聯第二電阻R2,由此增加輸出電壓Vout。例如,第二電阻R2的電阻值為1歐母。基此,在開關S被開啟的狀態下,記憶體控制器104與非揮發性記憶體模組106就能夠在正常的操作電壓下根據主機系統1000的指令來運作。 In the present exemplary embodiment, when the non-volatile memory storage device 100 is coupled to the host system 1000, the capacitor group C stores backup power. The backup power stored in the capacitor group C is used to maintain the short-term operation of the memory controller 104 and the non-volatile memory module 106 when the input voltage provided by the host system 1000 is insufficient. In the present exemplary embodiment, for example, the capacity of the capacitor group is 470 to 2200 microfarads (uF). It should be noted that, in the present exemplary embodiment, the first resistor R1 is to avoid a large amount of inrush current caused by the capacitor group C when the non-volatile memory storage device 100 is coupled to the host system 1000. For example, the resistance of the first resistor R1 is 200 ohms. In particular, the first resistor R1 causes the output voltage Vout to be low, so that the memory controller 104 and the non-volatile memory module 106 cannot operate normally. Therefore, in the present exemplary embodiment, the memory controller 104 (or the memory of the memory controller 104) is received when receiving the Small Computer Standard Interface (SCSI) from the host system 1000 for the first time. The body management circuit 202) turns on the switch S to close the switch S to connect the second resistor R2 in parallel, thereby increasing the output voltage Vout. For example, the resistance value of the second resistor R2 is 1 ohm. Accordingly, in a state where the switch S is turned on, the memory controller 104 and the non-volatile memory module 106 can operate according to an instruction of the host system 1000 at a normal operating voltage.
必須瞭解的是,在本發明範例實施例中,記憶體控制器104(或記憶體控制器104的記憶體管理電路202)會在被致能後 第一次接收到來自於主機系統1000的SCSI指令時,開啟開關S。然而,本發明不限於此,在本發明另一範例實施例中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)亦可在被致能後第一次接收到來自於主機系統1000的寫入指令時,開啟開關S。或者,在在本發明另一範例實施例中,記憶體控制器104(或記憶體控制器104的記憶體管理電路202)會被致能且等待一延遲時間後,開啟開關S。例如,此延遲時間為3秒鐘。 It should be understood that in an exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202 of the memory controller 104) may be enabled after being enabled. When the SCSI command from the host system 1000 is received for the first time, the switch S is turned on. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also be received for the first time after being enabled. When a write command from the host system 1000 is issued, the switch S is turned on. Alternatively, in another exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202 of the memory controller 104) is enabled and waits for a delay time to turn on the switch S. For example, this delay time is 3 seconds.
在本發明範例實施例中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會偵測對應輸入電壓Vin的偵測訊號。並且,當偵測訊號指示輸入電壓Vin在一預設時間(例如,10秒鐘)內持續小於一預設電壓(例如,4伏特(V))時,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會啟動特殊寫入模式將暫存於緩衝記憶體208中的資料寫入至非揮發性記憶體模組106中。 In an exemplary embodiment of the present invention, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) detects a detection signal corresponding to the input voltage Vin. And, when the detection signal indicates that the input voltage Vin continues to be less than a predetermined voltage (for example, 4 volts (V)) for a preset time (for example, 10 seconds), the memory controller 104 (for example, a memory) The memory management circuit 202) of the controller 104 activates the special write mode to write the data temporarily stored in the buffer memory 208 to the non-volatile memory module 106.
特別是,在特殊寫入模式中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會從備用區404中提取一個實體區塊,並且將暫存於緩衝記憶體208中的資料在所提取之實體區塊的實體頁面中依序地寫入。具體來說,暫存於緩衝記憶體208中的資料會從所提取之實體區塊的第0個實體頁面開始依序地被寫入。也就是說,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)不會依據邏輯存取位址的對應關係來寫入資料(即,如圖6~圖8所示的一般寫入模式)。基此,記 憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)可以較少的時間將暫存於緩衝記憶體208中的資料寫入至非揮發性記憶體模組106中。 In particular, in the special write mode, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) extracts a physical block from the spare area 404 and temporarily stores it in the buffer memory. The data in 208 is sequentially written in the physical page of the extracted physical block. Specifically, the data temporarily stored in the buffer memory 208 is sequentially written from the 0th physical page of the extracted physical block. That is, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) does not write data according to the correspondence of the logical access addresses (ie, as shown in FIGS. 6-8). General write mode). Based on this, remember The memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) can write data temporarily stored in the buffer memory 208 to the non-volatile memory module 106 in less time.
在特殊寫入模式中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會在所提取之實體區塊之實體頁面的冗餘位元區中記錄特殊標記,以將以特殊寫入模式來運作的實體區塊和其他實體區塊來區別。此外,對應暫存於緩衝記憶體208中的資料的邏輯位址(即,映射資訊)亦會被記錄在所提取之實體區塊之實體頁面的冗餘位元區中,以利於非揮發性記憶體儲存裝置100被重新啟動時記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)能夠正確地將以特殊寫入模式所寫入的資料搬移(即,重新寫入)至所映射的實體區塊中。 In the special write mode, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) records a special flag in the redundant bit area of the physical page of the extracted physical block to The physical block that operates in the special write mode is distinguished from other physical blocks. In addition, the logical address (ie, mapping information) corresponding to the data temporarily stored in the buffer memory 208 is also recorded in the redundant bit area of the physical page of the extracted physical block to facilitate non-volatile When the memory storage device 100 is restarted, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) can correctly move the data written in the special write mode (ie, rewrite) ) to the mapped physical block.
必須瞭解的是,在本範例實施例中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)是在所提取之實體區塊之實體頁面的冗餘位元區中記錄特殊標記與對應暫存於緩衝記憶體208中的資料的映射資訊。然而,本發明不限於此,在本發明另一範例實施例中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)亦可從備用區404中提取另一個實體區塊作為特殊實體區塊,來記錄哪些實體區塊的哪些實體頁面被用來以特殊寫入模式來寫入暫存於緩衝記憶體208中的資料以及對應暫存於緩衝記憶體208中的資料的映射資訊。之後,當非揮發性記憶體儲存裝置100被重新啟動時,記憶體控制器104 (例如,記憶體控制器104的記憶體管理電路202)會從此特殊實體區塊中讀取相關的映射資訊,由此將以特殊寫入模式所寫入的資料正確地搬移至所映射的實體區塊中。值得一提的是,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會預先設定某些實體區塊可被用來作為特殊實體區塊。例如,在一範例實施例中,實體區塊304(D+1)~實體區塊304(D+10)會被用來作為特殊實體區塊。基此,當非揮發性記憶體儲存裝置100被重新啟動時,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)僅需確認實體區塊304(D+1)~實體區塊304(D+10)中的資料,就可獲知在前次關機時暫存於緩衝記憶體208中的資料是否是以特殊寫入模式被寫入的至非揮發性記憶體模組106中,由此判斷是否需執行搬移資料的運作。 It should be understood that in the present exemplary embodiment, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) is in the redundant bit area of the physical page of the extracted physical block. The mapping information of the special mark and the data corresponding to the temporary storage in the buffer memory 208 is recorded. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also extract another physical area from the spare area 404. The block acts as a special physical block to record which physical pages of the physical blocks are used to write the data temporarily stored in the buffer memory 208 and the data temporarily stored in the buffer memory 208 in a special write mode. Mapping information. Thereafter, when the non-volatile memory storage device 100 is restarted, the memory controller 104 (For example, the memory management circuit 202 of the memory controller 104) reads the relevant mapping information from the special physical block, thereby correctly moving the data written in the special write mode to the mapped entity. In the block. It is worth mentioning that the memory controller 104 (e.g., the memory management circuit 202 of the memory controller 104) pre-sets that certain physical blocks can be used as special physical blocks. For example, in an exemplary embodiment, physical block 304 (D+1) ~ physical block 304 (D+10) will be used as a special physical block. Accordingly, when the non-volatile memory storage device 100 is restarted, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) only needs to confirm the physical block 304 (D+1)~ The data in the physical block 304 (D+10) can know whether the data temporarily stored in the buffer memory 208 during the previous shutdown is written to the non-volatile memory module in the special write mode. In 106, it is judged whether or not the operation of moving the data needs to be performed.
此外,在本發明另一範例實施例中,在特殊寫入模式中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)更可僅使用所提取之實體區塊的實體頁面之中屬於下頁面的實體頁面來寫入暫存於緩衝記憶體208中的資料。 In addition, in another exemplary embodiment of the present invention, in the special write mode, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) can use only the extracted physical block. The physical pages belonging to the next page among the physical pages are written to the data temporarily stored in the buffer memory 208.
具體來說,NAND型快閃記憶體可根據每一記憶胞中可儲存的位元數區分為SLC NAND型快閃記憶體與MLC NAND型快閃記憶體。在對SLC NAND型快閃記憶體的記憶胞進行寫入(亦稱為程式化(program))時僅能執行單階的程式化,因此每一記憶胞僅能儲存一個位元的資料。而MLC NAND型快閃記憶體之實體區塊的程式化可分為多階段。例如,以4層記憶胞為例,實體 區塊的程式化可分為2階段。第一階段是下頁面(lower page)的寫入部分,其物理特性類似於單層記憶胞(Single Level Cell,SLC)NAND快閃記憶體。第二階段為程式化上頁面(upper page),其中下頁面的寫入速度會快於上頁面。因此,每一實體區塊的頁面可區分為慢速頁面(即,上頁面)與快速頁面(即,下頁面)。類似地,在8層記憶胞或16層記憶胞的案例中,記憶胞會包括更多個頁面並且會以更多階段來寫入。在此,將寫入速度最快的頁面稱為下頁面,其他寫入速度較慢的頁面統稱為上頁面。例如,上頁面包括具有不同寫入速度的多個頁面。此外,在其他實施例中,上頁面也可為寫入速度最慢的頁面,或者寫入速度最慢與部份寫入速度快於寫入速度最慢頁面的頁面。例如,在4層記憶胞中,下頁面為寫入速度最快與寫入速度次快的頁面,上頁面則為寫入速度最慢與寫入速度次慢的頁面。在本範例實施例中,實體區塊的實體頁面可根據其寫入特性區分為屬於上頁面或下頁面。 Specifically, the NAND type flash memory can be classified into SLC NAND type flash memory and MLC NAND type flash memory according to the number of bits that can be stored in each memory cell. In the writing (also called program) of the memory cells of the SLC NAND type flash memory, only a single-order stylization can be performed, so that each memory cell can store only one bit of data. The stylization of the physical block of the MLC NAND type flash memory can be divided into multiple stages. For example, taking a 4-layer memory cell as an example, an entity The stylization of the block can be divided into two phases. The first stage is the write portion of the lower page, which has physical characteristics similar to Single Level Cell (SLC) NAND flash memory. The second stage is the upper page, where the lower page will be written faster than the previous page. Therefore, the pages of each physical block can be divided into a slow page (ie, an upper page) and a fast page (ie, a lower page). Similarly, in the case of 8-layer memory cells or 16-layer memory cells, the memory cells will include more pages and will be written in more stages. Here, the page with the fastest write speed is called the next page, and the other pages with slower write speed are collectively referred to as the upper page. For example, the upper page includes multiple pages with different write speeds. In addition, in other embodiments, the upper page may also be the page with the slowest write speed, or the page with the slowest write speed and partial write speed faster than the slowest write page. For example, in a 4-layer memory cell, the lower page is the page with the fastest write speed and the faster write speed, and the upper page is the page with the slowest write speed and the slower write speed. In this exemplary embodiment, the physical page of the physical block may be classified as belonging to the upper page or the lower page according to its writing characteristics.
基此,藉由僅使用所提取之實體區塊的實體頁面之中屬於下頁面的實體頁面來寫入暫存於緩衝記憶體208中的資料,可更縮短寫入暫存於緩衝記憶體208中的資料所需的時間。 Therefore, the write temporary storage in the buffer memory 208 can be further shortened by writing the data temporarily stored in the buffer memory 208 by using only the physical page belonging to the lower page among the physical pages of the extracted physical block. The time required for the information in .
此外,在本發明範例實施例中,非揮發性記憶體儲存裝置100配置有存取指示燈(未繪示),以顯示非揮發性記憶體儲存裝置100正在進行存取運作。例如,此存取指示燈為LED燈。 In addition, in the exemplary embodiment of the present invention, the non-volatile memory storage device 100 is configured with an access indicator light (not shown) to indicate that the non-volatile memory storage device 100 is performing an access operation. For example, this access indicator is an LED light.
特別是,在本發明另一範例實施例中,在特殊寫入模式中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電 路202)更會關閉存取指示燈以減少耗電。 In particular, in another exemplary embodiment of the present invention, in the special write mode, the memory controller 104 (eg, the memory management of the memory controller 104) Path 202) will also turn off the access indicator to reduce power consumption.
值得一提的是,在本範例實施例中,當偵測訊號指示輸入電壓Vin在預設時間內持續小於預設電壓時,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會啟動特殊寫入模式。然而,本發明不限於此,例如,在本發明另一範例實施例中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)亦可根據指示連接器102之非作動狀態的偵測訊號來啟動特殊寫入模式。具體來說,在連接器102為USB 3.0的例子中,當非揮發性記憶體儲存裝置100與主機系統1000之間的超速(superspeed)連接失敗時,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會偵測到連接器102的非作動(SS.Inactive)狀態,由此判定非揮發性記憶體儲存裝置100可能被不正常地從主機系統1000中被拔除。此外,在本發明另一範例實施例中,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)亦可根據來自於主機系統1000的暫停模式(suspend mode)訊號、暖重置(warm reset)訊號或熱重置(hot reset)訊號來啟動特殊寫入模式,其中暖重置訊號是用以在電壓不下降之狀態下重新驅動系統的信號,熱動置訊號則是使系統重新整理資料且使系統在系統起始點(starting point)啟動之信號。 It should be noted that, in the exemplary embodiment, when the detection signal indicates that the input voltage Vin continues to be less than the preset voltage for a preset time, the memory controller 104 (for example, the memory management of the memory controller 104) Circuit 202) initiates a special write mode. However, the present invention is not limited thereto. For example, in another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also be inactive according to the indication connector 102. The status detection signal activates the special write mode. Specifically, in the example where the connector 102 is USB 3.0, when the superspeed connection between the non-volatile memory storage device 100 and the host system 1000 fails, the memory controller 104 (eg, memory control) The memory management circuit 202) of the device 104 detects the inactive (SS.Inactive) state of the connector 102, thereby determining that the non-volatile memory storage device 100 may be improperly removed from the host system 1000. In addition, in another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also be based on a suspend mode signal from the host system 1000. A special reset mode is initiated by a warm reset signal or a hot reset signal, wherein the warm reset signal is a signal for re-driving the system in a state where the voltage does not drop, and the thermal activation signal is A signal that causes the system to rearrange the data and initiate the system at the starting point of the system.
圖10是根據本發明範例實施例所繪示的資料儲存方法的流程圖。 FIG. 10 is a flowchart of a data storage method according to an exemplary embodiment of the present invention.
請參照圖10,在非揮發性記憶體儲存裝置100運作期 間,在步驟S1001中來自於主機系統1000的輸入電壓會被判斷是否在預設時間內持續小於預設電壓。具體來說,在步驟S1001,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會持續偵測來自於主機系統1000的輸入電壓,以判斷此輸入電壓是否在預設時間內持續小於預設電壓。 Please refer to FIG. 10, during the operation period of the non-volatile memory storage device 100. Meanwhile, the input voltage from the host system 1000 in step S1001 is judged whether it continues to be less than the preset voltage for a preset time. Specifically, in step S1001, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) continuously detects the input voltage from the host system 1000 to determine whether the input voltage is preset. The duration continues to be less than the preset voltage.
倘若來自於主機系統的輸入電壓在預設時間內持續小於預設電壓時,在步驟S1003中會判斷緩衝記憶體208中是否暫存有尚未寫入至非揮發性記憶體106中的資料。 If the input voltage from the host system continues to be less than the preset voltage for a preset time, it is determined in step S1003 whether or not the data that has not been written into the non-volatile memory 106 is temporarily stored in the buffer memory 208.
倘若緩衝記憶體208中暫存有尚未寫入至非揮發性記憶體106中的資料時,在步驟S1005中暫存於緩衝記憶體208中的資料會以特殊寫入模式來被寫入至非揮發性記憶體106中。倘若來自於主機系統的輸入電壓未在預設時間內持續小於預設電壓或緩衝記憶體208中無暫存有尚未寫入至非揮發性記憶體106中的資料時,則步驟S1001會被執行以繼續偵測來自於主機系統的輸入電壓。在本範例實施例中,圖10所示的流程會於非揮發性記憶體儲存裝置100致能後持續的運作直到非揮發性記憶體儲存裝置100中止運作為止。 If the buffer memory 208 temporarily stores data that has not been written into the non-volatile memory 106, the data temporarily stored in the buffer memory 208 in step S1005 is written to the non-special write mode. Volatile memory 106. If the input voltage from the host system does not continue to be less than the preset voltage within the preset time or the buffer memory 208 has no temporary storage data that has not been written into the non-volatile memory 106, then step S1001 is performed. To continue to detect the input voltage from the host system. In the present exemplary embodiment, the flow shown in FIG. 10 continues to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 ceases to operate.
圖11是根據本發明另一範例實施例所繪示的資料儲存方法的流程圖。 FIG. 11 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.
請參照圖11,在非揮發性記憶體儲存裝置100運作期間,在步驟S1101中會判斷是否偵測到連接器102的非作動狀態。具體來說,在步驟S1101,記憶體控制器104(例如,記憶體控制器 104的記憶體管理電路202)會判斷是否偵測到連接器102的非作動狀態。 Referring to FIG. 11, during the operation of the non-volatile memory storage device 100, it is determined in step S1101 whether the non-actuated state of the connector 102 is detected. Specifically, in step S1101, the memory controller 104 (for example, a memory controller) The memory management circuit 202 of 104 determines whether the non-actuated state of the connector 102 is detected.
倘若偵測到連接器102的非作動狀態時,在步驟S1103中會判斷緩衝記憶體208中是否暫存有尚未寫入至非揮發性記憶體106中的資料。 If the non-actuated state of the connector 102 is detected, it is determined in step S1103 whether or not the data that has not been written into the non-volatile memory 106 is temporarily stored in the buffer memory 208.
倘若緩衝記憶體208中暫存有尚未寫入至非揮發性記憶體106中的資料時,在步驟S1105中暫存於緩衝記憶體208中的資料會以特殊寫入模式來寫入至非揮發性記憶體106中。 If the buffer memory 208 temporarily stores data that has not been written into the non-volatile memory 106, the data temporarily stored in the buffer memory 208 in step S1105 is written to the non-volatile state in a special write mode. In the memory 106.
倘若未偵測到連接器102的非作動狀態或緩衝記憶體208中無暫存有尚未寫入至非揮發性記憶體106中的資料時,則步驟S1101會被執行以繼續偵測來自於主機系統的輸入電壓。同樣的,在此一範例實施例中,圖11所示的流程會於非揮發性記憶體儲存裝置100致能後持續的運作直到非揮發性記憶體儲存裝置100中止運作為止。 If the non-actuated state of the connector 102 is not detected or the buffer memory 208 does not temporarily store data that has not been written into the non-volatile memory 106, then step S1101 is executed to continue detecting the host. The input voltage of the system. Similarly, in this exemplary embodiment, the flow shown in FIG. 11 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 ceases to operate.
圖12是根據本發明另一範例實施例所繪示的資料儲存方法的流程圖。 FIG. 12 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.
請參照圖12,在非揮發性記憶體儲存裝置100運作期間,在步驟S1201中會判斷是否接收到來自於主機系統1000的暫停模式訊號、暖重置訊號或熱重置訊號。具體來說,在步驟S1201,記憶體控制器104(例如,記憶體控制器104的記憶體管理電路202)會判斷是否接收到來自於主機系統1000的暫停模式訊號、暖重置訊號或熱重置訊號。 Referring to FIG. 12, during the operation of the non-volatile memory storage device 100, it is determined in step S1201 whether a pause mode signal, a warm reset signal, or a warm reset signal from the host system 1000 is received. Specifically, in step S1201, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) determines whether a pause mode signal, a warm reset signal, or a hot weight from the host system 1000 is received. Signal number.
倘若接收到來自於主機系統1000的暫停模式訊號、暖重置訊號或熱重置訊號時,在步驟S1203中會判斷緩衝記憶體208中是否暫存有尚未寫入至非揮發性記憶體106中的資料。 If the pause mode signal, the warm reset signal or the hot reset signal from the host system 1000 is received, it is determined in step S1203 whether the buffer memory 208 is temporarily stored in the non-volatile memory 106. data of.
倘若緩衝記憶體208中暫存有尚未寫入至非揮發性記憶體106中的資料時,在步驟S1205中暫存於緩衝記憶體208中的資料會以特殊寫入模式來寫入至非揮發性記憶體106中。 If the buffer memory 208 temporarily stores data that has not been written into the non-volatile memory 106, the data temporarily stored in the buffer memory 208 in step S1205 is written to the non-volatile state in a special write mode. In the memory 106.
倘若未接收到來自於主機系統1000的暫停模式訊號、暖重置訊號或熱重置訊號或緩衝記憶體208中無暫存有尚未寫入至非揮發性記憶體106中的資料時,則步驟S1201會被執行以繼續判斷是否接收到來自於主機系統1000的暫停模式訊號、暖重置訊號或熱重置訊號。同樣的,在此一範例實施例中,圖11所示的流程會於非揮發性記憶體儲存裝置100致能後持續的運作直到非揮發性記憶體儲存裝置100中止運作為止。 If the pause mode signal, the warm reset signal or the warm reset signal from the host system 1000 is not received, or the buffer memory 208 does not temporarily store the data that has not been written into the non-volatile memory 106, then the step S1201 is executed to continue to determine whether a pause mode signal, a warm reset signal, or a warm reset signal from the host system 1000 is received. Similarly, in this exemplary embodiment, the flow shown in FIG. 11 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 ceases to operate.
綜上所述,本發明範例實施例的非揮發性記憶體儲存裝置、記憶體控制器與資料儲存方法能夠避免因不正常的斷電所造成之緩衝記憶體內的資料的遺失。 In summary, the non-volatile memory storage device, the memory controller and the data storage method of the exemplary embodiments of the present invention can avoid loss of data in the buffer memory caused by abnormal power failure.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧非揮發性記憶體儲存裝置 100‧‧‧Non-volatile memory storage device
102‧‧‧連接器 102‧‧‧Connector
104‧‧‧記憶體控制器 104‧‧‧ memory controller
106‧‧‧非揮發性記憶體模組 106‧‧‧Non-volatile memory module
108‧‧‧電源轉換與供應電路 108‧‧‧Power conversion and supply circuit
110‧‧‧儲能電路 110‧‧‧storage circuit
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TWI685792B (en) * | 2018-03-14 | 2020-02-21 | 神雲科技股份有限公司 | Computer aparatus, server apparatus and controlling method for hybrid memory unit thereof |
US10817188B2 (en) | 2016-05-30 | 2020-10-27 | Silicon Motion, Inc. | Data storing method and system initializing method after sudden power-off event |
US10872018B2 (en) | 2018-01-30 | 2020-12-22 | Quanta Computer Inc. | Memory data preservation solution |
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US10817188B2 (en) | 2016-05-30 | 2020-10-27 | Silicon Motion, Inc. | Data storing method and system initializing method after sudden power-off event |
US10872018B2 (en) | 2018-01-30 | 2020-12-22 | Quanta Computer Inc. | Memory data preservation solution |
TWI685792B (en) * | 2018-03-14 | 2020-02-21 | 神雲科技股份有限公司 | Computer aparatus, server apparatus and controlling method for hybrid memory unit thereof |
US10802918B2 (en) | 2018-03-14 | 2020-10-13 | Mitac Computing Technology Corporation. | Computer device, server device, and method for controlling hybrid memory unit thereof |
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