TW201428829A - 半導體裝置之製造方法 - Google Patents
半導體裝置之製造方法 Download PDFInfo
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Abstract
一種半導體裝置之製造方法,其包含:在半導體基板上形成虛擬閘極之步驟;在基板及虛擬閘極上堆積埋入絕緣膜且藉由埋入絕緣膜將虛擬閘極埋入之步驟;將埋入絕緣膜一部分蝕刻而在虛擬閘極的周邊部形成空隙之步驟;對因形成空隙而露出的虛擬閘極進行蝕刻,藉以將虛擬閘極及該虛擬閘極上的埋入絕緣膜除去之步驟;及,透過閘極絕緣膜在因除去虛擬閘極而露出的基板上形成閘極電極之步驟。
Description
本發明係有關於半導體裝置之製造方法。
隨著在CMOS邏輯電路之微細化進展,為了實現低EOT(等效物理氧化物厚度;Equivalent Physical Oxide Thickness),係在元件應用高介電常數(high-k)膜。而且,為了避免因該high-k膜的熱負荷所致之臨限值(threshold value)變動和形成低介電常數層,或為了在通道導入應變,係在SD區域形成後,使用形成閘極絕緣膜的取代閘極(鑲嵌式閘極;damascene gate)製程來進行元件製造。
在先前的取代閘極(replacement gate)製程,係在虛擬閘極形成後,形成SD區域且藉由使用SiO2等的絕緣膜將虛擬閘極埋入且使用CMP(化學機械研磨;Chemical Mechanical Polishing)法使虛擬閘極上面露出。其次,將虛擬閘極除去之後,藉由再次形成閘極絕緣膜及閘極電極來形成閘極。藉此,SD區域形成時,不會蒙受高熱負荷而能夠形成閘極堆疊。
如上述,在進行取代閘極製程時,在堆積埋入絕
緣膜之後,必須使用CMP法將虛擬閘極上面露出之步驟。但是,CMP法係隨著晶圓面積大口徑化,抑制產生刮痕和碟形凹陷(dishing)、侵蝕,係在技術上逐漸變為困難。而且,由於大口徑化,預料CMP製程的成本増大,就今後晶圓大口徑化而言,預料取代閘極製程的應用會變為困難。
專利文獻1:日本特開2001-93861號公報
專利文獻2:日本特開2003-158263號公報
本發明欲解決之課題,係提供一種半導體裝置之製造方法,其不使用CMP法而能夠進行取代閘極製程,而且可抑制基底膜(層間絕緣膜)的面內偏差和缺陷,同時能夠謀求製程的簡略化從而減低製程成本。
有關本發明的一態樣之半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成虛擬閘極之步驟;在前述基板及前述虛擬閘極上堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述虛擬閘極埋入之步驟;將前述埋入絕緣膜一部分蝕刻而在前述虛擬閘極的周邊部形成空隙之步驟;對因形成前述空隙而露出的前述虛擬閘極進行蝕刻,藉以將前述虛擬閘極及該虛擬閘極上的前述埋入絕緣
膜除去之步驟;及,透過閘極絕緣膜在因除去前述虛擬閘極而露出的前述基板上形成閘極電極之步驟。
有關本發明之另一態樣之半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成鰭狀結構之步驟;在前述基板及前述鰭狀結構的表面上,形成與前述基板不同的半導體層之步驟;在形成有前述半導體層之前述基板及前述鰭狀結構上,堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述鰭狀結構埋入之步驟;將前述埋入絕緣膜一部分蝕刻而在前述鰭狀結構的周邊部形成空隙之步驟;及,從因前述空隙而露出的前述鰭狀結構下部,對在前述鰭狀結構的外周成膜而成之前述半導體層進行蝕刻,藉以除去前述鰭狀結構(fin structure)外周部的前述半導體層及前述鰭狀結構上部的前述埋入絕緣膜之步驟。
有關本發明之另一態樣之半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成鰭狀結構之步驟;在前述基板及前述鰭狀結構上堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述鰭狀結構埋入之步驟;將前述埋入絕緣膜一部分蝕刻而在前述鰭狀結構的周邊部形成空隙之步驟;及,對因前述空隙而露出的前述鰭狀結構下部進行蝕刻,使前述鰭狀結構上部從前述基板漂浮之步驟。
有關本發明之另一態樣之半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成鰭狀結構之步驟;在前述基板及前述鰭狀結構上堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述鰭狀結構埋入步驟;將前述埋入絕
緣膜一部分蝕刻而在前述鰭狀結構的周邊部形成空隙之步驟;及,令因前述空隙而露出的前述鰭狀結構下部氧化,使前述鰭狀結構與前述基板電性分離之步驟。
依照本發明,因為不使用CMP法而能夠進行取代閘極製程,所以能夠抑制在CMP法成為問題之碟形凹陷、侵蝕、刮痕等基底膜(層間絕緣膜)的面內偏差和缺陷。
又,因為不使用CMP法,所以可望因製程簡略化而降低製程成本。而且,因為埋入後的閘極形狀成為逆錐體形狀,能夠減低閘極電阻及抑制閘極電極的埋入不良。
1、21、31‧‧‧半導體基板
2、2'‧‧‧虛擬閘極絕緣膜
3‧‧‧虛擬閘極電極
4‧‧‧硬遮罩
5‧‧‧側壁膜
6‧‧‧虛擬閘極
7‧‧‧延伸區域
8‧‧‧Deep區域(SD區域)
9、24、33‧‧‧埋入絕緣膜
10、25、34‧‧‧空洞
11‧‧‧空孔
12‧‧‧閘極絕緣膜
13‧‧‧閘極電極
22、32‧‧‧鰭狀結構
23‧‧‧半導體層
35‧‧‧半導體漂浮層
36‧‧‧氧化膜
37‧‧‧半導體層
θ‧‧‧角度
圖1(a)~(f)係顯示有關第1實施形態之半導體裝置的製造步驟之剖面圖。
圖2係顯示依照第1實施形態所製造之半導體裝置的剖面結構之顯微鏡照片(剛埋入閘極後)。
圖3係顯示依照第1實施形態所製造之半導體裝置的剖面結構之顯微鏡照片(藉由HF處理形成有空隙者)。
圖4係顯示依照第1實施形態所製造之半導體裝置的剖面結構之顯微鏡照片(將多晶Si蝕刻後的狀態)。
圖5係顯示依照第1實施形態所製造之半導體裝置的剖面結構之顯微鏡照片(將多晶Si蝕刻後的狀態)。
圖6係顯示微細分割閘極圖案的例子之平面圖。
圖7(a)~(e)係顯示有關第2實施形態之半導體裝置的製造步驟之剖面圖。
圖8(a)~(e)係顯示有關第3實施形態之半導體裝置的製造步驟之剖面圖。
圖9(a)~(c)係顯示有關第4實施形態之半導體裝置的製造步驟之剖面圖。
圖10係用以說明階梯覆蓋率(step coverage)之示意圖。
圖11係顯示在基板上形成有段差結構的例子之剖面圖。
以下,藉由圖示的實施形態來說明本發明的詳細。
圖1(a)~(f)係顯示有關第1實施形態之半導體裝置的製造步驟之剖面圖。本實施形態係使用取代閘極製程之製造MOSFET之方法。
首先,如在圖1(a)所顯示,在半導體基板1上形成虛擬閘極絕緣膜2、虛擬閘極電極3、硬遮罩4之後,藉由微影術及RIE等的蝕刻製程而形成虛擬閘極圖案。具體而言,係在半導體基板1上堆積虛擬閘極絕緣膜2及虛擬閘極電極3之後,在虛擬閘極電極3上形成閘極圖案的硬遮罩4。然後,藉由RIE等的蝕刻製程而對虛擬閘極電極3進行選擇蝕刻。
其次,如在圖1(b)所顯示,藉由離子植入來進行形成用以降低通道與SD區域之間的寄生電阻之延伸區域
7,接著,在形成側壁膜5之後,進行形成Deep區域(S/D區域)8。在此,雖然未圖示,亦可進行形成用以提升短通道效果耐性提升之光暈(halo)區域。又,亦可在只形成Deep區域8之後,形成金屬SD區域,亦可以不是為了形成Deep區域8,而是進行用以降低金屬SD與通道半導體界面的肖特基(Schottky)障礙之離子植入。而且,不進行離子植入而只形成金屬SD區域亦無妨。
SD區域形成之後,將SD區域上的虛擬閘極絕緣膜2除去,來形成只有在虛擬閘極電極3的下面殘留有虛擬閘極絕緣膜2'之虛擬閘極6。隨後,藉由濕式蝕刻等將側壁膜5及硬遮罩4除去。在此,係在將SD區域上的虛擬閘極絕緣膜2除去之後,將側壁膜5及硬遮罩4除去,但是在將虛擬閘極絕緣膜2除去之前,將該等除去亦無妨。又,以下的圖1(c)以後,係說明將側壁膜5及硬遮罩4除去時的例子,但是任何膜之中的任一者、或任一者均殘留的狀態亦無妨。
其次,如在圖1(c)所顯示,在基板1及虛擬閘極6上堆積埋入絕緣膜9,使用絕緣膜9將虛擬閘極6埋入。在此,埋入絕緣膜9係從基板1表面及虛擬閘極電極3的表面各自成長,最後在虛擬閘極電極3的周邊部連接。而且,從基板1表面成長的部分與從虛擬閘極電極3表面成長的部分之連接部分(界線)之埋入絕緣膜9係變為稀疏。
作為埋入絕緣膜9,係堆積階梯覆蓋率(step coverage)低、或膜內應力強的絕緣膜而將虛擬閘極6埋入。或在堆積成為段差形狀時,亦可使用藉由液相或氣相蝕刻
在段差端部形成特定角度的空隙之絕緣膜,將其堆積而將虛擬閘極6埋入。
作為在埋入絕緣膜9之滿足上述條件的膜,例如可舉出於300℃以下之較低的溫度使用SiH4氣體等、N2O氣體等且藉由PECVD法而形成之SiO2膜;或同樣地藉由PECVD法而形成之SiN膜等。此外,於低溫藉由CVD法而成膜之LTO膜和TEOS膜亦無妨。此時,因為階梯覆蓋率低、或膜內應力的大小之緣故,在虛擬閘極側面與虛擬閘極附近的半導體基板所堆積的絕緣膜係在衝撞的區域(界線),所以絕緣膜容易變為稀疏。
上述所謂膜內應力強的絕緣膜,係指具有如以下的膜內應力之膜。具體而言,膜內應力的大小係以90MPa以上的壓縮應力為佳,以具有390MPa以上的膜內壓縮應力之膜為特佳。又,在此所謂之膜內應力的測定,係使用光槓桿(optical lever)法估計。例如,測定SiO2的膜內應力時,係測定在4英吋Si基板上堆積SiO2膜前後之基板的曲率半徑,從基板的彈性常數等且使用曲率半徑來估計膜內應力。
又,上述所謂階梯覆蓋率低的膜,係指具有在以下所表示的特徵之膜。具體而言,係指使用如在圖10所顯示之縱橫比(aspect ratio)為(H/W)≒1.9(=~130nm/~70nm)之段差形狀時,在段差結構堆積絕緣膜時在各部位使用絕緣膜厚,而側邊階梯覆蓋率(side step coverage)為(Ts/Tt)<0.47,或底部階梯覆蓋率(bottom step coverage)為(Tb/Tt)<0.51,或尖角化(cusping)為([Tc-Ts]/Ts)≧0.34之膜。
而且,在堆積成為上述段差形狀時,所謂藉由液相或氣相蝕刻而在段差端部形成特定角度的空隙之絕緣膜,係具有如以下的特徵之膜。如在圖11所表示,對在基板上所形成的段差結構堆積該絕緣膜,隨後,藉由液相或氣相進行蝕刻時,如在段差端部從對基板之法線於角度θ傾斜的方向形成空隙之絕緣膜。在此,θ係以滿足0°≦θ≦60°為佳。這是因為θ大於60°時,會使後述之極電極13的上部面積變大,而不利於單元的微細化。
其次,藉由濕式蝕刻法或氣體對埋入絕緣膜9進行蝕刻,如在圖1(d)所顯示,在虛擬閘極6的周邊部形成空隙10。該空隙10係沿著埋入絕緣膜9變為稀疏的部分、亦即埋入絕緣膜9從基板1表面成長的部分與從虛擬閘極電極3表面成長的部分之界線而傾斜地形成。
依照上述的製程,虛擬閘極電極3的底部係在空隙10露出。在該狀態下,藉由通過空隙使用液體或氣體對虛擬閘極電極3進行蝕刻,如在圖1(e)所顯示,能夠將虛擬閘極電極3剝落而形成空孔11。
在圖1(e),係顯示虛擬閘極絕緣膜2'為殘留之圖,但是虛擬閘極絕緣膜2'在蝕刻時與虛擬閘極電極3同時被除去亦無妨。但是,此時必須是不會同時蝕刻基板之類的絕緣膜種及蝕刻條件。
此後,係與使用先前的CMP法之取代閘極製程同樣。亦即如在圖1(f)所顯示,將虛擬閘極絕緣膜2'除去之後,洗淨MOS界面及半導體基板1的表面。隨後,藉由ALD法等
形成閘極絕緣膜12,進而埋入閘極電極13。埋入閘極電極13後,亦可藉由進行金屬CMP來進行閘極電極13的平坦化。此後,能夠藉由堆積層間絕緣膜且進行配線步驟來形成CMOS邏輯電路。
考慮在本實施形態之上述的製程條件時,各膜種和半導體層係能夠使用如以下的物質。使用Ge、InGaAs等III-V族化合物作為基板1時,可使用能夠被HCl、Na OH、HF等蝕刻的絕緣膜作為虛擬閘極絕緣膜2,其中該等HCl、NaOH、HF等係不會蝕刻該等半導體的藥液。例如,能夠將下列使用於虛擬閘極絕緣膜2:稱為SiO2或HfO2的high-k膜等能夠被HF蝕刻之膜;能夠被HCl或HF蝕刻之La2O3或LaAlOX等的膜;或是能夠被HF、HCl、NaOH蝕刻之Al2O3膜。
只有能夠被HF蝕刻之SiO2、或HfO2、HfAlOx等的high-k膜為虛擬閘極絕緣膜2時,作為虛擬閘極電極3,係能夠使用能夠以HF以外的藥液蝕刻之物質。例如,能夠使用下列等:能夠被NaOH和TMAH蝕刻之a-Si;能夠被含有H2O2之NaOH和HCl蝕刻之a-Ge;及只有能夠被HCl蝕刻之a-InP和Ni。而且,亦能夠使用能夠被HF蝕刻之SiO2等來形成虛擬閘極電極3,但是此時,必須使埋入絕緣膜9為以HF蝕刻為較慢的SiN等。
在能夠被HCl蝕刻之La2O3和LaAlOX等方面,將a-Si、a-Ge等使用在虛擬閘極電極3時,亦能夠以TMAH、NaOH、和在NaOH添加有H2O2之藥液來蝕刻。而且,將
a-InP、Ni等使用在虛擬閘極電極3時,能夠同時以HCl將虛擬閘極電極3及虛擬閘極絕緣膜2蝕刻。
其次,關於將能夠被HF、HCl、NaOH蝕刻之Al2O3膜等使用在虛擬閘極絕緣膜2時,係能夠在虛擬閘極電極3使用a-Si、a-Ge、a-InP、Ni、或Al2O3、SiO2等的絕緣膜。此時,能夠使用TMAH和NaOH、HCl、HF各自將虛擬閘極電極3及虛擬閘極絕緣膜2同時剝落。
硬遮罩4和側壁膜5係能夠使用SiO2或SiN。埋入絕緣膜9係能夠使用階梯覆蓋率低或膜內壓縮應力大的SiO2膜和SiN膜。藉此,能夠藉由HF和H3PO4來形成空隙10且能夠將虛擬閘極電極3從該空隙10剝落。
使用SiO2、Al2O3等的絕緣膜形成虛擬閘極電極3及虛擬閘極絕緣膜2時,或是設為a-Si/Al2O3時,藉由使用NH4OH和TMAH、HF進行蝕刻,虛擬閘極絕緣膜2及虛擬閘極電極3係同時溶解。此時,因為半導體基板1係幾乎不溶解於NH4OH和TMAH、HF,所以不產生基板窪陷的問題。因此,因為該結構能夠減少步驟數,乃是較佳。
從以上的情形考慮,在Ge和III-V族基板作為最佳結構的一個例子,可舉出以下的結構:在虛擬閘極絕緣膜2使用Al2O3,在虛擬閘極電極3使用a-Si,而且在埋入絕緣膜9使用藉由PECVD法所形成之階梯覆蓋率低、或膜內壓縮應力大的SiO2。此時,使用TMAH和NaOH系藥液,係不會蝕刻埋入絕緣膜9和半導體,而能夠將虛擬閘極電極3及虛擬閘極絕緣膜2同時蝕刻。又,在上述的a-Si/Al2O3結構,
依照a-Si除去步驟的處理時間和溫度,亦有產生Ge和InGaAs基板窪陷之可能性。考慮該可能性時,最佳結構之一亦可舉出以下的結構:在虛擬閘極電極3使用a-Si,在虛擬閘極絕緣膜2使用HfAlOx和SiO2。以上所敘述的閘極堆疊,因為硬遮罩4係能夠剝落,使用SiO2和SiN亦無妨,在側壁係以使用能夠容易被HF蝕刻之SiO2等為佳。
如半導體基板1、或半導體基板表面為Si和Si1-XGeX(x<0.7)之Si含量多的半導體層時,因氨藥液引起基板窪陷。因此,作為虛擬閘極6的結構,必須使用與Ge和III-V族不同者。
虛擬閘極絕緣膜2,係可使用能夠被HCl、H3PO4、HF等蝕刻之絕緣膜,其中該等HCl、H3PO4、HF等係不會蝕刻半導體之藥液。例如,可在虛擬閘極絕緣膜2使用能夠被HF蝕刻之SiO2或HfO2、HfAlOx等的high-k膜;能夠被HF、HCl蝕刻之Al2O3、La2O3、LaAlOX等的膜;或是能夠被H3PO4蝕刻之SiN膜。在使用該等虛擬閘極絕緣膜2時,能夠使用a-Si、a-InP、Ni、a-Ge或SiO2或SiN等的絕緣膜作為虛擬閘極電極3。而且,能夠使用NaOH、TMAH、HCl;含有H2O2之NaOH、HCl;HF、或H3PO4來蝕刻虛擬閘極電極3。但是如前述,只有使用Al2O3膜時,不能夠在虛擬閘極電極使用a-Si。因為a-Si、Al2O3、Si會同時被TMAH和NaOH系藥液蝕刻掉,致使產生基板窪陷之緣故。
在上述的結構,係在埋入絕緣膜9使用階梯覆蓋率低、或膜內應力強的SiO2和SiN即可。但是,只有在虛擬
閘極電極3使用SiO2和SiN時,各自埋入絕緣膜必須是不同種的膜,使在除去虛擬閘極電極時,不會產生蝕刻埋入絕緣膜。亦即,在虛擬閘極電極3為SiO2的情況,必須使埋入絕緣膜9為SiN等。最後,硬遮罩4和側壁5係各自能夠使用SiO2、SiN等的絕緣膜。
作為虛擬閘極與埋入絕緣膜之組合,可舉出作為最佳結構的一個例子,係以下的情況:於虛擬閘極絕緣膜2使用SiN,於虛擬閘極電極3使用a-Si,而且於埋入絕緣膜9使用藉由PECVD法所形成之階梯覆蓋率低、或膜內壓縮應力大的SiO2。此時,在藉由HF液形成空隙10之後,能夠藉由TMAH和NH4OH液蝕刻虛擬閘極電極3且能夠形成空孔11。其次,藉由使用熱磷酸將虛擬閘極絕緣膜2除去,能夠不產生基板窪陷而將半導體層露出。
又,可舉出作為最佳結構的另外一個例子,係只有使用SiN形成虛擬閘極(亦即虛擬閘極絕緣膜2及虛擬閘極電極3)之情況。此時,就不必形成側壁而言,而且就形成空隙之後,只要使用H3PO4處理的一個步驟就能夠將虛擬閘極全體剝落且將表面露出而言,係能夠使製程簡略化。
以上,上述的虛擬閘極結構和埋入絕緣膜之條件,係不限定於此,使用其他物質亦無妨。
以下,將在本實施形態之實驗結果顯示在圖2~圖5。在半導體基板1使用Si,在虛擬閘極絕緣膜2使用藉由熱氧化所形成的SiO2(10nm),在虛擬閘極電極3使用多晶Si(70nm),在硬遮罩4使用藉由ALD法所形成的SiN(20nm),
在埋入絕緣膜9使用SiH4氣體(10sccm以T)及N2O氣體(460sccm)且於250℃下藉由PECVD成膜而成的SiO2(250nm)。又,在此,係不進行形成側壁膜5和SD區域。又,只有圖2之虛擬閘極電極3的厚度係顯示與其他為不同的條件,圖3以後係顯示全部上述的條件之結果。
首先,在圖2係顯示剛閘極埋入後之剖面SEM影像,相當於本實施形態的說明圖1(c)。從該圖,得知在閘極側面附近於後來形成空隙10的區域係變為稀疏。其次,將藉由HF處理而形成有空隙10者(相當於圖1(d))顯示在圖3。在此,係進行用以將SiO2蝕刻之HF處理1分鐘。
其次,在圖4、圖5,係顯示為了從空隙10對虛擬閘極電極3的多晶Si進行蝕刻,而將經稀釋後的NH4OH液加熱至45℃且浸漬15分鐘左右之後的剖面SEM影像。圖4係閘極長度~50nm的圖案係以間距500nm所排列而成之剖面影像,確認能夠在全部的閘極圖案,多晶Si係完全被除去。又,在圖5,係使閘極圖案的間距為150nm以下而使用相同蝕刻條件進行多晶Si除去。此時,在閘極間的間隔所存在的埋入SiO2膜亦大致被除去,而且在2μm範圍之圖案係被除去。
從該情形,在任意的閘極長度,藉由如圖6將閘極圖案分割成為比其更微細的閘極圖案,或是分割成為方塊,能夠縮短用以剝落之閘極電極蝕刻時間。
如此,依照本實施形態,藉由在虛擬閘極6的周邊部設置空洞10,利用該空洞10而蝕刻虛擬閘極6的下部,
能夠不使用CMP法而進行取代閘極製程。因此,能夠抑制CMP法成為問題之碟形凹陷和侵蝕、刮痕等基底膜(層間絕緣膜)的面內偏差和缺陷。又,因為不使用CMP法,故可望因製程簡略化而降低製程成本。而且,因為埋入後的閘極形狀成為逆錐體形狀,能夠減低閘極電阻及抑制閘極電極的埋入不良。
圖7(a)~(e)係顯示有關第2實施形態之半導體裝置的製造步驟之剖面圖。本實施形態係製造Fin-FET之方法。首先,如在圖7(a)所顯示,在半導體基板(支撐基板)21上使用微影術及RIE等的蝕刻製程而形成鰭狀(Fin)結構22。在此,在支撐基板21及鰭狀結構22,係可以是將半導體基板21蝕刻加工而形成鰭狀結構22者,亦可以是各自以不同的半導體構成者。例如,亦可以是基板21為Si或Ge,鰭狀結構22係在基板21上,由藉由磊晶成長等所形成的SiGe、Ge、或III-V族化合物所構成者。
其次,如在圖7(b)所顯示,在基板21表面上及鰭狀結構22表面上形成與基板表面為不同的半導體層23。
其次,如在圖7(c)所顯示,在基板21及鰭狀結構22上堆積埋入絕緣膜24且藉由埋入絕緣膜24將鰭狀結構22埋入。該埋入絕緣膜24係與第1實施形態同樣,使用階梯覆蓋率低、或膜內應力大的膜。
其次,如在圖7(d)所顯示,藉由使用濕式蝕刻等的製程,將埋入絕緣膜24的稀疏區域蝕刻而形成空隙25。
藉此,在鰭狀結構22的底部,半導體層23係在空隙25露出。
其次,藉由通過空隙25使用液體或氣體進行蝕刻半導體層23,能夠將在鰭狀結構22上部所堆積的絕緣膜24剝落。藉此,如在圖7(e)所顯示,能夠形成主體鰭狀結構。
此後,雖然未圖示,能夠藉由透過閘極絕緣膜而在鰭狀結構22表面上形成閘極電極,來製造Fin-FET製造。
如此,依照本實施形態,因為在鰭狀結構22的周邊部之基板21上殘留絕緣膜24,透過閘極絕緣膜而在鰭狀結構22形成閘極電極時,能夠將閘極電極接近基板21防患於未然。亦即,藉由存在圖7(e)的絕緣膜24而成為實質的SOI鰭狀結構,能夠有助於提升單元特性。
圖8(a)~(e)係顯示有關第3實施形態之半導體裝置的製造步驟之剖面圖。本實施形態亦是與第2實施形態同樣地為製造Fin-FET之方法。
首先,如在圖8(a)所顯示,至使用微影術及RIE等的蝕刻製程在半導體基板(支撐基板)31上,形成鰭狀結構32為止,係與第2實施形態同樣。在此,亦與第2實施形態同樣地,支撐基板31及鰭狀結構32之構成的半導體係可以相同而且不同亦無妨。
其次,如在圖8(b)所顯示,在基板31及鰭狀結構32上堆積埋入絕緣膜33且藉由階梯覆蓋率低或膜內應力大的埋入絕緣膜33將鰭狀結構32埋入。
其次,如在圖8(c)所顯示,使用濕式蝕刻等的蝕
刻製程,在鰭狀結構的附近之絕緣膜33為稀疏的區域形成空隙34。藉此,鰭狀結構32的底部係在空隙34露出。
其次,如在圖8(d)所顯示,通過空隙34使用濕式蝕刻或氣體蝕刻對鰭狀結構32的下部進行蝕刻,來形成半導體漂浮層35,在形成半導體漂浮層35時,藉由在其兩端預先形成例如SD-Pad區域之比鰭狀結構部更大面積的區域且Pad區域係與支撐基板31連接,能夠將半導體漂浮層35保持在空中。
其次,藉由使用濕式蝕刻等將在半導體漂浮層35的外周部成膜之埋入絕緣膜33除去,能夠得到如在圖8(e)所顯示之半導體漂浮結構。
此後,形成半導體漂浮層35之後,藉由ALD法堆積閘極絕緣膜,而且藉由CVD法堆積閘極電極。然後,藉由使用微影術及RIE等,能夠形成GAA(環繞閘極;Gate all around)的Fin-FET。
如此,依照本實施形態,藉由在鰭狀結構32的周邊部設置空洞34,利用該空洞34而對鰭狀結構32的下部進行蝕刻,能夠形成半導體漂浮層35。然後,藉由在該半導體漂浮層35形成閘極絕緣膜及閘極電極,能夠簡易地製造GAA結構的Fin-FET。
圖9(a)~(c)係顯示有關第4實施形態之半導體裝置的製造步驟之剖面圖。又,與圖8(a)~(e)相同部分係附加相同符號而省略其詳細的說明。
該實施形態係在前面所說明的第3實施形態,在形成半導體漂浮層時之變形例。
如在圖9(a)所顯示,至形成前述圖8(c)的空隙為止係與第3實施形態同樣。其次,如在圖9(b)所顯示,藉由通過空隙34令鰭狀結構下部氧化而形成氧化膜36,能夠形成與基板31為電性分離之半導體層37。藉此,能夠形成模擬SemOI(絕緣層上覆半導體;Semiconductor On Insulator)結構。
其次,如在圖9(c)所顯示,將在半導體層37的外周部所堆積之埋入絕緣膜33除去。此後,藉由在半導體層37表面上透過閘極絕緣膜而形成閘極電極,能夠製造在鰭狀結構32的3面形成有閘極之Fin-FET。
又,在此,在除去埋入絕緣膜33後,半導體層37的下部之氧化膜36係殘留。但是,依照埋入絕緣膜33的種類、及埋入絕緣膜蝕刻條件情形,半導體層37的下部之氧化膜36亦有被除去之情形,且亦有得到與圖8(e)同樣的結構之情況。此時,與第3實施形態同樣地,藉由將鰭狀結構的兩端形成如SD-Pad區域的面積之大的區域,能夠得到半導體漂浮層37。
又,本發明係不被上述的各實施形態限定。在實施形態係使用虛擬閘極絕緣膜及虛擬閘極電極的積層結構作為虛擬閘極,但是虛擬閘極係未必限定於積層結構,亦能夠以單層結構來實現。
而且,對埋入絕緣膜進行蝕刻未必限於濕式蝕刻法,能夠選擇性地蝕刻埋入絕緣膜即可。例如,亦可以是使用氣體之乾式蝕刻法。
又,半導體基板、虛擬閘極、及埋入絕緣膜的材料,進而對埋入絕緣膜進行蝕刻時的蝕刻條件等係能夠按照規格而適當地變更。
已說明本發明的若干實施形態,該等實施形態係作為例子而提示者,而未蓄意限定本發明的範圍。該等實施形態係能夠以其他各式各樣的形態來實施,在不脫離本發明的要旨之範圍,能夠進行各種的省略、調換及變更。該等實施形態和其變形係與被包含在本發明的範圍和要旨同樣地,被包含在申請專利範圍所記載之發明及其均等的範圍。
1‧‧‧半導體基板
2、2'‧‧‧虛擬閘極絕緣膜
3‧‧‧虛擬閘極電極
4‧‧‧硬遮罩
5‧‧‧側壁膜
6‧‧‧虛擬閘極
7‧‧‧延伸區域
8‧‧‧Deep區域(SD區域)
9‧‧‧埋入絕緣膜
10‧‧‧空洞
11‧‧‧空孔
12‧‧‧閘極絕緣膜
13‧‧‧閘極電極
Claims (14)
- 一種半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成虛擬閘極之步驟;在前述基板及前述虛擬閘極上堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述虛擬閘極埋入之步驟;將前述埋入絕緣膜一部分蝕刻而在前述虛擬閘極的周邊部形成空隙之步驟;對因形成前述空隙而露出的前述虛擬閘極進行蝕刻,藉以將前述虛擬閘極及該虛擬閘極上的前述埋入絕緣膜除去之步驟;及透過閘極絕緣膜在因除去前述虛擬閘極而露出的前述基板上形成閘極電極之步驟。
- 如請求項1之半導體裝置之製造方法,其中形成前述虛擬閘極之步驟,在前述基板上形成虛擬閘極絕緣膜及虛擬閘極電極的積層結構之後,將前述虛擬閘極電極加工形成閘極圖案。
- 如請求項1之半導體裝置之製造方法,其中藉由前述埋入絕緣膜將前述虛擬閘極埋入之步驟,係使埋入絕緣膜從前述基板表面側及前述虛擬閘極表面側成長;形成前述空隙之步驟,係藉由濕式蝕刻法沿著前述埋入絕緣膜從前述基板表面成長的部分、與從前述虛擬閘極表面成長的部分之界線,蝕刻前述埋入絕緣膜。
- 如請求項2之半導體裝置之製造方法,其中前述基板係 Si基板;在前述虛擬閘極絕緣膜使用SiN或SiO2,在前述虛擬閘極電極使用a-Si,在前述埋入絕緣膜使用SiO2膜;在前述埋入絕緣膜形成空隙時使用氟酸,在將前述虛擬閘極電極除去時使用氨或TMAH,在將前述虛擬閘極絕緣膜除去時使用磷酸。
- 如請求項2之半導體裝置之製造方法,其中前述基板係III-V族化合物半導體;在前述虛擬閘極絕緣膜使用Al2O3或SiO2,在前述虛擬閘極電極使用a-Si,在前述埋入絕緣膜使用SiO2膜;在前述埋入絕緣膜形成空隙時使用氟酸,在將前述虛擬閘極電極除去時使用氨或TMAH,在將前述虛擬閘極絕緣膜除去時使用鹽酸或氨藥液。
- 如請求項1之半導體裝置之製造方法,其中前述埋入絕緣膜,係使用堆積成為預定段差形狀之後,藉由液相或氣相蝕刻在相對前述基板表面呈傾斜的方向形成空隙之絕緣膜。
- 一種半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成鰭狀結構之步驟;在前述基板及前述鰭狀結構的表面上,形成與前述基板不同的半導體層之步驟;在形成有前述半導體層之前述基板及前述鰭狀結構上,堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述鰭狀結構埋入之步驟; 將前述埋入絕緣膜一部分蝕刻而在前述鰭狀結構的周邊部形成空隙之步驟;及從因前述空隙而露出的前述鰭狀結構下部,對在前述鰭狀結構的外周成膜而成之前述半導體層進行蝕刻,藉以除去前述鰭狀結構外周部的前述半導體層及前述鰭狀結構上部的前述埋入絕緣膜之步驟。
- 一種半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成鰭狀結構之步驟;在前述基板及前述鰭狀結構上堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述鰭狀結構埋入之步驟;將前述埋入絕緣膜一部分蝕刻而在前述鰭狀結構的周邊部形成空隙之步驟;及對因前述空隙而露出的前述鰭狀結構下部進行蝕刻,使前述鰭狀結構上部從前述基板漂浮之步驟。
- 一種半導體裝置之製造方法,其特徵在於包含:在半導體基板上形成鰭狀結構之步驟;在前述基板及前述鰭狀結構上堆積埋入絕緣膜且藉由前述埋入絕緣膜將前述鰭狀結構埋入之步驟;將前述埋入絕緣膜一部分蝕刻而在前述鰭狀結構的周邊部形成空隙之步驟;及令因前述空隙而露出的前述鰭狀結構下部氧化,使前述鰭狀結構與前述基板電性分離之步驟。
- 如請求項7至9項中任一項之半導體裝置之製造方法,其中藉由前述埋入絕緣膜將前述鰭狀結構埋入之步驟,係 使埋入絕緣膜從前述基板表面側及前述鰭狀結構表面側成長;形成前述空隙之步驟,係藉由濕式蝕刻法沿著前述埋入絕緣膜從前述基板表面成長的部分、與從前述鰭狀結構表面成長的部分之界線,蝕刻前述埋入絕緣膜。
- 如請求項7至9項中任一項之半導體裝置之製造方法,其中前述鰭狀結構係與前述基板相同材料或是在前述基板上磊晶成長而成之SiGe層、Ge層、或III-V族化合物半導體層。
- 如請求項7至9項中任一項之半導體裝置之製造方法,其中前述埋入絕緣膜,係使用階梯覆蓋率為預定值以下的膜、或是膜內壓縮應力為90MPa以上的絕緣膜。
- 如請求項12項之半導體裝置之製造方法,其中前述埋入絕緣膜係使用SiO2膜,該SiO2膜係藉由PECVD法且使用SiH4氣體及N2O氣體在小於300℃的溫度下成膜。
- 如請求項7至9項中任一項之半導體裝置之製造方法,其中前述埋入絕緣膜,係使用堆積成為預定段差形狀之後,藉由液相或氣相蝕刻在相對前述基板表面呈傾斜的方向形成空隙之絕緣膜。
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