TW201423759A - Reference cell circuit and method of producing a reference current - Google Patents
Reference cell circuit and method of producing a reference current Download PDFInfo
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本發明係關於一種參考單元電路，特別係關於一種包括複數具有紫外線閾值電壓之浮閘電晶體的參考單元電路。 The present invention relates to a reference cell circuit, and more particularly to a reference cell circuit including a plurality of floating gate transistors having ultraviolet threshold voltages.
可電性抹除以及編程的非易失性記憶體(non-volatile memory device)係將電荷儲存在浮閘電晶體(floating-gate transistor)中，以儲存資料。浮閘電晶體具有一浮置閘極，電荷可藉由既定之方式注入(injected into)以及抽離(evacuates from)浮閘電晶體之浮置閘極，其中浮閘中之電荷會影響場效電晶體之閾值大小。舉例而言，當電子注入浮閘時，所注入的電子會提高場效電晶體之閾值。 An electrically erasable and programmed non-volatile memory device stores charge in a floating-gate transistor to store data. The floating gate transistor has a floating gate, and the charge can be injected into and evacuated from the floating gate of the floating gate transistor, wherein the charge in the floating gate affects the field effect The threshold size of the transistor. For example, when electrons are injected into the floating gate, the injected electrons increase the threshold of the field effect transistor.
此外，非易失性記憶體需要具有優異的數據保留(data retention)能力。隨著製程技術的進步，非易失性記憶體越來越難以實現優異之數據保留能力。有鑑於此，本發明提供一種裝置和方法，以在製程技術的進步中，達成非易失性記憶體對優異的數據保留能力之需求。 In addition, non-volatile memory needs to have excellent data retention capabilities. With advances in process technology, it is increasingly difficult for non-volatile memory to achieve superior data retention. In view of this, the present invention provides an apparatus and method for achieving a demand for excellent data retention capability of a nonvolatile memory in advances in process technology.
本發明提供一種參考單元電路，適用於一非易失性記憶體。參考單元電路包括一參考單元陣列、一第一電流鏡電路以及一第二電流鏡電路。參考單元陣列包括至少一列浮閘電晶體，用以產生一參考電流。第一電流鏡電路用以 根據上述參考單元陣列所產生之上述參考電流，產生一鏡射電流。第二電流鏡電路用以接收上述鏡射電流，並根據上述鏡射電流以及複數致能訊號中之一被選取者，產生一已調整參考電流，其中上述致能訊號分別相應於上述非易失性記憶體之複數操作，並且上述已調整參考電流係用以決定上述非易失性記憶體之複數記憶體單元的邏輯狀態。 The invention provides a reference unit circuit suitable for use in a non-volatile memory. The reference unit circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one column of floating gate transistors for generating a reference current. The first current mirror circuit is used A mirror current is generated based on the reference current generated by the reference cell array. The second current mirror circuit is configured to receive the mirror current, and generate an adjusted reference current according to one of the mirror current and the plurality of enable signals, wherein the enable signals respectively correspond to the nonvolatile The plural operation of the memory, and the adjusted reference current is used to determine the logic state of the plurality of memory cells of the non-volatile memory.
本發明另提供一種用以產生參考電流之方法，適用於一參考單元電路。用以產生參考電流之方法包括藉由一參考單元陣列產生一參考電流，其中上述參考單元陣列包括至少一列浮閘電晶體；鏡射上述參考電流，並藉以產生一鏡射電流；以及根據複數致能訊號中之一被選取者，鏡射上述鏡射電流，並藉以產生一已調整參考電流，其中每一上述致能訊號分別相應於一非易失性記憶體之複數操作，並且上述已調整參考電流係用以決定上述非易失性記憶體之複數記憶體單元的邏輯狀態。 The present invention further provides a method for generating a reference current suitable for use in a reference unit circuit. The method for generating a reference current includes generating a reference current by a reference cell array, wherein the reference cell array includes at least one column of floating gate transistors; mirroring the reference current to generate a mirror current; and generating a mirror current according to the complex number A selected one of the signal signals, mirroring the mirror current, and generating an adjusted reference current, wherein each of the enabling signals respectively corresponds to a plurality of non-volatile memory operations, and the above adjustment The reference current is used to determine the logic state of the complex memory cells of the non-volatile memory.
以下將詳細討論本發明各種實施例之裝置及使用方法。然而值得注意的是，本發明所提供之許多可行的發明概念可實施在各種特定範圍中。這些特定實施例僅用於舉例說明本發明之裝置及使用方法，但非用於限定本發明之範圍。 The apparatus and method of use of various embodiments of the present invention are discussed in detail below. However, it is to be noted that many of the possible inventive concepts provided by the present invention can be implemented in various specific ranges. These specific examples are only intended to illustrate the apparatus and methods of use of the present invention, but are not intended to limit the scope of the invention.
第1圖為本發明所提供之一參考單元電路之方塊圖，其中參考單元電路100適用於一非易失性記憶體(未圖示)，並且非易失性記憶體具有複數記憶體單元。參考單元 電路100包括一參考單元陣列102，複數感測電晶體1041~104N，一第一電流鏡電路(current mirror circuit)105，一第二電流鏡電路106，以及一選擇裝置110。 1 is a block diagram of a reference unit circuit provided by the present invention, wherein the reference unit circuit 100 is applied to a non-volatile memory (not shown), and the non-volatile memory has a complex memory unit. Reference unit The circuit 100 includes a reference cell array 102, a plurality of sensing transistors 1041 104104N, a first current mirror circuit 105, a second current mirror circuit 106, and a selection device 110.
參考單元陣列102係用以產生一參考電流Irc。參考單元陣列102包括至少一列1021-102N之浮閘電晶體，其中每一列1021-102N中之浮閘電晶體具有複數浮閘電晶體1031-103N。每一浮閘電晶體1031-103N具有一第一端分別耦接至感測電晶體1041~104N，一第二端耦接至接地GND，以及一閘極耦接至一參考字元線REFWL。值得注意的是參考單元陣列102係為紫外線閾值基礎之參考單元。換言之，參考單元陣列102之浮閘電晶體1031-103N具有一閾值電壓，並且該閾值電壓係為一紫外線閾值電壓。由於參考單元陣列102係為紫外線基礎的，故參考單元陣列102不需要相應於程式化以及抹除功能之相關電路，使得本實施例之電路佈局的面積小於傳統電路之佈局，並且所需之測試時間亦小於傳統電路的測試時間。在另一實施例中，在從半導體製造廠製造為用於半導體製造的矽晶片(for semiconductor manufacture，FBA)後，參考單元陣列102中之浮閘電晶體1031-103N的閾值電壓，已被抹除或者程式化至一既定紫外線閾值電壓，以決定參考電壓。在另一實施例中，參考單元陣列102已經由紫外線，被抹除至一既定紫外線閾值電壓。另外，浮閘電晶體1031-103N亦經由程式化或者抹除，使得其電壓位準接***均紫外線閾值電壓，其中該平均紫外線閾值電壓係為既定紫外線閾值電壓。有鑑於此，浮閘電晶體1031-103N之數量可被縮減。 舉例而言，參考單元陣列102可僅包括四個浮閘電晶體1031-1034，但本發明不限於此。 The reference cell array 102 is used to generate a reference current Irc. The reference cell array 102 includes at least one column of 1021-102N floating gate transistors, wherein the floating gate transistors in each of the columns 1021-102N have a plurality of floating gate transistors 1031-103N. Each of the floating gates 1031-103N has a first end coupled to the sensing transistors 1041 104104N, a second end coupled to the ground GND, and a gate coupled to a reference word line REFWL. It is worth noting that the reference cell array 102 is a reference unit based on the UV threshold. In other words, the floating gate transistors 1031-103N of the reference cell array 102 have a threshold voltage, and the threshold voltage is a UV threshold voltage. Since the reference cell array 102 is UV-based, the reference cell array 102 does not require an associated circuit corresponding to the staging and erasing functions, so that the area of the circuit layout of the present embodiment is smaller than that of the conventional circuit, and the required test The time is also less than the test time of the traditional circuit. In another embodiment, the threshold voltage of the floating gate transistors 1031-103N in the reference cell array 102 has been erased after being fabricated from a semiconductor fabrication facility for semiconductor fabrication (FBA). In addition to or programmed to a predetermined UV threshold voltage to determine the reference voltage. In another embodiment, the reference cell array 102 has been erased to a predetermined ultraviolet threshold voltage by ultraviolet light. In addition, the floating gate crystals 1031-103N are also programmed or erased such that their voltage levels are close to the average ultraviolet threshold voltage, wherein the average ultraviolet threshold voltage is a predetermined ultraviolet threshold voltage. In view of this, the number of floating gate transistors 1031-103N can be reduced. For example, the reference cell array 102 may include only four floating gate crystals 1031-1034, but the invention is not limited thereto.
感測電晶體1041~104N耦接於參考單元陣列102以及第一電流鏡電路105之間。每一感測電晶體1041~104N具有一第一端分別耦接至每一列1021-102N之每一浮閘電晶體1031-103N的第一端，一第二端耦接至第一P型電晶體1051，以及一閘極耦接至一選擇致能線YSEN。值得注意的是，本發明中之P型電晶體以及N型電晶體可為P型以及N型之雙極性電晶體，或者P型以及N型之場效電晶體。 The sensing transistors 1041 104104N are coupled between the reference cell array 102 and the first current mirror circuit 105. Each of the sensing transistors 1041 - 104N has a first end coupled to a first end of each of the floating gate transistors 1031-103N of each of the columns 1021-102N, and a second end coupled to the first P-type The crystal 1051 and a gate are coupled to a selection enable line YSEN. It should be noted that the P-type transistor and the N-type transistor in the present invention may be P-type and N-type bipolar transistors, or P-type and N-type field effect transistors.
第一電流鏡電路105係用以根據參考電流Irc，產生一鏡射電流Imc。第一電流鏡電路105包括一第一P型電晶體1051以及一第二P型電晶體1052。第一P型電晶體1051具有一源極耦接至一電壓VDD1，一汲極耦接至感測電晶體1041~104N，以及一閘極耦接至汲極。第二P型電晶體1052具有一源極耦接至電壓VDD1，一汲極耦接至第二電流鏡電路106中之第一N型電晶體1061的汲極，以及一閘極耦接至第一P型電晶體1051之閘極。 The first current mirror circuit 105 is configured to generate a mirror current Imc according to the reference current Irc. The first current mirror circuit 105 includes a first P-type transistor 1051 and a second P-type transistor 1052. The first P-type transistor 1051 has a source coupled to a voltage VDD1, a drain coupled to the sense transistors 1041 104104N, and a gate coupled to the drain. The second P-type transistor 1052 has a source coupled to the voltage VDD1, a drain coupled to the drain of the first N-type transistor 1061 in the second current mirror circuit 106, and a gate coupled to the first The gate of a P-type transistor 1051.
值得注意的是第一P型電晶體1051具有一長寬比(W/L)，以及第一P型電晶體1051之長寬比係為浮閘電晶體1031-103N之長寬比的X倍，其中X係為浮閘電晶體1031-103N之數量。舉例而言，當參考單元陣列102包括30個浮閘電晶體1031-10330並且浮閘電晶體1031-103N之長寬比係為1時，第一P型電晶體1051之長寬比係為30。當參考單元陣列102包括60個浮閘電晶體1031-10360並且浮閘電晶體1031-103N之長寬比係為2時，第一P型電 晶體1051之長寬比係為120，依此類推。另外，第二P型電晶體1052具有與浮閘電晶體1031-103N相同之長寬比(W/L)，但本發明不限於此。 It is worth noting that the first P-type transistor 1051 has an aspect ratio (W/L), and the aspect ratio of the first P-type transistor 1051 is X times the aspect ratio of the floating gate crystal 1031-103N. Where X is the number of floating gate transistors 1031-103N. For example, when the reference cell array 102 includes 30 floating gate crystals 1031-10330 and the aspect ratio of the floating gate crystals 1031-103N is 1, the aspect ratio of the first P-type transistor 1051 is 30. . When the reference cell array 102 includes 60 floating gate transistors 1031-10360 and the aspect ratio of the floating gate transistors 1031-103N is 2, the first P-type electricity The aspect ratio of the crystal 1051 is 120, and so on. In addition, the second P-type transistor 1052 has the same aspect ratio (W/L) as the floating gate crystals 1031-103N, but the present invention is not limited thereto.
第二電流鏡電路106係用以接收鏡射電流Imc，並根據鏡射電流Imc以及致能訊號EN1~ENN中之一者，產生一已調整參考電流Iarc，其中致能訊號EN1~ENN分別相應於非易失性記憶體之複數操作，並且已調整參考電流Iarc係用以決定非易失性記憶體之複數記憶體單元的邏輯狀態。第二電流鏡電路106包括第一N型電晶體1061以及複數控制電路10621~1062N。第一N型電晶體1061具有一汲極耦接至第一電流鏡電路105之第二P型電晶體1052的汲極，一源極耦接至接地GND，以及一閘極耦接至源極。控制電路10621~1062N係用以根據致能訊號EN1~ENN，鏡射鏡射電流Imc以分別產生至少一支電流I1~IN，其中已調整參考電流Iarc係為所產生之支電流的總合。換言之，致能訊號EN1~ENN係用以分別致能控制電路10621~1062N，以分別產生支電流I1~IN。每一控制電路10621~1062N包括一第二N型電晶體1063以及一第三N型電晶體1064。第二N型電晶體1063具有一汲極耦接至第三N型電晶體1064，一源極耦接至接地GND，以及一閘極耦接至第一N型電晶體1061之閘極。第三N型電晶體1064具有一汲極耦接至電壓VDD2，一源極耦接至第二N型電晶體1063之汲極，以及一閘極用以接收致能訊號EN1~ENN中之一者。值得注意的是，電壓VDD2與電壓VDD1在本實施例中係不相同的。在另一實施例中，電壓 VDD2可相同於電壓VDD1，但本發明不限於此。 The second current mirror circuit 106 is configured to receive the mirror current Imc and generate an adjusted reference current Iarc according to one of the mirror current Imc and the enable signals EN1~ENN, wherein the enable signals EN1~ENN respectively correspond The complex operation of the non-volatile memory, and the adjusted reference current Iarc is used to determine the logic state of the complex memory cells of the non-volatile memory. The second current mirror circuit 106 includes a first N-type transistor 1061 and a plurality of control circuits 10621~1062N. The first N-type transistor 1061 has a drain coupled to the drain of the second P-type transistor 1052 of the first current mirror circuit 105, a source coupled to the ground GND, and a gate coupled to the source . The control circuit 10621~1062N is configured to mirror the mirror current Imc to generate at least one current I1~IN according to the enable signals EN1~ENN, wherein the adjusted reference current Iarc is the sum of the generated branch currents. In other words, the enable signals EN1~ENN are used to respectively enable the control circuits 10621~1062N to generate the branch currents I1~IN, respectively. Each control circuit 10621~1062N includes a second N-type transistor 1063 and a third N-type transistor 1064. The second N-type transistor 1063 has a gate coupled to the third N-type transistor 1064, a source coupled to the ground GND, and a gate coupled to the gate of the first N-type transistor 1061. The third N-type transistor 1064 has a drain coupled to the voltage VDD2, a source coupled to the drain of the second N-type transistor 1063, and a gate for receiving one of the enable signals EN1~ENN. By. It is worth noting that the voltage VDD2 and the voltage VDD1 are different in this embodiment. In another embodiment, the voltage VDD2 may be the same as the voltage VDD1, but the invention is not limited thereto.
值得注意的是，第一N型電晶體1061具有一長寬比(W/L)，該長寬比係第二電流鏡電路106中之控制電路10621中的第二N型電晶體1063之長寬比的16倍。因此，已調整參考電流Iarc之精準度(accuracy)係為鏡射電流Imc之1/16，但本發明不限於此。舉例而言，當第一N型電晶體1061之長寬比為控制電路10621中之第二N型電晶體1063的長寬比之4倍時，已調整參考電流Iarc之精準度係鏡射電流Imc之1/4。當第一N型電晶體1061之長寬比為控制電路10621中之第二N型電晶體1063的長寬比之8倍時，已調整參考電流Iarc之精準度係鏡射電流Imc之1/8，依此類推。 It should be noted that the first N-type transistor 1061 has an aspect ratio (W/L) which is the length of the second N-type transistor 1063 in the control circuit 10621 in the second current mirror circuit 106. 16 times wider than the width. Therefore, the accuracy of the adjusted reference current Iarc is 1/16 of the mirror current Imc, but the present invention is not limited thereto. For example, when the aspect ratio of the first N-type transistor 1061 is 4 times the aspect ratio of the second N-type transistor 1063 in the control circuit 10621, the accuracy of the adjusted reference current Iarc is a mirror current. 1/4 of Imc. When the aspect ratio of the first N-type transistor 1061 is 8 times the aspect ratio of the second N-type transistor 1063 in the control circuit 10621, the accuracy of the adjusted reference current Iarc is 1/ of the mirror current Imc. 8, and so on.
另外，每一控制電路10621~1062N中之第二N型電晶體1063具有一長寬比(W/L)，其中每一第二N型電晶體1063之長寬比彼此不同並相差2的n次冪。舉例而言，控制電路10621之第二N型電晶體1063的長寬比可為20，控制電路10622之第二N型電晶體1063的長寬比可為21，控制電路10623之第二N型電晶體1063的長寬比可為22，控制電路1062N之第二N型電晶體1063的長寬比可為2n，依此類推。值得注意的是，每一支電流I1~IN彼此不同，並由於控制電路10621~1062N中第二N型電晶體1063之長寬比的差異，每一支電流I1~IN亦彼此相差2的n次冪。 In addition, the second N-type transistor 1063 of each of the control circuits 10621~1062N has an aspect ratio (W/L), wherein the length-to-width ratio of each of the second N-type transistors 1063 is different from each other and differs by 2 n. Power. For example, the second N-type transistor control circuit 1063 to 10621 of the aspect ratio may be 20, second N-type transistor control circuit 1063 to 10622 of the aspect ratio may be 21, the control circuit 10623 of the second The aspect ratio of the N-type transistor 1063 can be 2 2 , and the aspect ratio of the second N-type transistor 1063 of the control circuit 1062N can be 2 n , and so on. It is worth noting that each of the currents I1 to IN is different from each other, and because of the difference in the aspect ratio of the second N-type transistor 1063 in the control circuits 10621 to 1062N, each of the currents I1 to IN is also different from each other by 2 n. Power.
在本實施例中，每一致能訊號EN1~ENN係為一二進制碼，並且二進制碼中之每一位元<n：0>係用以分別提供至第二電流鏡電路106中之每一第三N型電晶體1064的 閘極，以分別控制控制電路10621~1062N是否進行導通，但本發明不限於此。值得注意的是，非易失性記憶體(未圖示)之操作包括確認非易失性記憶體之記憶體單元的一低閾值電壓(low threshold voltage)，正常讀取(normal reading)非易失性記憶體之記憶體單元，確認非易失性記憶體之記憶體單元的一高閾值電壓(high threshold voltage)，以及確認非易失性記憶體之記憶體單元的一後程式化閾值電壓(post program threshold voltage)等等，本發明不加以限制。 In this embodiment, each of the uniform energy signals EN1~ENN is a binary code, and each bit <n:0> in the binary code is respectively provided to each of the second current mirror circuits 106. Three N-type transistor 1064 The gates are respectively controlled to control whether or not the control circuits 10621 to 1062N are turned on, but the present invention is not limited thereto. It should be noted that the operation of the non-volatile memory (not shown) includes confirming a low threshold voltage of the memory unit of the non-volatile memory, and normal reading is not easy. a memory unit of the memory of the memory, confirming a high threshold voltage of the memory unit of the non-volatile memory, and confirming a post-programmed threshold voltage of the memory unit of the non-volatile memory (post program threshold voltage) and the like, the invention is not limited.
選擇裝置110係用以根據非易失性記憶體之操作，選擇致能訊號EN1~ENN中之一者，以及提供所選擇之致能訊號至第二電流鏡電路106。換言之，選擇裝置110係用以根據非易失性記憶體之操作，選擇致能訊號EN1~ENN中之一者，並提供被選擇之致能訊號至每一控制電路10621~1062N中之第三N型電晶體1064的閘極。舉例而言，當參考單元電路100被致能以產生已調整參考電流Iarc時，選擇裝置110根據非易失性記憶體之操作，選擇致能訊號EN1~ENN中之一者，選擇致能線YSEN致使感測電晶體1041~104N導通，並且參考字元線REFWL致使每一列1021-102N之浮閘電晶體1031-103N導通。因此，參考單元陣列102在第一電流鏡電路105之第一P型電晶體1051上產生參考電流Irc，並且第一電流鏡電路105鏡射參考電流Irc以在第二P型電晶體1052上產生鏡射電流Imc，其中由於第一P型電晶體1051以及第二P型電晶體1052之長寬比的差異，鏡射電流Imc係為參考電流Irc之1/X倍。值得注意的是，X係為參考單元陣列102中之浮閘電 晶體的數量。接著，第二電流鏡電路106中之第一N型電晶體1061接收鏡射電流Imc，並且第二電流鏡電路106將鏡射電流Imc鏡射至被致能訊號所致能之控制電路上。最後，被致能之控制電路分別產生支電流，使得已調整參考電流Iarc產生於第二電流鏡電路106上。 The selecting device 110 is configured to select one of the enable signals EN1~ENN according to the operation of the non-volatile memory, and provide the selected enable signal to the second current mirror circuit 106. In other words, the selecting device 110 is configured to select one of the enable signals EN1~ENN according to the operation of the non-volatile memory, and provide the selected enable signal to the third of each control circuit 10621~1062N. The gate of the N-type transistor 1064. For example, when the reference unit circuit 100 is enabled to generate the adjusted reference current Iarc, the selection device 110 selects one of the enable signals EN1~ENN according to the operation of the non-volatile memory, and selects the enable line. YSEN causes the sense transistors 1041~104N to turn on, and the reference word line REFWL causes the floating gate transistors 1031-103N of each column 1021-102N to conduct. Therefore, the reference cell array 102 generates a reference current Irc on the first P-type transistor 1051 of the first current mirror circuit 105, and the first current mirror circuit 105 mirrors the reference current Irc to be generated on the second P-type transistor 1052. The mirror current Imc, in which the mirror current Imc is 1/X times the reference current Irc due to the difference in the aspect ratio of the first P-type transistor 1051 and the second P-type transistor 1052. It is worth noting that the X system is the floating gate in the reference cell array 102. The number of crystals. Next, the first N-type transistor 1061 in the second current mirror circuit 106 receives the mirror current Imc, and the second current mirror circuit 106 mirrors the mirror current Imc onto the control circuit enabled by the enable signal. Finally, the enabled control circuit generates a branch current, respectively, such that the adjusted reference current Iarc is generated on the second current mirror circuit 106.
第2圖為本發明所提供之另一參考單元電路之方塊圖，其中參考單元電路200適用於一非易失性記憶體(未圖示)，非易失性記憶體具有複數記憶體單元。參考單元電路200相似於第1圖所示之參考單元電路100，不同之處在於參考單元電路200更包括一電流電壓轉換器108。 2 is a block diagram of another reference unit circuit provided by the present invention, wherein the reference unit circuit 200 is applied to a non-volatile memory (not shown), and the non-volatile memory has a complex memory unit. The reference unit circuit 200 is similar to the reference unit circuit 100 shown in FIG. 1 except that the reference unit circuit 200 further includes a current-voltage converter 108.
電流電壓轉換器108用以將已調整參考電流Iarc轉換為一已調整參考電壓Varc，其中已調整參考電壓Varc用以提供至一輸出節點OUT。電流電壓轉換器108包括一P型電晶體1082，一N型電晶體1084，以及一反相器1086。P型電晶體1082具有一源極耦接至電壓VDD2，一汲極耦接至輸出節點OUT，以及一閘極耦接至汲極。值得注意的是，在本實施例中，電壓VDD2與電壓VDD1係不相同的。在另一實施例中，電壓VDD2相同於電壓VDD1，但本發明不限於此。N型電晶體1084具有一汲極耦接至P型電晶體1082之汲極，一源極耦接至第二電流鏡電路106，以及一閘極耦接至反相器1086。反相器1086具有一輸入端耦接至N型電晶體1084之源極，以及一輸出端耦接至N型電晶體1084之閘極。 The current-to-voltage converter 108 is configured to convert the adjusted reference current Iarc into an adjusted reference voltage Varc, wherein the adjusted reference voltage Varc is provided to an output node OUT. Current-to-voltage converter 108 includes a P-type transistor 1082, an N-type transistor 1084, and an inverter 1086. The P-type transistor 1082 has a source coupled to the voltage VDD2, a drain coupled to the output node OUT, and a gate coupled to the drain. It should be noted that in the present embodiment, the voltage VDD2 is different from the voltage VDD1. In another embodiment, the voltage VDD2 is the same as the voltage VDD1, but the invention is not limited thereto. The N-type transistor 1084 has a drain coupled to the drain of the P-type transistor 1082, a source coupled to the second current mirror circuit 106, and a gate coupled to the inverter 1086. The inverter 1086 has an input coupled to the source of the N-type transistor 1084 and an output coupled to the gate of the N-type transistor 1084.
在本實施例中，當參考單元電路200被致能並產生已調整參考電壓Varc時，選擇裝置110根據非易失性記憶體 之操作，選擇致能訊號EN1~ENN中之一者，選擇致能線YSEN致使感測電晶體1041~104N導通，並且參考字元線REFWL致使每一列1021-102N之浮閘電晶體1031-103N導通。因此，參考單元陣列102在第一電流鏡電路105之第一P型電晶體1051上，產生一參考電流Irc，並且第一電流鏡電路105鏡射參考電流Irc並在第二P型電晶體1052上產生鏡射電流Imc，其中由於第一P型電晶體1051以及第二P型電晶體1052之長寬比的差異，鏡射電流Imc係為參考電流Irc之1/X倍。值得注意的是，X係為參考單元陣列102中之浮閘電晶體的數量。接著，第二電流鏡電路106之第一N型電晶體1061接收鏡射電流Imc，並且第二電流鏡電路106將鏡射電流Imc鏡射至被致能訊號所致能之控制電路上。被致能之控制電路分別產生支電流，使得已調整參考電流Iarc產生於電流電壓轉換器108上。最後，電流電壓轉換器108將已調整參考電流Iarc轉換為已調整參考電壓Varc，並將已調整參考電壓Varc提供至輸出節點OUT。 In the present embodiment, when the reference unit circuit 200 is enabled and generates the adjusted reference voltage Varc, the selection device 110 is based on the non-volatile memory. Operation, selecting one of the enable signals EN1~ENN, selecting the enable line YSEN causes the sense transistors 1041~104N to be turned on, and the reference word line REFWL causes the floating gate transistors 1031-103N of each column 1021-102N Turn on. Therefore, the reference cell array 102 generates a reference current Irc on the first P-type transistor 1051 of the first current mirror circuit 105, and the first current mirror circuit 105 mirrors the reference current Irc and is in the second P-type transistor 1052. The mirror current Imc is generated, wherein the mirror current Imc is 1/X times the reference current Irc due to the difference in the aspect ratio of the first P-type transistor 1051 and the second P-type transistor 1052. It is worth noting that X is the number of floating gate transistors in the reference cell array 102. Next, the first N-type transistor 1061 of the second current mirror circuit 106 receives the mirror current Imc, and the second current mirror circuit 106 mirrors the mirror current Imc to the control circuit enabled by the enable signal. The enabled control circuit generates a branch current, respectively, such that the adjusted reference current Iarc is generated on the current-to-voltage converter 108. Finally, the current-to-voltage converter 108 converts the adjusted reference current Iarc into the adjusted reference voltage Varc and provides the adjusted reference voltage Varc to the output node OUT.
第3圖為本發明所提供之一產生參考電流方法的流程圖，其中產生參考電流方法適用於第1圖所示之參考單元電路100。流程開始於步驟S300。 FIG. 3 is a flow chart of a method for generating a reference current according to the present invention, wherein the method of generating a reference current is applied to the reference unit circuit 100 shown in FIG. 1. The flow begins in step S300.
在步驟300中，選擇裝置110根據非易失性記憶體之操作，選擇致能訊號EN1~ENN中之一者，並且當參考單元電路200被致能以產生已調整參考電流Iarc時，包括至少一列1021-102N之浮閘電晶體的參考單元陣列102被選擇致能線YSEN以及參考字元線REFWL所致能，其中複 數致能訊號EN1~ENN分別相應於非易失性記憶體之複數操作，並且非易失性記憶體具有複數記憶體單元。值得注意的是，非易失性記憶體(未圖示)之操作包括確認非易失性記憶體之記憶體單元的一低閾值電壓(low threshold voltage)，正常讀取(normal reading)非易失性記憶體之記憶體單元，確認非易失性記憶體之記憶體單元的一高閾值電壓(high threshold voltage)，以及確認非易失性記憶體之記憶體單元的一後程式化閾值電壓(post program threshold voltage)等等，本發明不加以限制。 In step 300, the selection device 110 selects one of the enable signals EN1~ENN according to the operation of the non-volatile memory, and when the reference unit circuit 200 is enabled to generate the adjusted reference current Iarc, including at least The reference cell array 102 of a row of 1021-102N floating gate transistors is selected by the enable line YSEN and the reference word line REFWL, wherein The digital signals EN1~ENN correspond to the complex operation of the non-volatile memory, respectively, and the non-volatile memory has a complex memory unit. It should be noted that the operation of the non-volatile memory (not shown) includes confirming a low threshold voltage of the memory unit of the non-volatile memory, and normal reading is not easy. a memory unit of the memory of the memory, confirming a high threshold voltage of the memory unit of the non-volatile memory, and confirming a post-programmed threshold voltage of the memory unit of the non-volatile memory (post program threshold voltage) and the like, the invention is not limited.
接著，在步驟S302中，選擇裝置110提供被選擇之致能訊號至控制電路10621~1062N。值得注意的是，每一致能訊號EN1~ENN係為一二進制碼，並且二進制碼中之每一位元<n：0>係用以分別提供至第二電流鏡電路106中之控制電路10621-1062N，以分別控制控制電路10621~1062N是否進行導通，但本發明不限於此。另外，已致能之參考單元陣列102產生一參考電流Irc，其中參考單元陣列102中之浮閘電晶體1031-103N具有一閾值電壓，該閾值電壓係為一紫外線閾值電壓。在另一實施例中，在從半導體製造廠製造為用於半導體製造的矽晶片(for semiconductor manufacture，FBA)後，參考單元陣列102中之浮閘電晶體1031-103N的閾值電壓，已被抹除或者程式化至一既定紫外線閾值電壓，以決定參考電壓。另外，浮閘電晶體1031-103N亦經由程式化或者抹除，使得其電壓位準接***均紫外線閾值電壓。因此，浮閘電晶體1031-103N之數量可被縮減。舉例而言，參考單元陣列102可僅包括四個 浮閘電晶體1031-1034，但本發明不限於此。 Next, in step S302, the selection device 110 provides the selected enable signal to the control circuits 10621~1062N. It should be noted that each of the consistent energy signals EN1~ENN is a binary code, and each bit <n:0> in the binary code is provided to the control circuit 10621 in the second current mirror circuit 106, respectively. 1062N to control whether the control circuits 10621 to 1062N are turned on, respectively, but the present invention is not limited thereto. In addition, the enabled reference cell array 102 generates a reference current Irc, wherein the floating gate transistors 1031-103N in the reference cell array 102 have a threshold voltage, which is a UV threshold voltage. In another embodiment, the threshold voltage of the floating gate transistors 1031-103N in the reference cell array 102 has been erased after being fabricated from a semiconductor fabrication facility for semiconductor fabrication (FBA). In addition to or programmed to a predetermined UV threshold voltage to determine the reference voltage. In addition, the floating gate transistors 1031-103N are also programmed or erased such that their voltage levels are close to the average ultraviolet threshold voltage. Therefore, the number of floating gate transistors 1031-103N can be reduced. For example, the reference cell array 102 may include only four The floating gate crystals 1031-1034, but the invention is not limited thereto.
接著，在步驟S304中，第一電流鏡電路105鏡射參考電流Irc，並藉以產生一鏡射電流Imc。值得注意的是，由於第一電流鏡電路105之第一P型電晶體1051以及第二P型電晶體1052之長寬比的差異，鏡射電流Imc係為參考電流Irc之1/X倍。X係為參考單元陣列102中之浮閘電晶體的數量。 Next, in step S304, the first current mirror circuit 105 mirrors the reference current Irc and thereby generates a mirror current Imc. It is to be noted that the mirror current Imc is 1/X times the reference current Irc due to the difference in the aspect ratio of the first P-type transistor 1051 and the second P-type transistor 1052 of the first current mirror circuit 105. X is the number of floating gate transistors in the reference cell array 102.
接著，在步驟S306中，第二電流鏡電路106根據被選擇之致能訊號EN1~ENN，鏡射鏡射電流Imc，並藉以產生一已調整參考電流Iarc，其中已調整參考電流Iarc係用以決定非易失性記憶體之複數記憶體單元的邏輯狀態。鏡射鏡射電流Imc之步驟更包括根據致能訊號EN1~ENN中之一被選擇者，致能至少一複數控制電路10621~1062N，鏡射鏡射電流Imc以致能控制電路中之至少一者，以及藉由被致能之控制電路產生至少一支電流I1~IN。流程結束於步驟S306。值得注意的是，已調整參考電流Iarc係支電流I1~IN之加總，其中每一支電流I1~IN彼此不同，並由於控制電路10621~1062N中第二N型電晶體1063之長寬比的差異，每一支電流I1~IN亦彼此相差2的n次冪。舉例而言，每一第二N型電晶體1063之長寬比彼此不同並相差2的n次冪。例如，控制電路10621之第二N型電晶體1063的長寬比可為20，控制電路10622之第二N型電晶體1063的長寬比可為21，控制電路10623之第二N型電晶體1063的長寬比可為22，控制電路1062N之第二N型電晶體1063的長寬比可為2n，依此類推。 Next, in step S306, the second current mirror circuit 106 mirrors the mirror current Imc according to the selected enable signals EN1~ENN, and generates an adjusted reference current Iarc, wherein the adjusted reference current Iarc is used. Determining the logic state of the complex memory cells of the non-volatile memory. The step of mirroring the current Imc further includes enabling at least one of the plurality of control circuits 10621~1062N according to one of the enable signals EN1~ENN, and mirroring the mirror current Imc to enable at least one of the control circuits And generating at least one current I1~IN by the enabled control circuit. The flow ends in step S306. It is worth noting that the sum of the reference current Iarc is supported by the current I1~IN, wherein each of the currents I1~IN is different from each other, and because of the aspect ratio of the second N-type transistor 1063 in the control circuits 10621~1062N The difference, each current I1~IN is also different from each other by 2 to the power of n. For example, the aspect ratio of each of the second N-type transistors 1063 is different from each other and differs by n to the power of n. For example, the second N-type transistor control circuit 1063 to 10621 of the aspect ratio may be 20, second N-type transistor control circuit 1063 to 10622 of the aspect ratio may be 21, the control circuit 10623 of the second N-type The aspect ratio of the transistor 1063 can be 2 2 , and the aspect ratio of the second N-type transistor 1063 of the control circuit 1062N can be 2 n , and so on.
第4圖為本發明所提供之另一產生參考電流方法的流程圖，其中產生參考電流方法適用於第2圖所示之參考單元電路200。第4圖所示產生參考電流方法相似於第3圖所示之產生參考電流方法，其不同之處在於第4圖所示產生參考電流方法更包括步驟S308。 4 is a flow chart of another method for generating a reference current according to the present invention, wherein the method of generating a reference current is applied to the reference unit circuit 200 shown in FIG. The method of generating a reference current shown in FIG. 4 is similar to the method of generating a reference current shown in FIG. 3, except that the method of generating a reference current shown in FIG. 4 further includes step S308.
在步驟S308中，電流電壓轉換器108將已調整參考電流Iarc轉換為一已調整參考電壓Varc。流程結束於步驟S308。 In step S308, the current-to-voltage converter 108 converts the adjusted reference current Iarc into an adjusted reference voltage Varc. The flow ends in step S308.
本發明所揭露之參考單元電路100以及200與產生參考電流之方法，可提供已調整參考電流Iarc至記憶體單元，並且縮小電路布局之面積。另外，參考單元電路100以及200係為一紫外線閾值基礎之參考單元，使得閘極在紫外線抹除閾值狀態中不具有自由電子。因此，參考單元電路100以及200具有較好之穩定性的資料保存能力。 The reference unit circuits 100 and 200 disclosed in the present invention and the method of generating a reference current can provide the adjusted reference current Iarc to the memory unit and reduce the area of the circuit layout. In addition, the reference unit circuits 100 and 200 are reference units based on a UV threshold such that the gate does not have free electrons in the ultraviolet erase threshold state. Therefore, the reference unit circuits 100 and 200 have better data storage capabilities.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍內。另外本發明的任一實施例或申請專利範圍不須達成本發明所揭露之全部目的或優點或特點。此外，摘要部分和標題僅是用來輔助專利文件搜尋之用，並非用來限制本發明之權利範圍。 The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.
100、200‧‧‧參考單元電路 100, 200‧‧‧ reference unit circuit
105‧‧‧第一電流鏡電路 105‧‧‧First current mirror circuit
1051、1052、1082‧‧‧P型電晶體 1051, 1052, 1082‧‧‧P type transistor
1061、1063、1064、1084‧‧‧N型電晶體 1061, 1063, 1064, 1084‧‧‧N type transistors
1041-104N‧‧‧感測電晶體 1041-104N‧‧‧Sense Transistor
102‧‧‧參考單元陣列 102‧‧‧Reference cell array
1021-102N‧‧‧列 1021-102N‧‧‧
1031-103N‧‧‧浮閘電晶體 1031-103N‧‧‧Floating transistor
106‧‧‧第二電流鏡電路 106‧‧‧second current mirror circuit
10621-1062N‧‧‧控制電路 10621-1062N‧‧‧Control circuit
110‧‧‧選擇裝置 110‧‧‧Selection device
108‧‧‧電流電壓轉換器 108‧‧‧current voltage converter
1086‧‧‧反相器 1086‧‧‧Inverter
VDD1、VDD2‧‧‧電壓 VDD1, VDD2‧‧‧ voltage
Varc‧‧‧已調整參考電壓 Varc‧‧ has adjusted the reference voltage
GND‧‧‧接地 GND‧‧‧ Grounding
Irc‧‧‧參考電流 Irc‧‧‧reference current
Imc‧‧‧鏡射電流 Imc‧‧ Mirror current
I1-IN‧‧‧支電流 I1-IN‧‧‧ current
Iarc‧‧‧已調整參考電流 Iarc‧‧ has adjusted the reference current
REFWL‧‧‧參考字元線 REFWL‧‧‧ reference word line
YSEN‧‧‧選擇致能線 YSEN‧‧‧Selection line
EN1-ENN‧‧‧致能訊號 EN1-ENN‧‧‧Enable Signal
OUT‧‧‧輸出節點 OUT‧‧‧ output node
第1圖為本發明所提供之一參考單元電路之方塊圖；第2圖為本發明所提供之另一參考單元電路之方塊圖；第3圖為本發明所提供之一產生參考電流方法的流程圖；以及第4圖為本發明所提供之另一產生參考電流方法的流程圖。 1 is a block diagram of a reference unit circuit provided by the present invention; FIG. 2 is a block diagram of another reference unit circuit provided by the present invention; and FIG. 3 is a method for generating a reference current according to the present invention. A flow chart; and FIG. 4 is a flow chart of another method for generating a reference current according to the present invention.
100‧‧‧參考單元電路 100‧‧‧reference unit circuit
105‧‧‧第一電流鏡電路 105‧‧‧First current mirror circuit
1051、1052‧‧‧P型電晶體 1051, 1052‧‧‧P type transistor
1041-104N‧‧‧感測電晶體 1041-104N‧‧‧Sense Transistor
102‧‧‧參考單元陣列 102‧‧‧Reference cell array
1021-102N‧‧‧列 1021-102N‧‧‧
1031-103N‧‧‧浮閘電晶體 1031-103N‧‧‧Floating transistor
106‧‧‧第二電流鏡電路 106‧‧‧second current mirror circuit
10621-1062N‧‧‧控制電路 10621-1062N‧‧‧Control circuit
1061、1063、1064‧‧‧N型電晶體 1061, 1063, 1064‧‧‧N type transistors
110‧‧‧選擇裝置 110‧‧‧Selection device
VDD1、VDD2‧‧‧電壓 VDD1, VDD2‧‧‧ voltage
GND‧‧‧接地 GND‧‧‧ Grounding
Irc‧‧‧參考電流 Irc‧‧‧reference current
Imc‧‧‧鏡射電流 Imc‧‧ Mirror current
I1-IN‧‧‧支電流 I1-IN‧‧‧ current
Iarc‧‧‧已調整參考電流 Iarc‧‧ has adjusted the reference current
REFWL‧‧‧參考字元線 REFWL‧‧‧ reference word line
YSEN‧‧‧選擇致能線 YSEN‧‧‧Selection line
Claims (21)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101146529A TWI485713B (en) | 2012-12-11 | 2012-12-11 | Reference cell circuit and method of producing a reference current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101146529A TWI485713B (en) | 2012-12-11 | 2012-12-11 | Reference cell circuit and method of producing a reference current |
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| Publication Number | Publication Date |
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| TW201423759A true TW201423759A (en) | 2014-06-16 |
| TWI485713B TWI485713B (en) | 2015-05-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW101146529A TWI485713B (en) | 2012-12-11 | 2012-12-11 | Reference cell circuit and method of producing a reference current |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116520928A (en) * | 2023-07-03 | 2023-08-01 | 芯天下技术股份有限公司 | Reference current quick establishment circuit and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE69911591D1 (en) * | 1999-07-22 | 2003-10-30 | St Microelectronics Srl | Read circuit for a non-volatile memory |
| JP4113423B2 (en) * | 2002-12-04 | 2008-07-09 | シャープ株式会社 | Semiconductor memory device and reference cell correction method |
| JP2005285197A (en) * | 2004-03-29 | 2005-10-13 | Renesas Technology Corp | Semiconductor storage device |
| KR100865326B1 (en) * | 2006-12-26 | 2008-10-27 | 삼성전자주식회사 | Semiconductor device and data sensing method preventing mismatch of reference signal at data sensing |
| US7843726B2 (en) * | 2008-06-12 | 2010-11-30 | Micron Technology, Inc. | Sensing against a reference cell |
| JP5088387B2 (en) * | 2010-02-01 | 2012-12-05 | 日本精工株式会社 | Cross shaft type universal joint |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116520928A (en) * | 2023-07-03 | 2023-08-01 | 芯天下技术股份有限公司 | Reference current quick establishment circuit and method |
| CN116520928B (en) * | 2023-07-03 | 2023-11-03 | 芯天下技术股份有限公司 | Reference current quick establishment circuit and method |
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| TWI485713B (en) | 2015-05-21 |
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