TW201416821A - Frequency testing circuit - Google Patents
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本發明係關於一種頻率測試電路,尤其係關於一種用於測試伺服器中處理器的時鐘訊號的頻率。The present invention relates to a frequency test circuit, and more particularly to a frequency for testing a clock signal of a processor in a server.
伺服器工作的穩定性是工程人員以及用戶較為關心的重點,伺服器中處理器的時鐘訊號是整個伺服器能否穩定工作的關鍵。由此,處理器時鐘訊號的頻率需要非常準確。目前,工程人員通常採用示波器對時鐘訊號進行測試以獲得該時鐘訊號的頻率,然而,示波器的價格通常較為昂貴,也不適應於大批量的測試。The stability of the server work is the focus of the engineers and users. The clock signal of the processor in the server is the key to the stable operation of the entire server. Thus, the frequency of the processor clock signal needs to be very accurate. At present, engineers often use an oscilloscope to test the clock signal to obtain the frequency of the clock signal. However, the price of the oscilloscope is usually expensive and is not suitable for large-volume testing.
有鑑於此,有必要提供一種結構簡單、價格相對較低,並能夠準確測試處理器時鐘訊號頻率的測試電路。In view of this, it is necessary to provide a test circuit that is simple in structure, relatively inexpensive, and capable of accurately testing the frequency of the processor clock signal.
一種頻率測試電路,用於對伺服器的第一時鐘訊號進行測試,該第一時鐘訊號具有第一時鐘頻率,該頻率測試電路包括第一控制單元與第一計數單元,該第一控制單元工作於第二時鐘訊號下,該第二時鐘訊號具有第二時鐘頻率,該第一控制單元依據該第二時鐘訊號輸出對應的第一控制訊號與第二控制訊號至該第一計數單元,該第一計數單元接收該第一時鐘訊號,並在第一控制訊號的控制下開始對該第一時鐘訊號的脈衝數量進行計數,在該第二控制訊號的控制下停止計數並獲得計數結果,該計數結果為該第一時鐘頻率。a frequency test circuit for testing a first clock signal of a server, the first clock signal having a first clock frequency, the frequency test circuit comprising a first control unit and a first counting unit, the first control unit working The second clock signal has a second clock frequency, and the first control unit outputs the corresponding first control signal and the second control signal to the first counting unit according to the second clock signal. a counting unit receives the first clock signal, and starts counting the number of pulses of the first clock signal under the control of the first control signal, stops counting under the control of the second control signal, and obtains a counting result, the counting The result is the first clock frequency.
相較於先前技術,該頻率測試電路的結構簡單,可以大批量地應用於生產線的產品頻率測試,價格相對較低。Compared with the prior art, the frequency test circuit has a simple structure and can be applied to a product frequency test of a production line in a large amount, and the price is relatively low.
請參閱圖1及圖2,圖1描述了本發明一較佳實施方式的頻率測試電路10的電路示意圖。圖2為本發明頻率測試電路10的工作時序圖。該頻率測試電路10用於測試輸入中央處理器(CPU, Central Processing Unit)的第一時鐘訊號CLK1的第一時鐘頻率。該中央處理器可以用於電腦、伺服器等,一較佳實施方式中,該第一時鐘頻率為32768Hz。Please refer to FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram of a frequency test circuit 10 according to a preferred embodiment of the present invention. 2 is a timing chart showing the operation of the frequency test circuit 10 of the present invention. The frequency test circuit 10 is configured to test a first clock frequency of the first clock signal CLK1 input to a central processing unit (CPU). The central processing unit can be used for a computer, a server, etc. In a preferred embodiment, the first clock frequency is 32768 Hz.
頻率測試電路10包括第一控制單元100、第一計數單元110、第一鎖存單元120、第一比較單元130以及第一指示單元140。The frequency test circuit 10 includes a first control unit 100, a first counting unit 110, a first latch unit 120, a first comparison unit 130, and a first indication unit 140.
第一計數單元110包括第一時鐘訊號輸入端CK1,使能端ENABLE以及重設端RST,第一時鐘訊號輸入端CK1接收該第一時鐘訊號CLK1,並且對該第一時鐘訊號CLK1的脈衝數量進行計數,獲得的計數結果即表示該第一時鐘頻率的頻率值。使能端ENABLE用於接收第一控制訊號C1,重設端RST用於接收第二控制訊號C2。第一計數單元110依據該第一控制訊號C1開始對該第一時鐘訊號CLK1的脈衝數量進行計數,依據該第二控制訊號C2停止計數。The first counting unit 110 includes a first clock signal input terminal CK1, an enable terminal ENABLE and a reset terminal RST. The first clock signal input terminal CK1 receives the first clock signal CLK1, and the number of pulses of the first clock signal CLK1. Counting is performed, and the obtained counting result represents the frequency value of the first clock frequency. The enable terminal ENABLE is configured to receive the first control signal C1, and the reset terminal RST is configured to receive the second control signal C2. The first counting unit 110 starts counting the number of pulses of the first clock signal CLK1 according to the first control signal C1, and stops counting according to the second control signal C2.
第一控制單元100包括第二時鐘訊號輸入端CK2,第一輸出端OUT1與第二輸出端OUT2,第二時鐘訊號輸入端CK2接收第二時鐘訊號CLK2,該第二時鐘訊號CLK2具有第二時鐘頻率,也即是第一控制單元100工作於第二時鐘頻率下。本實施方式中,第二時鐘頻率為1Hz。第一控制單元100依據該第二時鐘訊號CLK2分別產生該第一控制訊號C1與該第二控制訊號C2,且分別至第一輸出端OUT1與第二輸出端OUT2輸出,即第一控制訊號C1從第一輸出端OUT1輸出,第二控制訊號C2從第二輸出端OUT2輸出。該第一控制訊號C1輸出至該第一計數單元110,該第二控制訊號C2分別輸出至該第一計數單元110及第一鎖存單元120。The first control unit 100 includes a second clock signal input terminal CK2, a first output terminal OUT1 and a second output terminal OUT2, a second clock signal input terminal CK2 receives a second clock signal CLK2, and the second clock signal CLK2 has a second clock. The frequency, that is, the first control unit 100 operates at the second clock frequency. In this embodiment, the second clock frequency is 1 Hz. The first control unit 100 generates the first control signal C1 and the second control signal C2 according to the second clock signal CLK2, and outputs the first control signal OUT1 and the second output terminal OUT2, respectively, that is, the first control signal C1. Outputted from the first output terminal OUT1, the second control signal C2 is output from the second output terminal OUT2. The first control signal C1 is output to the first counting unit 110, and the second control signal C2 is output to the first counting unit 110 and the first latch unit 120, respectively.
具體地,第一計數單元110包括第一子計數單元111、第二子計數單元112、第三子計數單元113、第四子計數單元114以及第五子計數單元115。Specifically, the first counting unit 110 includes a first sub-counting unit 111, a second sub-counting unit 112, a third sub-counting unit 113, a fourth sub-counting unit 114, and a fifth sub-counting unit 115.
該第一子計數單元111接收該第一時鐘訊號CLK1與該第一控制訊號C1,並開始對該第一時鐘訊號CLK1的脈衝數量進行計數,獲得第一計數值,以及判定該第一計數值是否等於十,當該第一計數值等於十,該第一子計數單元111的計數值清零,並輸出第一進位元訊號至該第二子計數單元112。The first sub-counting unit 111 receives the first clock signal CLK1 and the first control signal C1, and starts counting the number of pulses of the first clock signal CLK1, obtains a first count value, and determines the first count value. Whether it is equal to ten, when the first count value is equal to ten, the count value of the first sub-counting unit 111 is cleared, and the first carry signal is output to the second sub-counting unit 112.
該第二子計數單元112接收該第一進位元訊號,且每次在接收到該第一進位元訊號時該第二子計數單元112的計數值累計加一,獲得第二計數值,以及判定該第二計數值是否等於十,當該第二計數值等於十,該第二子計數單元112清零,並且輸出第二進位元訊號至該第三子計數單元113。The second sub-counting unit 112 receives the first carry signal, and each time the first carry unit receives the first carry signal, the count value of the second sub-counting unit 112 is incremented by one to obtain a second count value, and the determination Whether the second count value is equal to ten, when the second count value is equal to ten, the second sub-counting unit 112 is cleared, and outputs the second carry signal to the third sub-counting unit 113.
該第三子計數單元113接收該第二進位元訊號,且每次在接收到該第二進位元訊號時計數值累計加一,獲得第三計數值,並且判定該第三計數值是否等於十,當該第三計數值等於十,該第三子計數單元113清零,並且輸出第三進位元訊號至該第四子計數單元114。The third sub-counting unit 113 receives the second carry signal, and the count value is incremented by one every time the second carry signal is received, the third count value is obtained, and it is determined whether the third count value is equal to ten. When the third count value is equal to ten, the third sub-counting unit 113 is cleared, and the third carry signal is output to the fourth sub-counting unit 114.
該第四子計數單元114接收該第三進位元訊號時,且每次在接收到該第三進位元訊號時計數值累計加一,獲得第四計數值,以及判定該第四計數值是否等於十,當該第四計數值等於十,該第四子計數單元114清零,並且輸出第四進位元訊號至第五子計數單元115。When the fourth sub-counting unit 114 receives the third carry signal, and each time the third carry signal is received, the count value is incremented by one to obtain a fourth count value, and it is determined whether the fourth count value is equal to ten. When the fourth count value is equal to ten, the fourth sub-counting unit 114 is cleared, and outputs the fourth carry signal to the fifth sub-counting unit 115.
該第五子計數單元115接收該第四進位元訊號,且每次接收到該第四進位元訊號時,其計數值累計加一,獲得第五計數值。The fifth sub-counting unit 115 receives the fourth carry signal, and each time the fourth carry signal is received, the count value is incremented by one to obtain a fifth count value.
當該第一、二、三、四、五子計數單元111、112、113、114、115接收到該第二控制訊號C2時,均同時停止計數,並且將該第一、二、三、四、五計數值作為該計數結果輸出至第一鎖存單元120。When the first, second, third, fourth, and fifth sub-counting units 111, 112, 113, 114, and 115 receive the second control signal C2, the counting is stopped at the same time, and the first, second, third, fourth, The five count value is output to the first latch unit 120 as the count result.
可以理解,本實施方式中,第一計數單元110的計數值可以包括4個資料輸出端(圖未示),每個輸出輸出端採用二進位資料表示,例如0001、0010等,當四個輸出端的資料為1010時表示該計數單元的計數值為十。It can be understood that, in this embodiment, the count value of the first counting unit 110 may include four data output ends (not shown), and each output output end is represented by binary data, such as 0001, 0010, etc., when four outputs When the data of the terminal is 1010, it indicates that the counting value of the counting unit is ten.
第一鎖存單元120包括鎖存端LOAD,用於接收該第二控制訊號C2,第一鎖存單元120依據該第二控制訊號C2對第一計數單元110的計數值進行鎖存,並且將鎖存後的資料輸出至第一比較單元130。The first latch unit 120 includes a latch terminal LOAD for receiving the second control signal C2, and the first latch unit 120 latches the count value of the first counting unit 110 according to the second control signal C2, and The latched data is output to the first comparison unit 130.
第一鎖存單元120包括第一子鎖存單元121、第二子鎖存單元122、第三子鎖存單元123、第四子鎖存單元124以及第五子鎖存單元125。The first latch unit 120 includes a first sub-latch unit 121, a second sub-latch unit 122, a third sub-latch unit 123, a fourth sub-latch unit 124, and a fifth sub-latch unit 125.
第一子鎖存單元121用於接收第一子計數單元111的該第一計數值,並且在接收到該第二控制訊號C2時鎖存並輸出該第一計數值。The first sub-latch unit 121 is configured to receive the first count value of the first sub-count unit 111, and latch and output the first count value when the second control signal C2 is received.
第二子鎖存單元122接收第二子計數單元112的該第二計數值,並且在接收到該第二控制訊號C2時鎖存並輸出該第二計數值。The second sub-latch unit 122 receives the second count value of the second sub-counting unit 112, and latches and outputs the second count value when the second control signal C2 is received.
第三子鎖存單元123接收第三子計數單元113的該第三計數值,並且在接收到該第二控制訊號C2時鎖存並輸出該第三計數值。The third sub-latch unit 123 receives the third count value of the third sub-count unit 113, and latches and outputs the third count value when the second control signal C2 is received.
第四子鎖存單元124接收第四子計數單元114的該第四計數值,並且在接收到該第二控制訊號C2時鎖存並輸出該第四計數值。The fourth sub-latch unit 124 receives the fourth count value of the fourth sub-counting unit 114, and latches and outputs the fourth count value when the second control signal C2 is received.
第五子鎖存單元125接收該第五子計數單元115的該第五計數值,並且在接收到該第二控制訊號C2時鎖存並輸出該第五計數值。The fifth sub-latch unit 125 receives the fifth count value of the fifth sub-counting unit 115, and latches and outputs the fifth count value when the second control signal C2 is received.
第一比較單元130用於接收第一鎖存單元120輸出的計數結果,並且該計數結果與預定值進行比較,以判定該計數結果是否與預定值相等,並且依據比較結果輸出對應的指示訊號。The first comparison unit 130 is configured to receive the counting result output by the first latch unit 120, and compare the counting result with a predetermined value to determine whether the counting result is equal to a predetermined value, and output a corresponding indication signal according to the comparison result.
具體地,該第一比較單元130包括第一子比較單元131、第二子比較單元132、第三子比較單元133、第四子比較單元134以及第五子比較單元135。Specifically, the first comparison unit 130 includes a first sub-comparison unit 131, a second sub-comparison unit 132, a third sub-comparison unit 133, a fourth sub-comparison unit 134, and a fifth sub-comparison unit 135.
第一子比較單元131接收該第一計數值,並且將該第一計數值與第一預定值進行比較,依據比較結果輸出對應的第一比較訊號,例如,當第一計數值等於該第一預定值時,第一子比較單元131輸出一高電位訊號;反之,當該第一計數值不等於該第一預定值時,該第一子比較單元131輸出一低電位訊號。可以理解,該高電位、低電位訊號為該指示訊號。本實施方式中,第一預定值為8。The first sub-comparison unit 131 receives the first count value, and compares the first count value with the first predetermined value, and outputs a corresponding first comparison signal according to the comparison result, for example, when the first count value is equal to the first When the predetermined value is used, the first sub-comparison unit 131 outputs a high-potential signal; otherwise, when the first count value is not equal to the first predetermined value, the first sub-comparison unit 131 outputs a low-potential signal. It can be understood that the high potential and low potential signals are the indication signals. In the present embodiment, the first predetermined value is 8.
第二子比較單元132接收該第二計數值,並且將該第二計數值與第二預定值進行比較,依據比較結果輸出對應的第二比較訊號,例如,當第二計數值等於該第二預定值時,第二子比較單元132輸出一高電位訊號;反之,當該第二計數值不等於該第二預定值時,該第二子比較單元132輸出一低電位訊號。本實施方式中,第二預定值為6。The second sub-comparison unit 132 receives the second count value, and compares the second count value with the second predetermined value, and outputs a corresponding second comparison signal according to the comparison result, for example, when the second count value is equal to the second When the predetermined value is used, the second sub-comparison unit 132 outputs a high-potential signal; otherwise, when the second count value is not equal to the second predetermined value, the second sub-comparison unit 132 outputs a low-potential signal. In the present embodiment, the second predetermined value is 6.
第三子比較單元133接收該第三計數值,並且將該第三計數值與第三預定值進行比較,依據比較結果輸出對應的第三比較訊號,例如,當第三計數值等於該第三預定值時,該第三子比較單元133輸出一高電位訊號;反之,當該第三計數值不等於該第三預定值時,該第三子比較單元133輸出一低電位訊號。本實施方式中,第三預定值為7。The third sub-comparison unit 133 receives the third count value, and compares the third count value with a third predetermined value, and outputs a corresponding third comparison signal according to the comparison result, for example, when the third count value is equal to the third When the predetermined value is used, the third sub-comparison unit 133 outputs a high-potential signal; otherwise, when the third count value is not equal to the third predetermined value, the third sub-comparison unit 133 outputs a low-potential signal. In the present embodiment, the third predetermined value is 7.
第四子比較單元134接收該第四計數值,並且將該第四計數值與第四預定值進行比較,依據比較結果輸出對應的第四比較訊號,例如,當第四計數值等於該第四預定值時,該第四子比較單元134輸出一高電位訊號;反之,當該第四計數值不等於該第四預定值時,第四子比較單元134輸出一低電位訊號。本實施方式中,第四預定值為2。The fourth sub-comparison unit 134 receives the fourth count value, and compares the fourth count value with the fourth predetermined value, and outputs a corresponding fourth comparison signal according to the comparison result, for example, when the fourth count value is equal to the fourth When the predetermined value is used, the fourth sub-comparison unit 134 outputs a high-potential signal; otherwise, when the fourth count value is not equal to the fourth predetermined value, the fourth sub-comparison unit 134 outputs a low-potential signal. In the present embodiment, the fourth predetermined value is 2.
第五子比較單元135接收該第五計數值,並且將該第五計數值與第五預定值進行比較,依據比較結果輸出對應的第五比較訊號,例如,當第五計數值等於該第五預定值時,該第五子比較單元135輸出一高電位訊號;反之,當該第五計數值不等於該第五預定值時,該第五子比較單元135輸出一高電位訊號。本實施方式中,第五預定值為3。可以理解,第一、二、三、四、五預定值組成該預定值。The fifth sub-comparison unit 135 receives the fifth count value, and compares the fifth count value with a fifth predetermined value, and outputs a corresponding fifth comparison signal according to the comparison result, for example, when the fifth count value is equal to the fifth When the predetermined value is used, the fifth sub-comparison unit 135 outputs a high-potential signal; otherwise, when the fifth count value is not equal to the fifth predetermined value, the fifth sub-comparison unit 135 outputs a high-potential signal. In the present embodiment, the fifth predetermined value is 3. It can be understood that the first, second, third, fourth, and fifth predetermined values constitute the predetermined value.
第一指示單元140用於指示該第一計數單元110的計數結果與預定值是否相等,當該計數結果與該預定值不相等時,該第一指示單元140進行指示。第一指示單元140包括電源端Vdd與發光二極體141與限流電阻142,該電源端Vdd用於接收一電源訊號,該電源訊號可以為3V,該發光二極體141與該限流電阻142串聯於該第一比較單元130與該電源端Vdd之間。The first indicating unit 140 is configured to indicate whether the counting result of the first counting unit 110 is equal to a predetermined value, and when the counting result is not equal to the predetermined value, the first indicating unit 140 performs an indication. The first indicating unit 140 includes a power terminal Vdd, a light emitting diode 141 and a current limiting resistor 142. The power terminal Vdd is configured to receive a power signal, and the power signal may be 3V. The light emitting diode 141 and the current limiting resistor are used. 142 is connected in series between the first comparison unit 130 and the power terminal Vdd.
發光二極體141的陰極電性連接於該第一比較單元130,該發光二極體141的陽極通過該限流電阻電性連接於該電源端Vdd,當該指示訊號為低電位訊號,該發光二極體141導通並發光。The cathode of the LED 141 is electrically connected to the first comparison unit 130. The anode of the LED 141 is electrically connected to the power terminal Vdd through the current limiting resistor. When the indication signal is a low potential signal, the indicator signal is a low potential signal. The light emitting diode 141 is turned on and emits light.
相較於先前技術,該頻率測試電路的結構簡單,可以大批量地應用於生產線的產品頻率測試,價格相對較低。Compared with the prior art, the frequency test circuit has a simple structure and can be applied to a product frequency test of a production line in a large amount, and the price is relatively low.
進一步,通過設置第一指示單元140,可以清楚地瞭解第一時鐘頻率是否與預定值相同。Further, by setting the first indicating unit 140, it is possible to clearly understand whether the first clock frequency is the same as the predetermined value.
下面結合圖2時序圖,具體說明頻率測試電路10的工作過程。The working process of the frequency test circuit 10 will be specifically described below with reference to the timing chart of FIG.
CLK1為待測試的時鐘訊號,即第一時鐘訊號。CLK1 is the clock signal to be tested, that is, the first clock signal.
CLK2為第二時鐘訊號,該第一控制單元100工作在該第二時鐘訊號CLK2下,同時,第一控制單元100依據該第二時鐘訊號CLK2輸出第一控制訊號C1,其中,第一控制單元100使得第一控制訊號C1在第二時鐘訊號CLK2每個週期中的上升沿時刻t1變化為高電位,在連續的下一個上升沿時刻,即t2時刻,變換為低電位,第一控制訊號C1後續的波形圖可依次類推,本處不再贅述。CLK2 is a second clock signal, the first control unit 100 operates under the second clock signal CLK2, and the first control unit 100 outputs a first control signal C1 according to the second clock signal CLK2, wherein the first control unit 100 causes the first control signal C1 to change to a high potential at a rising edge time t1 in each cycle of the second clock signal CLK2, and to a low potential at a continuous next rising edge time, that is, at time t2, the first control signal C1 Subsequent waveform diagrams can be deduced by analogy, and will not be described here.
第一控制單元100依據該第二時鐘訊號CLK2輸出第二控制訊號C2,第二控制訊號C2與第一控制訊號C1的相位相反,也即是第一控制單元100使得第二控制訊號C2在的第二時鐘訊號CLK2的上升沿T1時刻為低電位,在連續的下一個上升沿時刻,t2時刻,變換為高電位,同理,第二控制訊號C2後續的波形圖可依此類推,不再贅述。The first control unit 100 outputs the second control signal C2 according to the second clock signal CLK2. The second control signal C2 is opposite to the phase of the first control signal C1, that is, the first control unit 100 makes the second control signal C2 The rising edge of the second clock signal CLK2 is at a low potential at the time of T1, and is converted to a high potential at the time of the next rising edge, at time t2. Similarly, the subsequent waveform of the second control signal C2 can be deduced by analogy. Narration.
第一時鐘訊號CLK1輸入第一子計數單元111,第二時鐘訊號CLK2輸入第一控制單元100,第一控制單元100依據第二時鐘訊號CLK2分別輸出第一控制訊號C1與第二控制訊號C2。The first clock signal CLK1 is input to the first sub-counting unit 111, and the second clock signal CLK2 is input to the first control unit 100. The first control unit 100 outputs the first control signal C1 and the second control signal C2 according to the second clock signal CLK2.
計數單元110的使能端ENABLE接收該第一控制訊號C1,重設端RST接收該第二控制訊號C2,第一計數單元110在第一控制訊號C1的t1時刻開始對第一時鐘訊號CLK1的脈衝數量進行計數,第一計數單元110在第二控制訊號C2的t2時刻停止對第一時鐘訊號CLK1計數。The enable terminal ENABLE of the counting unit 110 receives the first control signal C1, and the reset terminal RST receives the second control signal C2. The first counting unit 110 starts the first clock signal CLK1 at the time t1 of the first control signal C1. The number of pulses is counted, and the first counting unit 110 stops counting the first clock signal CLK1 at time t2 of the second control signal C2.
具體地,第一子計數單元111、第二子計數單元112、第三子計數單元113、第四子計數單元114以及第五子計數單元115在第一控制訊號C1下開始計數,並正且在第二控制訊號C2的控制下停止計數。Specifically, the first sub-counting unit 111, the second sub-counting unit 112, the third sub-counting unit 113, the fourth sub-counting unit 114, and the fifth sub-counting unit 115 start counting under the first control signal C1, and The counting is stopped under the control of the second control signal C2.
第一鎖存單元120的鎖存端LOAD接收該第二控制訊號C2,並且在第二控制訊號C2的t2時刻對接收的資料進行鎖存並輸出。The latch terminal LOAD of the first latch unit 120 receives the second control signal C2, and latches and outputs the received data at time t2 of the second control signal C2.
第一比較單元130接收自第一鎖存單元120輸出的資料,並且將該資料與該預定值進行,並且依據比較結果輸出對應的指示訊號。The first comparison unit 130 receives the data output from the first latch unit 120, and performs the data with the predetermined value, and outputs a corresponding indication signal according to the comparison result.
第一指示單元140接收該指示訊號,當該指示訊號為低電位時,發光二極體141導通並發光進行提示。The first indicating unit 140 receives the indication signal. When the indication signal is low, the LED 141 is turned on and emits light for prompting.
可替換地,第一計數單元110可以依據實際需要設置其他個數的子計數單元,例如1個,2個,3個,4個或者6個等,對應地,第一鎖存單元120、第一比較單元130中子鎖存單元、子比較單元的個數也可為1個,2個,3個,4個或者6個等,並不以此為限。Alternatively, the first counting unit 110 may set other number of sub-counting units according to actual needs, for example, one, two, three, four or six, etc., correspondingly, the first latch unit 120, The number of the sub-latch unit and the sub-comparison unit in the comparison unit 130 may be one, two, three, four or six, etc., and is not limited thereto.
請參閱圖3,為本發明另一實施方式的頻率測試電路的電路示意圖。該實施方式中的頻率測試電路1相較於前述較佳實施例的頻率測試電路10結構,區別在於,頻率測試電路1還包括一計數判定電路20,計數判定電路20用於頻率測試電路10是否正常工作。Please refer to FIG. 3 , which is a circuit diagram of a frequency test circuit according to another embodiment of the present invention. The frequency test circuit 1 in this embodiment is different in structure from the frequency test circuit 10 of the foregoing preferred embodiment. The difference is that the frequency test circuit 1 further includes a count determination circuit 20, and the count determination circuit 20 is used for the frequency test circuit 10. normal work.
計數判定電路包括第二控制單元200、第二計數單元210、第二鎖存單元220、第二比較單元230以及第二指示單元240。The count determination circuit includes a second control unit 200, a second counting unit 210, a second latch unit 220, a second comparison unit 230, and a second indication unit 240.
第二控制單元200與第一控制單元100結構與訊號埠均完全相同,接收一第三時鐘訊號CLK3(圖未示出),該第三時鐘訊號CLK3與第二時鐘訊號CLK2的頻率與相位均相同,為1Hz。The second control unit 200 and the first control unit 100 are identical in structure and signal ,, and receive a third clock signal CLK3 (not shown). The frequency and phase of the third clock signal CLK3 and the second clock signal CLK2 are both The same is 1 Hz.
第二計數單元210與第一計數單元110結構與訊號埠以及連接方式均相同,接收該第一時鐘訊號CLK1,依據第一控制訊號C1與第二控制訊號C2對第一時鐘訊號CLK1的脈衝數量進行計數,獲得一計數值。The second counting unit 210 and the first counting unit 110 are the same in structure and signal, and receive the first clock signal CLK1, and the number of pulses of the first clock signal CLK1 according to the first control signal C1 and the second control signal C2. Counting is performed to obtain a count value.
第二鎖存單元220與第一鎖存單元120結構與訊號埠以及連接方式均相同,依據第二控制訊號C2對第二計數單元210的該計數值進行鎖存並進行輸出。The second latch unit 220 and the first latch unit 120 are configured in the same manner as the signal 埠 and the connection manner, and the count value of the second counting unit 210 is latched and output according to the second control signal C2.
第二比較單元230,用於接收第一鎖存單元120與第二鎖存單元220的計數值,並且將該第一、第二鎖存單元120、220的計數值進行比較,當該第一、第二鎖存單元120、220的計數值相同,表示頻率測試電路10計數正常,第二比較單元230輸出一高電位訊號至第二指示單元240;當該第一、第二鎖存單元120、220的計數值不相同,表示頻率測試電路10計數異常,第二比較單元230輸出一低電位訊號至第二指示單元240。The second comparison unit 230 is configured to receive the count values of the first latch unit 120 and the second latch unit 220, and compare the count values of the first and second latch units 120, 220, when the first The second latch unit 120, 220 has the same count value, indicating that the frequency test circuit 10 counts normally, and the second comparison unit 230 outputs a high potential signal to the second indication unit 240; when the first and second latch units 120 The count value of 220 is different, indicating that the frequency test circuit 10 counts abnormally, and the second comparison unit 230 outputs a low potential signal to the second indication unit 240.
第二指示單元240與第一指示單元140結構相同,第二指示單元240依據接收到該第二比較單元230輸出的高電位訊號或者低電位訊號進行指示,具體地,第二指示單元240接收到該高電位訊號時,指示燈並不發光;第二指示單元240在接收到該低電位訊號時,指示燈發光。The second indication unit 240 is configured in the same manner as the first indication unit 140. The second indication unit 240 is instructed to receive the high-level signal or the low-level signal output by the second comparison unit 230. Specifically, the second indication unit 240 receives the second indication unit 240. When the high-level signal is received, the indicator light does not emit light; when the second indicator unit 240 receives the low-level signal, the indicator light is illuminated.
通過設置該計數判定電路20,可以準確地判定頻率測試電路10接收的第二時鐘訊號CLK2的第二時鐘頻率是否準確,以及頻率測試電路10能否正常計數,提高了頻率測試電路10的準確率。By setting the count determination circuit 20, it is possible to accurately determine whether the second clock frequency of the second clock signal CLK2 received by the frequency test circuit 10 is accurate, and whether the frequency test circuit 10 can count normally, improving the accuracy of the frequency test circuit 10. .
當然,本發明並不局限於上述公開的實施例,本發明還可以是對上述實施例進行各種變更。本技術領域人員可以理解,只要在本發明的實質精神範圍之內,對以上實施例所作的適當改變和變化都落在本發明要求保護的範圍之內。Of course, the present invention is not limited to the above-disclosed embodiments, and the present invention may be variously modified in the above embodiments. Those skilled in the art will appreciate that appropriate changes and modifications of the above embodiments are within the scope of the invention as claimed.
1、10...頻率測試電路1,10. . . Frequency test circuit
100...第一控制單元100. . . First control unit
CK1...第一時鐘訊號輸入端CK1. . . First clock signal input
OUT1...第一輸出端OUT1. . . First output
OUT2...第二輸出端OUT2. . . Second output
110...第一計數單元110. . . First counting unit
CK2...第二時鐘訊號輸入端CK2. . . Second clock signal input
ENABLE...使能端ENABLE. . . Enable end
RST...重設端RST. . . Reset end
111...第一子計數單元111. . . First sub-counting unit
112...第二子計數單元112. . . Second sub-counting unit
113...第三子計數單元113. . . Third sub-count unit
114...第四子計數單元114. . . Fourth sub-counting unit
115...第五子計數單元115. . . Fifth sub-counting unit
120...第一鎖存單元120. . . First latch unit
LOAD...鎖存端LOAD. . . Latch end
121...第一子鎖存單元121. . . First sub-latch unit
122...第二子鎖存單元122. . . Second sub-latch unit
123...第三子鎖存單元123. . . Third sub-latch unit
124...第四子鎖存單元124. . . Fourth sub-latch unit
125...第五子鎖存單元125. . . Fifth sub-latch unit
130...第一比較單元130. . . First comparison unit
131...第一子比較單元131. . . First sub-comparison unit
132...第二子比較單元132. . . Second sub-comparison unit
133...第三子比較單元133. . . Third sub-comparison unit
134...第四子比較單元134. . . Fourth sub-comparison unit
135...第五子比較單元135. . . Fifth sub-comparison unit
140...第一指示單元140. . . First indicating unit
141...發光二極體141. . . Light-emitting diode
142...限流電阻142. . . Current limiting resistor
Vdd...電源端Vdd. . . Power terminal
20...計數判定電路20. . . Counting decision circuit
200...第二控制單元200. . . Second control unit
210...第二計數單元210. . . Second counting unit
220...第二鎖存單元220. . . Second latch unit
230...第二比較單元230. . . Second comparison unit
240...第二指示單元240. . . Second indicating unit
CLK1...第一時鐘訊號CLK1. . . First clock signal
CLK2...第二時鐘訊號CLK2. . . Second clock signal
CLK3...第三時鐘訊號CLK3. . . Third clock signal
C1...第一控制訊號C1. . . First control signal
C2...第二控制訊號C2. . . Second control signal
圖1是本發明頻率測試電路一較佳實施方式的方框示意圖。1 is a block schematic diagram of a preferred embodiment of a frequency test circuit of the present invention.
圖2是本發明頻率測試電路一時序圖。2 is a timing diagram of the frequency test circuit of the present invention.
圖3是本發明另一實施方式的頻率測試電路的電路示意圖。3 is a circuit diagram of a frequency test circuit according to another embodiment of the present invention.
10...頻率測試電路10. . . Frequency test circuit
100...第一控制單元100. . . First control unit
CK1...第一時鐘訊號輸入端CK1. . . First clock signal input
OUT1...第一輸出端OUT1. . . First output
OUT2...第二輸出端OUT2. . . Second output
110...第一計數單元110. . . First counting unit
CK2...第二時鐘訊號輸入端CK2. . . Second clock signal input
ENABLE...使能端ENABLE. . . Enable end
RST...重設端RST. . . Reset end
111...第一子計數單元111. . . First sub-counting unit
112...第二子計數單元112. . . Second sub-counting unit
113...第三子計數單元113. . . Third sub-count unit
114...第四子計數單元114. . . Fourth sub-counting unit
115...第五子計數單元115. . . Fifth sub-counting unit
120...第一鎖存單元120. . . First latch unit
LOAD...鎖存端LOAD. . . Latch end
121...第一子鎖存單元121. . . First sub-latch unit
122...第二子鎖存單元122. . . Second sub-latch unit
123...第三子鎖存單元123. . . Third sub-latch unit
124...第四子鎖存單元124. . . Fourth sub-latch unit
125...第五子鎖存單元125. . . Fifth sub-latch unit
130...第一比較單元130. . . First comparison unit
131...第一子比較單元131. . . First sub-comparison unit
132...第二子比較單元132. . . Second sub-comparison unit
133...第三子比較單元133. . . Third sub-comparison unit
134...第四子比較單元134. . . Fourth sub-comparison unit
135...第五子比較單元135. . . Fifth sub-comparison unit
140...第一指示單元140. . . First indicating unit
141...發光二極體141. . . Light-emitting diode
142...限流電阻142. . . Current limiting resistor
Vdd...電源端Vdd. . . Power terminal
Claims (12)
該第二子計數單元接收該第一進位元訊號,且每次在接收到該第一進位元訊號時該第二子計數單元的計數值累計加一,獲得第二計數值,以及判定該第二計數值是否等於十,當該第二計數值等於十,該第子二計數單元清零,並且輸出第二進位元訊號至該第三子計數單元;
該第三子計數單元接收該第二進位元訊號,且每次在接收到該第二進位元訊號時計數值累計加一,獲得第三計數值,並且判定該第三計數值是否等於十,當該第三計數值等於十,該第三子計數單元清零,並且輸出第三進位元訊號至該第四子計數單元;
該第四子計數單元接收該第三進位元訊號時,且每次在接收到該第三進位元訊號時計數值累計加一,獲得第四計數值,以及判定該第四計數值是否等於十,當該第四計數值等於十,該第四子計單元清零,並且輸出第四進位元訊號至第五子計數單元;
該第五子計數單元接收該第四進位元訊號,且每次接收到該第四進位元訊號時,該第五子計數單元之計數值累計加一,獲得第五計數值;
當該第一、二、三、四、五子計數單元接收到該第二控制訊號時,均同時停止計數,並且將該第一、二、三、四、五計數值作為該計數結果。The frequency test circuit of claim 5, wherein the first counting unit comprises a first sub-counting unit, a second sub-counting unit, a third sub-counting unit, a fourth sub-counting unit, and a fifth sub-count a unit, the first sub-counting unit receives the first clock signal and counts the number of pulses of the first clock signal to obtain a first count value, and determines whether the first count value is equal to ten, when the first count value Equal to ten, the count value of the first sub-counting unit is cleared, and the first carry signal is output to the second sub-counting unit;
The second sub-counting unit receives the first carry signal, and each time the first carry unit receives the first carry signal, the count value of the second sub-count unit is incremented by one, obtaining a second count value, and determining the first Whether the second count value is equal to ten, when the second count value is equal to ten, the second sub-count unit is cleared, and the second carry signal is output to the third sub-count unit;
The third sub-counting unit receives the second carry signal, and the count value is incremented by one every time the second carry signal is received, obtaining a third count value, and determining whether the third count value is equal to ten, when The third count value is equal to ten, the third sub-counting unit is cleared, and the third carry signal is output to the fourth sub-counting unit;
When the fourth sub-counting unit receives the third carry signal, and each time the third carry signal is received, the count value is incremented by one to obtain a fourth count value, and whether the fourth count value is equal to ten, When the fourth count value is equal to ten, the fourth sub-count unit is cleared, and the fourth carry signal is output to the fifth sub-count unit;
The fifth sub-counting unit receives the fourth carry signal, and each time the fourth carry signal is received, the count value of the fifth sub-count unit is incremented by one to obtain a fifth count value;
When the first, second, third, fourth, and fifth sub-counting units receive the second control signal, the counting is stopped at the same time, and the first, second, third, fourth, and fifth count values are used as the counting result.
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