TW201414879A - Method for producing core-shell structure - Google Patents
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本發明是有關於一種核-殼結構的製備方法，特別是指一種利用多孔性模板製備核-殼結構的方法。 The present invention relates to a method for preparing a core-shell structure, and more particularly to a method for preparing a core-shell structure using a porous template.
當金屬材料以奈米結構，例如奈米粒、奈米線、奈米柱，或奈米薄膜存在時，由於會具有極大的表面積且會產生特殊的表面性質，因此已被廣泛的應用在不同的領域。例如，金屬奈米粒子會因為其表面性質而具有強大的催化性質；金屬奈米線則因為具有低電阻的特性而可作為積體電阻的內連接線；而具有巨磁性質(GMR)的磁儲存材料若能將其做成奈米尺寸，則預期將可有效提高磁紀錄的密度；此外，利用具有奈米柱的電極則由於可提供極大的比表面積且可有效的增加電子傳輸速率，因此可更適用於的電化學或光化學領域。而其中，以具有核-殼結構(core-chell structure)的奈米柱而言，由於可進一步利用該核層及殼層的構成材料搭配而可具有更多樣化的應用，因此也受到廣泛的研究。 When the metal material is present in a nanostructure, such as a nanoparticle, a nanowire, a nanocolumn, or a nanofilm, it has been widely used in various applications because it has a large surface area and produces special surface properties. field. For example, metal nanoparticles have strong catalytic properties due to their surface properties; metal nanowires can be used as internal interconnects for integrated resistors due to their low resistance; magnetics with giant magnetic properties (GMR) If the storage material can be made into a nanometer size, it is expected to effectively increase the density of the magnetic record; in addition, the use of an electrode having a nanocolumn can provide an extremely large specific surface area and can effectively increase the electron transport rate. It is more suitable for the field of electrochemistry or photochemistry. Among them, a nano column having a core-chell structure is widely used because it can further utilize the constituent materials of the core layer and the shell layer to have a more diverse application. Research.
目前常用於製備核-殼結構奈米柱的方法有化學浴法、化學沉積法、水熱法等，例如Kuang Q.等人(Kuang Q.,Jiang Z.Y.,Xie Z.X.,Lin S.C.,Lin Z.W.,Xie S.Y.,Huang R.B.,Zheng L.S.,J.Am.Chem.Soc.2005,127,11777)利用磊晶成長(Eputaxy growth)方式得到ZnO-SnO2核-殼結構奈米柱；Kim等人(Kim D.W.,Hwang I.S.,Kwon S.J.,Kang H. Y.,Park K.S.,Choi Y.J.,Choi K.J.,Park J.G.,Nano Lett.2007,7,3041)利用熱蒸鍍法(Thermal evaporation)製得SnO2-In2O3核-殼結構奈米柱；而Jun Pan等人(Jun Pan,Sven-Martin H€uhne,Hao Shen,Lisong Xiao,Philip Born,Werner Mader,and Sanjay Mathur,J.Phys.Chem.C.2011,115,17265-17269)則藉由金屬催化的氣-液-固(VLS)成長方式，以兩段式化學沉積法得到SnO2-TiO2核-殼結構奈米柱。 At present, methods commonly used for preparing core-shell nano columns are chemical bath method, chemical deposition method, hydrothermal method, etc., for example, Kuang Q., Jiang ZY, Xie ZX, Lin SC, Lin ZW, Xie SY, Huang RB, Zheng LS, J. Am. Chem. Soc. 2005, 127, 11777) ZnO-SnO 2 core-shell structure nano-pillars were obtained by Eputaxy growth; Kim et al. (Kim DW, Hwang IS, Kwon SJ, Kang HY, Park KS, Choi YJ, Choi KJ, Park JG, Nano Lett. 2007, 7, 3041) Preparation of SnO 2 -In 2 O 3 by Thermal evaporation Nuclear-shell structure nanopillar; and Jun Pan et al. (Jun Pan, Sven-Martin H.uhne, Hao Shen, Lisong Xiao, Philip Born, Werner Mader, and Sanjay Mathur, J. Phys . Chem . C. 2011, 115, 17265-17269) A SnO 2 -TiO 2 core-shell nano column was obtained by a two-stage chemical deposition method by a metal-catalyzed gas-liquid-solid (VLS) growth method.
然而，前述無論是採用何種方式所製得的核-殼結構奈米柱均是呈現散亂且彼此堆疊的分布狀態，因此，使用時並無法完全展現核-殼結構的特性，所以提供一種製程簡便易於控制且可令製得之核-殼結構奈米柱呈現有序的排列，則為發明人積極研究開發的方向。 However, the core-shell structure nano-pillars produced in any of the foregoing manners are distributed in a state of being scattered and stacked on each other, and therefore, the characteristics of the core-shell structure cannot be fully exhibited when used, so that a kind is provided. The process is simple and easy to control, and the ordered arrangement of the prepared core-shell nano columns is an active research and development direction for the inventors.
因此，本發明之目的，即在提供一種製程簡易，且可呈現有序排列的核-殼結構的製備方法。 Accordingly, it is an object of the present invention to provide a method of preparing a core-shell structure which is simple in process and which can exhibit an ordered arrangement.
於是，本發明一種具有核-殼結構的製備方法，包含：一多孔性模板製備步驟、一第一沉積步驟、一移除步驟，及一第二沉積步驟。 Thus, a method of preparing a core-shell structure of the present invention comprises: a porous template preparation step, a first deposition step, a removal step, and a second deposition step.
該多孔性模板製備步驟是先準備一個基板，該基板具有一個基材及一層形成於該基材表面的鋁層，接著將該基板進行陽極氧化及擴孔處理，令該鋁層氧化轉變成陽極氧化鋁層並形成多個貫通該陽極氧化鋁層且令該基材表面露出的通孔，得到一多孔性模板。 The porous template preparation step is to prepare a substrate having a substrate and a layer of aluminum formed on the surface of the substrate, and then anodizing and reaming the substrate to convert the aluminum layer into an anode. The aluminum oxide layer forms a plurality of through holes penetrating the anodized aluminum layer and exposing the surface of the substrate to obtain a porous template.
該第一沉積步驟是利用原子層沉積方式於該些通孔填置一導電材料，得到多個對應形成於該些通孔並與該基材表面連接的核層。 The first deposition step is to fill a conductive material in the via holes by atomic layer deposition to obtain a plurality of core layers corresponding to the via holes and connected to the surface of the substrate.
該移除步驟是將該多孔性模板移除，令該些核層露出。 The removing step removes the porous template to expose the core layers.
該第二沉積步驟是將一功能性材料以原子層沉積方式沉積於該些核層的表面，形成一殼層，即可完成該核-殼結構的製備。 The second deposition step is to deposit a functional material on the surface of the core layers by atomic layer deposition to form a shell layer, thereby completing the preparation of the core-shell structure.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一個較佳實施例的詳細說明中，將可清楚的呈現。 The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.
參閱圖1本發明核-殼結構的製備方法的該較佳實施例，是用以製備如圖1所示具有核-殼結構的電極為例做說明，該具有核-殼結構的電極包含一個基板2、多個具有核-殼結構的奈米柱3，及一層表層4。 Referring to FIG. 1 , the preferred embodiment of the method for preparing a core-shell structure of the present invention is described by taking an electrode having a core-shell structure as shown in FIG. 1 . The electrode having a core-shell structure includes a The substrate 2, a plurality of nano-pillars 3 having a core-shell structure, and a surface layer 4.
該基板2具有一個可導電的表面213。 The substrate 2 has an electrically conductive surface 213.
該些奈米柱3呈陣列間隔分布於該表面213，該每一個奈米柱3具有由一核層31及一形成於該核層31表面的殼層32所構成的核-殼結構，該核層31是由一導電材料構成，且該殼層32是由功能性材料所構成。 The nano-pillars 3 are distributed on the surface 213 in an array, and each of the nano-pillars 3 has a core-shell structure composed of a core layer 31 and a shell layer 32 formed on the surface of the core layer 31. The core layer 31 is composed of a conductive material, and the shell layer 32 is composed of a functional material.
該表層4形成於該表面213未形成有該些奈米柱3的部分，並與該些奈米柱3的殼層32彼此連接，且該表層4的構成材料與該殼層32的材料相同。 The surface layer 4 is formed on a portion of the surface 213 where the nano-pillars 3 are not formed, and is connected to the shell layers 32 of the plurality of nano-pillars 3, and the constituent material of the surface layer 4 is the same as the material of the shell layer 32. .
配合參閱圖2、圖3，該具有核-殼結構電極的製備方法的較佳實施例包含以下步驟。 Referring to Figures 2 and 3, a preferred embodiment of the method for preparing a core-shell electrode comprises the following steps.
一多孔性模板製備步驟51，首先準備一個表面具有一層鋁層22a的基板2，接著將該基板2進行陽極氧化處理，令該鋁層22a氧化轉變成陽極氧化鋁層(AAO)22後，再進行擴孔處理，藉由擴孔時間控制，形成多個貫通該陽極氧化鋁層22且與該基材21的表面213連通的通孔23，得到一具有適當孔洞直徑之多孔性模板。 In a porous template preparation step 51, first, a substrate 2 having an aluminum layer 22a on its surface is prepared, and then the substrate 2 is anodized to convert the aluminum layer 22a into an anodized aluminum layer (AAO) 22 by oxidation. Further, the hole expanding process is performed to form a plurality of through holes 23 penetrating the anodized aluminum layer 22 and communicating with the surface 213 of the substrate 21 by the hole expanding time control to obtain a porous template having a proper hole diameter.
具體的說，該基板2包含一個具有可導電的表面213的基材21及一層形成於該基材21表面213的鋁層22a，要說明的是，該基材21可是選自導電材料所構成，或是利用在一絕緣本體的表面形成一層由導電材料構成的導電層而得。該導電材料可選自金屬或金屬氧化物，例如金、銀、鉑、鎳、銅、氧化銦錫(ITO)、氟摻雜的氧化錫(FTO)、鋁摻雜的氧化鋅(AZO)，或鎵摻雜的氧化鋅(GZO)等導電材料構成，該絕緣本體則可選自玻璃、石英，及塑膠等絕緣材料，於本實施例中該基材21是以具有一由玻璃構成的絕緣本體211，及一形成於該絕緣本體211表面，由氧化銦錫(ITO)為材料構成的導電層212為例作說明，該鋁層22a係形成於該導電層212的表面213。 Specifically, the substrate 2 includes a substrate 21 having an electrically conductive surface 213 and an aluminum layer 22a formed on the surface 213 of the substrate 21. The substrate 21 may be selected from conductive materials. Or by forming a conductive layer made of a conductive material on the surface of an insulating body. The conductive material may be selected from a metal or a metal oxide such as gold, silver, platinum, nickel, copper, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), Or a conductive material such as gallium-doped zinc oxide (GZO), the insulating body may be selected from insulating materials such as glass, quartz, and plastic. In the embodiment, the substrate 21 has an insulation composed of glass. The main body 211 and a conductive layer 212 formed of indium tin oxide (ITO) are formed on the surface of the insulating body 211. The aluminum layer 22a is formed on the surface 213 of the conductive layer 212.
然而，在製備該多孔性模板的陽極氧化過程中，若為了要將該氧化鋁阻障層完全移除而增加蝕刻時間，該導電層212容易因為過蝕刻被破壞，導致後續製成之元件整體的導電性不佳，或是該陽極氧化鋁層22因為過蝕刻被破 壞，自該基材21表面213剝離而無法成功製得該多孔性模板，因此，本發明該步驟51是由具有不同厚度的鋁層22a並進一步配合偵測陽極氧化過程中電流密度的變化決定該陽極氧化處理的蝕刻終止點，以確保可成功的製得該多孔性模板。 However, in the anodizing process for preparing the porous template, if the etching time is increased in order to completely remove the aluminum oxide barrier layer, the conductive layer 212 is easily destroyed by over-etching, resulting in a subsequently fabricated component as a whole. Poor conductivity, or the anodized aluminum layer 22 is broken due to over-etching Otherwise, the porous template is not successfully formed by peeling off the surface 213 of the substrate 21. Therefore, the step 51 of the present invention is determined by the aluminum layer 22a having different thicknesses and further detecting the change of current density during the anodization process. The anodization treats the etch stop point to ensure that the porous template can be successfully fabricated.
詳細的說，該步驟51的鋁層22a是先在該基材21表面213蒸鍍形成一層第一鋁膜，再於該第一鋁膜表面設置一個圖案化的遮罩進行第二次蒸鍍，而於該第一鋁膜上形成一層圖案化的第二鋁膜，得到如圖3所示該具有兩種厚度(第一厚度A與第二厚度B，且該第一厚度A小於第二厚度B)的鋁層22a。 In detail, the aluminum layer 22a of the step 51 is first vapor deposited on the surface 213 of the substrate 21 to form a first aluminum film, and then a patterned mask is disposed on the surface of the first aluminum film for the second evaporation. And forming a patterned second aluminum film on the first aluminum film, which has two thicknesses as shown in FIG. 3 (the first thickness A and the second thickness B, and the first thickness A is smaller than the second Aluminum layer 22a of thickness B).
此外，要說明的是，該第二鋁膜可以利用不同圖案的遮罩，而形成例如直條狀、斜條狀、正交狀、交叉狀或弧形狀等之結構，而形成具有不同厚度且不同之形狀，圖3所示僅為該具有不同厚度的鋁層22a的其中一種態樣，而不應視為本發明實施之限制。 In addition, it should be noted that the second aluminum film may be formed into a different thickness by using a mask of different patterns to form a structure such as a straight strip, a diagonal strip, an orthogonal shape, a cross shape, or an arc shape. And different shapes, only one of the aluminum layers 22a having different thicknesses is shown in FIG. 3, and should not be construed as limiting the implementation of the present invention.
更進一步說，該步驟51的陽極氧化處理為一種電化學蝕刻反應，是將該基板2放在一酸性電解液中且在外加電場的條件下，令該鋁層22a進行氧化、蝕刻反應而形成一陽極氧化鋁層(Anodic Aluminum oxide,AAO)之後再進行擴孔處理即可形成該些具有如蜂巢式結構的六角形單胞且與該導電層212表面213連通的通孔23，而製得該多孔性模板。 Furthermore, the anodizing treatment of the step 51 is an electrochemical etching reaction, in which the substrate 2 is placed in an acidic electrolyte and the aluminum layer 22a is oxidized and etched under an applied electric field. An anodized aluminum oxide (AAO) layer is further subjected to a reaming treatment to form the through holes 23 having a hexagonal unit cell such as a honeycomb structure and communicating with the surface 213 of the conductive layer 212. The porous template.
要說明的是，由於利用陽極氧化處理的過程於該些孔 洞23a的四周會形成不導電的氧化鋁阻障層(barrier layer)，因此若未完全將該些氧化鋁阻障層移除，則後續填置的核層31就會在該多孔性模板的移除過程中一併被移除，而無法得到所要的核-殼結構奈米柱，因此，確保該氧化鋁阻障層能被完全移除，令該些經過陽極氧化及擴孔過程形成的孔洞23a可與該表面213連通而形成通孔23是該步驟51最重要的過程。 It should be noted that due to the process of anodizing, the holes are used. A non-conductive aluminum barrier layer is formed around the hole 23a, so if the aluminum barrier layer is not completely removed, the subsequently filled core layer 31 is in the porous template. The removal process is also removed, and the desired core-shell structure nano column cannot be obtained. Therefore, it is ensured that the aluminum barrier layer can be completely removed, and the anodization and reaming processes are formed. The hole 23a can communicate with the surface 213 to form the through hole 23, which is the most important process of this step 51.
參閱圖4，圖4是利用該鋁層22a進行陽極氧化處理的電流密度-蝕刻時間曲線圖：在陽極氧化的過程中，當自該陽極氧化鋁層向下穩定形成孔洞23a時，觀測到的電流呈現穩定狀態(如圖4中a區域)；當對應該第一厚度A處形成的孔洞23a底部的氧化鋁阻障層部分到達底部(因均勻度關係，對應形成於第一厚度A的孔洞23a底部的部分氧化鋁阻障層會先達底部)時電流會開始下降，當該電流下降到最低處(圖4中b點)表示對應形成於該第一厚度A的孔洞23a的氧化鋁阻障層幾乎皆已到達底部，此時再繼續蝕刻則會開始有氧化鋁阻障層蝕穿，且因該基材21的導電層212直接與電解液接觸，因此電流會開始上升，且隨著孔洞23a底部的氧化鋁阻障層蝕穿形成通孔23的數量增加，電流上升更明顯。然而，若為了要將該些孔洞23a底部的氧化鋁阻障層完全移除而增加蝕刻時間，該基材21的導電層212將被破壞，且該多孔性模板也容易會從該基材21表面213剝離；因此本發明藉由該第二厚度B處未蝕穿之陽極氧化鋁牽制住第一厚度A處之陽極氧化鋁而使該多孔性模板不易 剝離。 Referring to FIG. 4, FIG. 4 is a graph of current density-etching time of anodizing treatment using the aluminum layer 22a: during the anodization, when the pores 23a are stably formed downward from the anodized aluminum layer, The current assumes a steady state (as in the area a in FIG. 4); when the portion of the aluminum barrier layer corresponding to the bottom of the hole 23a formed at the first thickness A reaches the bottom (corresponding to the uniformity relationship, corresponding to the hole formed in the first thickness A) When a part of the aluminum oxide barrier layer at the bottom of 23a reaches the bottom first, the current starts to decrease, and when the current drops to the lowest point (point b in FIG. 4), the aluminum oxide barrier corresponding to the hole 23a formed in the first thickness A is indicated. Almost all of the layers have reached the bottom. At this point, the etching continues to begin with the barrier layer of the aluminum oxide barrier, and since the conductive layer 212 of the substrate 21 is in direct contact with the electrolyte, the current begins to rise, and along with the holes. The number of through-holes 23 formed by the erosion of the aluminum oxide barrier layer at the bottom of 23a is increased, and the current rise is more pronounced. However, if the etching time is increased in order to completely remove the aluminum oxide barrier layer at the bottom of the holes 23a, the conductive layer 212 of the substrate 21 will be destroyed, and the porous template will also easily escape from the substrate 21. The surface 213 is peeled off; therefore, the present invention makes the porous template difficult by holding the anodized aluminum at the first thickness A by the non-etched anodized aluminum at the second thickness B. Stripped.
此外，當對應該第二厚度B處的孔洞23a的氧化鋁阻障層到達底部時，可觀察到電流又會從最高值(如圖4中c點)逐漸下降，直到第二厚度B處孔洞23a底部的部分氧化鋁阻障層有蝕穿電流產生時才會再上升(如圖4中d點)；所以本發明利用將該蝕刻終止點控制於該電流密度曲線的c點(即，該電流密度-蝕刻時間曲線的斜率第一次由正值變為負值之處)，或是控制在c~d之間，此時該些對應於第一厚度A處的未蝕穿孔洞的氧化鋁阻障層已變薄，可輕易藉由擴孔形成與該表面213連通的通孔23；而對應該第二厚度B處的孔洞的氧化鋁阻障層因尚未被完全蝕刻移除，因此可用來穩固該多孔性模板，提升該多孔性模板與該基材21的附著性。 In addition, when the aluminum barrier layer corresponding to the hole 23a at the second thickness B reaches the bottom, it can be observed that the current is gradually decreased from the highest value (point c in FIG. 4) until the hole at the second thickness B. A portion of the aluminum oxide barrier layer at the bottom of 23a will rise again when the etch current is generated (as point d in FIG. 4); therefore, the present invention utilizes the etch stop point to control point c of the current density curve (ie, the The current density - the slope of the etch time curve changes from a positive value to a negative value for the first time), or is controlled between c and d, which corresponds to the oxidation of the unetched perforation hole at the first thickness A. The aluminum barrier layer has been thinned, and the via hole 23 communicating with the surface 213 can be easily formed by reaming; and the aluminum oxide barrier layer corresponding to the hole at the second thickness B is not completely removed by etching, It can be used to stabilize the porous template and improve the adhesion of the porous template to the substrate 21.
一第一沉積步驟52，接著利用原子層沉積(atomic layer deposition，ALD)方法於該些通孔23填置一導電材料，得到多個對應形成於該些通孔23並與該基材21的表面213連接的核層31。 a first deposition step 52, followed by filling a conductive material in the via holes 23 by an atomic layer deposition (ALD) method, to obtain a plurality of corresponding via holes 23 formed in the via holes 23 and the substrate 21 The core layer 31 to which the surface 213 is attached.
詳細的說，該步驟52是將該步驟51製得，形成有該多孔性模板的基材21放在一真空反應腔體中，再利用原子層沉積方法於該些通孔23填置一導電材料，得到該些由該導電材料構成並與該表面213連接的核層31。 In detail, the step 52 is performed in the step 51, and the substrate 21 on which the porous template is formed is placed in a vacuum reaction chamber, and then a conductive layer is filled in the through holes 23 by an atomic layer deposition method. Materials, the core layer 31 composed of the conductive material and connected to the surface 213 is obtained.
該導電材料可選自金屬、金屬氧化物，或合金金屬；該原子層沉積方法所用的前驅物及反應條件是視該所欲沉積的第一導電材料的選擇而有不同，而該前驅物及反應條 件的選擇為本技術領域所知悉，故不再多加敘述。 The conductive material may be selected from a metal, a metal oxide, or an alloy metal; the precursor and reaction conditions used in the atomic layer deposition method are different depending on the choice of the first conductive material to be deposited, and the precursor and Reaction strip The selection of the parts is known in the art and will not be described again.
一移除步驟53，將該多孔性模板移除，令該些核層31露出。 Upon removal of step 53, the porous template is removed to expose the core layers 31.
詳細的說，該步驟52除了會在該些通孔23中沉積該導電材料外，也會同時在該多孔性模板的頂面沉積該導電材料，因此該步驟53會先利用乾式蝕刻(例如反應性離子蝕刻)或濕式蝕刻將形成在該多孔性模板頂面的導電材料移除，接著再利用濕式蝕刻將該多孔性模板自該基材21表面213移除，令該些核層31裸露，而得到一具有多個與該表面213連接的核層31的半成品100。 In detail, in step 52, in addition to depositing the conductive material in the through holes 23, the conductive material is simultaneously deposited on the top surface of the porous template, so the step 53 first uses dry etching (for example, reaction). Ion etching or wet etching removes the conductive material formed on the top surface of the porous template, and then removes the porous template from the surface 213 of the substrate 21 by wet etching, so that the core layers 31 are removed. Exposed, a semi-finished product 100 having a plurality of core layers 31 connected to the surface 213 is obtained.
一第二沉積步驟54，最後將一功能性材料以原子層沉積方式沉積於該半成品100的表面，即可完成該核-殼結構的製備。 A second deposition step 54 is finally performed by depositing a functional material on the surface of the semi-finished product 100 in atomic layer deposition to complete the preparation of the core-shell structure.
具體的說，該步驟54是將經過該步驟53得到的半成品放在一真空反應腔體中，利用原子層沉積方法於該些核層31裸露的表面沉積一功能性材料形成該些殼層32，並同時於該基材21裸露的表面213沉積一層由該功能性材料所構成的表層4後，即可完成該具有核-殼結構之電極的製備。 Specifically, the step 54 is to place the semi-finished product obtained through the step 53 in a vacuum reaction chamber, and deposit a functional material on the exposed surface of the core layer 31 by an atomic layer deposition method to form the shell layer 32. At the same time, a surface layer 4 composed of the functional material is deposited on the exposed surface 213 of the substrate 21 to complete the preparation of the electrode having the core-shell structure.
要說明的是，該功能性材料可選自金屬、金屬氧化物，或合金金屬，而該原子層沉積方法所用的前驅物及反應條件如前所述是視該所欲沉積的功能性材料的選擇而有不同，且為本技術領域所周知，故不再多加敘述。此外，由於該表層4及該殼層32是於該原子層沉積過程同時形 成，因此該表層4及該殼層32會彼此連接。 It should be noted that the functional material may be selected from a metal, a metal oxide, or an alloy metal, and the precursors and reaction conditions used in the atomic layer deposition method are as described above, depending on the functional material to be deposited. The choices vary and are well known in the art and will not be described again. In addition, since the surface layer 4 and the shell layer 32 are simultaneously formed during the deposition process of the atomic layer Thus, the surface layer 4 and the shell layer 32 are connected to each other.
值得一提的是，本發明該具有核-殼結構的電極可藉由該核層31及該殼層32的材料選擇而適用於不同的應用領域。例如，當該些核-殼結構奈米柱3是用於光觸媒電極時，為了令該核層31及該殼層32可產生能階差，讓自該殼層332產生的電子可更快速的傳遞到核層31，並產生電子捕捉效果防止電子回傳到該些殼層32，以降低電子復合損失，因此，較佳地，該導電材料可選自導電帶能階低於該功能性材料的導電材料，例如，該導電材料可選自二氧化錫，而該功能性材料則選自二氧化鈦。 It is worth mentioning that the electrode having the core-shell structure of the present invention can be applied to different application fields by the material selection of the core layer 31 and the shell layer 32. For example, when the core-shell structure nano-pillars 3 are used for a photocatalyst electrode, in order for the core layer 31 and the shell layer 32 to generate an energy level difference, electrons generated from the shell layer 332 can be made faster. Passing to the core layer 31 and generating an electron trapping effect to prevent electrons from being transmitted back to the shell layers 32 to reduce electron recombination loss. Therefore, preferably, the conductive material may be selected from a conductive strip energy level lower than the functional material. The electrically conductive material, for example, the electrically conductive material may be selected from the group consisting of tin dioxide, and the functional material is selected from the group consisting of titanium dioxide.
此外，要再說明的是，由於該殼層32是利用原子層沉積方式而得，而當原子層沉積的反應溫度是在低溫(200℃)條件進行時，該殼層32會呈現表面平整度高的薄膜態樣，而當原子層沉積的反應溫度是在高溫條件(300~400℃)進行時，該殼層32則會由多個功能性材料構成的顆粒堆積而成，因此該殼層32的表面會具有較高的粗糙度，而表面粗糙則可提供更多的接觸表面積，因此，較佳地，該殼層32的沉積溫度是在300~400℃。 In addition, it is to be noted that since the shell layer 32 is obtained by atomic layer deposition, when the reaction temperature of the atomic layer deposition is performed under low temperature (200 ° C) conditions, the shell layer 32 exhibits surface flatness. a high film state, and when the reaction temperature of the atomic layer deposition is performed under high temperature conditions (300 to 400 ° C), the shell layer 32 is formed by stacking particles composed of a plurality of functional materials, so the shell layer The surface of 32 will have a higher roughness, while the surface roughness will provide more contact surface area. Therefore, preferably, the deposition temperature of the shell layer 32 is 300 to 400 °C.
又要說明的是，該些奈米柱3還可以依據該些通孔23的直徑及該核層31、殼層32的厚度控制而形成具有如圖5所示具有多層核-殼結構的奈米管3a。 It should be noted that the nano-pillars 3 can also be formed according to the diameters of the through-holes 23 and the thickness of the core layer 31 and the shell layer 32 to form a nano-layer having a multi-layer core-shell structure as shown in FIG. Rice tube 3a.
具體的說，該具有多層核-殼結構之奈米管3a是在該第一沉積步驟53時，利用原子層沉積方式先於界定出該些通孔23的孔壁沉積形成一由導電材料構成並呈中空狀的第一 核層311，接著再利用原子層沉積方式於該些第一核層311界定的空間沉積形成一層第二核層312，得到多個對應形成於該些通孔23並與該基材21的表面連接的核層32，如此再經過該移除步驟54及該第二沉積步驟55之後即可得到該具有多層核-殼結構的奈米管3a；而該第二核層312的構成材料與該第一核層311的導電材料不同，並可視用途及需求而可與該殼層312的構成材料相同或不同，因此不再多加贅述。 Specifically, the nanotube tube 3a having a multi-layer core-shell structure is formed by a conductive material in the first deposition step 53 by depositing a hole wall defining the through holes 23 by atomic layer deposition. First in a hollow shape The core layer 311 is then deposited by a layer deposition method on the space defined by the first core layers 311 to form a second core layer 312, and a plurality of surfaces corresponding to the through holes 23 and the substrate 21 are obtained. The connected core layer 32 is further obtained by the removing step 54 and the second deposition step 55 to obtain the nanotube tube 3a having a multi-layer core-shell structure; and the constituent material of the second core layer 312 and the The conductive material of the first core layer 311 is different and may be the same as or different from the constituent material of the shell layer 312 depending on the application and needs, and therefore will not be further described.
有關本發明之前述及其他技術內容、特點與功效，在以下1個具體例的詳細說明中，將可清楚的呈現，但應瞭解的是，該具體例僅為說明之用，而不應被解釋為本發明實施之限制。 The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the specific embodiments, but it should be understood that the specific examples are only illustrative and should not be It is to be construed as limiting the implementation of the invention.
具體例1Specific example 1
SnO2-TiO2核-殼結構奈米柱電極的製備。 Preparation of SnO 2 -TiO 2 core-shell structured nanopillar electrode.
首先將長x寬(2cmx3cm)的ITO導電玻璃基材進行清潔風乾後備用。接著利用電子束蒸鍍系統(E-850，倍強公司)於該基材的ITO層表面蒸鍍一層厚度為1μm的第一鋁膜及一層厚度為0.5μm的第二鋁膜，製得該基板。 First, the ITO conductive glass substrate having a length x width (2 cm x 3 cm) was cleaned and air-dried for use. Then, a first aluminum film having a thickness of 1 μm and a second aluminum film having a thickness of 0.5 μm are deposited on the surface of the ITO layer of the substrate by an electron beam evaporation system (E-850, Beyond). Substrate.
蒸鍍條件： Evaporation conditions:
壓力：2.0x10-6 torr Pressure: 2.0x10 -6 torr
基板溫度：300K Substrate temperature: 300K
蒸鍍速率：0.07~0.12nm/s Evaporation rate: 0.07~0.12nm/s
接著將該基板置於一酸性電解液(H3PO4)中，將該基板接正極，另一個不銹鋼板接負極，並提供電壓對該鋁層進 行陽極氧化處理，並同時監控該陽極氧化處理的電流變化，於該電流自極大值反轉向下時即停止蝕刻，並進行擴孔，而在該基材上形成一如圖6所示由陽極氧化鋁層22構成，具有多數通孔23的多孔性模板。 Then, the substrate is placed in an acidic electrolyte (H 3 PO 4 ), the substrate is connected to the positive electrode, the other stainless steel plate is connected to the negative electrode, and a voltage is applied to the aluminum layer for anodizing, and the anodizing treatment is simultaneously monitored. The current change is stopped when the current is inverted from the maximum value, and the hole is reamed, and a base layer 23 is formed on the substrate and formed of an anodized aluminum layer 22 as shown in FIG. Porous template.
陽極氧化處理條件Anodizing treatment conditions
電解液：5wt% H3PO4 Electrolyte: 5wt% H 3 PO 4
溫度：278K Temperature: 278K
電壓：100V Voltage: 100V
擴孔條件Reaming condition
電解液：5wt% H3PO4 Electrolyte: 5wt% H 3 PO 4
溫度：300K Temperature: 300K
時間：30min Time: 30min
接著將具有該多孔性模板的基材置於一真空反應腔體內，利用原子層沉積方式於該些通孔及該基材的表面沉積一層二氧化錫。 Next, the substrate having the porous template is placed in a vacuum reaction chamber, and a layer of tin dioxide is deposited on the through holes and the surface of the substrate by atomic layer deposition.
原子層沉積條件Atomic layer deposition conditions
反應腔體溫度：350℃ Reaction chamber temperature: 350 ° C
SnCl4注入量：0.16cc SnCl 4 injection amount: 0.16cc
H2O注入量：0.8cc H 2 O injection amount: 0.8cc
氣體循環次數：1000cycle Number of gas cycles: 1000cycle
單次循環時間：8sec/cycle Single cycle time: 8sec/cycle
接著利用反應性離子蝕刻(RIE)將沉積在該些通孔頂面的SnO2移除，然後再將其浸入磷酸蝕刻液中，以濕蝕刻方式將該多孔性模板自該基材的表面移除，即可得到一個如 圖7所示具有多個由SnO2構成的核層的半成品。 Next, the SnO 2 deposited on the top surface of the via holes is removed by reactive ion etching (RIE), and then immersed in a phosphoric acid etching solution to wet the porous template from the surface of the substrate. In addition, a semi-finished product having a plurality of core layers composed of SnO 2 as shown in FIG. 7 can be obtained.
反應性離子蝕刻條件Reactive ion etching conditions
電漿功率：20W Plasma power: 20W
反應氣體：H2 Reaction gas: H 2
氣體流量：20sccm Gas flow: 20sccm
壓力：20mtorr Pressure: 20mtorr
蝕刻時間：40min Etching time: 40min
濕式蝕刻條件Wet etching condition
蝕刻液：5wt%磷酸 Etching solution: 5wt% phosphoric acid
溫度：323K Temperature: 323K
時間：6hr Time: 6hr
最後再將該半成品置入一真空反應腔體中，利用原子層沉積方式於該基材的表面及該些核層表面沉積形成一層二氧化鈦，即可得到該具有呈陣列排列並站立於該基材表面的SnO2-TiO2核-殼奈米柱的電極。 Finally, the semi-finished product is placed in a vacuum reaction chamber, and a layer of titanium dioxide is deposited on the surface of the substrate and the surface of the core layer by atomic layer deposition to obtain the array and stand on the substrate. Electrode of a surface SnO 2 -TiO 2 core-shell nano column.
原子層沉積條件Atomic layer deposition conditions
腔體溫度：200~400℃ Cavity temperature: 200~400°C
TiCl4注入量：0.196cc TiCl4 injection amount: 0.196cc
H2O注入量：0.8cc H 2 O injection amount: 0.8cc
氣體循環次數：200cycle Number of gas cycles: 200cycle
單次循環時間：8sec/cycle Single cycle time: 8sec/cycle
參閱圖8~圖10，圖8是該TiO2殼層的沉積溫度為200℃的SEM照片，由圖8可看到該殼層的表面呈現平整的薄膜態樣，圖9、圖10則是將該TiO2殼層的沉積溫度控制在 400℃條件下的SEM及TEM照片，由圖9、圖10可清楚的看到該TiO2是由多數的晶粒堆積而成，因此，該殼層表面具有較高的粗糙度。 Referring to FIG. 8 to FIG. 10, FIG. 8 is a SEM photograph of the deposition temperature of the TiO 2 shell layer at 200 ° C. It can be seen from FIG. 8 that the surface of the shell layer exhibits a flat film state, and FIG. 9 and FIG. The SEM and TEM photographs of the deposition temperature of the TiO 2 shell layer were controlled at 400 ° C. It can be clearly seen from FIGS. 9 and 10 that the TiO 2 is formed by stacking a large number of crystal grains. Therefore, the shell layer is formed. The surface has a high roughness.
綜上所述，本發明主要利用陽極氧化的製程控制得到具有多個貫通的通孔23的多孔性模板，由於該些通孔23可與該基材21連通，因此，利用原子層沉積方式即可於該些通孔23中沉積形成與該基材21連接的核層31，而該多孔性模板則可利用濕式蝕刻方式輕易移除；將該多孔性模板移除後即可得到多個呈陣列排列並與該基材21連結的核層31，之後再利用原子層沉積方式於該些核層31表面沉積殼層32後即可得到多個有序排列於該基材21表面的核-殼結構奈米柱；此外，本發明還可利用該具有不同厚度的鋁層22b的結構設計，藉由陽極氧化蝕刻時間的控制，而在對應該第一厚度A及第二厚度B的位置達成不同的蝕刻程度，增加該多孔性模板與該基材21的接著性，而可降低因為鋁層的厚度均一時，蝕刻時間控制不當、或是完全產生該些通孔23時，由於該多孔性模板與該基材21之間因為接觸面積變少造成接著性變差而剝落的缺點，不僅製程簡便且因為製得的核-殼結構奈米柱為有序排列的站立在該基材21，因此三度空間效益佳，可更簡易且廣泛的應用在不同的領域，故確實可達成本發明之目的。 In summary, the present invention mainly uses a process control of anodization to obtain a porous template having a plurality of through-holes 23 therethrough. Since the through-holes 23 can communicate with the substrate 21, the atomic layer deposition method is used. A core layer 31 connected to the substrate 21 may be deposited in the through holes 23, and the porous template may be easily removed by wet etching; and the porous template may be removed to obtain a plurality of The core layer 31 is arranged in an array and connected to the substrate 21, and then the shell layer 32 is deposited on the surface of the core layer 31 by atomic layer deposition to obtain a plurality of cores arranged in order on the surface of the substrate 21. - Shell structure nano column; in addition, the present invention can also utilize the structural design of the aluminum layer 22b having different thicknesses, by controlling the anodization etching time, at positions corresponding to the first thickness A and the second thickness B Different degrees of etching are achieved to increase the adhesion between the porous template and the substrate 21, and the porosity can be reduced because the thickness of the aluminum layer is uniform, the etching time is improperly controlled, or the through holes 23 are completely generated. Template and the substrate 21 The disadvantage of peeling off due to poor contact area due to less contact area, not only is the process simple, but also because the prepared core-shell structure nano column is arranged in order on the substrate 21, so the three-dimensional space is good. It can be applied more easily and widely in different fields, so it can be achieved for the purpose of the invention.
惟以上所述者，僅為本發明之較佳實施例而已，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍內。 The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are Still It is within the scope of the patent of the present invention.
2‧‧‧基板 2‧‧‧Substrate
21‧‧‧基材 21‧‧‧Substrate
211‧‧‧絕緣本體 211‧‧‧Insulated body
212‧‧‧導電層 212‧‧‧ Conductive layer
213‧‧‧表面 213‧‧‧ surface
22a‧‧‧鋁層 22a‧‧‧Aluminum layer
22‧‧‧陽極氧化鋁層 22‧‧‧anodized aluminum oxide layer
23a‧‧‧孔洞 23a‧‧‧ Hole
23‧‧‧通孔 23‧‧‧through hole
3‧‧‧奈米柱 3‧‧‧Neizhu
3a‧‧‧奈米管 3a‧‧‧Nei tube
31‧‧‧核層 31‧‧‧ nuclear layer
311‧‧‧第一核層 311‧‧‧ first nuclear layer
312‧‧‧第二核層 312‧‧‧Second nuclear
32‧‧‧殼層 32‧‧‧ Shell
4‧‧‧表層 4‧‧‧ surface layer
51‧‧‧多孔性模板製備步驟 51‧‧‧Porous template preparation steps
52‧‧‧第一沉積步驟 52‧‧‧First deposition step
53‧‧‧移除步驟 53‧‧‧Remove steps
54‧‧‧第二沉積步驟 54‧‧‧Second deposition steps
100‧‧‧半成品 100‧‧‧ semi-finished products
A‧‧‧第一厚度 A‧‧‧first thickness
B‧‧‧第二厚度 B‧‧‧second thickness
圖1是一示意圖，說明由該較佳實施例製得的核-殼結構奈米柱；圖2是一流程圖，說明本發明核-殼結構奈米柱電極的製備方法的該較佳實施例；圖3是一流程示意圖，輔助說明圖2；圖4是一電流密度-時間曲線圖，說明該蝕刻終止點；圖5是一示意圖，說明由該較佳實施例的核-殼結構為具有多層的態樣圖6是一SEM圖，說明該具體例1製得的多孔性模板；圖7是一SEM圖，說明該具體例1製得的半成品的俯視圖；圖8是一SEM圖，說明該具體例1於200℃沉積條件下製得的核-殼結構奈米柱；圖9是一SEM圖，說明該具體例1於400℃沉積條件下製得的核-殼結構奈米柱；及圖10是一TEM圖，輔助說明圖9。 1 is a schematic view showing a core-shell structure nano column prepared by the preferred embodiment; and FIG. 2 is a flow chart showing the preferred embodiment of the method for preparing a core-shell structure nano column electrode of the present invention. FIG. 3 is a schematic flow chart for assistance in explaining FIG. 2; FIG. 4 is a current density-time graph illustrating the etching termination point; FIG. 5 is a schematic view showing the core-shell structure of the preferred embodiment FIG. 6 is an SEM image illustrating the porous template prepared in the specific example 1; FIG. 7 is an SEM image illustrating a top view of the semi-finished product obtained in the specific example 1, and FIG. 8 is an SEM image. The core-shell structure nano column prepared by the specific example 1 under the deposition condition of 200 ° C is illustrated; FIG. 9 is an SEM image illustrating the core-shell structure nano column prepared by the specific example 1 under the deposition condition of 400 ° C. And FIG. 10 is a TEM diagram, and FIG. 9 is assisted.
51‧‧‧多孔性模板製備步驟 51‧‧‧Porous template preparation steps
53‧‧‧移除步驟 53‧‧‧Remove steps
52‧‧‧第一沉積步驟 52‧‧‧First deposition step
54‧‧‧第二沉積步驟 54‧‧‧Second deposition steps
Claims (9)
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|---|---|---|---|
| TW101137705A TW201414879A (en) | 2012-10-12 | 2012-10-12 | Method for producing core-shell structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101137705A TW201414879A (en) | 2012-10-12 | 2012-10-12 | Method for producing core-shell structure |
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| Publication Number | Publication Date |
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| TW201414879A true TW201414879A (en) | 2014-04-16 |
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2012
- 2012-10-12 TW TW101137705A patent/TW201414879A/en unknown
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