TW201351901A - High frequency wiring structure, high frequency installation substrate, manufacturing method for high frequency wiring structure, and waveform rectification method for high frequency signals - Google Patents
High frequency wiring structure, high frequency installation substrate, manufacturing method for high frequency wiring structure, and waveform rectification method for high frequency signals Download PDFInfo
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本發明係有關於一種高頻用配線構造體、高頻用安裝基板、高頻用配線構造體之製造方法、及高頻訊號之波形整形方法，其係形成高頻訊號之訊號波形。 The present invention relates to a high-frequency wiring structure, a high-frequency mounting substrate, a method for manufacturing a high-frequency wiring structure, and a waveform shaping method for a high-frequency signal, which form a signal waveform of a high-frequency signal.
若將複數條傳輸線接近配置，則傳輸線間會互相帶來雜訊而產生所謂串音的現象。串音會造成電流流至無訊號之傳輸線，或者傳輸訊號之傳輸線間使訊號的電壓波形互相變形。產生串音的原因係將訊號輸入至傳輸線時，有時會因該訊號而產生電磁力，進而電磁力線使鄰接的傳輸線產生感應電動勢。串音所造成的雜訊帶有越高頻而雜訊會越大的性質。 If a plurality of transmission lines are arranged close to each other, the transmission lines will cause noise to each other to cause so-called crosstalk. Crosstalk causes current to flow to the signal-free transmission line, or the signal waveforms of the transmission signal cause the voltage waveforms of the signals to be deformed. The reason for the crosstalk is that when the signal is input to the transmission line, the electromagnetic force is sometimes generated by the signal, and the electromagnetic force line causes the adjacent transmission line to generate an induced electromotive force. The noise caused by crosstalk has the property of higher frequency and higher noise.
第31圖係將引起串音的二條傳輸線11、12加以模型化的電路圖。將二條傳輸線11、12中其中一條作為傳輸訊號的有效線路11，另一條則作為無訊號的靜止線路12。第31圖中的Rd係阻尼電阻、Rt係終端電阻，任一電阻皆係為了阻抗匹配而連接。 Fig. 31 is a circuit diagram in which two transmission lines 11, 12 causing crosstalk are modeled. One of the two transmission lines 11, 12 is used as the effective line 11 for transmitting signals, and the other is used as the stationary line 12 without signals. The Rd-type damping resistor and the Rt-type terminating resistor in Fig. 31 are connected for impedance matching.
第32圖係將250MHz的低頻訊號及5GHz的高頻訊號輸入至第31圖的有效線路11時各串音的模擬波形圖。如第32圖所示，將低頻訊號輸入至有效線路11時，有效線路11與靜止線路12雙方之雜訊的影響皆小，有效線路11的訊號波形幾乎未變形，在靜止線路12產生的雜訊成份亦小。相對於此，將高頻訊號輸入至有效線路11時，串音的影響變大， 有效線路11的訊號波形變形，在靜止線路12則出現大的雜訊訊號。 Fig. 32 is an analog waveform diagram of each crosstalk when a low frequency signal of 250 MHz and a high frequency signal of 5 GHz are input to the effective line 11 of Fig. 31. As shown in Fig. 32, when the low frequency signal is input to the effective line 11, the influence of the noise of both the effective line 11 and the stationary line 12 is small, the signal waveform of the effective line 11 is hardly deformed, and the noise generated in the stationary line 12 is small. The content of the news is also small. In contrast, when a high frequency signal is input to the effective line 11, the influence of crosstalk becomes large. The signal waveform of the active line 11 is distorted, and a large noise signal appears on the stationary line 12.
因應串音之最有效的對策係將傳輸線間的間隔擴大，但在LSI等高積體零件間進行配線時，並不容易擴大配線間的距離，勢必需要其他對策。 The most effective countermeasure against crosstalk is to increase the interval between transmission lines. However, when wiring is performed between high-product parts such as LSI, it is not easy to increase the distance between wirings, and other measures are necessary.
本發明者在過去因應在配線圖案上阻抗失配之反射波所帶來之波形變形的對策，設計了一種分割區段傳輸線(STL：Segmental Transmission Line)：將配線圖案分割為複數區段，利用使反射波發生在各區段的邊界，使反射波之間重合而互相抵消，以進行訊號的波形整形(參照專利文獻1)。 The inventors of the present invention have designed a segmented transmission line (STL: Segmental Transmission Line) in response to a countermeasure against waveform distortion caused by a reflected wave of impedance mismatch on a wiring pattern: dividing a wiring pattern into a plurality of segments, and utilizing The reflected wave is generated at the boundary of each segment, and the reflected waves are superimposed on each other to cancel each other to perform waveform shaping of the signal (see Patent Document 1).
專利文獻1：日本特開2005-150644號公報 Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-150644
專利文獻1所揭示的STL僅以單一配線圖案為對象，並未揭示針對對應於可能產生串音之複數傳輸線的複數配線圖案，進行STL設計的具體作法。 The STL disclosed in Patent Document 1 is only for a single wiring pattern, and does not disclose a specific method of performing STL design for a complex wiring pattern corresponding to a complex transmission line that may generate crosstalk.
為了解決上述課題，本發明提供一種高頻用配線構造體、高頻用配線構造體之形成方法、及高頻訊號之波形整形方法，其能減少可能產生串音之複數傳輸線上訊號的變形或因串音而起之雜訊。 In order to solve the above problems, the present invention provides a high-frequency wiring structure, a method for forming a high-frequency wiring structure, and a waveform shaping method for a high-frequency signal, which can reduce distortion of a signal on a complex transmission line where crosstalk may occur or The noise caused by crosstalk.
為了解決上述課題，本發明之一態樣，係一種高頻用配線構造體，其具有對應於分別傳輸高頻訊號且鄰接配置 之複數傳輸線的複數配線圖案。前述複數配線圖案之各配線圖案係連續地將分別具有固有之特性阻抗及區段長度的複數區段連結者。鄰接配置之前述複數配線圖案之中，相鄰之二條配線圖案係配置於會發生因串音而起之雜訊的距離內。前述複數配線圖案各別具有之各前述複數區段的前述特性阻抗及區段長度係決定成：利用發生在鄰接的二個前述區段間之境界的反射波與前述雜訊重疊而互相抵消，以使傳播於前述複數傳輸線之訊號的波形於該等傳輸線上的觀測點成形。 In order to solve the above problems, an aspect of the present invention provides a high-frequency wiring structure having a high-frequency signal and an adjacent configuration corresponding to each other. A plurality of wiring patterns of the plurality of transmission lines. Each of the wiring patterns of the plurality of wiring patterns continuously connects a plurality of segments each having a specific characteristic impedance and a segment length. Among the plurality of wiring patterns arranged adjacent to each other, the adjacent two wiring patterns are disposed within a distance at which noise due to crosstalk occurs. The characteristic impedance and the segment length of each of the plurality of segments included in each of the plurality of wiring patterns are determined such that a reflected wave generated at a boundary between two adjacent segments overlaps with the noise to cancel each other. The waveforms of the signals transmitted through the plurality of transmission lines are formed on the observation points of the transmission lines.
又，本發明之一態樣，係一種高頻用配線構造體之製造方法，係將對應於分別傳輸高頻訊號且鄰接配置之複數傳輸線的複數配線圖案形成於基板上。前述複數配線圖案之各配線圖案係連續地將分別具有固有之特性阻抗及區段長度的複數區段連結者。利用最佳化演算法，對前述複數配線圖案之各配線圖案中各前述複數區段的前述特性抗阻及區段長度進行設計，以使在已將具有預定訊號波形之指令訊號輸入至鄰接配置之前述複數配線圖案中至少一條的狀態下，可減少傳播於前述複數配線圖案之因應前述指令訊號的高頻訊號波形變形及雜訊的反射波，發生在前述複數配線圖案之各配線圖案中鄰接的二個前述區段間之境界，前述反射波與前述雜訊重疊而互相抵消，使傳播前述複數傳輸線之高頻訊號於該等傳輸線上的觀測點進行整形。 Further, an aspect of the present invention provides a method of manufacturing a high-frequency wiring structure in which a plurality of wiring patterns corresponding to respective high-frequency transmission lines and adjacent to each other are formed on a substrate. Each of the wiring patterns of the plurality of wiring patterns continuously connects a plurality of segments each having a specific characteristic impedance and a segment length. Using the optimization algorithm, the characteristic resistance and the segment length of each of the plurality of segments in each of the plurality of wiring patterns are designed to input a command signal having a predetermined signal waveform to the adjacent configuration. In a state in which at least one of the plurality of wiring patterns is provided, the high-frequency signal waveform distortion and the reflected wave of the noise transmitted through the plurality of wiring patterns in response to the command signal are reduced, and the adjacent wiring patterns of the plurality of wiring patterns are adjacent to each other. The boundary between the two aforementioned segments, the reflected wave and the noise overlap and cancel each other, so that the high-frequency signals propagating the complex transmission line are shaped on the observation points on the transmission lines.
依據本發明，能適當地將傳播於可能產生串音地接近配置之複數配線圖案上的高頻訊號進行整形。 According to the present invention, it is possible to appropriately shape a high-frequency signal that propagates on a plurality of wiring patterns that are likely to generate crosstalk.
第1圖係本發明之一實施形態的高頻用配線構造體1的STL設計模型圖。 Fig. 1 is a view showing an STL design model of the high-frequency wiring structure 1 according to an embodiment of the present invention.
第2圖係STL設計後各區段4的形狀的示意圖。 Figure 2 is a schematic illustration of the shape of each segment 4 after STL design.
第3圖係顯示STL設計之處理順序的流程圖。 Figure 3 is a flow chart showing the processing sequence of the STL design.
第4圖係顯示將染色體對映至第1圖的主配線圖案之例的圖。 Fig. 4 is a view showing an example in which a chromosome is mapped to the main wiring pattern of Fig. 1.
第5(a)圖係STL中之1點交叉的概要圖；第5(b)圖係混合交叉的概要圖。 Fig. 5(a) is a schematic diagram of the intersection of one point in the STL; and Fig. 5(b) is a schematic diagram of the hybrid intersection.
第6圖係說明誤差面積的圖。 Figure 6 is a diagram illustrating the error area.
第7圖係MGG的概要圖。 Figure 7 is a schematic diagram of the MGG.
第8圖係評估有2種類時之Pareto解(Pareto solution)的概要圖。 Fig. 8 is a schematic diagram of the Pareto solution when there are two types of evaluations.
第9圖係顯示將配線圖案分割為16個區段，並以第3圖之處理順序將各區段之參數進行計算的結果的圖。 Fig. 9 is a view showing a result of dividing the wiring pattern into 16 segments and calculating the parameters of the respective segments in the processing order of Fig. 3.
第10圖係將第9圖圖示化的圖。 Fig. 10 is a diagram in which Fig. 9 is illustrated.
第11圖係將250MHz的時脈訊號輸入至有效線路2時，在有效線路2及靜止線路3之兩觀測點的訊號波形圖。 Fig. 11 is a signal waveform diagram of two observation points of the effective line 2 and the stationary line 3 when the 250 MHz clock signal is input to the effective line 2.
第12圖係未進行STL設計之一般配線的訊號波形圖。 Figure 12 is a signal waveform diagram of a general wiring without STL design.
第13圖係顯示將有效線路2的波形變形及靜止線路3的雜訊波形納入考慮而進行了STL設計之結果的圖。 Fig. 13 is a view showing the result of performing STL design in consideration of the waveform distortion of the effective line 2 and the noise waveform of the stationary line 3.
第14圖係將第13圖圖示化的圖。 Fig. 14 is a diagram showing the Fig. 13 diagram.
第15圖係利用了第13圖及第14圖的STL設計結果時，在有效線路2及靜止線路3之兩觀測點的訊號波形圖。 Fig. 15 is a diagram showing signal waveforms at two observation points of the effective line 2 and the stationary line 3 when the STL design results of Figs. 13 and 14 are used.
第16圖係顯示將時脈訊號亦輸入至靜止線路3時之傳輸線模型的圖。 Fig. 16 is a view showing a transmission line model when a clock signal is also input to the stationary line 3.
第17圖係將同相位之時脈訊號輸入至未進行STL設計之二個一般配線圖案時，在觀測點的訊號波形圖。 Figure 17 shows the signal waveform at the observation point when the clock signal of the same phase is input to the two general wiring patterns that are not designed for STL.
第18圖係將1/4相位差之時脈訊號輸入至未進行STL設計之二個一般配線圖案時，在觀測點的訊號波形圖。 Figure 18 is a signal waveform diagram at the observation point when a clock signal of 1/4 phase difference is input to two general wiring patterns that are not designed for STL.
第19圖係將同相位之時脈訊號輸入至已進行STL設計之二個配線圖案時，在觀測點的訊號波形圖。 Figure 19 is a signal waveform diagram at the observation point when the clock signal of the same phase is input to the two wiring patterns that have been designed for STL.
第20圖係將1/4相位差之時脈訊號輸入至已進行STL設計之二個配線圖案時，在觀測點的訊號波形圖。 Figure 20 is a signal waveform diagram at the observation point when a clock signal of 1/4 phase difference is input to two wiring patterns that have been designed for STL.
第21圖係利用於訊號波形之觀測的印刷基板10的外觀圖。 Fig. 21 is an external view of the printed circuit board 10 used for observation of signal waveforms.
第22圖係輸入至印刷基板10之時脈訊號的波形圖。 Fig. 22 is a waveform diagram of a clock signal input to the printed circuit board 10.
第23圖係形成於印刷基板10之一般配線圖案11、12上的觀測點的訊號波形圖。 Fig. 23 is a signal waveform diagram of observation points formed on the general wiring patterns 11, 12 of the printed circuit board 10.
第24圖係在形成於印刷基板10上且進行了STL設計之配線圖案上的觀測點的訊號波形圖。 Fig. 24 is a signal waveform diagram of observation points on a wiring pattern formed on the printed circuit board 10 and subjected to STL design.
第25圖係說明符碼間干擾的圖。 Figure 25 is a diagram illustrating inter-symbol interference.
第26(a)圖係說明孤立波的位元模式、第26(b)圖係說明以孤立波作為指令訊號時之誤差面積的圖。 Fig. 26(a) shows the bit pattern of the solitary wave, and Fig. 26(b) shows the error area when the solitary wave is used as the command signal.
第27圖說明眼圖的圖。 Figure 27 illustrates a diagram of the eye diagram.
第28圖係顯示使用孤立波訊號進行了STL設計之一條 配線圖案上的觀測波形及指令波形的圖。 Figure 28 shows one of the STL designs using solitary wave signals. A diagram of the observed waveform and the command waveform on the wiring pattern.
第29圖係顯示使指令訊號之上升部分過衝，且下降部分下衝的例子的圖。 Fig. 29 is a view showing an example in which the rising portion of the command signal is overshooted and the falling portion is undershooted.
第30圖係顯示使指令訊號之上升部分過衝，且下降部分下衝而進行了STL設計時，觀測訊號波形的波形圖。 Figure 30 is a waveform diagram showing the waveform of the observed signal when the rising portion of the command signal is overshooted and the falling portion is undershooted and the STL design is performed.
第31圖係將引起串音之二條傳輸線11、12加以模型化的電路圖。 Fig. 31 is a circuit diagram in which two transmission lines 11, 12 causing crosstalk are modeled.
第32圖係將250MHz的低頻訊號及5GHz的高頻訊號輸入至第31圖的有效線路11時，各串音的模擬波形圖。 Fig. 32 is an analog waveform diagram of each crosstalk when a low frequency signal of 250 MHz and a high frequency signal of 5 GHz are input to the effective line 11 of Fig. 31.
以下，將針對本發明之實施形態詳細地作說明。 Hereinafter, embodiments of the present invention will be described in detail.
第1圖係本發明之一實施形態的高頻用配線構造體1的STL設計模型圖。第1圖的高頻用配線構造體1係形成於絕緣基板上者，且具有會產生串音地接近配置的二條配線圖案2、3。二條配線圖案2、3分別根據STL設計分割為複數區段4。在第1圖的STL設計模型中，二條配線圖案2、3的間隔為0.4mm、二條配線圖案2、3的長度皆為400mm、訊號頻率為250MHz。若考量電腦零件或LSI等，傳輸線長度為400mm並不真實，但其係假設成傳輸線長度20mm、傳輸線間隔0.02mm、5GHz的放大比例為20倍者。 Fig. 1 is a view showing an STL design model of the high-frequency wiring structure 1 according to an embodiment of the present invention. The high-frequency wiring structure 1 of the first embodiment is formed on an insulating substrate, and has two wiring patterns 2 and 3 that are arranged close to each other in a crosstalk. The two wiring patterns 2 and 3 are respectively divided into a plurality of sections 4 in accordance with the STL design. In the STL design model of Fig. 1, the interval between the two wiring patterns 2 and 3 is 0.4 mm, the lengths of the two wiring patterns 2 and 3 are both 400 mm, and the signal frequency is 250 MHz. If you consider computer parts or LSI, etc., the transmission line length of 400mm is not true, but it is assumed to be 20mm of transmission line length, 0.02mm of transmission line spacing, and 20 times magnification of 5GHz.
在第1圖中，將二條配線圖案2、3中其中一條作為有效線路2，其一端透過阻尼電阻Rd連接有訊號源5，該訊號源5係將250MHz的時脈訊號輸入至有效線路2的一端。有效線路另一端係透過終端電阻Rt接地。又，另一條配線圖案則 作為靜止線路3不輸入訊號，其二端透過終端電阻Rd、Rt接地。 In the first figure, one of the two wiring patterns 2, 3 is used as the effective line 2, and one end thereof is connected to the signal source 5 through the damping resistor Rd. The signal source 5 inputs the 250 MHz clock signal to the effective line 2. One end. The other end of the active line is grounded through the terminating resistor Rt. Again, another wiring pattern As the stationary line 3, no signal is input, and the two ends thereof are grounded through the terminating resistors Rd and Rt.
以下將針對二條配線圖案2、3的STL設計作說明。第2圖係顯示STL設計後各區段4的形狀的示意圖。在STL中，係將傳輸線分割為複數區段4，並給予每一區段4相異的配線長度及配線寬度(特性阻抗)。在相異配線寬度之區段4的境界會引起阻抗失配，發生訊號的反射。在STL中，係使在各區段4之境界的反射波、與因串音等其他原因而變形的輸入訊號重合，而對訊號變形的成份進行補償，藉此，於觀測點進行訊號波形的整形。 The STL design of the two wiring patterns 2 and 3 will be described below. Figure 2 is a schematic diagram showing the shape of each segment 4 after STL design. In the STL, the transmission line is divided into a plurality of sections 4, and each of the sections 4 is given a different wiring length and wiring width (characteristic impedance). The boundary of the segment 4 of the different wiring width causes an impedance mismatch and a reflection of the signal occurs. In the STL, the reflected waves at the boundary of each segment 4 are superimposed on the input signals deformed by other causes such as crosstalk, and the components of the signal distortion are compensated, thereby performing signal waveforms at the observation points. Plastic surgery.
反射波到達觀測點當然係在使該反射波發生的輸入訊號之後。於觀測點，例如係輸入時脈訊號作為輸入訊號時，係利用與時脈訊號發生的反射波重合而進行整形。 The reflected wave arrives at the observation point, of course, after the input signal that causes the reflected wave to occur. At the observation point, for example, when the input pulse signal is used as the input signal, the reflection is performed by using the reflected wave generated by the clock signal to be shaped.
STL設計係指求算於觀測點可觀測出被整形程度最大訊號波形之各區段4的阻抗(由於在配線圖案的情況下，一般不易根據位置任意形成厚度或素材，因此，在本實施形態係固定材料或厚度，而線寬則可變化)及長度。由於各區段4之寬度及長度的組合存在龐大的數目，不可能對全部的組合進行評估。對此，STL設計係利用將生物進化模型化的最佳演算法，即遺傳基因演算法(GA：Genetic Algorithm)。GA已適用於針對組合總數龐大之各種組合展開問題，且其有效性已獲高度評價。 The STL design refers to the impedance of each segment 4 that can be observed at the observation point to observe the most shaped signal waveform. (In the case of the wiring pattern, it is generally difficult to form the thickness or material arbitrarily according to the position. Therefore, in the present embodiment, The material or thickness is fixed, and the line width is variable) and the length. Since there is a large number of combinations of the widths and lengths of the segments 4, it is impossible to evaluate all the combinations. In this regard, the STL design system utilizes the best algorithm for modeling biological evolution, namely the Genetic Algorithm (GA). GA has been applied to develop problems for various combinations of large combinations, and its effectiveness has been highly valued.
第3圖係顯示STL設計之處理順序的流程圖。在GA中，首先生成以亂數決定各區段4之參數(寬度及長度)的初期 個體，之後重複進行交叉、突變、適合評估及選擇，至滿足結束條件為止。結束條件係指判斷是否已進化至預先決定的世代數目。 Figure 3 is a flow chart showing the processing sequence of the STL design. In GA, first, the initial parameters (width and length) of each segment 4 are determined by random numbers. Individuals, then repeat crossovers, mutations, suitable assessments and selections until the end condition is met. The end condition refers to determining whether it has evolved to a predetermined number of generations.
在第3圖中的GA係利用染色體進行遺傳性的操作。例如，第4圖係顯示將染色體對映至第1圖的主配線圖案之例。如第4圖所示，染色體係以各區段的配線長度Li及特性阻抗Zi二種類的基因所構成，一種染色體代表一種電路。在此，染色體與個體係以相同意思來使用。 The GA system in Fig. 3 uses a chromosome to perform hereditary operations. For example, Fig. 4 shows an example in which a chromosome is mapped to the main wiring pattern of Fig. 1. As shown in Fig. 4, the dyeing system is composed of two types of genes: the wiring length Li and the characteristic impedance Zi of each segment, and one chromosome represents a circuit. Here, the chromosome and the system are used in the same meaning.
在第3圖的GA中，首先進行隨機作成數百個染色體的初期個體生成(第1步驟S1)。該等數百個染色體，即數百個電路為初期個體。使用該初期個體，進行GA的解搜尋。 In the GA of Fig. 3, first, initial generation of hundreds of chromosomes is randomly performed (first step S1). These hundreds of chromosomes, hundreds of circuits, are early individuals. Using the initial individual, a GA search was performed.
接著，進行交叉(第2步驟S2)。交叉係將生物經由交配留有子孫一事加以模型化者，且係更換個體基因的操作。真實的生命係經由交叉生下兼具雙親特徵的子代。在本實施形態的STL設計中，係於特性阻抗的交叉使用1點交叉，於區段長度的交叉使用混合交叉(BLX-α)(參照小野功，佐藤浩，小林重信，“利用單峰常態分配交叉UNDX之實數編碼基因演算法的函數最適化”，人工智慧學會誌，vol14,no.6,pp.1146-1155,Nov.1999)。 Next, the intersection is performed (second step S2). The cross system models the organisms by mating with the offspring, and is the operation of replacing the individual genes. The real life system is a child born through cross-section with both parents. In the STL design of the present embodiment, the crossover of the characteristic impedance is performed at one point, and the crossover of the segment length is used by the hybrid crossover (BLX-α) (refer to Ono, Sato, Kobayashi, "Using the unimodal normal state" The function of assigning real-coded gene algorithms for crossover UNDX is optimized", AI, vol14, no.6, pp.1146-1155, Nov. 1999).
1點交叉係以亂數選擇1點染色體的交叉點，再交換該點前後的元素的方法。第5(a)圖係STL之1點交叉的概要圖。 The 1-point crossover method is a method of selecting the intersection of the 1-point chromosome by random numbers and exchanging the elements before and after the point. Fig. 5(a) is a schematic diagram showing the intersection of 1 point of the STL.
混合交叉係在參數的決定上選擇近似雙親之性質的方法。第5(b)圖係混合交叉的概要圖。如第5(b)圖所示， 以Ln為親代1的區段長度比，以Mn為親代2的區段長度比。在混合交叉中，係取得雙親間的差值d，並將該值向區間兩側擴張α d(α係常數)的區域作為子代的解空間。藉由亂數從該解空間中選擇複數子代個體。作成的子代個體數量一定，並作為參數而給予之。 The hybrid crossover system selects a method that approximates the nature of the parent on the decision of the parameters. Figure 5(b) is a schematic diagram of a hybrid intersection. As shown in Figure 5(b), The ratio of the length of the segment with Ln as the parent 1 and the length ratio of the segment with Mn as the parent 2. In the hybrid intersection, the difference d between the parents is obtained, and the region where the value is expanded to the α d (α-system constant) on both sides of the interval is used as the solution space of the child. Multiple child generations are selected from the solution space by random numbers. The number of children produced is a certain number and is given as a parameter.
在第3圖的GA中，針對執行了第2步驟S2之交叉的雙親及子代個體進行適合度評估，求算各個體的評估值(第3步驟S3)。在此，利用所求得之各區段4的特性阻抗及配線長度的組合作成電路，對該電路的訊號波形進行評估。 In the GA of FIG. 3, the parental and child progeny who performed the intersection of the second step S2 are evaluated for suitability, and the evaluation value of each body is calculated (third step S3). Here, the signal waveform of the circuit is evaluated by a combination of the characteristic impedance and the wiring length of each of the obtained sections 4.
更具體而言，首先，利用由GA所求得的阻抗及配線長度的組合，作成電路模擬器(例如SPICE)的網路表(netlist)。將所作成的網路表讀入SPICE(第4步驟S4)，輸出波形資料(第5步驟S5)。所得到的波形資料係用於評估函數的計算(第6步驟S6)。評估函數係計算理想波形與觀測波形的誤差面積。又，在本實施形態中，係根據理想波形與觀測波形的誤差面積進行評估，而亦可使用高、低(H,L)階邏輯境界或靜止線路之最大電壓、偏向、上升時間等作為指標。高、低階邏輯境界係表示於訊號線中高階、低階之電壓以最小長度從閾值偏離多少的指標。例如於有效線路中設閾值為0.5V，該值係越大(最大係0.5)越好，數位訊號反轉而傳播的可能性會降低。靜止線路最大電壓係於靜止線路中作為雜訊而產生之電壓的最大值。偏向在本說明書中係表示相對於理想時脈訊號超過閾值(例如0.5V)的時刻，觀測波形超過閾值的時刻偏差多少程度的 指標。該值係越接近0越好，而不易引起時點偏差等問題。上升時間係表示訊號由L變化至H時訊號的上升時間的指標，例如作為20-80%的上升時間，係使用訊號之波形由高階電壓值的20%變化至80%的時間。藉此，對訊號之重要的上升時間進行評估。 More specifically, first, a netlist of a circuit simulator (for example, SPICE) is created using a combination of impedance and wiring length obtained by GA. The created network table is read into the SPICE (step 4 S4), and the waveform data is output (the fifth step S5). The obtained waveform data is used for the calculation of the evaluation function (step 6 S6). The evaluation function calculates the error area of the ideal waveform and the observed waveform. Further, in the present embodiment, the error waveform is evaluated based on the ideal waveform and the observed waveform, and the maximum voltage, the bias, the rise time, and the like of the high and low (H, L)-order logical boundaries or the stationary line may be used as indicators. . The high and low-order logic states are indicators that indicate how much the high-order, low-order voltages in the signal line deviate from the threshold with a minimum length. For example, if the threshold value is 0.5V in the effective line, the larger the value is (the maximum is 0.5), the better the digital signal is reversed and the probability of propagation is reduced. The maximum voltage of the stationary line is the maximum value of the voltage generated as noise in the stationary line. In the present specification, the degree of deviation from the time when the observed waveform exceeds the threshold is indicated with respect to the time when the ideal clock signal exceeds the threshold (for example, 0.5 V). index. The closer the value is to 0, the less likely it is to cause problems such as time-point deviation. The rise time is an index indicating the rise time of the signal when the signal changes from L to H. For example, as a rise time of 20-80%, the waveform of the signal is changed from 20% of the high-order voltage value to 80% of the time. In this way, the important rise time of the signal is evaluated.
第6圖係說明誤差面積的圖。在第6圖中，理想波形I(t)與觀測波形O(t)的差值為誤差面積S。理想波形I(t)係形成進化目標的理想指令波形，而觀測波形O(t)係在STL設計所觀測的波形。在STL設計的GA係進行使觀測波形O(t)進化而漸漸近似指令波形的處理，以使誤差面積變小。然後，輸出更接近指令波形之波形的個體，稱之為優良的解。 Figure 6 is a diagram illustrating the error area. In Fig. 6, the difference between the ideal waveform I(t) and the observed waveform O(t) is the error area S. The ideal waveform I(t) is the ideal command waveform that forms the evolutionary target, and the observed waveform O(t) is the waveform observed in the STL design. In the GA system designed by STL, the observation waveform O(t) is evolved to gradually approximate the command waveform, so that the error area is reduced. Then, the individual who outputs the waveform closer to the command waveform is called an excellent solution.
誤差面積S係利用以下列之第(1)式表示。 The error area S is expressed by the following formula (1).
第(1)式S=ʃ|I(t)-O(t)|dt………(1) Equation (1) S=ʃ|I(t)-O(t)|dt.........(1)
在第3圖的GA中，第3步驟S3的處理結束後則進行選擇處理(第7步驟S7)。該選擇處理係將自然淘汰加以模型化者。自然淘汰係指生物進化中所產生的變化於該生物所處之環境下若為有利的話，該變化會殘留下來者。在選擇處理中，首先求出各個體之下一代的易殘存程度，即該個體的優良程度，再據此形成下一世代的母群體。該下一世代的易殘存程度則稱為適合度(Fitness)。 In the GA of Fig. 3, after the processing of the third step S3 is completed, the selection processing is performed (the seventh step S7). This selection process will naturally eliminate the modeler. Natural elimination refers to the change that occurs in the evolution of a living being, if it is advantageous in the environment in which the organism is located, the change will remain. In the selection process, first, the degree of resilience of the next generation of each body, that is, the degree of excellence of the individual, is determined, and then the parent group of the next generation is formed accordingly. The degree of resilience of the next generation is called fitness.
在STL設計中，係將Minimum Generation Gap(MGG)應用在第3圖之選擇處理的模型(佐藤浩，小野功，小林重信，“GA之世代交替模型的提案與評估”，人工智慧學會 誌，vol.12,no.5,pp.734-744,Sep.1997)。 In the STL design, the Minimum Generation Gap (MGG) is applied to the model selected and processed in Figure 3 (Sato Sato, Ono, Kobayashi, "Proposal and Evaluation of GA Generational Alternation Model", Artificial Intelligence Society Zhi, vol. 12, no. 5, pp. 734-744, Sep. 1997).
第7圖係MGG的概要圖。MGG係利用盡可能地減少在世代交替時更換的個體，來抑制適合度突出之個體的特徵在個體群體內快速擴張。結果，因搜尋的中後期亦存在多樣的個體，可抑制進化在途中停止。 Figure 7 is a schematic diagram of the MGG. The MGG system utilizes as much as possible to reduce individuals that are replaced during generational alternations to suppress the rapid expansion of the characteristics of individuals with outstanding fitness within the individual population. As a result, there are also diverse individuals in the middle and late stages of the search, which can inhibit the evolution from stopping on the way.
在MGG中，首先從母群體隨機且不放回地選出二個個體，並將其作為親代。不放回係指一旦被選出者則不放回母群體。 In the MGG, two individuals are first selected from the parent population randomly and without returning, and they are used as parents. Not returning means that once selected, they are not returned to the parent group.
接著，針對被選出的親代實施交叉，生成子代個體(第11步驟S11)，在此，結合親代與子代的群體稱之為家族(第12步驟S12)。 Next, the selected parent is cross-processed to generate a child individual (step 1111), where the group combining the parent and the child is called a family (12th step S12).
然後，從家族中選出一個個體。為了選出一個個體，首先要決定二個候補(第13步驟S13)。第1個選出最佳個體。最佳個體係指在家族之中，誤差面積之值最小、最優良的個體。第2個係從除去最佳個體之家族內，藉由因應適合度之輪盤作選擇。該輪盤係適合度越高的個體、即越優良的個體越容易被選出。 Then, select an individual from the family. In order to select an individual, two candidates are first determined (step 13 S13). The first one selects the best individual. The best system refers to the smallest and best individuals in the family with the smallest error area. The second is selected from the family that removes the best individual, by the roulette according to suitability. The roulette is the more suitable individual, that is, the more excellent the individual is, the easier it is to be selected.
將這些已選擇的個體放回原母群體，前進一世代(第14步驟S14)。更具體而言，重複進行第3圖的步驟S2~S7至滿足預定的結束條件為止(第3圖的第8步驟S8)。 These selected individuals are returned to the original parent group for advancement (step 14 S14). More specifically, steps S2 to S7 of FIG. 3 are repeated until the predetermined end condition is satisfied (eighth step S8 of FIG. 3).
選擇最佳解時，將解的評估有複數個時之最佳解稱為Pareto解。例如，考慮如下之情況：設解的評估為(評估1，評估2)，且解1的評估為(2000,1500)，而解2的評估為(1500,1600)。只看評估1的話，解2較好，但只看評估2的 話，解1較好。 When choosing the best solution, the best solution for the evaluation of the solution is called the Pareto solution. For example, consider the case where the evaluation of the solution is (Evaluation 1, Evaluation 2), and the evaluation of Solution 1 is (2000, 1500), and the evaluation of Solution 2 is (1500, 1600). Just look at the evaluation 1, the solution 2 is better, but only look at the evaluation 2 Words, solution 1 is better.
依此，存在複數評估時，最佳解並不限於一個。因此，會利用Pareto解。 Accordingly, in the case of a complex evaluation, the optimal solution is not limited to one. Therefore, the Pareto solution will be utilized.
Pareto解係在對其他全部解的評估與本身之評估，依評估一一進行比較時，具有任一項良好評估的解。 The Pareto solution is based on an assessment of all other solutions and an assessment of itself, and is based on any one of the evaluations.
第8圖係評估有2種類時之Pareto解的概要圖。於第8圖顯示：以橫軸為評估1，縱軸為評估2時之解的分布中，Pareto解相當於何者。第8圖的斜線部分係優於本身之解的範圍。在優於本身之解的範圍未存在任一解者則為Pareto解。該範圍顯示評估1與2皆優於本身的範圍。相反地，非Pareto解之其他解全在優於本身之解的範圍存在有一個以上其他解。 Figure 8 is a summary diagram of the Pareto solution when there are two types of evaluation. As shown in Fig. 8, the Pareto solution is equivalent to the distribution in which the horizontal axis is the evaluation 1 and the vertical axis is the solution of the evaluation 2 . The shaded portion of Fig. 8 is superior to the range of its own solution. A Pareto solution is found if there is no solution beyond the scope of the solution itself. This range shows that both evaluations 1 and 2 outperform themselves. Conversely, there are more than one other solution for other solutions of non-Pareto solutions that are better than their own solutions.
STL設計係以第3圖所示之處理順序進行。首先，為了探討是否能以STL設計減輕串音的影響，進行了不考慮有效線路2的波形變形，而將靜止線路3(第1圖中的觀測點31)之雜訊電壓變小的STL設計。以該條件進行了STL設計的結果如第9圖。第9圖係將配線圖案分割為16個區段，並以第3圖之處理順序將各區段之參數(特性阻抗及區段長度)進行計算的結果。 The STL design is performed in the order shown in Figure 3. First, in order to investigate whether the influence of crosstalk can be mitigated by the STL design, the STL design in which the noise voltage of the stationary line 3 (the observation point 31 in Fig. 1) is reduced without considering the waveform distortion of the effective line 2 is performed. . The results of the STL design under this condition are shown in Fig. 9. Fig. 9 shows the result of dividing the wiring pattern into 16 segments and calculating the parameters (characteristic impedance and segment length) of each segment in the processing order of Fig. 3.
第10圖係將第9圖圖示化者。橫軸為區段長度，縱軸係特性阻抗。在該STL設計中，有效線路2與靜止線路3皆分割為16個區段4，各線路相對應之區段間的特性阻抗相同，又，相對應之區段間的區段長度也相同。 Figure 10 is a graphical representation of Figure 9. The horizontal axis is the segment length and the vertical axis is the characteristic impedance. In the STL design, the effective line 2 and the stationary line 3 are divided into 16 sections 4, the characteristic impedances of the sections corresponding to the respective lines are the same, and the lengths of the sections between the corresponding sections are also the same.
第11圖係進行了不考慮有效線路2的波形變形，而將靜止線路3之雜訊電壓變小的STL設計，將250MHz的時脈訊號 輸入至有效線路2時，在有效線路2與靜止線路3之兩觀測點的訊號波形圖。有效線路2的訊號波形為觀測波形(STL波形)及理想波形。理想波形係輸入至有效線路2的輸入訊號波形。相對於此，第12圖係未進行STL設計之一般配線的訊號波形圖(除了為STL配線或一般配線之差異以外，其他為相同條件)。 Figure 11 shows the STL design that reduces the noise voltage of the stationary line 2 without considering the waveform distortion of the active line 2. The 250MHz clock signal is used. The signal waveform of the two observation points of the effective line 2 and the stationary line 3 when input to the effective line 2. The signal waveform of the effective line 2 is an observed waveform (STL waveform) and an ideal waveform. The ideal waveform is the input signal waveform that is input to active line 2. On the other hand, Fig. 12 is a signal waveform diagram of a general wiring in which the STL design is not performed (except for the difference of the STL wiring or the general wiring, the other conditions are the same).
若比較第11圖及第12圖，可知有效線路2的觀測波形係在第11圖呈現較為減弱的波形形狀，而靜止線路3之觀測波形係在第11圖呈現較小的振幅(一般配線為0.42V，STL配線則改善至0.18V)，雜訊減少。 Comparing Fig. 11 and Fig. 12, it can be seen that the observed waveform of the effective line 2 exhibits a weaker waveform shape in Fig. 11, and the observed waveform of the stationary line 3 exhibits a smaller amplitude in Fig. 11 (the general wiring is 0.42V, STL wiring is improved to 0.18V), and noise is reduced.
接著，將有效線路2的波形變形及靜止線路3的雜訊波形納入考慮，進行了STL設計。此時的STL設計的結果如第13圖。第14圖係將第13圖圖示化者。又，第15圖係利用了第13圖及第14圖的STL設計結果，將250MHz的時脈訊號輸入至有效線路2時，在有效線路2之遠端的觀測點21與靜止線路3之遠端的觀測點31之兩觀測點的訊號波形圖。 Next, the waveform of the effective line 2 and the noise waveform of the stationary line 3 are taken into consideration, and the STL design is performed. The result of the STL design at this time is as shown in Fig. 13. Figure 14 is a graphical representation of Figure 13. Further, Fig. 15 utilizes the STL design results of Figs. 13 and 14 to input the observation signal 21 at the far end of the effective line 2 to the stationary line 3 when the 250 MHz clock signal is input to the effective line 2. The signal waveform of the two observation points of the observation point 31 at the end.
若比較第15圖及第12圖可知，第15圖的有效線路2上的觀測點21的觀測波形，係較於第12圖的觀測波形更接近理想波形。又，第15圖的靜止線路3上的觀測點31的觀測波形，係較於第12圖之觀測波形更少雜訊。若調查評估值，相較於一般配線，偏向改善了9倍，在有效線路2上誤差面積則改善了1.27倍。特別是時脈訊號的偏向大(不佳)，會使時點偏差之虞變大，因此，能改善偏向係最理想的結果。又，相較於一般配線，靜止線路3側係靜止最大電壓從0.42V 降至0.25V，改善了1.7倍，誤差面積亦改善了1.6倍。 Comparing Fig. 15 and Fig. 12, it can be seen that the observation waveform of the observation point 21 on the effective line 2 of Fig. 15 is closer to the ideal waveform than the observation waveform of Fig. 12. Further, the observation waveform of the observation point 31 on the stationary line 3 of Fig. 15 is less noise than the observation waveform of Fig. 12. If the evaluation value is investigated, the bias is improved by 9 times compared with the general wiring, and the error area is improved by 1.27 times on the effective line 2. In particular, the bias of the clock signal is large (poor), which will increase the deviation of the time point. Therefore, the optimal result of the bias system can be improved. Moreover, compared to the general wiring, the static line 3 side is stationary at a maximum voltage of 0.42V. Dropped to 0.25V, improved by 1.7 times and the error area improved by 1.6 times.
可知：相較於只有在靜止線路3進行了整形的STL，將主動線路2的波形變形及靜止線路3的雜訊變形都納入考慮進行的STL設計，並未讓靜止線路3側的改善率大幅惡化，還能使針對有效線路2之全部的評估項目獲得了改善，減輕了二個傳輸線的串音。 It can be seen that the STL design in which the waveform of the active line 2 and the noise of the stationary line 3 are taken into consideration in comparison with the STL which has been shaped only on the stationary line 3 does not make the improvement rate of the stationary line 3 side large. The deterioration can also improve the evaluation items for all of the effective lines 2, reducing the crosstalk of the two transmission lines.
在上述說明中，係將時脈訊號只輸入有效線路2，而相較於只在印刷基板上所形成之鄰接的二條配線圖案2、3其中之一流入訊號、另一條配線圖案未流入訊號的模型，二條配線圖案2、3兩者皆流入訊號的模型較為實際。例如，以平行(同時並行地)傳輸複數訊號的匯排傳輸方式中，係在複數線路依相同方向地傳輸訊號。對此，將時脈訊號輸入至鄰接的二條配線圖案2、3兩者時，驗證是否能減輕在各配線圖案上的觀測點的串音。更具體而言，針對將同相位之時脈訊號輸入至二條配線圖案2、3之情況，以及將1/4相位差之時脈訊號輸入至二條配線圖案2、3之情況進行驗証。 In the above description, the clock signal is input only to the effective line 2, and the one of the two adjacent wiring patterns 2, 3 formed on the printed substrate only flows into the signal, and the other wiring pattern does not flow into the signal. The model, the two wiring patterns 2, 3, both of which flow into the signal model are more practical. For example, in a parallel transmission mode in which a complex signal is transmitted in parallel (simultaneously in parallel), signals are transmitted in the same direction on a plurality of lines. On the other hand, when the clock signal is input to both of the adjacent two wiring patterns 2 and 3, it is verified whether or not the crosstalk of the observation points on the respective wiring patterns can be reduced. More specifically, it is verified that the clock signal of the same phase is input to the two wiring patterns 2 and 3, and the clock signal of the 1/4 phase difference is input to the two wiring patterns 2 and 3.
直接利用第13圖及第14圖所示的STL設計結果，亦將時脈訊號輸入至第1圖的靜止線路3。用於該驗證的傳輸線模型如第16圖。以第16圖的虛線表示的模組6，係表示用於將1/4波長相位偏移的HSPICE的T-model。HSPICE的T-model的傳輸線係理想的傳輸線模組，僅考慮線路長度所引起之延遲及特性阻抗。 Directly using the STL design results shown in Figs. 13 and 14, the clock signal is also input to the stationary line 3 of Fig. 1. The transmission line model used for this verification is as shown in Fig. 16. The module 6 shown by the broken line in Fig. 16 indicates a T-model of the HSPICE for shifting the 1/4 wavelength phase. HSPICE's T-model transmission line is an ideal transmission line module that only considers the delay and characteristic impedance caused by the line length.
第17圖係將同相位之時脈訊號輸入至未進行STL設計 之二個一般配線圖案時，在觀測點(觀測點21、31)的訊號波形圖，第18圖係將1/4相位差之時脈訊號輸入至未進行STL設計之二個一般配線圖案時，在觀測點的訊號波形圖。第17圖及第18圖皆圖示有有效線路及靜止線路兩者的觀測波形(一般波形)及理想波形。 Figure 17 shows the clock signal of the same phase input to the STL design. In the case of two general wiring patterns, the signal waveforms at the observation points (observation points 21, 31), and the 18th picture when the 1/4 phase difference clock signal is input to the two general wiring patterns that are not subjected to the STL design. , the signal waveform at the observation point. Both Fig. 17 and Fig. 18 show the observed waveforms (general waveforms) and ideal waveforms of both the active line and the stationary line.
第19圖係將同相位之時脈訊號輸入至已進行STL設計之二個配線圖案時，在觀測點的訊號波形圖，第20圖係將1/4相位差之時脈訊號輸入至已進行STL設計之二個配線圖案時，在觀測點的訊號波形圖。第19圖及第20圖皆圖示有有效線路及靜止線路兩者的觀測波形(STL波形)及理想波形。 Figure 19 shows the signal waveform at the observation point when the clock signal of the same phase is input to the two wiring patterns that have been designed for STL. Figure 20 shows the clock signal of 1/4 phase difference input to the existing signal. The signal waveform of the observation point when the two wiring patterns of the STL are designed. Both Fig. 19 and Fig. 20 show the observed waveform (STL waveform) and the ideal waveform of both the active line and the stationary line.
輸入了同相位的時脈訊號時，如第17圖所示，在一般配線圖案中，觀測波形與理想波形之間的相位差(偏向)變大。相對於此，如第19圖所示，在已進行STL設計的配線圖案中，偏向幾乎不存在。 When the clock signal of the same phase is input, as shown in Fig. 17, in the general wiring pattern, the phase difference (bias) between the observed waveform and the ideal waveform becomes large. On the other hand, as shown in Fig. 19, in the wiring pattern in which the STL design has been performed, the deflection hardly exists.
輸入了1/4相位差的時脈訊號時，如第18圖所示，在一般配線圖案中，串音的影響造成訊號大大地變形，而如第20圖所示，可知在已進行STL設計的配線圖案中，可抑制訊號波形的變形，且適當地進行波形整形。 When a clock signal of 1/4 phase difference is input, as shown in Fig. 18, in the general wiring pattern, the influence of crosstalk causes the signal to be greatly deformed, and as shown in Fig. 20, it is known that the STL design has been performed. In the wiring pattern, the distortion of the signal waveform can be suppressed, and waveform shaping can be appropriately performed.
以上的波形觀測係藉由模擬來進行，實際上係在印刷基板上執行已進行了STL設計的配線圖案，藉由計測器對訊號波形進行觀測。 The above waveform observation is performed by simulation. Actually, the wiring pattern in which the STL design has been performed is performed on the printed substrate, and the signal waveform is observed by the measuring instrument.
第21圖係利用於訊號波形之觀測的印刷基板10的外觀圖。該印刷基板10有以0.4mm間隔形成且已進行STL設計的 二條配線2、3，又，有以0.4mm間隔形成且與該等二條配線圖案2、3間隔充份距離、未進行STL設計的二條一般配線圖案11、12。該等共計四條的配線圖案的一端側設有訊號輸入用的端子，另一端側則形成有探針接觸用的襯墊。該襯墊為觀測點。 Fig. 21 is an external view of the printed circuit board 10 used for observation of signal waveforms. The printed substrate 10 is formed at intervals of 0.4 mm and has been designed in an STL The two wirings 2 and 3 have two general wiring patterns 11 and 12 which are formed at intervals of 0.4 mm and are spaced apart from each other by the two wiring patterns 2 and 3 and are not designed in an STL. A terminal for signal input is provided on one end side of the four wiring patterns, and a pad for probe contact is formed on the other end side. This pad is the observation point.
首先，將時脈訊號輸入至二條一般配線圖案11、12中其中一條(有效線路11)，觀測有效線路11及靜止線路12上之觀測點的訊號波形。 First, the clock signal is input to one of the two general wiring patterns 11, 12 (the effective line 11), and the signal waveforms of the observation points on the effective line 11 and the stationary line 12 are observed.
第22圖係輸入至印刷基板10之時脈訊號的波形圖，第23圖係形成於印刷基板10之一般配線圖案11、12上的觀測點的訊號波形圖。第23圖之上側的波形係有效線路11上的觀測波形，下側的波形係靜止線路12上的觀測波形。可知在一般配線圖案11、12中，有效線路11上的觀測波形大大地變形。又，於靜止線路12亦重疊有極大的雜訊。 Fig. 22 is a waveform diagram of a clock signal input to the printed circuit board 10. Fig. 23 is a signal waveform diagram of observation points formed on the general wiring patterns 11, 12 of the printed circuit board 10. The waveform on the upper side of Fig. 23 is the observed waveform on the effective line 11, and the waveform on the lower side is the observed waveform on the stationary line 12. It can be seen that in the general wiring patterns 11 and 12, the observed waveform on the effective line 11 is greatly deformed. Moreover, a great amount of noise is superimposed on the stationary line 12.
相對於此，第24圖係在形成於印刷基板10上且進行了STL設計之配線圖案上的觀測點的訊號波形圖。相較於第23圖，第24圖之上側的有效線路2的觀測波形的變形減少，同樣地，相較於第23圖，第24圖之下側的靜止線路3的觀測波形的雜訊也減少，顯示STL設計係有效的。 On the other hand, Fig. 24 is a signal waveform diagram of observation points on the wiring pattern formed on the printed circuit board 10 and subjected to the STL design. Compared with Fig. 23, the deformation of the observed waveform of the effective line 2 on the upper side of Fig. 24 is reduced, and similarly, the noise of the observed waveform of the stationary line 3 on the lower side of Fig. 24 is also compared with that of Fig. 23. Reduced, showing that the STL design is effective.
在上述的探討中，係說明在將時脈訊號輸入至會產生串音地接近配置的二條配線圖案2、3中至少一條的狀態下，進行STL設計的例子。實際上，輸入至配線圖案的訊號非僅限定於一定周期的時脈訊號，亦可能係輸入頻率在任意時點變化的隨機訊號的情況。對此，針對在將隨機訊號 輸入至二條配線圖案2、3中至少之一的狀態下，進行STL設計的例子作說明。 In the above discussion, an example in which the STL design is performed in a state in which the clock signal is input to at least one of the two wiring patterns 2 and 3 which are arranged in a crosstalk close to each other is described. In fact, the signal input to the wiring pattern is not limited to a clock signal of a certain period, and may be a case where a random signal whose frequency changes at an arbitrary time is input. In response to this, the random signal is An example in which the STL design is performed in a state where at least one of the two wiring patterns 2 and 3 is input is described.
隨機訊號的波形變形係由符碼間干擾(ISI：Inter Symbol Interference)所引起。如第25圖所示，符碼間干擾係某一位元資訊接受其之前的位元資訊的影響，而在訊號波形發生變形。隨機訊號並非係交互地重複0、1，而係0、1隨機地出現，因此，因位元資訊的切換而發生的反射波互相干擾，故而引起符碼間干擾。 The waveform distortion of the random signal is caused by Inter Symbol Interference (ISI). As shown in Fig. 25, inter-symbol interference is caused by the influence of a bit information of the previous bit information on the signal waveform. The random signal does not overlap 0 and 1 interactively, but the systems 0 and 1 appear randomly. Therefore, the reflected waves generated by the switching of the bit information interfere with each other, thus causing inter-symbol interference.
由於STL設計係在配線圖案上的各區段間4有目的地使反射波發生者，關於會出現各式各樣的位元模式的隨機訊號，容易引起符碼間干擾。因此，利用隨機訊號進行主配線圖案及分支配線圖案的STL設計時，必須決定各區段4的參數，以使在主配線圖案上的傳輸線上盡量不受鄰接位元的影響。以下係在主配線圖案給予隨機訊號而進行主配線圖案及分支配線圖案的STL設計，稱其為隨機訊號用STL。 Since the STL design has a purpose to cause a reflected wave to occur in each of the sections 4 on the wiring pattern, it is easy to cause inter-symbol interference with respect to a random signal in which various types of bit patterns appear. Therefore, when the STL design of the main wiring pattern and the branch wiring pattern is performed by the random signal, it is necessary to determine the parameters of each of the segments 4 so that the transmission line on the main wiring pattern is not affected by the adjacent bit as much as possible. Hereinafter, the STL design of the main wiring pattern and the branch wiring pattern is performed by giving a random signal to the main wiring pattern, and it is referred to as a random signal STL.
在隨機訊號用STL中，係提供預定的位元模式的孤立波訊號至鄰接的二條配線圖案2、3中至少一條。在此，孤立波如第26(a)圖所示，係在1之後0持續複數個位元的串列位元模式訊號。又，亦可將1、0反轉的位元模式作為孤立波。(連續0或1之中，僅有1個1位元(或數個位元長度)的方形波) In the STL for random signals, a solitary wave signal of a predetermined bit pattern is supplied to at least one of the adjacent two wiring patterns 2, 3. Here, the solitary wave is a tandem bit pattern signal of a plurality of bits after 1 after 0 as shown in Fig. 26(a). Further, the bit pattern in which 1, 0 is inverted may be used as a solitary wave. (In the case of consecutive 0 or 1, there is only one 1-bit (or several bit length) square wave)
若將孤立波訊號輸入至主配線圖案，則因1的上升、下降會發生雜訊，該雜訊在1之後的複數個位元的0之間，係作為反射波而殘留。此為殘反射。持續於孤立波之1的0， 會持續至因1的上升、下降而發生的雜訊所造成的反射波幾乎消失為止。 When the isolated wave signal is input to the main wiring pattern, noise is generated due to the rise or fall of 1, and the noise remains as a reflected wave between 0 and a plurality of bits after one. This is a residual reflection. 0 that lasts for 1 of the solitary wave, It will continue until the reflected wave caused by the noise caused by the rise and fall of 1 almost disappears.
在隨機訊號用STL中，係設指令訊號為孤立波，因此，觀測訊號本來也是孤立波。因此，將以第26(b)圖的斜線部分表示的殘反射的誤差面積進行計算，為使誤差面積變小，針對二條配線圖案2、3進行STL設計。 In the STL for random signals, the command signal is set to a solitary wave. Therefore, the observation signal is also an isolated wave. Therefore, the error area of the residual reflection indicated by the hatched portion of the figure 26(b) is calculated, and the STL design is performed for the two wiring patterns 2 and 3 in order to reduce the error area.
如上述，在隨機訊號用STL中係使用孤立波作為指令訊號，而針對隨機訊號的回應的評估係使用眼圖。眼圖亦利用於PCI-EXPRESS或DDR3等高速傳輸系的訊號品質評估，為隨機訊號之一般的評估方法。 As described above, the solitary wave is used as the command signal in the STL for random signals, and the eye diagram is used for the evaluation of the response to the random signal. The eye diagram is also used for signal quality evaluation of high-speed transmission systems such as PCI-EXPRESS or DDR3, and is a general evaluation method for random signals.
第27圖係說明眼圖的圖。眼圖係將隨機訊號依各1位元的期間t進行切割，並將其重合者。眼圖之命名由來係因為其形狀相似於人類的眼睛。在眼圖中，波形的變形越小、眼睛開得越大，評估為良好的眼圖。相反地，波形的變形越大、眼睛開得越小，評估為不良的眼圖。 Figure 27 is a diagram illustrating an eye diagram. The eye diagram cuts the random signal according to the period t of each 1-bit and overlaps it. The naming of the eye diagram is due to its shape similar to that of the human eye. In the eye diagram, the smaller the deformation of the waveform and the larger the eye opening, the better the eye diagram is evaluated. Conversely, the larger the deformation of the waveform, the smaller the eye is opened, and the evaluation is a poor eye pattern.
在將孤立波輸入至鄰接的二條配線圖案2、3中至少一條的狀態下，對該等二條配線圖案2、3進行STL設計，藉此，獲得可對應於由任意位元模式所形成的隨機訊號的高頻用配線構造體1。 In a state where the solitary wave is input to at least one of the adjacent two wiring patterns 2, 3, the two wiring patterns 2, 3 are subjected to STL design, thereby obtaining a random which can be formed corresponding to any bit pattern The high-frequency wiring structure 1 of the signal.
印刷基板10上形成有時脈訊號、資料訊號、位址訊號及控制訊號等之配線圖案，關於時脈訊號用的配線圖案，宜輸入時脈訊號來進行STL設計，關於資料訊號、位址訊號及控制訊號，宜輸入由第26(a)圖所示之位元模式所形成的孤立波訊號來進行STL設計。又，即使於輸入孤立波訊號 而進行了STL設計的配線圖案輸入時脈訊號，亦可較佳地抑制訊號變形，因此，亦可利用輸入孤立波訊號而進行了STL設計的配線圖案來作為時脈訊號用。 The wiring pattern of the pulse signal, the data signal, the address signal, and the control signal is formed on the printed circuit board 10. For the wiring pattern for the clock signal, the clock signal should be input for the STL design, and the data signal and the address signal are used. And the control signal, it is advisable to input the solitary wave signal formed by the bit pattern shown in Fig. 26(a) for the STL design. Also, even when inputting solitary wave signals In the STL design, the wiring pattern input clock signal can also suppress the signal distortion. Therefore, the wiring pattern of the STL design can be used as the clock signal by inputting the isolated wave signal.
在利用由第26(a)圖所示之位元模式所形成的孤立波訊號進行了STL設計的配線圖案中，可對隨機訊號的波形進行整形，但在觀測點的訊號波形的上升部分及下降部分會有減弱的問題。 In the wiring pattern in which the STL design is performed using the solitary wave signal formed by the bit pattern shown in Fig. 26(a), the waveform of the random signal can be shaped, but at the rising portion of the signal waveform at the observation point and The drop will have a weakening problem.
第28圖係顯示使用孤立波訊號進行了STL設計之一條配線圖案上的觀測波形(曲線a)及指令波形(曲線b)的圖。如圖示，觀測波形的上升部分及下降部分呈現減弱的狀態。 Fig. 28 is a view showing an observation waveform (curve a) and a command waveform (curve b) on one wiring pattern of the STL design using the solitary wave signal. As shown, the rising and falling portions of the observed waveform exhibit a weakened state.
如第29圖所示，要將此般波形的減弱部分消除，宜使指令訊號的上升部分過衝，且下降部分下衝。利用如第29圖的指令訊號進行STL設計時，能抑制觀測波形的上升部分及下降部分的減弱，使觀測波形近似於指令訊號波形。 As shown in Fig. 29, to eliminate the weakened portion of the waveform, it is preferable to overshoot the rising portion of the command signal and the lower portion to undershoot. When the STL design is performed using the command signal as shown in Fig. 29, the weakening of the rising portion and the falling portion of the observed waveform can be suppressed, and the observed waveform is approximated to the command signal waveform.
在上述說明中，係說明對會產生串音地接近配置之二條配線圖案2、3進行STL設計的例子，亦可對3條以上的配線圖案進行同樣的STL設計，藉此可適當地對傳播於各配線圖案的訊號波形進行調整。進行3條以上配線圖案的STL設計時，可全部一起處理3條以上配線圖案，藉由GA來計算各配線圖案的各區段的特性阻抗及區段長度，亦可將3條以上配線圖案分成例如一組二條，在每一組進行STL設計後，與其他組之間再度進行STL設計。 In the above description, an example in which the STL design is performed on the two wiring patterns 2 and 3 in which the crosstalk is arranged close to each other is described, and the same STL design may be performed on three or more wiring patterns, whereby the propagation can be appropriately performed. The signal waveform of each wiring pattern is adjusted. When STL design of three or more wiring patterns is performed, three or more wiring patterns can be processed together, and the characteristic impedance and the segment length of each segment of each wiring pattern can be calculated by GA, and three or more wiring patterns can be divided. For example, a set of two, after each group of STL design, and then with the other groups STL design.
總結上述，在本實施形態中，係在使時脈訊號或預定 的位元模式的孤立波訊號輸入至會產生串音地鄰近配置的複數條配線圖案中至少一條的狀態下，進行STL設計，因此，能使於各配線圖案上因各式各樣的原因而發生的反射波、與因串音而起之雜訊重合而進行補償，進而能適當地對各配線圖案上的訊號波形進行整形。 Summarizing the above, in this embodiment, the clock signal or the reservation is made. In the state in which the isolated wave signal of the bit pattern is input to at least one of a plurality of wiring patterns arranged adjacent to each other in a crosstalk manner, the STL design is performed, and therefore, it is possible to cause various wiring patterns for various reasons. The generated reflected wave is compensated by overlapping with the noise due to the crosstalk, and the signal waveform on each wiring pattern can be appropriately shaped.
又，為了因應在觀測點的訊號波形的上升部分及下降部分減弱的問題，使在STL設計時的遺傳基因演算法所使用的指令訊號波形的上升部分過衝，且下降部分下衝，而進行了STL設計。第30圖係顯示利用此般指令訊號波形進行了STL設計的結果的波形圖，可知觀測訊號(曲線a)的波形近似於指令訊號(曲線b)的波形，能抑制觀測訊號波形的上升部分及下降部分的減弱。 In addition, in order to reduce the rising portion and the falling portion of the signal waveform at the observation point, the rising portion of the command signal waveform used in the genetic algorithm at the time of STL design is overshooted, and the falling portion is undershooted. The STL design. Figure 30 is a waveform diagram showing the results of the STL design using the command signal waveform. It can be seen that the waveform of the observation signal (curve a) approximates the waveform of the command signal (curve b), and can suppress the rising portion of the observed signal waveform and The decline is weakened.
本發明之態樣不限定於上述各個實施形態，亦包含相關領域者可想到的各式各樣的變化，本發明之效果亦不限定於上述內容。即，可在未脫離由專利請求範圍所規範之內容及其均等物所導出之本發明的概念性思想及主旨的範圍內，作各式各樣的追加、變更及部分的削除。 The aspect of the present invention is not limited to the above-described respective embodiments, and various modifications are conceivable in the related art, and the effects of the present invention are not limited to the above. That is, various additions, modifications, and partial deletions can be made without departing from the spirit and scope of the present invention as defined by the appended claims.
1‧‧‧高頻用配線構造體 1‧‧‧High-frequency wiring structure
α‧‧‧常數 ‧‧‧‧ constant
2‧‧‧有效線路(配線圖案) 2‧‧‧Effective line (wiring pattern)
3‧‧‧靜止線路(配線圖案) 3‧‧‧Still line (wiring pattern)
4‧‧‧區段 4‧‧‧ Section
5‧‧‧訊號源 5‧‧‧Signal source
6‧‧‧傳輸線模組 6‧‧‧Transmission line module
10‧‧‧印刷基板 10‧‧‧Printing substrate
11‧‧‧有效線路(一般配線圖案) 11‧‧‧Effective line (general wiring pattern)
12‧‧‧靜止線路(一般配線圖案) 12‧‧‧Still line (general wiring pattern)
21、31‧‧‧觀測點 21, 31‧‧ ‧ observation points
a、b‧‧‧曲線 a, b‧‧‧ curve
d‧‧‧雙親間的差值 D‧‧‧ difference between parents
I(t)‧‧‧理想波形 I(t)‧‧‧ ideal waveform
Ln‧‧‧親代2的區段長度比 Section length ratio of Ln‧‧‧ parent 2
Mn‧‧‧親代2的區段長度比 Section length ratio of Mn‧‧‧ parent 2
O(t)‧‧‧觀測波形 O(t)‧‧‧ observation waveform
Rd‧‧‧阻尼電阻 Rd‧‧‧damping resistor
Rt‧‧‧終端電阻 Rt‧‧‧ terminating resistor
S‧‧‧誤差面積 S‧‧‧ error area
S1~S14‧‧‧第1步驟~第14步驟 S1~S14‧‧‧Step 1~Step 14
第1圖係本發明之一實施形態的高頻用配線構造體1的STL設計模型圖。 Fig. 1 is a view showing an STL design model of the high-frequency wiring structure 1 according to an embodiment of the present invention.
第2圖係STL設計後各區段4的形狀的示意圖。 Figure 2 is a schematic illustration of the shape of each segment 4 after STL design.
第3圖係顯示STL設計之處理順序的流程圖。 Figure 3 is a flow chart showing the processing sequence of the STL design.
第4圖係顯示將染色體對映至第1圖的主配線圖案之例的圖。 Fig. 4 is a view showing an example in which a chromosome is mapped to the main wiring pattern of Fig. 1.
第5(a)圖係STL中之1點交叉的概要圖；第5(b)圖係混合交叉的概要圖。 Fig. 5(a) is a schematic diagram of the intersection of one point in the STL; and Fig. 5(b) is a schematic diagram of the hybrid intersection.
第6圖係說明誤差面積的圖。 Figure 6 is a diagram illustrating the error area.
第7圖係MGG的概要圖。 Figure 7 is a schematic diagram of the MGG.
第8圖係評估有2種類時之Pareto解(Pareto solution)的概要圖。 Fig. 8 is a schematic diagram of the Pareto solution when there are two types of evaluations.
第9圖係顯示將配線圖案分割為16個區段，並以第3圖之處理順序將各區段之參數進行計算的結果的圖。 Fig. 9 is a view showing a result of dividing the wiring pattern into 16 segments and calculating the parameters of the respective segments in the processing order of Fig. 3.
第10圖係將第9圖圖示化的圖。 Fig. 10 is a diagram in which Fig. 9 is illustrated.
第11圖係將250MHz的時脈訊號輸入至有效線路2時，在有效線路2及靜止線路3之兩觀測點的訊號波形圖。 Fig. 11 is a signal waveform diagram of two observation points of the effective line 2 and the stationary line 3 when the 250 MHz clock signal is input to the effective line 2.
第12圖係未進行STL設計之一般配線的訊號波形圖。 Figure 12 is a signal waveform diagram of a general wiring without STL design.
第13圖係顯示將有效線路2的波形變形及靜止線路3的雜訊波形納入考慮而進行了STL設計之結果的圖。 Fig. 13 is a view showing the result of performing STL design in consideration of the waveform distortion of the effective line 2 and the noise waveform of the stationary line 3.
第14圖係將第13圖圖示化的圖。 Fig. 14 is a diagram showing the Fig. 13 diagram.
第15圖係利用了第13圖及第14圖的STL設計結果時，在有效線路2及靜止線路3之兩觀測點的訊號波形圖。 Fig. 15 is a diagram showing signal waveforms at two observation points of the effective line 2 and the stationary line 3 when the STL design results of Figs. 13 and 14 are used.
第16圖係顯示將時脈訊號亦輸入至靜止線路3時之傳輸線模型的圖。 Fig. 16 is a view showing a transmission line model when a clock signal is also input to the stationary line 3.
第17圖係將同相位之時脈訊號輸入至未進行STL設計之二個一般配線圖案時，在觀測點的訊號波形圖。 Figure 17 shows the signal waveform at the observation point when the clock signal of the same phase is input to the two general wiring patterns that are not designed for STL.
第18圖係將1/4相位差之時脈訊號輸入至未進行STL設計之二個一般配線圖案時，在觀測點的訊號波形圖。 Figure 18 is a signal waveform diagram at the observation point when a clock signal of 1/4 phase difference is input to two general wiring patterns that are not designed for STL.
第19圖係將同相位之時脈訊號輸入至已進行STL設計 之二個配線圖案時，在觀測點的訊號波形圖。 Figure 19 shows the clock signal of the same phase input to the STL design. The signal waveform at the observation point when the two wiring patterns are used.
第20圖係將1/4相位差之時脈訊號輸入至已進行STL設計之二個配線圖案時，在觀測點的訊號波形圖。 Figure 20 is a signal waveform diagram at the observation point when a clock signal of 1/4 phase difference is input to two wiring patterns that have been designed for STL.
第21圖係利用於訊號波形之觀測的印刷基板10的外觀圖。 Fig. 21 is an external view of the printed circuit board 10 used for observation of signal waveforms.
第22圖係輸入至印刷基板10之時脈訊號的波形圖。 Fig. 22 is a waveform diagram of a clock signal input to the printed circuit board 10.
第23圖係形成於印刷基板10之一般配線圖案11、12上的觀測點的訊號波形圖。 Fig. 23 is a signal waveform diagram of observation points formed on the general wiring patterns 11, 12 of the printed circuit board 10.
第24圖係在形成於印刷基板10上且進行了STL設計之配線圖案上的觀測點的訊號波形圖。 Fig. 24 is a signal waveform diagram of observation points on a wiring pattern formed on the printed circuit board 10 and subjected to STL design.
第25圖係說明符碼間干擾的圖。 Figure 25 is a diagram illustrating inter-symbol interference.
第26(a)圖係說明孤立波的位元模式、第26(b)圖係說明以孤立波作為指令訊號時之誤差面積的圖。 Fig. 26(a) shows the bit pattern of the solitary wave, and Fig. 26(b) shows the error area when the solitary wave is used as the command signal.
第27圖說明眼圖的圖。 Figure 27 illustrates a diagram of the eye diagram.
第28圖係顯示使用孤立波訊號進行了STL設計之一條配線圖案上的觀測波形及指令波形的圖。 Fig. 28 is a view showing observation waveforms and command waveforms on one wiring pattern of the STL design using the solitary wave signal.
第29圖係顯示使指令訊號之上升部分過衝，且下降部分下衝的例子的圖。 Fig. 29 is a view showing an example in which the rising portion of the command signal is overshooted and the falling portion is undershooted.
第30圖係顯示使指令訊號之上升部分過衝，且下降部分下衝而進行了STL設計時，觀測訊號波形的波形圖。 Figure 30 is a waveform diagram showing the waveform of the observed signal when the rising portion of the command signal is overshooted and the falling portion is undershooted and the STL design is performed.
第31圖係將引起串音之二條傳輸線11、12加以模型化的電路圖。 Fig. 31 is a circuit diagram in which two transmission lines 11, 12 causing crosstalk are modeled.
第32圖係將250MHz的低頻訊號及5GHz的高頻訊號輸入至第31圖的有效線路11時，各串音的模擬波形圖。 Fig. 32 is an analog waveform diagram of each crosstalk when a low frequency signal of 250 MHz and a high frequency signal of 5 GHz are input to the effective line 11 of Fig. 31.
1‧‧‧高頻用配線構造體 1‧‧‧High-frequency wiring structure
2‧‧‧有效線路(配線圖案) 2‧‧‧Effective line (wiring pattern)
3‧‧‧靜止線路(配線圖案) 3‧‧‧Still line (wiring pattern)
4‧‧‧區段 4‧‧‧ Section
5‧‧‧訊號源 5‧‧‧Signal source
31‧‧‧觀測點 31‧‧‧ observation points
Rd‧‧‧阻尼電阻 Rd‧‧‧damping resistor
Rt‧‧‧終端電阻 Rt‧‧‧ terminating resistor
Claims (12)
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|---|---|---|---|
| TW101120595A TW201351901A (en) | 2012-06-07 | 2012-06-07 | High frequency wiring structure, high frequency installation substrate, manufacturing method for high frequency wiring structure, and waveform rectification method for high frequency signals |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101120595A TW201351901A (en) | 2012-06-07 | 2012-06-07 | High frequency wiring structure, high frequency installation substrate, manufacturing method for high frequency wiring structure, and waveform rectification method for high frequency signals |
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| TW201351901A true TW201351901A (en) | 2013-12-16 |
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2012
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