TW201342550A - Embedded through-silicon-via - Google Patents

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Publication number
TW201342550A
TW201342550A TW101146178A TW101146178A TW201342550A TW 201342550 A TW201342550 A TW 201342550A TW 101146178 A TW101146178 A TW 101146178A TW 101146178 A TW101146178 A TW 101146178A TW 201342550 A TW201342550 A TW 201342550A
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Taiwan
Prior art keywords
substrate
die
semiconductor
pads
vias
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TW101146178A
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Chinese (zh)
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TWI506745B (en
Inventor
Choong Kooi Chee
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Intel Corp
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Publication of TW201342550A publication Critical patent/TW201342550A/en
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Publication of TWI506745B publication Critical patent/TWI506745B/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

Electronic assemblies and their manufacture are described. One embodiment relates to a device including a multilayer substrate comprising a plurality of dielectric layers and metal layers, the multilayer substrate including a first side and a second side. A semiconductor die is embedded in the substrate, the die including a plurality of through-semiconductor-vias extending from a first end to a second end of the die. The through-semiconductor-vias are electrically coupled to electrically conducting pathways defined by the metal layers, including pathways extending from the first end of the die to pads on the first side of the substrate, and pathways extending from the second end of the die to pads on the second side of the substrate. The through-semiconductor-vias in the die have a pitch that is smaller than that of the pads on the first side of the substrate. The through-semiconductor-vias in the die have a pitch that also is smaller than that of the pads on the second side of the substrate.

Description

嵌入式矽穿孔 Embedded 矽 perforation

本發明係有關嵌入式矽穿孔技術。 The present invention relates to an embedded boring technique.

已開發具有矽穿孔(TSV)互連結構的三維(3D)積體電路。TSV晶粒結構一般包含在矽中的垂直穿孔(取決於製程，界定穿孔的側壁可以不是垂直的)，垂直穿孔中含有導電材料且被用來製造互連。使用延伸穿過矽的矽穿孔(TSV)，可以造成比其它路由方法更縮短的互連長度、增進的電性能、及降低的耗電。 Three-dimensional (3D) integrated circuits with germanium via (TSV) interconnect structures have been developed. The TSV grain structure typically includes vertical vias in the crucible (depending on the process, the sidewalls defining the vias may not be vertical), the vias contain conductive material and are used to make the interconnect. The use of vias (TSV) extending through the turns can result in shorter interconnect lengths, improved electrical performance, and reduced power consumption than other routing methods.

於下將參考圖式，其中，類似的結構係由類似代號來予以標示。為了最清楚地顯示各種實施例的結構，包含於其中的圖式包含電子裝置的概圖表示。因此，製成的結構之真正外觀可能不同，但是仍然具有所示的實施例之主張結構。此外，圖式僅顯示瞭解所示的實施例所需的結構。並未包含此技藝中所知的其它結構以使圖式簡明清楚。 Reference will be made to the drawings, in which like structures are designated by like reference numerals. To best show the structure of the various embodiments, the drawings contained therein contain an overview representation of an electronic device. Thus, the actual appearance of the fabricated structure may vary, but still have the claimed structure of the illustrated embodiment. Moreover, the drawings only show the structure required to understand the illustrated embodiment. Other structures known in the art are not included to make the drawings concise.

某些實施例係有關於組成件結構，組成件結構包括嵌入於基板中的包含矽穿孔之晶粒(此處也稱為TSV晶粒)、以及間距大於晶粒中的矽穿孔的間距之從穿孔延伸至基板表面上的電路徑。 Some embodiments relate to a component structure comprising a germanium-perforated die (also referred to herein as a TSV die) embedded in a substrate, and a pitch greater than a pitch of the turns in the die. The perforations extend to an electrical path on the surface of the substrate.

圖1顯示依據某些實施例之組成件(assembly)的互 連細節，該組成件包含基板2，基板2包含具有矽穿孔(TSV)6的嵌入晶粒4。基板2包含多個介電層8、10、12、14、16。不同數目的層(更多或更少)也是可能的。如圖1中所示，基板2包含頂部介電層8上的第一表面18及底部介電層16上的第二表面20。在圖1中所示的實施例中，TSV晶粒4係位於堆疊中的中央介電層12之內。在其它實施例中，TSV晶粒可位於與圖1所示之不同的層堆疊中的垂直位置。TSV 6包含導電材料於其中。可以使用任何適當的導電材料，包含例如金屬。如同此處所使用般，金屬一詞包含純金屬及合金。基板2也包含從TSV延伸至第一表面18上的接合墊22以及第二表面20上的接合墊24之導電路徑。導電路徑可行經穿孔及沿著介電層之內的佈線層。訊號可以經由組成件而往返，包含例如從接合墊24經過介電層16中的穿孔26及佈線層28、經過介電層14中的穿孔30及佈線層32、經過介電層12中晶粒4的TSV 6、經過介電層10中的佈線層34及穿孔36、以及經過介電層8中的佈線層38及穿孔40，以便到達接合墊22。 Figure 1 shows the mutual components of an assembly in accordance with certain embodiments. In detail, the component comprises a substrate 2 comprising an embedded die 4 having a turns of perforation (TSV) 6. The substrate 2 comprises a plurality of dielectric layers 8, 10, 12, 14, 16. Different numbers of layers (more or less) are also possible. As shown in FIG. 1, substrate 2 includes a first surface 18 on top dielectric layer 8 and a second surface 20 on bottom dielectric layer 16. In the embodiment shown in FIG. 1, the TSV die 4 is located within the central dielectric layer 12 in the stack. In other embodiments, the TSV dies may be in a vertical position in a different layer stack than that shown in FIG. The TSV 6 contains a conductive material therein. Any suitable electrically conductive material can be used, including, for example, a metal. As used herein, the term metal includes both pure metals and alloys. The substrate 2 also includes conductive paths extending from the TSV to the bond pads 22 on the first surface 18 and the bond pads 24 on the second surface 20. The conductive path is preferably perforated and along a wiring layer within the dielectric layer. The signal can be reciprocated via the component, including, for example, the vias 26 and the wiring layer 28 from the bonding pad 24 through the dielectric layer 16, through the vias 30 and the wiring layer 32 in the dielectric layer 14, and through the die in the dielectric layer 12. The TSV 6 of 4, through the wiring layer 34 and the via 36 in the dielectric layer 10, and through the wiring layer 38 and the via 40 in the dielectric layer 8 to reach the bonding pad 22.

如圖1中所示，在矽晶粒4中的TSV具有小於第一表面18上的接合墊22的間距並且小於第二表面20上的接合墊24的間距之晶距(它們之間的間隔)。此種結構致使設有TSV 6的嵌入晶粒4能夠更容易被連接至其它結構，例如經由凸塊42而被耦合至基板2的組件48。在某些實施例中，組件48可以選自由處理器及記憶體組成的 族群。如圖1中所示的基板2也經由凸塊44而被耦合至結構50。在某些實施例中，結構50可為主機板(motherboard)。基板2的第一表面18上的墊22的間距無需與基板2的第二表面20上的墊24的間距相同。如圖1中所示，在基板2的第一表面18上的墊22的間距係小於第二表面20上的墊24的間距。 As shown in FIG. 1, the TSV in the germanium die 4 has a pitch smaller than the pitch of the bond pads 22 on the first surface 18 and less than the pitch of the bond pads 24 on the second surface 20 (the spacing between them) ). This configuration enables the embedded die 4 provided with the TSV 6 to be more easily connected to other structures, such as via the bumps 42 to the component 48 of the substrate 2. In some embodiments, component 48 can be selected from the group consisting of a processor and a memory. Ethnic group. The substrate 2 as shown in FIG. 1 is also coupled to the structure 50 via bumps 44. In some embodiments, structure 50 can be a motherboard. The pitch of the pads 22 on the first surface 18 of the substrate 2 need not be the same as the pitch of the pads 24 on the second surface 20 of the substrate 2. As shown in FIG. 1, the pitch of the pads 22 on the first surface 18 of the substrate 2 is less than the pitch of the pads 24 on the second surface 20.

某些實施例係有關包含嵌入式矽穿孔晶粒之基板的製造方法。實施例可有關於具有核心的基板及無核心基板兩者的形成。可以使用各種適當的方法來製造此種基板。矽穿孔(TSV)晶粒，單獨地、或是位於介電層之內的一個矽穿孔(TSV)晶粒在某些實施例中用作為初始層，而其它層可以被形成在此初始層上。在其它實施例中，下層可用作為初始層及位於其上的矽穿孔(TSV)晶粒。 Some embodiments relate to a method of fabricating a substrate comprising embedded germanium via dies. Embodiments may be directed to the formation of both a cored substrate and a coreless substrate. Such a substrate can be fabricated using various suitable methods. A germanium via (TSV) die, either alone or within a dielectric layer, is used as an initial layer in some embodiments, while other layers may be formed on the initial layer. . In other embodiments, the lower layer can be used as the initial layer and the turns of the via (TSV) grains thereon.

圖2顯示無核心基板處理實施例中的操作，其中，使用包含例如Cu等金屬之暫時的核心材料52。在圖2中所示的無核心基板製造實施例中，介電質及金屬層可被累增於暫時核心52的相對側上，並且，暫時的核心稍後被移除以產生二個基板結構。如圖2所示，具有與圖1中的基板2相同的層結構之基板結構可以被形成於暫時的核心52之相對側上。在移除暫時的核心52之後，將會造成均包含嵌入式矽穿孔晶粒4之二個基板結構。 2 shows the operation in a coreless substrate processing example in which a temporary core material 52 comprising a metal such as Cu is used. In the coreless substrate fabrication embodiment shown in FIG. 2, the dielectric and metal layers can be added to the opposite side of the temporary core 52, and the temporary core is later removed to create two substrate structures. . As shown in FIG. 2, a substrate structure having the same layer structure as the substrate 2 in FIG. 1 can be formed on the opposite side of the temporary core 52. After the temporary core 52 is removed, two substrate structures each comprising an embedded germanium via die 4 will result.

圖3顯示圖1的基板2的視圖，其包含介電層12，而包含矽穿孔(TSV)6的矽穿孔(TSV)晶粒4係位在介電層12中。矽穿孔(TSV)晶粒4係位於介電層12中的中 央開口內。在某些實施例中，可使用結合的介電層12及矽穿孔(TSV)晶粒4作為初始層，而其它層被形成於初始層上以便製造多層基板。圖3的放大部份顯示介電層12與矽穿孔(TSV)晶粒4之間的介面，並且，顯示黏著劑35出現在它們之間。在某些實施例中，取決於例如使用的材料及介電層12形成方法的特徵，要在介電層12與矽穿孔(TSV)晶粒4之間形成適當的接合，並不一定需要黏著劑35。使用任何適當方法(包含但不限於遮罩、蝕刻、及沈積製程)，形成如圖3中所例舉般其周圍被介電層所圍繞之矽穿孔(TSV)晶粒4。舉例而言，形成介電層，然後，開口被形成在介電層中，並且矽穿孔(TSV)晶粒係位在開口之內。或者，可設置矽穿孔(TSV)晶粒，然後介電層被沈積在晶粒周圍。 3 shows a view of the substrate 2 of FIG. 1 including a dielectric layer 12 with a tantalum via (TSV) die 4 comprising a tantalum via (TSV) 6 in the dielectric layer 12. Tantalum via (TSV) die 4 is located in dielectric layer 12. Inside the central opening. In some embodiments, a combined dielectric layer 12 and tantalum via (TSV) die 4 can be used as the initial layer, while other layers are formed on the initial layer to fabricate the multilayer substrate. The enlarged portion of Fig. 3 shows the interface between the dielectric layer 12 and the viat via (TSV) die 4, and shows that an adhesive 35 is present between them. In some embodiments, depending on, for example, the materials used and the features of the dielectric layer 12 formation process, proper bonding is required between the dielectric layer 12 and the via vias (TSV) die 4, and does not necessarily require adhesion. Agent 35. Using any suitable method (including but not limited to masking, etching, and deposition processes), a via via (TSV) die 4 surrounded by a dielectric layer as exemplified in FIG. 3 is formed. For example, a dielectric layer is formed, and then an opening is formed in the dielectric layer, and a via via (TSV) die is located within the opening. Alternatively, a via via (TSV) die can be placed and then a dielectric layer deposited around the die.

圖1-3顯示包含無核心基板的特徵。圖4顯示包含具有核心層127的基板102之實施例，其它層被形成在核心層127上。核心層127可以由任何適當的材料所形成，舉例而言，材料可為包含浸漬環氧樹脂材料之編織玻璃層的層疊多層結構。核心層127可包含多個延伸經過核心層127之電路徑129。設有矽穿孔106的矽穿孔晶粒104可位於核心層127上，且矽穿孔106中的導電材料係電耦合至核心層127中的電路徑129。矽穿孔晶粒104係位於介電層112之內。介電層110被形成在矽穿孔晶粒104上及介電層112上，並且，介電層108被形成在介電層110上。介電層114係位於與介電層112相對立的核心層127 的側上，並且，介電層116係形成於介電層114上。 Figures 1-3 show features that include a coreless substrate. 4 shows an embodiment comprising a substrate 102 having a core layer 127, the other layers being formed on the core layer 127. The core layer 127 can be formed of any suitable material, for example, the material can be a laminated multilayer structure comprising a woven glass layer impregnated with an epoxy resin material. The core layer 127 can include a plurality of electrical paths 129 that extend through the core layer 127. A meandering die 104 having a meandering via 106 may be located on the core layer 127 and the conductive material in the via 106 is electrically coupled to the electrical path 129 in the core layer 127. The germanium via die 104 is located within the dielectric layer 112. Dielectric layer 110 is formed over germanium via die 104 and dielectric layer 112, and dielectric layer 108 is formed over dielectric layer 110. The dielectric layer 114 is located on the core layer 127 opposite to the dielectric layer 112. On the side, and a dielectric layer 116 is formed on the dielectric layer 114.

如圖4所示，基板包含在頂部介電層108上的第一表面118、在底部介電層116上的第二表面120，第二表面120包含形成於其上的接合墊124。訊號可以經由組成件而往返，包含例如從接合墊24經過介電層116中的穿孔126及佈線層128、經過介電層114中的穿孔130及佈線層132、經過核心127中的導電路徑129、經過介電層112中晶粒104的矽穿孔106、經過介電層110中的金屬佈線層134及穿孔136、以及經過介電層108中的佈線層138及穿孔140，以便到達接合墊122。 As shown in FIG. 4, the substrate includes a first surface 118 on the top dielectric layer 108, a second surface 120 on the bottom dielectric layer 116, and a second surface 120 including bond pads 124 formed thereon. The signals may be reciprocated via components including, for example, vias 126 and wiring layers 128 from bond pads 24 through dielectric layer 116, through vias 130 and wiring layers 132 in dielectric layer 114, through conductive paths 129 in core 127. Through the via hole 106 of the die 104 in the dielectric layer 112, through the metal wiring layer 134 and the via 136 in the dielectric layer 110, and through the wiring layer 138 and the via 140 in the dielectric layer 108 to reach the bonding pad 122. .

圖5顯示包含具有核心227的基板之實施例中，其中，矽穿孔晶粒204係位於核心227中而非如圖4中所示般位於接鄰於核心的列中。如圖5所示，核心227及矽穿孔晶粒204係形成為具有相同的厚度，使得矽穿孔晶粒204可適配於核心227中的開口之內。由於含有矽穿孔晶粒204的層227是與圖5的介電層208、210、214、及216不同的核心層，而圖1中含有矽穿孔晶粒之層12是類似於或同於介電層8、10、14、及16，所以，圖5中的基板與圖1中所示的基板不同。訊號可行經基板，舉例而言，從穿孔126經過介電層216中的佈線層228、經過佈線層214中的穿孔230及佈線層232、經過核心層127中的矽穿孔206、經過介電層210中的佈線層234及穿孔236、經過佈線層238及穿孔240而至接合墊220。 5 shows an embodiment comprising a substrate having a core 227 in which the germanium via die 204 is located in the core 227 rather than in a column adjacent to the core as shown in FIG. As shown in FIG. 5, the core 227 and the meandering perforations 204 are formed to have the same thickness such that the perforated die 204 can fit within the opening in the core 227. Since layer 227 containing germanium via die 204 is a different core layer than dielectric layers 208, 210, 214, and 216 of FIG. 5, layer 12 containing germanium via grains is similar or identical to FIG. The electric layers 8, 10, 14, and 16, therefore, the substrate in Fig. 5 is different from the substrate shown in Fig. 1. The signal is via the substrate, for example, from the via 126 through the wiring layer 228 in the dielectric layer 216, through the vias 230 and the routing layer 232 in the wiring layer 214, through the via holes 206 in the core layer 127, through the dielectric layer The wiring layer 234 and the via 236 in 210 pass through the wiring layer 238 and the via 240 to the bonding pad 220.

實施例也可包含嵌入於基板內之一個以上的晶粒。舉 例而言，圖6顯示實施例，其包含介電層308、310、312、314、及316，且具有矽穿孔306的一個以上的矽穿孔晶粒304係位於介電層314之內。替代地，各矽穿孔晶粒結構304可位於基板的不同介電層中。雖然圖6中顯示二個矽穿孔晶粒結構304，但是，更多的矽穿孔晶粒結構304也可以位於基板之中。 Embodiments may also include more than one die embedded in the substrate. Lift For example, FIG. 6 shows an embodiment that includes dielectric layers 308, 310, 312, 314, and 316, and one or more via-perforated grains 304 having germanium vias 306 are located within dielectric layer 314. Alternatively, each of the turns of the doped grain structure 304 can be located in a different dielectric layer of the substrate. Although two perforated grain structures 304 are shown in FIG. 6, more of the perforated grain structures 304 may also be located in the substrate.

實施例提供與尺寸及製造容易度有關的一或更多個優點。首先，藉由將矽穿孔晶粒結構嵌入於基板中，可降低整體組成件的厚度。其次，藉由將矽穿孔晶粒結構嵌入於基板中，可在從嵌入式矽穿孔晶粒延伸至基板上及下表面之層中導出對裝置的接點，使得在表面處的接合墊具有的間距大於在嵌入式矽穿孔晶粒的表面處的接點。在某些實施例中，矽穿孔晶粒的頂端部在接點之間具有25至50微米的接點間距。為了將另一裝置(舉例而言，記憶體裝置)附接至緊密接點間距的矽穿孔晶粒，使用習稱為熱壓縮接合(TCB)之複雜及昂貴的附接製程。但是，藉由將矽穿孔晶粒嵌入在基板中，在矽穿孔晶粒與基板表面之間的層用以將接點的間距分散開至增加的值，其致能使用較不複雜及較不昂貴的附接製程而將晶粒或裝置附接至基板。 Embodiments provide one or more advantages associated with size and ease of manufacture. First, by embedding the tantalum perforated grain structure in the substrate, the thickness of the entire component can be reduced. Secondly, by embedding the germanium-perforated grain structure in the substrate, the contacts of the device can be derived in a layer extending from the embedded germanium-perforated die to the upper and lower surfaces of the substrate such that the bond pads at the surface have The pitch is greater than the joint at the surface of the embedded perforated die. In some embodiments, the tip end portion of the ruthenium perforated die has a contact pitch of between 25 and 50 microns between the contacts. In order to attach another device, for example, a memory device, to a perforated die of closely spaced pitch, a complex and expensive attachment process known as thermocompression bonding (TCB) is used. However, by embedding the perforated grains in the substrate, the layer between the perforated grains and the surface of the substrate is used to spread the pitch of the contacts to an increased value, which enables less complicated and less usable use. An expensive attachment process attaches the die or device to the substrate.

圖7顯示依據某些實施例之用以形成嵌入式矽穿孔晶粒基板及包含基板之組成件的流程圖。框401提供矽穿孔晶粒。框403在矽穿孔晶粒上增建介電層及金屬層，並且將矽穿孔的間距分散開，使得在基板表面的接點具有較不 濃密的間距而更容易附接至其它裝置。框405將銲球耦合至基板，以便用於後續附接至電路板(board)。框407將組成件(包含但不限於例如CPU(中央處理單元)或記憶體封裝組件等晶粒結構)附接至基板的頂表面。框409使用銲球連接而將基板(包含附接於其上的組成件)附接至電路板。 7 shows a flow diagram for forming an embedded perforated die substrate and components comprising the substrate in accordance with some embodiments. Block 401 provides a perforated die. Block 403 adds a dielectric layer and a metal layer on the ruthenium-perforated die, and spreads the pitch of the ruthenium perforations so that the contacts on the surface of the substrate are less The dense spacing makes it easier to attach to other devices. Block 405 couples the solder balls to the substrate for subsequent attachment to a board. Block 407 attaches components (including but not limited to, a grain structure such as a CPU (Central Processing Unit) or a memory package assembly) to the top surface of the substrate. Block 409 attaches the substrate (including the components attached thereto) to the circuit board using solder ball connections.

圖8顯示實施例，其包含依據某些實施例的記憶體裝置，其中，包含多個記憶體晶片的記憶體封裝組件被耦合至嵌入式矽穿孔晶粒基板。組成件包含經由銲材凸塊542而被耦合至多層基板502之多個記憶體晶粒結構548。下填充也出現在晶粒結構548之間以及下晶粒結構548與基板502之間。多層基板502包含入式矽穿孔晶粒504。基板502接著經由銲材凸塊544而耦合至電路板550。 8 shows an embodiment comprising a memory device in accordance with some embodiments, wherein a memory package assembly including a plurality of memory chips is coupled to an embedded germanium-perforated die substrate. The component includes a plurality of memory die structures 548 that are coupled to the multilayer substrate 502 via solder bumps 542. Underfill also occurs between the grain structures 548 and between the lower grain structure 548 and the substrate 502. The multilayer substrate 502 includes an in-line perforated die 504. Substrate 502 is then coupled to circuit board 550 via solder bumps 544.

應瞭解到，在此處所述的實施例的範圍之內，可以作很多改變。舉例而言，雖然將矽穿孔晶粒說明成矽晶粒結構，但是，穿孔也可以延伸通過其它材料，舉例而言，其它材料包含但不限於砷化鎵。延伸穿過半導體的這些穿孔稱為半導體穿孔。矽穿孔是延伸穿過矽的半導體穿孔的實例。結果，如此處所述的實施例可以應用至不是由矽所形成的晶粒結構。此處使用的晶粒一詞意指由不同製程操作轉換成所需電子裝置之工件。晶粒通常係切割自晶圓，而晶圓係由半導體、非半導體、或是半導體及非半導體材料的組合所製成。 It will be appreciated that many variations are possible within the scope of the embodiments described herein. For example, although the germanium perforated die is illustrated as a germanium grain structure, the vias may also extend through other materials, such as, but not limited to, gallium arsenide. These perforations extending through the semiconductor are referred to as semiconductor vias. Tantalum perforations are examples of semiconductor perforations that extend through the crucible. As a result, embodiments as described herein can be applied to grain structures that are not formed by tantalum. The term "grain" as used herein refers to a workpiece that is converted to the desired electronic device by different process operations. The grains are typically cut from the wafer, and the wafers are made of semiconductor, non-semiconductor, or a combination of semiconductor and non-semiconductor materials.

包含如上述實施例所述般形成的結構之組成件可被應 用在各種電子組件中。圖9顯示電子系統環境的一個實例，其中，具體實施上述實施例的態樣。其它實施例不需要包含圖9中所指的所有特徵，可以包含圖9中未指明的替代特徵。 A component comprising a structure formed as described in the above embodiments may be Used in a variety of electronic components. Fig. 9 shows an example of an electronic system environment in which the above-described embodiments are embodied. Other embodiments need not include all of the features referred to in FIG. 9, and may include alternative features not shown in FIG.

圖9的系統600可包含在封裝基板685中的至少一中央處理單元(CPU)683(也稱為微處理器)。在某些實施例中，CPU 683(由虛線指示以表示其被嵌入於基板685中)可為例如上述實施例中所述的嵌入式矽穿孔晶粒，嵌入式矽穿孔晶粒被耦合至印刷電路板687(舉例而言，主機板)。記憶體689a係位於基板685上以形成例如如上所述及圖8中所示的組成件。各式各樣的其它系統組件也可包含根據例如上述所述的實施例而形成的結構。藉由在基板685上設置各式各樣的組件(例如，記憶體689a)，可降低整個系統的尺寸。 The system 600 of FIG. 9 can include at least one central processing unit (CPU) 683 (also referred to as a microprocessor) in the package substrate 685. In some embodiments, the CPU 683 (indicated by a dashed line to indicate that it is embedded in the substrate 685) can be, for example, the embedded 矽 perforated die described in the above embodiments, the embedded 矽 perforated die is coupled to the print Circuit board 687 (for example, a motherboard). Memory 689a is located on substrate 685 to form components such as those described above and illustrated in FIG. A wide variety of other system components can also include structures formed in accordance with, for example, the embodiments described above. By providing a wide variety of components (e.g., memory 689a) on substrate 685, the overall system size can be reduced.

系統600可又包含額外的記憶體689b及也被配置在主機板687上的一或更多個控制器691a、691b、...、691n。主機板687可為具有多個導線的單層或多層板，多個導線提供介於封裝基板685中的電路與安裝至主機板687之其它組件之間的通訊。替代地，一或更多個各式各樣的組件可以被配置在例如子卡或是擴充卡等其它卡上。組件也可被安裝於插座中或是被直接連接至印刷電路板或全部整合在相同的封裝組件中。也可包含顯示器695。 System 600 can in turn include additional memory 689b and one or more controllers 691a, 691b, ..., 691n also disposed on motherboard 687. The motherboard 687 can be a single or multi-layer board having a plurality of wires that provide communication between circuitry in the package substrate 685 and other components mounted to the motherboard 687. Alternatively, one or more of the various components can be configured on other cards such as daughter cards or expansion cards. The components can also be mounted in a socket or directly connected to a printed circuit board or all integrated into the same package assembly. A display 695 can also be included.

任何適當的操作系統及各種應用程式執行於CPU 683中並且存在於記憶體689a、689b中。根據習知的快取技 術，可快取存在於記憶體689a、689b中的內容。在記憶體689a、689b中的程式及資料可被交換至儲存器693中，作為記憶體管理操作的一部份。系統600可包含任何適當的計算裝置，包含但不限於主電腦、伺服器、個人電腦、工作站、膝上型電腦、手持電腦、筆記型電腦、平板電腦、電子書閱讀器、手持遊戲裝置、手持娛樂裝置(舉例而言，MP3(動畫專家群組層-3)音頻播放器)、PDA(個人數位助理)電話裝置(無線或有線)、網路設備、虛擬化裝置、儲存控制器、網路控制器、路由器、等等。 Any suitable operating system and various applications are executed in CPU 683 and are present in memory 689a, 689b. According to the conventional cache technology The contents stored in the memories 689a, 689b can be cached. The programs and data in memory 689a, 689b can be swapped into memory 693 as part of the memory management operation. System 600 can include any suitable computing device including, but not limited to, a host computer, a server, a personal computer, a workstation, a laptop, a handheld computer, a notebook, a tablet, an e-book reader, a handheld gaming device, a handheld Entertainment devices (for example, MP3 (Animation Expert Group Layer-3) audio player), PDA (Personal Digital Assistant) telephone devices (wireless or wired), network devices, virtualization devices, storage controllers, networks Controllers, routers, and more.

控制器691a、691b、...691n可包含系統控制器、週邊控制器、記憶體控制器、集線器控制器、I/O(輸入/輸出)匯流排控制器、視頻控制器、網路控制器、儲存控制器、通訊控制器的其中之一或更多個系統。舉例而言，儲存控制器根據儲存協定層而控制對儲存器693之資料讀取及寫入。層的儲存協定可為多個已知的儲存協定中的任何協定。依據習知的快取技術，可快取寫至或讀自儲存器693的資料。網路控制器可包含一或更多個協定層以便在網路697上對遠端裝置傳送及接收網路封包。網路697可包括區域網路(LAN)、網際網路、廣域網路(WAN)、儲存區域網路(SAN)、等等。實施例可被配置成透過無線網路或連接而發送及接收資料。在某些實施例中，網路控制器及各種協定層採用經過未屏蔽之雙絞線電纜的乙太網路協定、符記環協定、光纖通道協定、等等、或是任何其它適當的網路通訊協定。 The controllers 691a, 691b, ... 691n may include a system controller, a peripheral controller, a memory controller, a hub controller, an I/O (input/output) bus controller, a video controller, a network controller One or more systems of the storage controller and the communication controller. For example, the storage controller controls the reading and writing of data to the storage 693 in accordance with the storage protocol layer. The layer's storage agreement can be any of a number of known storage agreements. The data written to or read from the storage 693 can be cached in accordance with conventional cache techniques. The network controller may include one or more protocol layers to transmit and receive network packets to the remote device over network 697. Network 697 may include a local area network (LAN), an internet, a wide area network (WAN), a storage area network (SAN), and the like. Embodiments can be configured to send and receive data over a wireless network or connection. In some embodiments, the network controller and various protocol layers use an Ethernet protocol, a token ring protocol, a Fibre Channel protocol, etc., or any other suitable network that is unshielded twisted pair cable. Road communication agreement.

此處使用之例如「第一」、「第二」等詞不一定代表任何特定的次序、數量、或重要性，但是用以區別一個元件與另一個元件。例如「頂部」、「底部」、「上」、「下」等詞僅作為說明之用且不被解釋為限定。可以用各種位置及方向來製造、使用及含有實施例。 The words "first" and "second", as used herein, are not intended to mean any particular order, quantity, or importance, but are used to distinguish one element from another. For example, the terms "top", "bottom", "upper", "lower" are used for illustration purposes only and are not to be construed as limiting. The embodiments can be made, used, and contained in various positions and orientations.

在前述的實施方式中，為了使揭示流暢而將各種特點分組在一起。本揭示的方法不應解釋為所主張的發明實施例要求比各申請專利範圍請求項所記載的特點還多的特徵。相反地，後附的申請專利範圍反應發明標的在於比單一揭示的實施例的所有特點更少的特點。因此，後附的申請專利範圍於此一併列入實施方式，以各申請專利範圍基於它自己分別的較佳實施例。 In the foregoing embodiments, various features are grouped together in order to make the disclosure smooth. The method of the present disclosure should not be construed as requiring that the claimed embodiments of the invention require more features than those described in the claims of the claims. Conversely, the scope of the appended claims is intended to be in a lesser feature than all features of the single disclosed embodiment. Therefore, the scope of the appended patent application is hereby incorporated by reference in its entirety in its entirety in its entirety in its entirety in its entirety.

雖然在上述及附圖中說明某些舉例說明的實施例，但是，要瞭解這些實施例僅為說明之用而非限定性，並且，由於具有此技藝中一般技術者瞭解修改，所以，實施例不限於所示及說明之特定結構及配置。 While certain embodiments have been described in the foregoing embodiments, the embodiments of the embodiments of the invention It is not limited to the specific structures and configurations shown and described.

2‧‧‧基板 2‧‧‧Substrate

4‧‧‧晶粒 4‧‧‧ grain

6‧‧‧矽穿孔 6‧‧‧矽Perforation

8‧‧‧介電層 8‧‧‧Dielectric layer

10‧‧‧介電層 10‧‧‧Dielectric layer

12‧‧‧介電層 12‧‧‧Dielectric layer

14‧‧‧介電層 14‧‧‧Dielectric layer

16‧‧‧介電層 16‧‧‧Dielectric layer

18‧‧‧第一表面 18‧‧‧ first surface

20‧‧‧第二表面 20‧‧‧ second surface

22‧‧‧接合墊 22‧‧‧Material pads

24‧‧‧接合墊 24‧‧‧Material pads

26‧‧‧穿孔 26‧‧‧Perforation

28‧‧‧佈線層 28‧‧‧ wiring layer

30‧‧‧穿孔 30‧‧‧Perforation

32‧‧‧佈線層 32‧‧‧ wiring layer

34‧‧‧佈線層 34‧‧‧ wiring layer

35‧‧‧黏著劑 35‧‧‧Adhesive

36‧‧‧穿孔 36‧‧‧Perforation

38‧‧‧佈線層 38‧‧‧ wiring layer

40‧‧‧穿孔 40‧‧‧Perforation

42‧‧‧凸塊 42‧‧‧Bumps

44‧‧‧凸塊 44‧‧‧Bumps

48‧‧‧組件 48‧‧‧ components

50‧‧‧結構 50‧‧‧ structure

52‧‧‧暫時的核心 52‧‧‧ temporary core

102‧‧‧基板 102‧‧‧Substrate

104‧‧‧矽穿孔晶粒 104‧‧‧矽Perforated grain

106‧‧‧穿孔 106‧‧‧Perforation

108‧‧‧介電層 108‧‧‧ dielectric layer

110‧‧‧介電層 110‧‧‧ dielectric layer

112‧‧‧介電層 112‧‧‧ dielectric layer

114‧‧‧介電層 114‧‧‧Dielectric layer

116‧‧‧介電層 116‧‧‧Dielectric layer

118‧‧‧第一表面 118‧‧‧ first surface

120‧‧‧第二表面 120‧‧‧second surface

122‧‧‧接合墊 122‧‧‧Join pad

124‧‧‧接合墊 124‧‧‧Join pad

126‧‧‧穿孔 126‧‧‧Perforation

127‧‧‧核心層 127‧‧‧ core layer

128‧‧‧佈線層 128‧‧‧ wiring layer

129‧‧‧電路徑 129‧‧‧Electric path

130‧‧‧穿孔 130‧‧‧Perforation

132‧‧‧佈線層 132‧‧‧ wiring layer

134‧‧‧佈線層 134‧‧‧ wiring layer

136‧‧‧穿孔 136‧‧‧Perforation

138‧‧‧佈線層 138‧‧‧ wiring layer

140‧‧‧穿孔 140‧‧‧Perforation

204‧‧‧矽穿孔晶粒 204‧‧‧矽Perforated grain

206‧‧‧穿孔 206‧‧‧Perforation

208‧‧‧介電層 208‧‧‧ dielectric layer

210‧‧‧介電層 210‧‧‧Dielectric layer

212‧‧‧介電層 212‧‧‧ dielectric layer

214‧‧‧介電層 214‧‧‧ dielectric layer

216‧‧‧介電層 216‧‧‧ dielectric layer

220‧‧‧墊 220‧‧‧ pads

226‧‧‧穿孔 226‧‧‧Perforation

227‧‧‧核心 227‧‧‧ core

228‧‧‧佈線層 228‧‧‧ wiring layer

230‧‧‧穿孔 230‧‧‧Perforation

232‧‧‧佈線層 232‧‧‧ wiring layer

234‧‧‧佈線層 234‧‧‧ wiring layer

236‧‧‧穿孔 236‧‧‧Perforation

238‧‧‧佈線層 238‧‧‧ wiring layer

240‧‧‧穿孔 240‧‧‧Perforation

304‧‧‧矽穿孔晶粒 304‧‧‧矽Perforated grain

308‧‧‧介電層 308‧‧‧ dielectric layer

310‧‧‧介電層 310‧‧‧Dielectric layer

312‧‧‧介電層 312‧‧‧ dielectric layer

314‧‧‧介電層 314‧‧‧ dielectric layer

316‧‧‧介電層 316‧‧‧ dielectric layer

502‧‧‧多層基板 502‧‧‧Multilayer substrate

504‧‧‧矽穿孔晶粒 504‧‧‧矽Perforated grain

542‧‧‧銲材凸塊 542‧‧‧weld bumps

544‧‧‧銲材凸塊 544‧‧‧weld bumps

548‧‧‧晶粒結構 548‧‧‧ grain structure

550‧‧‧電路板 550‧‧‧ boards

600‧‧‧系統 600‧‧‧ system

683‧‧‧中央處理單元 683‧‧‧Central Processing Unit

685‧‧‧基板 685‧‧‧Substrate

687‧‧‧印刷電路板 687‧‧‧Printed circuit board

689a‧‧‧記憶體 689a‧‧‧ memory

689b‧‧‧記憶體 689b‧‧‧ memory

691a‧‧‧控制器 691a‧‧‧ Controller

693‧‧‧儲存器 693‧‧‧Storage

695‧‧‧顯示器 695‧‧‧ display

697‧‧‧網路 697‧‧‧Network

將參考未依比例繪製的附圖，以舉例方式說明實施例。 Embodiments will be described by way of example with reference to the accompanying drawings.

圖1顯示依據某些實施例之嵌入於基板中的TSV晶粒的視圖。 1 shows a view of a TSV die embedded in a substrate in accordance with certain embodiments.

圖2顯示依據某些實施例之用於形成含有嵌入式TSV晶粒的形底之無核心基板形成製程期間的視圖。 2 shows a view during a coreless substrate formation process for forming a shaped substrate containing embedded TSV dies in accordance with certain embodiments.

圖3顯示依據某些實施例之嵌入於基板中的TSV晶粒的視圖，包含顯示晶粒與晶粒位於其中之基板的介電層之間的介面的放大部份。 3 shows a view of a TSV die embedded in a substrate, including an enlarged portion of the interface between the die and the dielectric layer of the substrate in which the die is located, in accordance with certain embodiments.

圖4顯示依據某些實施例之位於核心上及嵌入於基板中的TSV晶粒的視圖。 4 shows a view of a TSV die on a core and embedded in a substrate in accordance with certain embodiments.

圖5顯示依據某些實施例之嵌入於基板中的核心中的TSV晶粒的視圖。 Figure 5 shows a view of a TSV die embedded in a core in a substrate in accordance with certain embodiments.

圖6顯示依據某些實施例之均嵌入於基板中的第一TSV晶粒與第二TSV晶粒的視圖。 6 shows a view of a first TSV die and a second TSV die each embedded in a substrate in accordance with certain embodiments.

圖7顯示依據某些實施例之用於形成包含嵌入式TSV晶粒之電子組成件的操作流程圖。 7 shows an operational flow diagram for forming an electronic component including embedded TSV dies in accordance with some embodiments.

圖8顯示依據某些實施例之包含具有嵌入式TSV晶粒之基板及位於基板上的記憶體之組成件的實例。 8 shows an example of a component comprising a substrate having embedded TSV dies and a memory on the substrate, in accordance with certain embodiments.

圖9顯示可見到實施例的應用之電子系統配置。 Figure 9 shows the electronic system configuration of the application seen in the embodiment.

2‧‧‧基板 2‧‧‧Substrate

4‧‧‧晶粒 4‧‧‧ grain

6‧‧‧矽穿孔 6‧‧‧矽Perforation

8‧‧‧介電層 8‧‧‧Dielectric layer

10‧‧‧介電層 10‧‧‧Dielectric layer

12‧‧‧介電層 12‧‧‧Dielectric layer

14‧‧‧介電層 14‧‧‧Dielectric layer

16‧‧‧介電層 16‧‧‧Dielectric layer

18‧‧‧第一表面 18‧‧‧ first surface

20‧‧‧第二表面 20‧‧‧ second surface

22‧‧‧接合墊 22‧‧‧Material pads

24‧‧‧接合墊 24‧‧‧Material pads

26‧‧‧穿孔 26‧‧‧Perforation

28‧‧‧佈線層 28‧‧‧ wiring layer

30‧‧‧穿孔 30‧‧‧Perforation

32‧‧‧佈線層 32‧‧‧ wiring layer

34‧‧‧佈線層 34‧‧‧ wiring layer

36‧‧‧穿孔 36‧‧‧Perforation

38‧‧‧佈線層 38‧‧‧ wiring layer

40‧‧‧穿孔 40‧‧‧Perforation

42‧‧‧凸塊 42‧‧‧Bumps

44‧‧‧凸塊 44‧‧‧Bumps

48‧‧‧組件 48‧‧‧ components

50‧‧‧結構 50‧‧‧ structure

Claims (20)

一種裝置，包括：多層基板，包括多個介電層及金屬層，該多層基板包含第一側及第二側；半導體晶粒，係嵌入於該基板中，該晶粒包含從該晶粒的第一端延伸至第二端的多個半導體穿孔；該多個半導體穿孔，係電耦合至由該多個金屬層所界定的多個導電路徑，該多個導電路徑包含從該晶粒的該第一端延伸至該基板的該第一側上的多個墊之路徑、以及從該晶粒的該第二端延伸至該基板的該第二側上的多個墊之路徑；其中，在該晶粒中的該多個半導體穿孔具有小於該基板的該第一側上的該該等墊之間距的間距；並且其中，在該晶粒中的該多個半導體穿孔具有小於該基板的該第二側上的該該等墊之間距的間距。 A device comprising: a multilayer substrate comprising a plurality of dielectric layers and a metal layer, the multilayer substrate comprising a first side and a second side; a semiconductor die embedded in the substrate, the die comprising the die a plurality of semiconductor vias extending from the first end to the second end; the plurality of semiconductor vias being electrically coupled to the plurality of conductive paths defined by the plurality of metal layers, the plurality of conductive paths including the first from the die a path extending to one of the plurality of pads on the first side of the substrate, and a path extending from the second end of the die to the plurality of pads on the second side of the substrate; wherein The plurality of semiconductor vias in the die have a pitch less than a distance between the pads on the first side of the substrate; and wherein the plurality of semiconductor vias in the die have less than the first of the substrates The spacing between the pads on the two sides. 如申請專利範圍第1項之裝置，其中，該晶粒係設置成使得該多個介電層及金屬層係位於該晶粒與該基板的該第一側之間。 The device of claim 1, wherein the die is disposed such that the plurality of dielectric layers and metal layers are between the die and the first side of the substrate. 如申請專利範圍第1項之裝置，其中，該基板包括無核心基板。 The device of claim 1, wherein the substrate comprises a coreless substrate. 如申請專利範圍第1項之裝置，其中，該晶粒係位於介電層之內。 The device of claim 1, wherein the die is located within the dielectric layer. 如申請專利範圍第1項之裝置，其中，該晶粒包含被介電層所圍繞的外側邊緣。 The device of claim 1, wherein the die comprises an outer edge surrounded by a dielectric layer. 如申請專利範圍第5項之裝置，又包括位於該晶粒的該外側邊緣與該介電層之間的黏著劑。 The device of claim 5, further comprising an adhesive between the outer edge of the die and the dielectric layer. 如申請專利範圍第1項之裝置，其中，該基板包含核心，該核心包括不同於該介電及金屬層之成分的成分。 The device of claim 1, wherein the substrate comprises a core comprising a composition different from a composition of the dielectric and metal layers. 如申請專利範圍第1項之裝置，又包括嵌入於該基板中的額外晶粒，該額外晶粒包含多個半導體穿孔。 The device of claim 1, further comprising an additional die embedded in the substrate, the additional die comprising a plurality of semiconductor vias. 如申請專利範圍第1項之裝置，其中，該基板之該第二表面上的該等墊的該間距係大於該基板之該第一表面上的該等墊的該間距。 The device of claim 1, wherein the spacing of the pads on the second surface of the substrate is greater than the spacing of the pads on the first surface of the substrate. 如申請專利範圍第1項之裝置，又包括：額外的半導體晶粒，係嵌入於該基板中，該額外的晶粒包含從該額外的晶粒的第一端延伸至第二端的多個半導體穿孔；該額外的晶粒的多個半導體穿孔，係電耦合至由該多個金屬層所界定之額外的多個導電路徑，該多個導電路徑包含從該額外晶粒之該第一端延伸至該基板之該第一側上之額外墊的路徑、以及從該額外晶粒的該第二端延伸至該基板之該第二側上之額外墊的路徑；其中，該額外晶粒中之該等半導體穿孔具有小於該基板之該第一側上的該等額外墊之間距的間距；並且其中，該額外半導體晶粒中之該半導體穿孔具有小於該基板之該第二側上的該等額外墊之間距的間距。 The apparatus of claim 1, further comprising: an additional semiconductor die embedded in the substrate, the additional die comprising a plurality of semiconductors extending from a first end to a second end of the additional die a plurality of semiconductor vias electrically coupled to an additional plurality of conductive paths defined by the plurality of metal layers, the plurality of conductive paths including extending from the first end of the additional die a path to an additional pad on the first side of the substrate, and a path extending from the second end of the additional die to an additional pad on the second side of the substrate; wherein the additional die The semiconductor vias have a pitch less than a distance between the additional pads on the first side of the substrate; and wherein the semiconductor vias in the additional semiconductor die have less than the second side of the substrate The spacing between the extra pads. 如申請專利範圍第1項之裝置，其中，該半導體晶粒包括矽。 The device of claim 1, wherein the semiconductor die comprises germanium. 一種裝置，包括：多層基板，包括多個介電層及金屬層，該多層基板包含第一側及第二側；半導體晶粒，係嵌入於該基板中，該晶粒包含從該晶粒的第一端延伸至第二端的多個半導體穿孔；該多個半導體穿孔，係電耦合至由該金屬層所界定的多個導電路徑，該多個導電路徑包含從該半導體晶粒的該第一端延伸至該基板之該第一側上的多個墊的路徑、以及從該半導體晶粒的該第二端延伸至該基板之該第二側上的多個墊的路徑；其中，在該半導體晶粒中的該多個半導體穿孔具有小於該基板的該第一側上之該等墊的間距之間距；組件，係耦合至該基板的該第一側上的該等墊，該組件包含半導體晶粒；及電路板，係耦合至該基板的該第二側上的該等墊；其中，該基板係位於該組件與該電路板之間。 A device comprising: a multilayer substrate comprising a plurality of dielectric layers and a metal layer, the multilayer substrate comprising a first side and a second side; a semiconductor die embedded in the substrate, the die comprising the die a plurality of semiconductor vias extending from the first end to the second end; the plurality of semiconductor vias being electrically coupled to the plurality of conductive paths defined by the metal layer, the plurality of conductive paths including the first from the semiconductor die a path extending to a plurality of pads on the first side of the substrate, and a path extending from the second end of the semiconductor die to a plurality of pads on the second side of the substrate; wherein The plurality of semiconductor vias in the semiconductor die have a pitch less than a pitch of the pads on the first side of the substrate; the component is coupled to the pads on the first side of the substrate, the component comprising a semiconductor die; and a circuit board coupled to the pads on the second side of the substrate; wherein the substrate is between the component and the circuit board. 如申請專利範圍第12項之電子裝置，其中，該組件包括記憶體結構。 The electronic device of claim 12, wherein the component comprises a memory structure. 如申請專利範圍第12項之電子裝置，其中，該組件包括多個半導體晶粒結構。 The electronic device of claim 12, wherein the component comprises a plurality of semiconductor grain structures. 如申請專利範圍第12項之電子裝置，其中，該半導體晶粒包括矽。 The electronic device of claim 12, wherein the semiconductor die comprises germanium. 一種裝置製造方法，包括：將包含多個半導體穿孔的半導體晶粒嵌入於多層基板 內，該多個半導體穿孔具有間距；以及形成從該多個半導體穿孔延伸至該基板的第一及第二表面上的多個墊之佈線路徑，其中，該基板的該第一表面上的該等墊具有形成為大於該多個半導體穿孔之間距的間距，且其中，該基板的該第二表面上的該等墊具有形成為大於該多個半導體穿孔之間距的間距。 A device manufacturing method comprising: embedding a semiconductor die including a plurality of semiconductor vias in a multilayer substrate Internally, the plurality of semiconductor vias have a pitch; and forming a routing path extending from the plurality of semiconductor vias to the plurality of pads on the first and second surfaces of the substrate, wherein the first surface of the substrate The pad has a pitch formed to be greater than a distance between the plurality of semiconductor vias, and wherein the pads on the second surface of the substrate have a pitch formed to be greater than a distance between the plurality of semiconductor vias. 如申請專利範圍第16項之方法，其中，將半導體晶粒嵌入於多層基板內包含將介電層定位成延伸於該晶粒之周邊的周圍。 The method of claim 16, wherein embedding the semiconductor die in the multilayer substrate comprises positioning the dielectric layer to extend around a perimeter of the die. 如申請專利範圍第17項之方法，又包括將黏著劑定位於該半導體晶粒的外側邊緣與該介電層之間。 The method of claim 17, further comprising positioning an adhesive between the outer edge of the semiconductor die and the dielectric layer. 如申請專利範圍第16項之方法，又包括將組件耦合至該多層基板的該第一表面上。 The method of claim 16, further comprising coupling the component to the first surface of the multilayer substrate. 如申請專利範圍第19項之方法，其中，該組件包括記憶體組件。 The method of claim 19, wherein the component comprises a memory component.
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