TW201340184A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- TW201340184A TW201340184A TW102100917A TW102100917A TW201340184A TW 201340184 A TW201340184 A TW 201340184A TW 102100917 A TW102100917 A TW 102100917A TW 102100917 A TW102100917 A TW 102100917A TW 201340184 A TW201340184 A TW 201340184A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title abstract description 35
- 239000007769 metal material Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 60
- 239000002184 metal Substances 0.000 claims description 60
- 239000000758 substrate Substances 0.000 claims description 49
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- 229910001882 dioxygen Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims 1
- 229910052797 bismuth Inorganic materials 0.000 claims 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims 1
- 229910052758 niobium Inorganic materials 0.000 claims 1
- 239000010955 niobium Substances 0.000 claims 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 26
- 229910052732 germanium Inorganic materials 0.000 description 25
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 25
- 230000008569 process Effects 0.000 description 23
- 230000004048 modification Effects 0.000 description 21
- 238000012986 modification Methods 0.000 description 21
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 19
- 229910052707 ruthenium Inorganic materials 0.000 description 19
- 238000001020 plasma etching Methods 0.000 description 18
- 238000005468 ion implantation Methods 0.000 description 17
- 239000010410 layer Substances 0.000 description 15
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 9
- 238000000137 annealing Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 230000004913 activation Effects 0.000 description 7
- 229910052741 iridium Inorganic materials 0.000 description 7
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000000460 chlorine Substances 0.000 description 6
- 229910052801 chlorine Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 5
- 229910052763 palladium Inorganic materials 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910000420 cerium oxide Inorganic materials 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- NZIHMSYSZRFUQJ-UHFFFAOYSA-N 6-chloro-1h-benzimidazole-2-carboxylic acid Chemical compound C1=C(Cl)C=C2NC(C(=O)O)=NC2=C1 NZIHMSYSZRFUQJ-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- MOAOBEKGMNGXJG-UHFFFAOYSA-N [Te].[Te].[Te].[Au].[Au] Chemical compound [Te].[Te].[Te].[Au].[Au] MOAOBEKGMNGXJG-UHFFFAOYSA-N 0.000 description 2
- BOIGHUSRADNYQR-UHFFFAOYSA-N aluminum;lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Al+3].[La+3] BOIGHUSRADNYQR-UHFFFAOYSA-N 0.000 description 2
- 238000009412 basement excavation Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- PDPJQWYGJJBYLF-UHFFFAOYSA-J hafnium tetrachloride Chemical compound Cl[Hf](Cl)(Cl)Cl PDPJQWYGJJBYLF-UHFFFAOYSA-J 0.000 description 2
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 229910017817 a-Ge Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- TXFYZJQDQJUDED-UHFFFAOYSA-N germanium nickel Chemical compound [Ni].[Ge] TXFYZJQDQJUDED-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 229910001507 metal halide Inorganic materials 0.000 description 1
- 150000005309 metal halides Chemical class 0.000 description 1
- DEPMYWCZAIMWCR-UHFFFAOYSA-N nickel ruthenium Chemical compound [Ni].[Ru] DEPMYWCZAIMWCR-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- KJXBRHIPHIVJCS-UHFFFAOYSA-N oxo(oxoalumanyloxy)lanthanum Chemical compound O=[Al]O[La]=O KJXBRHIPHIVJCS-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
本發明係關於電場效應型之半導體裝置及其製造方法。 The present invention relates to an electric field effect type semiconductor device and a method of fabricating the same.
為求CMOS裝置之消耗電力之減低,MOSFET之源極/汲極區域(SD區域)之寄生電阻之減低成為重要之重點技術。近年來,以更進一步降低寄生電阻為目標,進行藉由使用了鎳矽等金屬矽化物的自我對齊製程來形成擴張區域的金屬SD化(例如參考非專利文獻1)。不論是使用這樣金屬SD構造的情況,還是使用普通p/n接合之SD構造,為了充分減低寄生電阻都需要將閘極側壁盡可能形成更薄。 In order to reduce the power consumption of the CMOS device, the reduction of the parasitic resistance of the source/drain region (SD region) of the MOSFET has become an important technology. In recent years, in order to further reduce the parasitic resistance, the metal formation of the expanded region by the self-alignment process using a metal telluride such as nickel ruthenium is performed (for example, refer to Non-Patent Document 1). Regardless of the case of using such a metal SD structure, or an SD structure using a normal p/n junction, it is necessary to form the gate sidewall as thin as possible in order to sufficiently reduce the parasitic resistance.
又金屬SD構造比起使用p/n接合之情況多出壓低漏電流之課題。在抑制短通道效應而實現已抑制了漏電流之金屬SD構造上,在除了與通道相接之擴張部之外的金屬SD區域下部形成p/n接合區域的方法為有效。(例如非專利文獻2)。因此,提案有採用於閘極之側壁形成用以減低寄生電阻之極薄之第1閘極側壁膜,並於其外側形成第2閘極 側壁膜這樣的二重側壁構造的半導體裝置(例如參考專利文獻1)。但是,即使是這樣的情況下,亦需要將閘極側壁(第1閘極側壁膜)盡可能形成更薄。 Further, the metal SD structure has a problem of lowering the leakage current than when the p/n junction is used. In the metal SD structure in which the short-channel effect is suppressed and the leakage current is suppressed, a method of forming a p/n junction region in the lower portion of the metal SD region other than the expanded portion in contact with the channel is effective. (for example, Non-Patent Document 2). Therefore, it is proposed to form a very thin first gate sidewall film for reducing parasitic resistance on the sidewall of the gate and to form a second gate on the outside thereof. A semiconductor device having a double sidewall structure such as a sidewall film (for example, refer to Patent Document 1). However, even in such a case, it is necessary to form the gate side wall (first gate side wall film) as thin as possible.
如此,不論是使用普通之p/n接合之SD區域之形成、使用金屬SD之SD區域之形成、或是使用二重側壁之組合了金屬SD與p/n接合之SD區域之形成中任何一種情況,均需要一面保持與閘極相接之側壁之絕緣性一面使其盡可能更薄。因此考慮到必須有以良好控制的方式形成閘極側壁膜之製程。 Thus, either the formation of an SD region using a common p/n junction, the formation of an SD region using a metal SD, or the formation of an SD region in which a metal SD and a p/n junction are combined using a double sidewall is used. In this case, it is necessary to keep the insulating side of the side wall that is in contact with the gate to be as thin as possible. Therefore, it is necessary to have a process of forming a gate sidewall film in a well-controlled manner.
習知之該閘極側壁膜一般係使用氮化矽或氧化矽等之絕緣膜。惟,使應該等膜進行薄側壁膜之形成上有RIE製程(反應式離子蝕刻製程)所產生之基板鑿掘的問題。亦即,當將氧化矽或氮化矽這樣的膜種形成做為閘極側壁膜時,可能會在側壁形成用之RIE時蝕刻到閘極絕緣膜及基板。這是因為側壁形成用之RIE所使用之三氟甲烷或四氟化碳等氣體之對閘極絕緣膜或基板之選擇比之渺小。該選擇比之渺小可能使製程界限狹小而導致引起基板鑿掘。如這樣的SD區域之基板鑿掘,特別是引起擴張區域之基板鑿掘時,可預見MOEFET之寄生電阻會大幅增加、每個元件之電阻變異增大及短通道效應之惡化。而此為產生零件特性劣化或變異之主因。 Conventionally, the gate sidewall film is generally made of an insulating film such as tantalum nitride or hafnium oxide. However, there is a problem in that the film is formed into a thin sidewall film by the RIE process (reactive ion etching process). That is, when a film species such as hafnium oxide or tantalum nitride is formed as a gate sidewall film, it may be etched to the gate insulating film and the substrate in the RIE for forming the sidewall. This is because the selection of the gate insulating film or the substrate of the gas such as trifluoromethane or carbon tetrafluoride used for the RIE for sidewall formation is smaller. This choice is smaller than this, which may cause the process boundary to be narrow and cause the substrate to be drilled. Such substrate excavation in the SD region, particularly in the case of substrate excavation in the expanded region, is expected to greatly increase the parasitic resistance of the MOEFET, increase the resistance variation of each element, and deteriorate the short channel effect. This is the main cause of deterioration or variation of part characteristics.
【專利文獻1】特開2005-217245號公報 [Patent Document 1] JP-A-2005-217245
【非專利文獻1】John M. Larson et al., Ieee Trans. Electron Devices, VOL. 53, No. 5 p1048 [Non-Patent Document 1] John M. Larson et al., Ieee Trans. Electron Devices, VOL. 53, No. 5 p1048
【非專利文獻2】A. Kinoshita et al., 2005 Symp. VLSI Tech., 158 [Non-Patent Document 2] A. Kinoshita et al., 2005 Symp. VLSI Tech., 158
本發明之目的係提供一種半導體裝置及其製造方法,其係可在不招致基板鑿掘等情況下控制性良好地於閘極側壁形成薄絕緣膜,而獲取零件之特性提升及變異減低。 An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can form a thin insulating film on the sidewall of a gate with good controllability without causing substrate boring or the like, and obtain characteristics improvement and variation of the component.
本發明之一實施形態之半導體裝置之製造方法係包含於半導體層上形成包含閘極絕緣膜及閘極電極之閘極構造部的程序、及於前述閘極構造部之側壁形程包含金屬材料之絕緣膜即閘極側壁膜的程序。 A method of manufacturing a semiconductor device according to an embodiment of the present invention includes a program for forming a gate structure portion including a gate insulating film and a gate electrode on a semiconductor layer, and a sidewall material including a metal material in the gate structure portion The procedure of the insulating film, that is, the gate sidewall film.
更具體而言,由於必須在不引起閘極側壁膜形成時之RIE所導致之基板鑿掘之情況下控制性良好地形成側壁膜,為了實現此事,如下述進行閘極形成後之側壁膜形成。 More specifically, since it is necessary to form the sidewall film with good control without causing the RIE by the RIE of the gate sidewall film formation, in order to achieve this, the sidewall film after the gate formation is performed as follows. form.
亦即,將氮化鉭或氮化鈦等容易氧化且可藉由金屬膜與氧化膜(閘極絕緣膜)之選擇比高之氯等氣體之RIE來進行蝕刻之金屬材料作為側壁膜來進行沉積,進而RIE 加工。之後,藉由在氧氣供給下照射電漿來僅使金屬膜氧化,並將其作為閘極側壁膜來使用。 In other words, a metal material which is easily oxidized by tantalum nitride or titanium nitride and can be etched by RIE of a metal film and an oxide film (gate insulating film) with a gas having a higher selectivity than chlorine is used as a sidewall film. Deposition, and then RIE machining. Thereafter, only the metal film is oxidized by irradiating the plasma under oxygen supply, and it is used as a gate sidewall film.
又,於閘極電極使用如氮化鉭或氮化鈦等容易氧化之電極材料。而在閘極構造形成後之電極表面露出之狀態下氧化電極表面,並將其作為極薄之側壁膜來使用。 Further, an electrode material which is easily oxidized such as tantalum nitride or titanium nitride is used for the gate electrode. On the other hand, the surface of the electrode is exposed in a state where the surface of the electrode after the formation of the gate electrode is exposed, and is used as an extremely thin sidewall film.
根據本發明,藉由於閘極構造部之側壁形成包含金屬材料之絕緣膜即閘極側壁膜,可在不招致基板鑿掘之情況下,控制性良好地於閘極側壁形成薄絕緣膜。因此,可獲取零件特性之提升即變異之減低。 According to the present invention, since the gate sidewall film which is an insulating film containing a metal material is formed on the sidewall of the gate structure portion, a thin insulating film can be formed on the sidewall of the gate with good controllability without causing the substrate to be drilled. Therefore, an increase in the characteristics of the part, that is, a decrease in variation can be obtained.
更具體而言,與習知技術之使用氮化矽、氧化矽之側壁之情況相比,具有以下優點。側壁形成之RIE製程時,金屬膜與氧化膜(閘極絕緣膜)之RIE選擇比,若為氯則為約20以上這麼高,因此可抑制過蝕刻造成之閘極絕緣膜之蝕刻即基板鑿掘,製程界限寬廣。前述之結果,可得到寄生電阻較小,且可抑制短通道效應之擴張構造。因此,可實現以較低閘極過策動(gate overdrive)得到高電流的MOS電晶體。 More specifically, it has the following advantages as compared with the case of using a side wall of tantalum nitride or tantalum oxide of the prior art. In the RIE process for forming the sidewalls, the RIE selection ratio of the metal film to the oxide film (gate insulating film) is as high as about 20 or more in the case of chlorine, so that the etching of the gate insulating film caused by over-etching can be suppressed. Digging, the process has a wide range of boundaries. As a result of the foregoing, an expanded structure in which the parasitic resistance is small and the short channel effect can be suppressed can be obtained. Therefore, it is possible to realize a MOS transistor which obtains a high current with a lower gate overdrive.
10‧‧‧半導體基板 10‧‧‧Semiconductor substrate
11、51‧‧‧閘極絕緣膜 11, 51‧‧‧ gate insulation film
12、22、52‧‧‧閘極電極 12, 22, 52‧‧ ‧ gate electrode
13‧‧‧閘極硬光罩 13‧‧‧ gate hard mask
14、17‧‧‧金屬膜 14, 17‧‧‧ metal film
16‧‧‧閘極側壁膜 16‧‧‧gate sidewall film
18‧‧‧金屬一半導體合金層(金屬SD構造) 18‧‧‧Metal-semiconductor alloy layer (metal SD structure)
19‧‧‧源極/汲極區域(SD區域) 19‧‧‧Source/bungee area (SD area)
26‧‧‧閘極側壁膜(氧化膜) 26‧‧‧ Gate sidewall film (oxide film)
36‧‧‧膜厚較厚之閘極側壁膜 36‧‧‧Thicker sidewall film with thick film thickness
46‧‧‧閘極側壁膜 46‧‧‧gate sidewall film
50‧‧‧嵌入絕緣膜 50‧‧‧Insulated insulating film
68‧‧‧金屬矽化物層 68‧‧‧metal telluride layer
69‧‧‧擴張區域 69‧‧‧Expanded area
100、200、300、400、500、600、700、800‧‧‧閘極構造部 100, 200, 300, 400, 500, 600, 700, 800‧‧‧ Gate Construction Department
圖1(a)~(d)係顯示關於第1實施形態之半導體裝置之製造程序之前半之剖面圖。 1(a) to 1(d) are cross-sectional views showing the first half of the manufacturing procedure of the semiconductor device of the first embodiment.
圖2(a)~(d)係顯示關於第1實施形態之半導體裝置之製造程序之後半之剖面圖。 2(a) to 2(d) are cross-sectional views showing the second half of the manufacturing procedure of the semiconductor device of the first embodiment.
圖3(a)~(c)係顯示第1實施形態之變形例之程序剖面 圖。 3(a) to (c) show a program profile of a modification of the first embodiment. Figure.
圖4(a)~(b)係顯示關於第2實施形態之半導體裝置之製造程序之剖面圖。 4(a) to 4(b) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the second embodiment.
圖5(a)~(d)係顯示關於第3實施形態之半導體裝置之製造程序之剖面圖。 5(a) to 5(d) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the third embodiment.
圖6(a)~(d)係顯示關於第4實施形態之半導體裝置之製造程序之剖面圖。 6(a) to 6(d) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the fourth embodiment.
圖7(a)~(d)係顯示第4實施形態之變形例之程序剖面圖。 7(a) to 7(d) are cross-sectional views showing the procedure of a modification of the fourth embodiment.
圖8(a)~(e)圖係顯示關於第5實施形態之半導體裝置之製造程序之剖面圖。 8(a) to 8(e) are cross-sectional views showing a manufacturing procedure of the semiconductor device of the fifth embodiment.
以下藉由圖示之實施形態說明本發明之詳情。 The details of the present invention are described below by way of embodiments shown in the drawings.
圖1及圖2係顯示關於第1實施形態之半導體裝置之製造程序的剖面圖。 1 and 2 are cross-sectional views showing a manufacturing procedure of a semiconductor device according to the first embodiment.
首先,如圖1(a)所示,於半導體基板10上將例如厚度5nm之閘極絕緣膜11、例如厚度30nm之閘極電極12及閘極硬光罩13以上述順序依序沉積。接著,藉由光刻法及RIE(反應性離子蝕刻法)製程蝕刻閘極硬光罩13及閘極電極12。藉此形成閘極構造部100。 First, as shown in FIG. 1(a), for example, a gate insulating film 11 having a thickness of 5 nm, for example, a gate electrode 12 having a thickness of 30 nm and a gate hard mask 13 are sequentially deposited on the semiconductor substrate 10 in the above-described order. Next, the gate hard mask 13 and the gate electrode 12 are etched by photolithography and RIE (Reactive Ion Etching). Thereby, the gate structure portion 100 is formed.
在此,作為半導體基板10亦可為從矽開始包含鍺或矽化鍺、砷化鎵、銻化鎵、磷化銦、銦鎵化砷或砷化銦 等高移動度材料的半導體。作為閘極絕緣膜11可使用包含於前述半導體材料之物質之氧化物或氮化物。又,作為閘極絕緣膜11可為以原位原子層沉積(ALD)或化學汽相沈積(CVD)、物理氣相沈積(PVD)(濺鍍法)等所形成之氧化鋁、氧化鉿、氧化鑭、氧化鋯、氧化鎦鑭(LaLuO3)、氧化鋁鑭(LaAlOx)、氧化鋁鉿(HfAlO)、氧化矽、氧化矽鋁鑭(LaAlSiOx)、非晶矽(a-Si)、矽晶(c-Si)、氧化釔或其等之混合物等之高介電係數材料等之絕緣膜。又,閘極電極12可為氮化鉭、氮化鈦、非晶矽、多晶矽、非晶鍺(a-Ge)、多晶鍺(poly-Ge)、鎢、鋁、鈀、鈦、鉻、鉑、鎳、金、矽化鎳、鎳化鍺(NiGe)、矽鍺化鎳(NiSiGe)等。又,閘極硬光罩13可為氮化矽或者氧化矽、多晶矽等。 Here, the semiconductor substrate 10 may be a semiconductor including a high mobility material such as germanium or germanium, gallium arsenide, gallium antimonide, indium phosphide, indium gallium arsenide or indium arsenide. As the gate insulating film 11, an oxide or a nitride of a substance contained in the above semiconductor material can be used. Further, as the gate insulating film 11, alumina or yttrium oxide formed by in-situ atomic layer deposition (ALD) or chemical vapor deposition (CVD), physical vapor deposition (PVD) (sputtering), or the like may be used. Cerium oxide, zirconium oxide, lanthanum oxide (LaLuO 3 ), aluminum oxide lanthanum (LaAlOx), aluminum oxide lanthanum (HfAlO), lanthanum oxide, lanthanum aluminum oxide (LaAlSiOx), amorphous yttrium (a-Si), twin An insulating film of a high dielectric constant material such as (c-Si), yttrium oxide or the like. Moreover, the gate electrode 12 may be tantalum nitride, titanium nitride, amorphous germanium, polycrystalline germanium, amorphous germanium (a-Ge), polycrystalline germanium (poly-Ge), tungsten, aluminum, palladium, titanium, chromium, Platinum, nickel, gold, nickel telluride, nickel germanium (NiGe), nickel telluride (NiSiGe), and the like. Further, the gate hard mask 13 may be tantalum nitride or tantalum oxide, polysilicon or the like.
接著如圖1(b)所示,藉由於氧氣環境氣體中照射電漿可容易氧化,且將以氯、三氯化硼、四氯化碳、四氯化矽氣體進行RIE之金屬膜14沉積大致所期望之膜厚(例如3nm)。金屬膜14矽以濺鍍或CVD等方法進行沉積。金屬膜14之材料可舉出有例如氮化鉭、氮化鈦、氮化鋁、鉭、鈦、鋁、鎳、鉿、鎢、非晶矽、多晶矽、非晶鍺、多晶鍺等。 Next, as shown in FIG. 1(b), the metal film 14 can be easily oxidized by irradiating the plasma in an oxygen atmosphere gas, and the metal film 14 is deposited by RIE using chlorine, boron trichloride, carbon tetrachloride, and hafnium tetrachloride gas. Approximately the desired film thickness (e.g., 3 nm). The metal film 14 is deposited by sputtering or CVD or the like. The material of the metal film 14 may, for example, be tantalum nitride, titanium nitride, aluminum nitride, tantalum, titanium, aluminum, nickel, tantalum, tungsten, amorphous germanium, polycrystalline germanium, amorphous germanium, polycrystalline germanium or the like.
然後,藉由以氯、三氯化硼、四氯化碳、四氯化矽等氣體進行RIE,如圖1(c)所示僅於閘極側壁剩餘金屬膜14。在此,氯等氣體所進行之RIE,其金屬膜與氧化膜之選擇比為20以上非常高。因此,幾乎不會蝕刻到閘極絕緣膜11,故不會蝕刻到閘極絕緣膜11下之半導體基板10。 Then, by performing RIE with a gas such as chlorine, boron trichloride, carbon tetrachloride or hafnium tetrachloride, the metal film 14 remains only on the sidewall of the gate as shown in Fig. 1(c). Here, in the RIE by a gas such as chlorine, the selection ratio of the metal film to the oxide film is extremely high at 20 or more. Therefore, the gate insulating film 11 is hardly etched, so that the semiconductor substrate 10 under the gate insulating film 11 is not etched.
將包含藉上述所形成之閘極側壁之金屬膜14的 閘極構造部100暴露於氧氣氣體、氧電漿或原子氧等來進行氧化。如此一來,如圖1(d)所示,氮化鉭等金屬膜14會成為氮氧化鉭(TaNOx)或者氧化鉭等絕緣性之氧化膜。藉此,可得到形成極薄(例如5nm)之閘極側壁膜16的閘極構造部200。 Will include the metal film 14 of the gate sidewall formed by the above The gate structure portion 100 is exposed to oxygen gas, oxygen plasma, atomic oxygen, or the like for oxidation. As a result, as shown in FIG. 1(d), the metal film 14 such as tantalum nitride becomes an insulating oxide film such as tantalum oxynitride (TaNOx) or ruthenium oxide. Thereby, the gate structure portion 200 forming the extremely thin (for example, 5 nm) gate sidewall film 16 can be obtained.
然後,如圖2(a)所示,去除露出於閘極構造部200以外之閘極絕緣膜11。接著,如圖2(b)所示,為了形成成為金屬擴張區域之金屬-半導體合金層,將金屬膜17沉積例如5nm之厚度。在此金屬膜17為包含例如鎳、鈷、鈦、鉑、鈀、鎢、鍺化金(AuGe)、金等即可。 Then, as shown in FIG. 2(a), the gate insulating film 11 exposed outside the gate structure portion 200 is removed. Next, as shown in FIG. 2(b), in order to form a metal-semiconductor alloy layer which is a metal-expanded region, the metal film 17 is deposited to have a thickness of, for example, 5 nm. Here, the metal film 17 may contain, for example, nickel, cobalt, titanium, platinum, palladium, tungsten, gold (AuGe), gold or the like.
然後,藉由進行合金層形成用之退火,使基板10之表面與金屬膜17產生反應,如圖2(c)所示,形成金屬-半導體合金層18(例如金屬矽化物)。接著,如圖2(d)所示,去除濕式加工中未反應之金屬膜17。也就是說藉此可得到來自自我對齊製程的金屬SD構造18。 Then, by annealing the alloy layer, the surface of the substrate 10 is reacted with the metal film 17, and as shown in Fig. 2(c), a metal-semiconductor alloy layer 18 (e.g., metal halide) is formed. Next, as shown in FIG. 2(d), the unreacted metal film 17 in the wet processing is removed. That is to say that the metal SD structure 18 from the self-aligning process can be obtained.
此後,與一般之MOEFET之製造方法一樣,將氧化矽等作為層間絕緣層而沉積,並藉由光刻法及RIE、濕式處理形成接觸孔。進而,進行與SD區域電性接觸所得到之接觸形成,並藉由進行配線形成完成MOS元件。 Thereafter, as in the conventional MOEFET manufacturing method, yttrium oxide or the like is deposited as an interlayer insulating layer, and contact holes are formed by photolithography, RIE, and wet processing. Further, contact is made by electrical contact with the SD region, and the MOS device is completed by wiring formation.
根據如此之本實施形態,將形成於閘極構造部100之側壁之閘極側壁膜16以包含金屬材料之絕緣膜形成,藉此可在不招致基板鑿掘之情況下於閘極側壁控制性良好地形成薄絕緣膜。因此,可獲取零件特性之提升及變異之減低。 According to the present embodiment, the gate sidewall film 16 formed on the sidewall of the gate structure portion 100 is formed of an insulating film containing a metal material, whereby the gate sidewall controllability can be performed without causing substrate boring. A thin insulating film is formed well. Therefore, the improvement of the characteristics of the parts and the reduction of the variation can be obtained.
做為第1實施形態之變形例,係顯示使用p/n接合之SD區域之例子而非金屬SD構造。 As a modification of the first embodiment, an example of an SD region using p/n bonding is shown instead of a metal SD structure.
如圖3(a)所示到得到閘極構造部200為止與第1實施形態(圖1(d))相同。但,在如以下所示使用離子注入導入雜質之情況中,必須防止雜質之閘極穿透所造成之朝閘極正下方之通道中之無預期之摻雜。因此,因應離子注入能量電極12必須形成較第1實施形態厚(例如50nm以上等)。 As shown in Fig. 3 (a), the gate structure portion 200 is obtained in the same manner as in the first embodiment (Fig. 1 (d)). However, in the case where the impurity is introduced by ion implantation as shown below, it is necessary to prevent the undesired doping in the channel directly under the gate caused by the gate of the impurity. Therefore, the ion implantation energy electrode 12 must be formed thicker than the first embodiment (for example, 50 nm or more).
然後,如圖3(b)所示,將閘極構造部200作為光罩於板導體基板10以離子注入法摻雜雜質,藉此形成由p/n接合形成之SD區域19。接著進行活性退火。在此,若為n-MOEFET,則摻雜n型雜質(例如若為矽或鍺基板則為磷或砷等,若為砷化鎵銦等III-V族化合物基板則為矽)即可。又,若為p-MOEFET則摻雜p型雜質(例如若為矽或鍺基板則為硼等,若為砷化鎵銦等III-V族化合物基板則為鈹)即可。又,亦可進行朝擴張區域之離子注入、或鹵素(Halo)形成用之離子注入。 Then, as shown in FIG. 3(b), the gate structure portion 200 is doped with impurities as a mask on the plate conductor substrate 10 by ion implantation, whereby the SD region 19 formed by p/n bonding is formed. Then, active annealing is performed. Here, in the case of an n-MOEFET, an n-type impurity is doped (for example, phosphorus or arsenic if the ruthenium or ruthenium substrate is used, and ruthenium as a III-V compound substrate such as gallium arsenide or the like). Further, in the case of the p-MOEFET, a p-type impurity is doped (for example, boron is used for the ruthenium or iridium substrate, and ruthenium is used for the III-V compound substrate such as gallium arsenide). Further, ion implantation into the expanded region or ion implantation for forming Halo may be performed.
最後,如圖3(c)所示,形成包含鎳、鈷、鈦、鉑、鈀、鎢、鍺化金及金等之金屬膜並進行矽化。藉此形成金屬矽化物層68,而使配線層之接觸電阻之減低及SD區域之深區域之電阻減低變得可能。然而,圖3(c)中矽顯示離子注入之擴張區域69。 Finally, as shown in FIG. 3(c), a metal film containing nickel, cobalt, titanium, platinum, palladium, tungsten, gold telluride, gold, or the like is formed and deuterated. Thereby, the metal germanide layer 68 is formed, and the contact resistance of the wiring layer is reduced and the resistance of the deep region of the SD region is reduced. However, 矽 in Figure 3(c) shows the expanded region 69 of ion implantation.
其後,沉積氧化矽等作為層間絕緣膜並進行接觸形成等,但後程序由於與第1實施形態相同,在此省略。 Thereafter, ruthenium oxide or the like is deposited as an interlayer insulating film to form a contact or the like, but the subsequent procedure is the same as that of the first embodiment, and is omitted here.
圖4係顯示關於第2實施形態之半導體裝置之製造程序之剖面圖。而於第1及圖2相同之部分賦予相同符號且省略其詳細說明。 Fig. 4 is a cross-sectional view showing a manufacturing procedure of the semiconductor device of the second embodiment. The same portions as those in the first and second portions are denoted by the same reference numerals, and detailed description thereof will be omitted.
如圖4(a)所示,到於半導體基板10上形成具有閘極絕緣膜11、閘極電極22及閘極硬光罩13之閘極構造部300為至矽與第1實施形態(圖1(a))實質相同。惟,本實施形態中閘極電極22之材料期望僅為包含氮化鉭、氮化鈦、氮化鋁、非晶矽、多晶矽、非晶鍺、多晶鍺、鈀、鈦、鎢、鋁、鎳、鉿等之易於藉由氧電漿處理等氧化表面之金屬者構成。 As shown in FIG. 4(a), the gate structure portion 300 having the gate insulating film 11, the gate electrode 22, and the gate hard mask 13 is formed on the semiconductor substrate 10 as in the first embodiment (Fig. 4) 1(a)) is essentially the same. However, in the present embodiment, the material of the gate electrode 22 is desirably only including tantalum nitride, titanium nitride, aluminum nitride, amorphous germanium, polycrystalline germanium, amorphous germanium, polycrystalline germanium, palladium, titanium, tungsten, aluminum, Nickel, ruthenium, etc. are easily formed by oxidizing the surface of the metal such as oxygen plasma treatment.
將前述以氮化鉭或氮化鈦為首之易氧化金屬作為閘極電極22形成閘極構造部300後,藉由將其曝露於氧氣氣體、氧電漿或原子氧等來使閘極電極22之側面氧化。而且,如圖4(b)所示,形成例如厚度5nm之氧化膜26。藉此,得到形成絕緣性之閘極側壁膜26之閘極構造部400。 After forming the gate structure portion 300 by using the oxidizable metal such as tantalum nitride or titanium nitride as the gate electrode 22, the gate electrode 22 is exposed to oxygen gas, oxygen plasma, atomic oxygen or the like. The side is oxidized. Further, as shown in FIG. 4(b), for example, an oxide film 26 having a thickness of 5 nm is formed. Thereby, the gate structure portion 400 forming the insulating gate sidewall film 26 is obtained.
形成閘極構造部400後,可與第1實施形態同樣地形成金屬SD構造18。而且,其以後之程序由於與第1實施形態相同因此在此省略。 After the gate structure portion 400 is formed, the metal SD structure 18 can be formed in the same manner as in the first embodiment. Further, since the subsequent procedures are the same as those in the first embodiment, they are omitted here.
如此本實施形態中,係藉由將閘極電極22氧化形成閘極側壁膜26,使形成閘極側壁膜26時不會產生基板鑿掘。因此,可得到與第1實施形態相同之效果。又,本實施形態中由於與第1實施形態相比沒有金屬膜14之形成及RIE之必要,因此可獲得製造製程簡化這樣的優點。 As described above, in the present embodiment, by forming the gate sidewall film 26 by oxidizing the gate electrode 22, the substrate can be prevented from being formed when the gate sidewall film 26 is formed. Therefore, the same effects as those of the first embodiment can be obtained. Further, in the present embodiment, since the formation of the metal film 14 and the RIE are not required as compared with the first embodiment, the advantage of simplifying the manufacturing process can be obtained.
做為第2實施形態之變形例,係顯示使用了p/n接合之SD區域形成而非金屬SD構造。 As a modification of the second embodiment, an SD region formation using p/n bonding is shown instead of a metal SD structure.
到得到閘極構造部400為止係與第2實施形態相同。惟,在以離子注入形成p/n接合之情況中,如同第1實施形態之變形例中既已描述,必須要增厚閘極電極之厚度。 It is the same as that of the second embodiment until the gate structure portion 400 is obtained. However, in the case where the p/n junction is formed by ion implantation, as described in the modification of the first embodiment, it is necessary to thicken the thickness of the gate electrode.
然後,藉由離子注入法等若為n-MOEFET,則摻雜n型雜質(例如若為矽或鍺基板則為磷或砷等,若為砷化鎵銦等III-V族化合物基板則為矽)即可。又,若為p-MOEFET則摻雜p型雜質(例如若為矽或鍺基板則為硼等,若為砷化鎵銦等III-V族化合物基板則為鈹)即可。又,亦可進行朝擴張區域之離子注入、或鹵素(Halo)形成用之離子注入。接著進行活化退火。 Then, if it is an n-MOEFET by an ion implantation method or the like, an n-type impurity is doped (for example, if the substrate is ruthenium or iridium, it is phosphorus or arsenic, and if it is a III-V compound substrate such as gallium arsenide or the like)矽) Just fine. Further, in the case of the p-MOEFET, a p-type impurity is doped (for example, boron is used for the ruthenium or iridium substrate, and ruthenium is used for the III-V compound substrate such as gallium arsenide). Further, ion implantation into the expanded region or ion implantation for forming Halo may be performed. Then, activation annealing is performed.
然後,沉積氧化矽做為層間絕緣層而形成接觸層,但由於後程序與第1實施形態相同在此省略。 Then, cerium oxide is deposited as an interlayer insulating layer to form a contact layer, but the post-procedure is omitted here as in the first embodiment.
圖5顯示關於第3實施形態之半導體裝置之製造程序之剖面圖。而於與第1至圖3相同部分賦予相同符號,並省略其詳細說明。 Fig. 5 is a cross-sectional view showing a manufacturing procedure of the semiconductor device of the third embodiment. The same portions as those in the first to third embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted.
到形成具有為絕緣膜之閘極側壁第閘極構造為止係與第1實施形態相同。亦即,考慮第1實施形態中所形成之閘極構造部200。然而,此也與第1實施形態之變形例相同,於後進行離子注入程序,因此閘極高度必須與第1實施形態之變形例提高相同程度。 It is the same as that of the first embodiment until the gate structure having the gate side wall which is an insulating film is formed. That is, the gate structure portion 200 formed in the first embodiment is considered. However, this is also the same as the modification of the first embodiment, and the ion implantation process is performed thereafter. Therefore, the gate height must be increased to the same extent as the modification of the first embodiment.
然後,如圖5(a)所示,對形成了閘極側壁膜16(第 1閘極側壁膜)之閘極構造部(前述閘極構造部200),形成形成了閘極側壁膜36(第2閘極側壁膜)之閘極構造部500。在此,閘極側壁膜36係氧化矽或氮化矽等絕緣膜即可。又,就閘極側壁膜36之形成來說係使用於全面沉積絕緣膜後已RIE進行蝕刻的所謂側壁餘留之技術即可。閘極側壁膜36之厚度係側壁形成後之離子注入及活化所造成之橫方向之雜質之擴散長度左右之厚度例如20nm即可。 Then, as shown in FIG. 5(a), the gate sidewall film 16 is formed. The gate structure portion (the gate structure portion 200) of the first gate film (the gate electrode film) has a gate structure portion 500 in which the gate sidewall film 36 (second gate sidewall film) is formed. Here, the gate sidewall film 36 may be an insulating film such as hafnium oxide or tantalum nitride. Further, in the formation of the gate sidewall film 36, a technique of so-called sidewall remaining which has been RIE-etched after the entire deposition of the insulating film is used may be used. The thickness of the gate sidewall film 36 may be, for example, about 20 nm, such as a diffusion length of the impurity in the lateral direction caused by ion implantation and activation after the sidewall formation.
然後,如圖5(b)所示,若為n-MOEFET,則摻雜n型雜質(例如若為矽或鍺基板則為磷或砷等,若為砷化鎵銦等III-V族化合物基板則為矽)即可。又,若為p-MOEFET則摻雜p型雜質(例如若為矽或鍺基板則為硼等,若為砷化鎵銦等III-V族化合物基板則為鈹)即可。再來,藉由進行活化退火來形成SD區域19。 Then, as shown in FIG. 5(b), if it is an n-MOEFET, it is doped with an n-type impurity (for example, if it is a germanium or germanium substrate, it is phosphorus or arsenic, etc., and if it is a III-V compound such as gallium indium arsenide) The substrate is 矽). Further, in the case of the p-MOEFET, a p-type impurity is doped (for example, boron is used for the ruthenium or iridium substrate, and ruthenium is used for the III-V compound substrate such as gallium arsenide). Further, the SD region 19 is formed by performing activation annealing.
然後,如圖5(c)所示,藉由氫氟酸等之濕式處理去除閘極側壁膜36。接著,已濕式處理等去除形成於SD區域19上之閘極絕緣膜11。 Then, as shown in FIG. 5(c), the gate sidewall film 36 is removed by a wet treatment such as hydrofluoric acid or the like. Next, the gate insulating film 11 formed on the SD region 19 is removed by wet processing or the like.
然後,如圖5(d)所示,與第1實施形態同樣地,藉由沉積金屬材料並進行退火處理來形成金屬SD構造18。在此,用以形成金屬-半導體合金層之金屬材料係包含鎳、鈷、鈦、鉑、鈀、鎢、鍺化金及金之金屬即可。藉此以自我對齊製程來形成金屬-半導體合金層18。接著,當有未反應金屬時,則將其以濕式處理等去除。 Then, as shown in FIG. 5(d), the metal SD structure 18 is formed by depositing a metal material and performing annealing treatment as in the first embodiment. Here, the metal material for forming the metal-semiconductor alloy layer may be a metal of nickel, cobalt, titanium, platinum, palladium, tungsten, gold telluride, and gold. Thereby, the metal-semiconductor alloy layer 18 is formed in a self-aligned process. Next, when there is an unreacted metal, it is removed by a wet treatment or the like.
藉由以上之程序,擴張係被金屬SD化,而摻雜區域形成了p/n接合之可實現低寄生電阻且低漏電流的SD 區域。 With the above procedure, the expansion is SD-metalized, and the doped region forms a p/n junction that can achieve low parasitic resistance and low leakage current. region.
如此藉由本實施形態,可使由鉭氧化鉭等形成之第1閘極側壁膜16與由氧化矽等形成之第2閘極側壁膜36之蝕刻選擇比增大。因此,蝕刻去除閘極側壁膜36時閘極側壁膜16會在幾乎沒有被蝕刻的狀態下餘留。因此,即使是使用二重側壁之組合了金屬SD與p/n接合之構造易可得到與之前的第1實施形態相同的效果。 According to this embodiment, the etching selectivity ratio of the first gate sidewall film 16 formed of tantalum oxide or the like and the second gate sidewall film 36 formed of tantalum oxide or the like can be increased. Therefore, when the gate sidewall film 36 is removed by etching, the gate sidewall film 16 remains in a state where it is hardly etched. Therefore, even if the structure in which the metal SD and the p/n junction are combined using the double side wall is used, the same effects as those of the first embodiment can be obtained.
做為第3實施形態之變形例,係顯示氧化與第2實施形態同樣之金屬閘極之側面,形成具有為絕緣膜之閘極側壁之閘極構造的例子。 As a modification of the third embodiment, the side surface of the metal gate similar to that of the second embodiment is oxidized, and an example of a gate structure having a gate side wall of the insulating film is formed.
首先,到氧化金屬閘極之側面,並形成由氧化膜26形成之側壁為止與第2實施形態(圖4(b))相同。亦即,考慮形成第2實施形態之閘極構造部400。以下由於到形成第2閘極側壁膜36形成金屬SD區域為止與第3實施形態相同,因此省略其詳情。 First, the side surface of the oxidized metal gate is formed to be the same as that of the second embodiment (Fig. 4(b)). That is, it is considered that the gate structure portion 400 of the second embodiment is formed. Hereinafter, since the metal SD region is formed by forming the second gate sidewall film 36, the third embodiment is the same, and thus the details thereof will be omitted.
做為第3實施形態即第3實施形態之變形例所得到之金屬SD構造之進一步之變形例,係顯示使用了p/n接合之SD區域形成的例子。 A further modification of the metal SD structure obtained as a modification of the third embodiment, which is a third embodiment, is an example in which an SD region using p/n bonding is formed.
第3實施形態即第3實施形態之變形例中,到進行摻雜區域之離子注入並去除第2閘極側壁膜36為止都相同(圖5(c))。然後,在第1閘極側壁膜16餘留之狀況下進行擴張區域之離子注入,並進行活化退火。其之後與第1實施形 態相同藉由進行後程序來進行接觸形成、配線形成。藉此可得到MOS元件。 In the modification of the third embodiment, the third embodiment is the same as the ion implantation in the doped region and the removal of the second gate sidewall film 36 (Fig. 5(c)). Then, ion implantation in the expanded region is performed while the first gate sidewall film 16 remains, and activation annealing is performed. After that, with the first embodiment In the same state, contact formation and wiring formation are performed by performing a post process. Thereby, a MOS element can be obtained.
圖6係顯示關於第4實施形態之半導體裝置之製造程序之剖面圖。然而,於與第1~圖3相同部分賦予相同符號,並省略其詳細說明。 Fig. 6 is a cross-sectional view showing a manufacturing procedure of the semiconductor device of the fourth embodiment. The same portions as those in the first to third embodiments are denoted by the same reference numerals, and the detailed description thereof will be omitted.
到形成側壁不氧化之閘極構造為止由於係與第1實施形態(圖1(c))相同因此在此省略。由此,如圖6(a)所示可視為形成了於閘極側壁形成有金屬膜14(第1閘極側壁膜)的閘極構造部600。 Since the gate structure in which the side wall is not oxidized is formed in the same manner as in the first embodiment (Fig. 1 (c)), it is omitted here. Thereby, as shown in FIG. 6(a), the gate structure portion 600 in which the metal film 14 (first gate sidewall film) is formed on the gate sidewall can be regarded as being formed.
然後,如圖6(b)所示,形成形成了閘極側壁膜36閘極構造部700。在此,閘極側壁膜36為氧化矽或氮化矽等絕緣膜即可。 Then, as shown in FIG. 6(b), a gate structure portion 700 in which the gate sidewall film 36 is formed is formed. Here, the gate sidewall film 36 may be an insulating film such as hafnium oxide or tantalum nitride.
然後,如圖6(c)所示,對形成該閘極構造部700之構造形成源極/汲極區域19。亦即,若為n-MOEFET,則注入n型雜質(例如若為矽或鍺基板則為磷或砷等,若為砷化鎵銦等III-V族化合物基板則為矽)即可。又,若為p-MOEFET則注入p型雜質(例如若為矽或鍺基板則為硼等,若為砷化鎵銦等III-V族化合物基板則為鈹等)。再來,進行活化退火。 Then, as shown in FIG. 6(c), the source/drain region 19 is formed for the structure in which the gate structure portion 700 is formed. In other words, in the case of an n-MOEFET, an n-type impurity is implanted (for example, phosphorus or arsenic if the ruthenium or iridium substrate is used, and ruthenium is a ruthenium III-V compound substrate such as gallium arsenide or the like). Further, in the case of a p-MOEFET, a p-type impurity is implanted (for example, boron is used for a ruthenium or iridium substrate, and ruthenium or the like for a III-V compound substrate such as gallium arsenide ores). Then, activation annealing is performed.
然後,如圖6(d)所示,將閘極側壁膜36藉由氫氟酸等濕式處理去除。在此,由於為閘極側壁膜之金屬膜14露出,因此藉由將其暴露於氧氣氣體、氧電漿、或原子氧等,氧化形成於閘極側壁之金屬膜14。藉由上述,得到形 成了絕緣性之膜即閘極側壁膜16(第3閘極側壁膜)的閘極構造部。 Then, as shown in FIG. 6(d), the gate sidewall film 36 is removed by a wet treatment such as hydrofluoric acid. Here, since the metal film 14 of the gate sidewall film is exposed, the metal film 14 formed on the sidewall of the gate is oxidized by exposing it to oxygen gas, oxygen plasma, atomic oxygen or the like. By the above, the shape is obtained The gate structure portion of the gate film 16 (third gate sidewall film) which is an insulating film is formed.
之後的金屬SD區域形成製程由於與第3實施形態相同,因此在此省略。進而,與第1實施形態同樣進行後程序藉此進行接觸形成、配線形成。藉此可得到MOS元件。 Since the subsequent metal SD region forming process is the same as that of the third embodiment, it is omitted here. Further, in the same manner as in the first embodiment, a post-program is performed to form contact formation and wiring. Thereby, a MOS element can be obtained.
如此若根據本實施形態,在於閘極構造100之側壁形成有做為的1閘極側壁膜之金屬膜14的狀態下,進行的2閘極側壁膜36之形成、離子注入、即側壁膜36之去除,並於最後將金屬膜14氧化而形成第3閘極絕緣膜16。藉此可在不招致基板鑿掘等之情況下控制性良好地於閘極側壁形成薄絕緣膜16。因此,即使於使用二重側壁的組合了金屬SD與p/n接合之構造中亦可得到與先前之第1實施形態同樣的效果。 According to the present embodiment, in the state in which the metal film 14 of the one-gate sidewall film is formed on the sidewall of the gate structure 100, the formation of the two-gate sidewall film 36 and ion implantation, that is, the sidewall film 36 are performed. This is removed, and finally, the metal film 14 is oxidized to form the third gate insulating film 16. Thereby, the thin insulating film 16 can be formed with good controllability on the sidewall of the gate without causing substrate drilling or the like. Therefore, even in the structure in which the metal SD and the p/n junction are combined using the double side wall, the same effects as those of the first embodiment can be obtained.
如圖7(a)所示,到形成閘極構造部300為止與第2實施形態(圖4(a))相同。亦即,做為閘極電極22之材料僅以包含氮化鉭、氮化鈦、氮化鋁、非晶矽、多晶矽、非晶鍺、鎢、鋁、鎳、鉿等之易於藉由氧電漿處理等氧化之金屬者所構成。 As shown in FIG. 7(a), the second embodiment (FIG. 4(a)) is the same as the formation of the gate structure portion 300. That is, the material of the gate electrode 22 is only easy to use oxygen oxide by including tantalum nitride, titanium nitride, aluminum nitride, amorphous germanium, polycrystalline germanium, amorphous germanium, tungsten, aluminum, nickel, germanium, and the like. It is composed of oxidized metal such as pulp.
然後,如圖7(b)所示,形成已形成了閘極側壁膜36(第1閘極側壁膜)之閘極構造部800。在此,閘極側壁膜36為氧化矽或氮化矽等絕緣膜即可。對形成該閘極構造部800之構造,若為n-MOEFET,則注入n型雜質(例如若為矽或鍺基板則為磷或砷等,若為砷化鎵銦等III-V族化合物基板則 為矽)即可。又,若為p-MOEFET則注入p型雜質(例如若為矽或鍺基板則為硼等,若為砷化鎵銦等III-V族化合物基板則為鈹等)。再來,進行活化退火。藉此形成由p/n接合構成之SD區域19。 Then, as shown in FIG. 7(b), a gate structure portion 800 in which the gate sidewall film 36 (first gate sidewall film) is formed is formed. Here, the gate sidewall film 36 may be an insulating film such as hafnium oxide or tantalum nitride. In the structure in which the gate structure portion 800 is formed, if it is an n-MOEFET, an n-type impurity is implanted (for example, if the substrate is germanium or germanium, it is phosphorus or arsenic, and the like is a III-V compound substrate such as gallium indium arsenide. then Yes, you can. Further, in the case of a p-MOEFET, a p-type impurity is implanted (for example, boron is used for a ruthenium or iridium substrate, and ruthenium or the like for a III-V compound substrate such as gallium arsenide ores). Then, activation annealing is performed. Thereby, the SD region 19 composed of the p/n junction is formed.
然後,如圖7(c)所示,藉由氫氟酸等濕式處理去除前述閘極側壁膜36。在此狀態下,由於閘極電極22之側面露出,因此藉由氧電漿處理等進行氧化來氧化閘極電極22之側面。藉此,如圖7(d)所示,可於閘極電極22之側壁形成具絕緣性閘極側壁膜46(第2閘極側壁膜)的閘極構造部。此時,閘極側壁膜46之厚度係藉由控制氧化時間等可形成為極薄。 Then, as shown in FIG. 7(c), the gate sidewall film 36 is removed by a wet treatment such as hydrofluoric acid. In this state, since the side surface of the gate electrode 22 is exposed, oxidation is performed by oxygen plasma treatment or the like to oxidize the side surface of the gate electrode 22. Thereby, as shown in FIG. 7(d), a gate structure portion having an insulating gate sidewall film 46 (second gate sidewall film) can be formed on the sidewall of the gate electrode 22. At this time, the thickness of the gate sidewall film 46 can be formed to be extremely thin by controlling the oxidation time or the like.
之後的金屬SD區域形成製程由於與第3實施形態相同在此省略。進而,與第1實施形態同樣地藉由進行後程序進行接觸形成及配線形成。藉此可得到MOS元件。 The subsequent metal SD region forming process is omitted here as in the third embodiment. Further, in the same manner as in the first embodiment, contact formation and wiring formation are performed by performing a post process. Thereby, a MOS element can be obtained.
做為對於第4實施形態及其變形例之變形例,係顯示使用了p/n接合之SD區域之形成之例子而非使用僅屬SD構造者。到進行深區域之離子注入並在去除第1閘極側壁膜36之後形成(氧化)第2閘極側壁膜46為止與圖7(d)相同。 As a modification of the fourth embodiment and its modifications, an example of formation of an SD region using p/n bonding is shown instead of using only an SD structure. The ion implantation in the deep region is performed in the same manner as in FIG. 7(d) until the second gate sidewall film 46 is formed (oxidized) after the first gate sidewall film 36 is removed.
然後,對擴張區域進行離子注入,並進行活化退火。之後,與第1實施形態同樣地藉由進行後程序來進行接觸形成、配線形成。藉此可得到MOS元件。 Then, ion implantation is performed on the expanded region, and activation annealing is performed. Thereafter, in the same manner as in the first embodiment, contact formation and wiring formation are performed by performing a post process. Thereby, a MOS element can be obtained.
圖8係顯示關於第5實施形態之半導體裝置之製 造程序的剖面圖。然而,於與圖5相同部分賦予相同符號並省略其詳細說明。 Fig. 8 is a view showing the system of the semiconductor device of the fifth embodiment; A profile view of the program. The same portions as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof will be omitted.
本實施形態係說明在組合了第1~第4實施形態所示之側壁形成製程、及使用鍺等III-V族化基板時之閘極介面特性提升方面具有前景之替換閘極製程的情況下之元件製作例子。 In the present embodiment, in the case where the sidewall forming process shown in the first to fourth embodiments is combined and the gate electrode process is improved in the case of using a III-V group substrate such as a germanium, there is a promising replacement gate process. Example of component making.
與第1~第4實施形態及其等之變形例同樣地,形成閘極構造部、閘極側壁膜及SD區域。在此,一個例子做為顯示於第3實施形態之圖5(d)之程序為止已進行者,使用閘極絕緣膜11、閘極電極12及閘極硬光罩13做為虛設閘極構造。 Similarly to the first to fourth embodiments and the modifications thereof, the gate structure portion, the gate sidewall film, and the SD region are formed. Here, as an example, as shown in the procedure of FIG. 5(d) of the third embodiment, the gate insulating film 11, the gate electrode 12, and the gate hard mask 13 are used as the dummy gate structure. .
然後,如圖8(a)所示,使用PECVD(電漿加強化學蒸氣沈積)等形成可足以充分嵌入虛設閘極之氧化矽等之絕緣膜50。 Then, as shown in FIG. 8(a), an insulating film 50 which is sufficient to sufficiently embed the yttrium oxide or the like of the dummy gate is formed by PECVD (plasma enhanced chemical vapor deposition) or the like.
然後,如圖8(b)所示,進行CMP(化學機械拋光)處理使閘極電極12或閘極硬光罩13之頭部露出、或者使閘極電極12及閘極硬光罩13減少數nm左右之程度。 Then, as shown in FIG. 8(b), CMP (Chemical Mechanical Polishing) treatment is performed to expose the head of the gate electrode 12 or the gate hard mask 13, or to reduce the gate electrode 12 and the gate hard mask 13. A few nm or so.
然後,如圖8(c)所示,藉由濕式處理或RIE去除閘極硬光罩13、閘極電極12、及閘極絕緣膜11。在此,閘極硬光罩13及閘極電極12之去除製程中,必須選擇與嵌入絕緣膜50之去除選擇比充分之材料。例如,嵌入絕緣膜50若為氧化矽,則閘極硬光罩13最好使用氮化矽等,而閘極電極12最好使用非晶矽等。此係由於若為氮化矽則使用磷酸,若為多晶矽則使用氫氧化四甲銨(TMAH),藉此可在不 蝕刻到氧化矽的情況下選擇性地去除該等之材料。 Then, as shown in FIG. 8(c), the gate hard mask 13, the gate electrode 12, and the gate insulating film 11 are removed by wet processing or RIE. Here, in the removal process of the gate hard mask 13 and the gate electrode 12, it is necessary to select a material having a sufficient removal selectivity from the embedded insulating film 50. For example, if the embedded insulating film 50 is yttrium oxide, the gate hard mask 13 is preferably tantalum nitride or the like, and the gate electrode 12 is preferably made of amorphous germanium or the like. This is because phosphoric acid is used if it is tantalum nitride, and tetramethylammonium hydroxide (TMAH) is used if it is polycrystalline germanium. The materials are selectively removed by etching to yttrium oxide.
又,關於閘極絕緣膜11不希望於閘極絕緣膜11之去除時有對基板10之損壞。因此,最好為可僅以濕式處理就去除且可藉由不會蝕刻到基板之蝕刻例如以氫氟酸等去除的膜。做為如此之膜可舉例有氧化矽、氧化氯等。 Further, it is undesirable for the gate insulating film 11 to be damaged by the substrate 10 when the gate insulating film 11 is removed. Therefore, it is preferable to remove the film which can be removed only by the wet process and can be removed by etching without etching to the substrate, for example, hydrofluoric acid or the like. As such a film, cerium oxide, oxidized chlorine or the like can be exemplified.
去除該等虛設閘極構造之全部後,如圖8(d)所示,再度以ALD或CVD沉積閘極絕緣膜51。進而,於其上以濺鍍或CVD等沉積閘極電極52。接著,如圖8(e)所示,藉由以CMP去除絕緣膜50上之閘極電極52進行閘極形成。之後,藉由進行層間絕緣膜形成及配線形成,可實現介面特性良好低寄生電阻且低漏電流之MOEFET。 After removing all of the dummy gate structures, as shown in FIG. 8(d), the gate insulating film 51 is again deposited by ALD or CVD. Further, the gate electrode 52 is deposited thereon by sputtering, CVD or the like. Next, as shown in FIG. 8(e), gate formation is performed by removing the gate electrode 52 on the insulating film 50 by CMP. Thereafter, by performing interlayer insulating film formation and wiring formation, a MOEFET having good interface characteristics and low parasitic resistance and low leakage current can be realized.
如此根據本實施形態,藉由使用氮氧化鉭等金屬之氧化膜做為虛設閘極構造之側壁膜16,可在去除虛設閘極構造時在幾乎不蝕刻到側壁膜16之狀態下使其餘留。因此,如第1~第4實施形態所示,可在沒有基板鑿掘之情況下薄側壁形成。又,藉由以濕式處理去除虛設閘極構造之閘極絕緣膜11可抑制基板鑿掘。因此,藉由組合第1~第4實施形態所示之側壁形成製程、以及替換閘極製程,可獲取進一步零件特性之提升及變異之減低。 According to the present embodiment, by using the oxide film of a metal such as ruthenium oxynitride as the sidewall film 16 of the dummy gate structure, the remaining portion can be left in a state where the sidewall film 16 is hardly etched when the dummy gate structure is removed. . Therefore, as shown in the first to fourth embodiments, the thin side wall can be formed without the substrate being drilled. Further, the substrate can be prevented from being drilled by removing the gate insulating film 11 of the dummy gate structure by a wet process. Therefore, by combining the sidewall forming process and the replacement gate process shown in the first to fourth embodiments, it is possible to obtain an improvement in further component characteristics and a reduction in variation.
而本發明不限定於上述個實施形態。 However, the present invention is not limited to the above embodiments.
用以形成第1實施形態之閘極側壁膜之金屬材料,不限於實施形態已說明者,只要是對閘極絕緣膜或基板具有充分蝕刻選擇比者即可。 The metal material for forming the gate sidewall film of the first embodiment is not limited to the embodiment, and may have a sufficient etching selectivity for the gate insulating film or the substrate.
第1實施形態中藉由在僅於閘極側壁餘留金屬膜之狀態下進行氧化來形成絕緣性閘極側壁膜,但不限於此。例如亦可在將形成於全面之金屬膜氧化形成了絕緣膜後,再藉由將該絕緣膜蝕刻來使絕緣膜僅於閘極側壁餘留。此時,由絕緣膜形成之閘極側壁膜之材料只要對閘極絕緣膜或基板具有充分蝕刻選擇比者即可。 In the first embodiment, the insulating gate sidewall film is formed by performing oxidation in a state where only the gate side wall is left with the metal film, but the invention is not limited thereto. For example, after the oxide film formed on the entire metal film is oxidized to form an insulating film, the insulating film is etched to leave the insulating film only on the sidewall of the gate. In this case, the material of the gate sidewall film formed of the insulating film may have a sufficient etching selectivity for the gate insulating film or the substrate.
又,半導體基板不一定限於塊體積板(bulk substrate),亦可為透過絕緣層於基板上形成半導體層者。 Further, the semiconductor substrate is not necessarily limited to a bulk substrate, and may be a semiconductor layer formed on the substrate through the insulating layer.
已說明了本發明之幾個實施形態,但該等實施形態係作為例子而提示者,並非意圖限定發明之範圍。該等實施形態可以其他各種形態來實施,在不脫離發明要旨之範圍內可進行各種省略、置換或變更。該等實施形態或其變形例,如同包含於發明範圍或要旨,係包含於專利請求範圍所記載之發明即其均等之範圍中。 The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The invention and its modifications are intended to be included within the scope of the invention as defined by the appended claims.
10‧‧‧半導體基板 10‧‧‧Semiconductor substrate
11‧‧‧閘極絕緣膜 11‧‧‧Gate insulation film
12‧‧‧閘極電極 12‧‧‧ gate electrode
13‧‧‧閘極硬光罩 13‧‧‧ gate hard mask
14‧‧‧金屬膜 14‧‧‧Metal film
16‧‧‧閘極側壁膜 16‧‧‧gate sidewall film
100、200‧‧‧閘極構造部 100, 200‧‧‧ Gate Construction Department
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