TW201337890A - Common voltage generating circuit - Google Patents
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Abstract
Description
本發明內容是有關於一種電壓產生電路，且特別是有關於一種顯示裝置中之共通電壓產生電路。SUMMARY OF THE INVENTION The present invention is directed to a voltage generating circuit, and more particularly to a common voltage generating circuit in a display device.
近年來，由於液晶顯示器具有高品質的影像顯示能力與低耗電之特性，因此其已普遍被使用作為顯示裝置。In recent years, liquid crystal displays have been widely used as display devices because of their high-quality image display capability and low power consumption.
以液晶顯示器而言，其顯示面板中配置有包含畫素電極的陣列基板、包含共通電極的濾光片基板以及置於兩者間的液晶分子。於操作上，畫素電極和共通電極被分別施以畫素電壓和共通電壓(VCOM)，藉此使得液晶分子因畫素電壓與共通電壓間的電位差而相對應地轉動或改變方向，藉由液晶分子的角度不同而影響光線的穿透度以呈現出顯示畫面。In the liquid crystal display, an array substrate including a pixel electrode, a filter substrate including a common electrode, and liquid crystal molecules interposed therebetween are disposed in the display panel. In operation, the pixel electrode and the common electrode are respectively applied with a pixel voltage and a common voltage (VCOM), whereby the liquid crystal molecules are correspondingly rotated or changed in direction due to a potential difference between the pixel voltage and the common voltage. The angle of the liquid crystal molecules is different to affect the transmittance of the light to present a display.
一般而言，顯示面板中通常設置有專用以產生前述共通電壓的積體電路(IC)。然而，在顯示面板中設置此一積體電路不僅會大幅地增加成本，不符合經濟效益，而且此類積體電路一般均設定有資料寫入次數的限制，使用上較不方便且不具彈性。In general, an integrated circuit (IC) dedicated to generate the aforementioned common voltage is usually provided in the display panel. However, the provision of such an integrated circuit in the display panel not only greatly increases the cost, but also is not economical, and such integrated circuits are generally set with a limit on the number of times of data writing, which is inconvenient and inflexible in use.
本發明內容是關於一種共通電壓產生電路，藉以解決顯示面板中設置專用以產生共通電壓的積體電路致使成本增加的問題。SUMMARY OF THE INVENTION The present invention is directed to a common voltage generating circuit for solving the problem that an integrated circuit provided in a display panel dedicated to generate a common voltage causes an increase in cost.
本發明內容之一實施方式係關於一種共通電壓產生電路，其包含時序控制器、資料控制器、記憶體、分壓單元以及電壓轉換單元。時序控制器用以傳送至少一信號。資料控制器用以透過內部積體電路介面接收信號。記憶體用以儲存相對應信號之電壓資料，其中資料控制器依據記憶體所儲存之電壓資料和信號產生控制信號。分壓單元用以依據控制信號產生類比電壓信號。電壓轉換單元用以將類比電壓信號轉換為共通電壓信號。其中，資料控制器與分壓單元共同整合於時序控制器中。One embodiment of the present invention is directed to a common voltage generating circuit including a timing controller, a data controller, a memory, a voltage dividing unit, and a voltage converting unit. The timing controller is configured to transmit at least one signal. The data controller is used to receive signals through the internal integrated circuit interface. The memory is used to store the voltage data of the corresponding signal, wherein the data controller generates the control signal according to the voltage data and signals stored in the memory. The voltage dividing unit is configured to generate an analog voltage signal according to the control signal. The voltage conversion unit is configured to convert the analog voltage signal into a common voltage signal. The data controller and the voltage dividing unit are integrated in the timing controller.
本發明內容之另一實施方式係關於一種共通電壓產生電路，其包含時序控制器、記憶體以及電壓轉換單元。時序控制器經整合具有資料控制器以及分壓單元，資料控制器之信號輸出端電性耦接分壓單元。記憶體電性耦接資料控制器。電壓轉換單元之輸入端電性耦接分壓單元，電壓轉換單元用以將分壓單元之輸出轉換為共通電壓信號。Another embodiment of the present disclosure is directed to a common voltage generating circuit including a timing controller, a memory, and a voltage converting unit. The timing controller is integrated with a data controller and a voltage dividing unit, and the signal output end of the data controller is electrically coupled to the voltage dividing unit. The memory is electrically coupled to the data controller. The input end of the voltage conversion unit is electrically coupled to the voltage dividing unit, and the voltage conversion unit is configured to convert the output of the voltage dividing unit into a common voltage signal.
根據本發明之技術內容，應用前述共通電壓產生電路，不僅可將大部分的單元或元件整合於時序控制器中，或者藉由時序控制器或功率積體電路(Power IC)內部原有的相關電路來實現大部分的單元或元件，因此可省去單一共通電壓積體電路的配置，而仍然可透過原有電路或僅需新增部分電路，產生所需的數位共通電壓信號，進而大幅地節省成本。此外，採用本發明實施例所述之共通電壓產生電路，便可選擇適合的記憶體來儲存資料，使得資料能方便且具彈性地多次寫入，不需受限於單一共通電壓積體電路設定有寫入次數的限制。According to the technical content of the present invention, the aforementioned common voltage generating circuit can be used to integrate not only most of the cells or components in the timing controller, but also the original correlation between the timing controller or the power IC (Power IC). The circuit realizes most of the cells or components, so that the configuration of the single common voltage integrated circuit can be omitted, and the required digital constant voltage signal can be generated through the original circuit or only a part of the newly added circuit, thereby greatly cut costs. In addition, by using the common voltage generating circuit described in the embodiment of the present invention, a suitable memory can be selected to store data, so that the data can be written multiple times conveniently and flexibly, without being limited by a single common voltage integrated circuit. Set the limit for the number of writes.
本發明內容旨在提供本揭示內容的簡化摘要，以使閱讀者對本揭示內容具備基本的理解。此發明內容並非本揭示內容的完整概述，且其用意並非在指出本發明實施例的重要(或關鍵)元件或界定本發明的範圍。This summary is intended to provide a simplified summary of the disclosure This Summary is not an extensive overview of the disclosure, and is intended to be illustrative of the embodiments of the invention.
下文係舉實施例配合所附圖式作詳細說明，但所提供之實施例並非用以限制本發明所涵蓋的範圍，而結構運作之描述非用以限制其執行之順序，任何由元件重新組合之結構，所產生具有均等功效的裝置，皆為本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of the structure operation is not intended to limit the order of execution, any component recombination The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions.
關於本文中所使用之『約』、『大約』或『大致』一般通常係指數值之誤差或範圍於百分之二十以內，較好地是於百分之十以內，而更佳地則是於百分之五以內。文中若無明確說明，其所提及的數值皆視作為近似值，即如『約』、『大約』或『大致』所表示的誤差或範圍。As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within 20%, preferably within 10%, and more preferably It is within 5 percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, that is, the errors or ranges indicated by "about", "about" or "roughly".
另外，關於本文中所使用之『耦接』或『連接』，均可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，而『耦接』還可指二或多個元件相互操作或動作。In addition, as used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "coupled" It can also mean that two or more elements operate or act on each other.
第1圖係依照本發明第一實施例繪示一種共通電壓產生電路的示意圖。如第1圖所示，共通電壓(common voltage，Vcom)產生電路100包含時序控制器110、資料控制器120、記憶體130、分壓單元140以及電壓轉換單元150，其中資料控制器120與分壓單元140係共同整合於時序控制器110中，使得時序控制器110經整合而具有資料控制器120以及分壓單元140於其中。FIG. 1 is a schematic diagram showing a common voltage generating circuit according to a first embodiment of the present invention. As shown in FIG. 1 , the common voltage (Vcom) generating circuit 100 includes a timing controller 110, a data controller 120, a memory 130, a voltage dividing unit 140, and a voltage converting unit 150, wherein the data controller 120 and the points The voltage unit 140 is integrated in the timing controller 110 such that the timing controller 110 is integrated with the data controller 120 and the voltage dividing unit 140 therein.
時序控制器110可藉由內部積體電路(inter-integrated circuit，I2C)介面與液晶顯示模組(例如包含閘極驅動器、資料驅動器、液晶面板...等元件)進行資料傳輸或信號傳輸，並可透過內部積體電路介面傳送至少一信號。以本實施例而言，時序控制器110可透過內部積體電路介面傳送資料信號SDA和時序信號SCL，其中資料信號SDA可代表時序控制器110與其他元件(如：液晶顯示模組)間的資料傳輸，而時序信號SCL可用以對前述資料傳輸作時程上的控制。The timing controller 110 can perform data transmission or signal by using an internal inter-integrated circuit (I 2 C) interface and a liquid crystal display module (for example, a component including a gate driver, a data driver, a liquid crystal panel, etc.). Transmit and transmit at least one signal through the internal integrated circuit interface. In this embodiment, the timing controller 110 can transmit the data signal SDA and the timing signal SCL through the internal integrated circuit interface, wherein the data signal SDA can represent the timing controller 110 and other components (such as a liquid crystal display module). Data transmission, and timing signal SCL can be used to control the timing of the aforementioned data transmission.
資料控制器120用以透過內部積體電路介面接收前述信號。記憶體130電性耦接資料控制器120，用以儲存相對應信號之電壓資料(或對應的影像資料)。資料控制器120則依據記憶體130所儲存之電壓資料(或對應的影像資料)和前述信號產生一控制信號CTR。實作上，記憶體130可以是可程式化(programmable)記憶體，例如：電子抹除式唯讀記憶體(electrically erasable programmable read only memory，EEPROM)或其他類型的記憶體，然而本發明不以上述為限。The data controller 120 is configured to receive the aforementioned signals through an internal integrated circuit interface. The memory 130 is electrically coupled to the data controller 120 for storing voltage data (or corresponding image data) of the corresponding signal. The data controller 120 generates a control signal CTR according to the voltage data (or corresponding image data) stored in the memory 130 and the foregoing signal. In practice, the memory 130 may be a programmable memory, such as an electrically erasable programmable read only memory (EEPROM) or other type of memory, but the present invention does not The above is limited.
資料控制器120之信號輸出端電性耦接分壓單元140，且分壓單元140用以接收資料控制器120所輸出的控制信號CTR，而依據控制信號CTR產生一類比電壓信號AVS。The signal output terminal of the data controller 120 is electrically coupled to the voltage dividing unit 140, and the voltage dividing unit 140 is configured to receive the control signal CTR output by the data controller 120, and generate an analog voltage signal AVS according to the control signal CTR.
電壓轉換單元150之輸入端電性耦接分壓單元140，並用以將分壓單元140產生的類比電壓信號AVS轉換為一共通電壓信號VCOM。The input end of the voltage conversion unit 150 is electrically coupled to the voltage dividing unit 140 and used to convert the analog voltage signal AVS generated by the voltage dividing unit 140 into a common voltage signal VCOM.
第2A圖係依照本發明實施例繪示一種如第1圖所示之共通電壓產生電路的電路示意圖。如第2A圖所示，於共通電壓產生電路200中，時序控制器210經整合具有資料控制器220(包含內部積體電路介面)以及分壓單元240，資料控制器220之信號輸出端電性耦接分壓單元240，記憶體230配置於時序控制器210的外部而電性耦接資料控制器220，電壓轉換單元250配置於時序控制器210的外部而電性耦接分壓單元240。2A is a circuit diagram showing a common voltage generating circuit as shown in FIG. 1 according to an embodiment of the invention. As shown in FIG. 2A, in the common voltage generating circuit 200, the timing controller 210 is integrated with a data controller 220 (including an internal integrated circuit interface) and a voltage dividing unit 240, and the signal output terminal of the data controller 220 is electrically connected. The voltage dividing unit 240 is coupled to the external controller of the timing controller 210 and electrically coupled to the data controller 220. The voltage converting unit 250 is disposed outside the timing controller 210 and electrically coupled to the voltage dividing unit 240.
實作上，分壓單元240可以為數位類比轉換器(DAC)或是配置於數位類比轉換器(DAC)中，且此數位類比轉換器係用以將資料控制器220所輸出的信號轉換為相對應的類比電壓信號，第2B圖係依照本發明實施例繪示一種前述數位類比轉換器的電路示意圖，如第2B圖所示，數位類比轉換器包含暫存器(register)262、解碼器(decoder)264以及分壓電路(R2)266。In practice, the voltage dividing unit 240 can be a digital analog converter (DAC) or a digital analog converter (DAC), and the digital analog converter is used to convert the signal output by the data controller 220 into Corresponding analog voltage signal, FIG. 2B is a schematic circuit diagram of a digital analog converter according to an embodiment of the present invention. As shown in FIG. 2B, the digital analog converter includes a register 262 and a decoder. (decoder) 264 and voltage dividing circuit (R2) 266.
同時參照第2A圖和第2B圖，在操作上，資料控制器220可從記憶體230中讀取相關資料或數據，再將所讀取的資料或數據寫入暫存器262中，而當需要輸出或調整共通電壓信號VCOM時，相關資料或數據可再透過資料信號SDA和時序信號SCL由資料控制器220寫入記憶體230或暫存器262中，然後解碼器264將相關資料或數據轉換為對應的信號，分壓電路266中的各個開關(S)依據對應的信號開啟或關閉，使得對應的類比電壓信號依據對應的分壓情形產生，並進而傳送至電壓轉換單元250。在一實施例中，前述有關內部積體電路介面、資料控制器220和分壓單元240的相關線路均可藉由時序控制器210內部具相同(或類似)功能或配置的原有電路來實現。在另一實施例中，時序控制器210原先不具有分壓單元240的相關線路，而分壓單元240的相關線路是新增並整合於時序控制器210中。Referring to FIG. 2A and FIG. 2B simultaneously, in operation, the data controller 220 can read related data or data from the memory 230, and then write the read data or data into the register 262, and when When the common voltage signal VCOM needs to be output or adjusted, the related data or data can be further written into the memory 230 or the temporary memory 262 by the data controller 220 through the data signal SDA and the timing signal SCL, and then the decoder 264 will correlate the data or data. Converted to the corresponding signal, each switch (S) in the voltage dividing circuit 266 is turned on or off according to the corresponding signal, so that the corresponding analog voltage signal is generated according to the corresponding partial voltage situation, and further transmitted to the voltage converting unit 250. In an embodiment, the related circuits related to the internal integrated circuit interface, the data controller 220, and the voltage dividing unit 240 can be implemented by using the original circuit with the same (or similar) function or configuration in the timing controller 210. . In another embodiment, the timing controller 210 does not originally have the associated line of the voltage dividing unit 240, and the associated line of the voltage dividing unit 240 is newly added and integrated in the timing controller 210.
實作上，當電壓轉換單元250配置於時序控制器210的外部時，電壓轉換單元250也可整合於一功率積體電路(Power IC)中，或是藉由功率積體電路內部具相同(或類似)功能或相同配置的原有電路來實現。In practice, when the voltage conversion unit 250 is disposed outside the timing controller 210, the voltage conversion unit 250 can also be integrated into a power integrated circuit (Power IC), or the same by the power integrated circuit ( Or similar) the original circuit of the function or the same configuration.
依據上述，由於共通電壓產生電路中的單元或元件可部分整合於時序控制器中，或者藉由時序控制器及功率積體電路內部原有的相關電路來實現，因此在不使用單一共通電壓積體電路的情形下，仍然可透過原有電路或僅需新增部分電路，即可據以產生所需的數位共通電壓信號，進而大幅地節省成本。According to the above, since the unit or component in the common voltage generating circuit can be partially integrated in the timing controller, or realized by the timing controller and the original related circuit inside the power integrated circuit, the single common voltage product is not used. In the case of a bulk circuit, the original digital circuit can still be transmitted through the original circuit or only a part of the circuit can be added, thereby generating a required digital common voltage signal, thereby greatly reducing the cost.
此外，採用本發明實施例所述之共通電壓產生電路，便可選擇適合的記憶體來儲存資料，使得資料能方便且具彈性地多次寫入，不需受限於單一共通電壓積體電路設定有寫入次數的限制。In addition, by using the common voltage generating circuit described in the embodiment of the present invention, a suitable memory can be selected to store data, so that the data can be written multiple times conveniently and flexibly, without being limited by a single common voltage integrated circuit. Set the limit for the number of writes.
第3圖係依照本發明第二實施例繪示一種共通電壓產生電路的示意圖。如第3圖所示，於共通電壓產生電路300中，電壓轉換單元350係與資料控制器320(包含內部積體電路介面)和分壓單元340共同整合於時序控制器310中，資料控制器320之信號輸出端電性耦接分壓單元340，記憶體330配置於時序控制器310的外部而電性耦接資料控制器320，電壓轉換單元350電性耦接分壓單元340。FIG. 3 is a schematic diagram showing a common voltage generating circuit according to a second embodiment of the present invention. As shown in FIG. 3, in the common voltage generating circuit 300, the voltage converting unit 350 is integrated with the data controller 320 (including the internal integrated circuit interface) and the voltage dividing unit 340 in the timing controller 310, and the data controller The signal output terminal of the battery is electrically coupled to the voltage dividing unit 340. The memory 330 is disposed outside the timing controller 310 and electrically coupled to the data controller 320. The voltage converting unit 350 is electrically coupled to the voltage dividing unit 340.
同樣地，前述有關內部積體電路介面、資料控制器320、分壓單元340和電壓轉換單元350的相關線路均可藉由時序控制器310內部具相同(或類似)功能或配置的原有電路來實現，而在另一實施例中，時序控制器310原先不具有分壓單元340和電壓轉換單元350的相關線路，分壓單元340和電壓轉換單元350的相關線路是新增並整合於時序控制器310中。Similarly, the related circuits related to the internal integrated circuit interface, the data controller 320, the voltage dividing unit 340, and the voltage converting unit 350 can be used by the original circuit having the same (or similar) function or configuration in the timing controller 310. In another embodiment, the timing controller 310 does not originally have the relevant line of the voltage dividing unit 340 and the voltage converting unit 350, and the related lines of the voltage dividing unit 340 and the voltage converting unit 350 are newly added and integrated in the timing. In controller 310.
依據上述，由於共通電壓產生電路中的單元或元件大部分均可整合於時序控制器，或者藉由時序控制器內部原有的相關電路來實現，因此在不使用單一共通電壓積體電路的情形下，仍然可透過原有電路或僅需新增部分電路，即可據以產生所需的數位共通電壓信號，進而大幅地節省成本。此外，資料亦能方便且具彈性地多次寫入所選用的適合記憶體中，不需受限於單一共通電壓積體電路設定有寫入次數的限制。According to the above, since most of the cells or components in the common voltage generating circuit can be integrated in the timing controller or realized by the existing related circuits in the timing controller, the case where a single common voltage integrated circuit is not used is used. Under the existing circuit, or only need to add some circuits, the required digital common voltage signal can be generated, thereby greatly saving the cost. In addition, the data can be easily and flexibly written into the selected memory for multiple times, without being limited by the limitation of the number of writes set by the single common voltage integrated circuit.
第4圖係依照本發明第三實施例繪示一種共通電壓產生電路的示意圖。如第4圖所示，於共通電壓產生電路400中，記憶體430係與資料控制器420(包含內部積體電路介面)和分壓單元440共同整合於時序控制器410中，資料控制器420之信號輸出端電性耦接分壓單元440，記憶體430電性耦接資料控制器420，電壓轉換單元450配置於時序控制器410的外部而電性耦接分壓單元440。Figure 4 is a schematic diagram showing a common voltage generating circuit in accordance with a third embodiment of the present invention. As shown in FIG. 4, in the common voltage generating circuit 400, the memory 430 is integrated with the data controller 420 (including the internal integrated circuit interface) and the voltage dividing unit 440 in the timing controller 410, and the data controller 420 The signal output terminal is electrically coupled to the voltage dividing unit 440 , and the memory 430 is electrically coupled to the data controller 420 . The voltage converting unit 450 is disposed outside the timing controller 410 and electrically coupled to the voltage dividing unit 440 .
同樣地，前述有關內部積體電路介面、資料控制器420、分壓單元440和記憶體430的相關線路均可藉由時序控制器410內部具相同(或類似)功能或配置的原有電路來實現，而在另一實施例中，時序控制器410原先不具有分壓單元440和記憶體430的相關線路，分壓單元440和記憶體430的相關線路是新增並整合於時序控制器410中。Similarly, the related circuits related to the internal integrated circuit interface, the data controller 420, the voltage dividing unit 440, and the memory 430 can be used by the original circuit having the same (or similar) function or configuration in the timing controller 410. In another embodiment, the timing controller 410 does not have the relevant circuit of the voltage dividing unit 440 and the memory 430. The related circuits of the voltage dividing unit 440 and the memory 430 are newly added and integrated in the timing controller 410. in.
第5圖係依照本發明第四實施例繪示一種共通電壓產生電路的示意圖。如第5圖所示，於共通電壓產生電路500中，資料控制器520(包含內部積體電路介面)、記憶體530、分壓單元540與電壓轉換單元550共同整合於時序控制器510中，資料控制器520之信號輸出端電性耦接分壓單元540，記憶體530電性耦接資料控制器520，電壓轉換單元550電性耦接分壓單元540。FIG. 5 is a schematic diagram showing a common voltage generating circuit according to a fourth embodiment of the present invention. As shown in FIG. 5, in the common voltage generating circuit 500, the data controller 520 (including the internal integrated circuit interface), the memory 530, the voltage dividing unit 540, and the voltage converting unit 550 are integrated in the timing controller 510. The signal output end of the data controller 520 is electrically coupled to the voltage dividing unit 540. The memory 530 is electrically coupled to the data controller 520. The voltage converting unit 550 is electrically coupled to the voltage dividing unit 540.
同樣地，前述有關內部積體電路介面、資料控制器520、分壓單元540、記憶體530和電壓轉換單元550的相關線路均可藉由時序控制器510內部具相同(或類似)功能或配置的原有電路來實現，而在另一實施例中，時序控制器510原先不具有分壓單元540、記憶體530和電壓轉換單元550的相關線路，分壓單元540、記憶體530和電壓轉換單元550的相關線路是新增並整合於時序控制器510中。Similarly, the related lines related to the internal integrated circuit interface, the data controller 520, the voltage dividing unit 540, the memory 530, and the voltage converting unit 550 can all have the same (or similar) function or configuration by the timing controller 510. The original circuit is implemented, and in another embodiment, the timing controller 510 does not have the relevant circuit of the voltage dividing unit 540, the memory 530 and the voltage converting unit 550, the voltage dividing unit 540, the memory 530, and the voltage conversion. The associated circuitry of unit 550 is new and integrated into timing controller 510.
實作上，前述記憶體可以是可程式化(programmable)記憶體，例如：電子抹除式唯讀記憶體(electrically erasable programmable read only memory，EEPROM)或其他類型的記憶體，本發明不以上述為限。其次，前述資料控制器(包含內部積體電路介面)、記憶體、分壓單元與電壓轉換單元均可選擇性地依據實際需求共同或個別整合於時序控制器中，本發明亦不以上述為限。In practice, the foregoing memory may be a programmable memory, such as an electrically erasable programmable read only memory (EEPROM) or other type of memory. Limited. Secondly, the data controller (including the internal integrated circuit interface), the memory, the voltage dividing unit and the voltage converting unit can be selectively integrated into the timing controller according to actual needs, and the present invention is not limit.
由上述本發明之實施例可知，由於在產生共通電壓的電路中大部分的單元或元件均可整合於時序控制器中，或者藉由時序控制器及功率積體電路(Power IC)內部原有的相關電路來實現大部分的單元或元件，因此可省去單一共通電壓積體電路的配置，而仍然可透過原有電路或僅需新增部分電路，產生所需的共通電壓信號，進而大幅地節省成本。此外，採用本發明實施例所述之共通電壓產生電路，便可選擇適合的記憶體來儲存資料，使得資料能方便且具彈性地多次寫入，不需受限於單一共通電壓積體電路設定有寫入次數的限制。It can be seen from the above embodiments of the present invention that most of the cells or components in the circuit for generating the common voltage can be integrated into the timing controller, or by the timing controller and the power integrated circuit (Power IC). The relevant circuit to realize most of the cells or components, so that the configuration of the single common voltage integrated circuit can be omitted, and the required common voltage signal can be generated through the original circuit or only a part of the newly added circuit. Save costs. In addition, by using the common voltage generating circuit described in the embodiment of the present invention, a suitable memory can be selected to store data, so that the data can be written multiple times conveniently and flexibly, without being limited by a single common voltage integrated circuit. Set the limit for the number of writes.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何本領域具通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.
100、200、300、400、500．．．共通電壓產生電路100, 200, 300, 400, 500. . . Common voltage generating circuit
110、210、310、410、520．．．時序控制器110, 210, 310, 410, 520. . . Timing controller
120、220、320、420、520．．．資料控制器120, 220, 320, 420, 520. . . Data controller
130、230、330、430、530．．．記憶體130, 230, 330, 430, 530. . . Memory
140、240、340、440、540．．．分壓單元140, 240, 340, 440, 540. . . Partition unit
150、250、350、450、550．．．電壓轉換單元150, 250, 350, 450, 550. . . Voltage conversion unit
262．．．暫存器262. . . Register
264．．．解碼器264. . . decoder
266．．．分壓電路266. . . Voltage dividing circuit
第1圖係依照本發明第一實施例繪示一種共通電壓產生電路的示意圖。FIG. 1 is a schematic diagram showing a common voltage generating circuit according to a first embodiment of the present invention.
第2A圖係依照本發明實施例繪示一種如第1圖所示之共通電壓產生電路的電路示意圖。2A is a circuit diagram showing a common voltage generating circuit as shown in FIG. 1 according to an embodiment of the invention.
第2B圖係依照本發明實施例繪示一種數位類比轉換器的電路示意圖。2B is a circuit diagram of a digital analog converter according to an embodiment of the invention.
第3圖係依照本發明第二實施例繪示一種共通電壓產生電路的示意圖。FIG. 3 is a schematic diagram showing a common voltage generating circuit according to a second embodiment of the present invention.
第4圖係依照本發明第三實施例繪示一種共通電壓產生電路的示意圖。Figure 4 is a schematic diagram showing a common voltage generating circuit in accordance with a third embodiment of the present invention.
第5圖係依照本發明第四實施例繪示一種共通電壓產生電路的示意圖。FIG. 5 is a schematic diagram showing a common voltage generating circuit according to a fourth embodiment of the present invention.
200．．．共通電壓產生電路200. . . Common voltage generating circuit
210．．．時序控制器210. . . Timing controller
220．．．資料控制器220. . . Data controller
230．．．記憶體230. . . Memory
240．．．分壓單元240. . . Partition unit
250．．．電壓轉換單元250. . . Voltage conversion unit
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| CN 201210066857 CN102592560B (en) | 2012-03-12 | 2012-03-12 | Common voltage generation circuit |
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