TW201322610A - Power supply - Google Patents
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Abstract
Description
本發明有關於一種電源供應器，且特別是有關於一種可以間歇式供電的電源供應器。The present invention relates to a power supply, and more particularly to a power supply that can be intermittently powered.
一般而言，當使用交換式電源供應裝置(switching mode power supply)做為電子裝置之電源時，通常會以一個高頻之脈衝寬度調變(pulse width modulation，PWM)信號來控制功率開關電路，使得輸入電壓可以被適當的轉換以供應給電子裝置。特別是，交換式電源供應裝置判斷電子裝置是在輕載或待機時，可以改為供應相對較低的電能(例如僅提供足以維持待機電路所需之電能)，以節省電力消耗。In general, when a switching mode power supply is used as the power source of the electronic device, the power switching circuit is usually controlled by a high frequency pulse width modulation (PWM) signal. The input voltage can be appropriately converted to be supplied to the electronic device. In particular, the switched power supply device determines that the electronic device can supply relatively low power (eg, only enough power to maintain the standby circuit) to save power when light or standby.
交換式電源供應裝置在工作電流的需求很小時，一般常會透過降頻或者進入間歇供電模式(burst mode)，來提供電子裝置所需的較低電能。以直接降頻來說，當習知之交換式電源供應裝置偵測電子裝置之狀態為待機狀態時，可降低脈衝寬度調變電路的切換頻率，減少功率開關電路之切換頻率，以節省功率損耗。另一方面，以間歇供電模式來說，交換式電源供應裝置可以在切換信號之工作頻率不變之情形下，控制脈衝寬度調變電路暫停一預設時間，當提供給電子裝置之電能低於一下限時，才重新輸出脈波，使得功率開關電路再次提供電能給電子裝置。Switching power supply devices have low operating current requirements, and typically provide lower power required by the electronic device by down-converting or entering a burst mode. In the case of direct down-conversion, when the state of the conventional switching power supply device detects that the electronic device is in the standby state, the switching frequency of the pulse width modulation circuit can be reduced, and the switching frequency of the power switching circuit can be reduced to save power loss. . On the other hand, in the intermittent power supply mode, the switching power supply device can control the pulse width modulation circuit to pause for a preset time when the operating frequency of the switching signal is constant, and the power supplied to the electronic device is low. At a lower limit, the pulse wave is re-outputted so that the power switch circuit supplies power to the electronic device again.
換句話說，間歇供電模式是將原本的連續脈波分割成連續的脈波群組輸出，使得脈波群組的頻率低於原本脈波的頻率，以減少提供電能給電子裝置。但是，為了進一步減少電子裝置的供電，而將脈波群組的頻率調低至音頻範圍時，反而會產生不悅耳的噪音。In other words, the intermittent power supply mode divides the original continuous pulse into a continuous pulse group output, so that the frequency of the pulse group is lower than the frequency of the original pulse to reduce the supply of power to the electronic device. However, in order to further reduce the power supply of the electronic device, when the frequency of the pulse group is lowered to the audio range, unpleasant noise is generated instead.
由於間歇供電模式乃是業界常用的省電手段，因此業界亟需一種可以解決在間歇供電模式產生噪音的電源供應器，除了可降低電源供應器在輕載時之切換次數以避免電能損失之外，更可進一步地達到免除噪音的問題。Since the intermittent power supply mode is a common power saving method in the industry, there is a need in the industry for a power supply that can generate noise in the intermittent power supply mode, in addition to reducing the number of switching of the power supply at light loads to avoid power loss. It can further achieve the problem of eliminating noise.
本發明提供一種電源供應器，所述電源供應器在間歇供電模式時，不僅可以將原本較高頻率的連續脈波轉換成為較低頻率的連續脈波群組，更可以在脈波群組的頻率落入音頻之前，強制於連續的脈波群組之間加入額外的脈波。因此，所述電源供應器在輕載時，可保持切換頻率始終高於音頻，而不生噪音的問題。The invention provides a power supply device, which can not only convert a continuous pulse wave of a relatively high frequency into a continuous pulse wave group of a lower frequency, but also a group of pulse waves in an intermittent power supply mode. Before the frequency falls into the audio, it is forced to add additional pulses between successive groups of pulses. Therefore, the power supply can keep the switching frequency always higher than the audio at a light load without causing noise.
本發明實施例提供一種電源供應器，用以提供輸出電壓給負載。所述電源供應器包括功率開關電路、負載判斷電路、脈衝寬度調變電路以及控制電路。所述功率開關電路受控於脈衝寬度調變信號，用以轉換輸入電壓成為輸出電壓。負載判斷電路用以判斷負載所乘載的工作電流之數值是否小於第一門限值，據以產生對應的第一指示信號。脈衝寬度調變電路受控於第二指示信號，據以產生脈衝寬度調變信號。控制電路用以接收並轉換第一指示信號成為第二指示信號，其中控制電路具有計時器，計時器累計第一指示信號位於低電壓位準之持續時間，若控制電路判斷持續時間之數值達到第二門限值，則強制輸出至少一電壓脈衝給脈衝寬度調變電路，而第二指示信號係為電壓脈衝與第一指示信號之合成信號。Embodiments of the present invention provide a power supply for providing an output voltage to a load. The power supply includes a power switch circuit, a load determination circuit, a pulse width modulation circuit, and a control circuit. The power switch circuit is controlled by a pulse width modulation signal for converting an input voltage into an output voltage. The load judging circuit is configured to determine whether the value of the operating current carried by the load is less than the first threshold value, thereby generating a corresponding first indication signal. The pulse width modulation circuit is controlled by the second indication signal to generate a pulse width modulation signal. The control circuit is configured to receive and convert the first indication signal into a second indication signal, wherein the control circuit has a timer, and the timer accumulates the duration of the first indication signal at the low voltage level, if the control circuit determines that the duration value reaches the first The second threshold value forcibly outputs at least one voltage pulse to the pulse width modulation circuit, and the second indication signal is a composite signal of the voltage pulse and the first indication signal.
於本發明一示範實施例中，當所述負載判斷電路判斷負載所乘載的工作電流之數值小於第一門限值時，則對應產生之第一指示信號係在低電壓位準與高電壓位準之間進行週期性地切換。此外，若控制電路判斷持續時間之數值未達到第二門限值，則控制電路不產生電壓脈衝，而使得第二指示信號與第一指示信號相同。另一方面，當所述負載判斷電路判斷負載所乘載的工作電流之數值不小於第一門限值時，則對應產生保持在高電壓位準之第一指示信號，並使控制電路不產生電壓脈衝，使得第二指示信號與第一指示信號相同。In an exemplary embodiment of the present invention, when the load determining circuit determines that the value of the operating current loaded by the load is less than the first threshold, the corresponding first indication signal is generated at a low voltage level and a high voltage. The levels are periodically switched between levels. In addition, if the control circuit determines that the value of the duration does not reach the second threshold, the control circuit does not generate a voltage pulse, so that the second indication signal is identical to the first indication signal. On the other hand, when the load judging circuit judges that the value of the operating current loaded by the load is not less than the first threshold value, the first indication signal that is maintained at the high voltage level is generated correspondingly, and the control circuit is not generated. The voltage pulse is such that the second indication signal is identical to the first indication signal.
綜上所述，本發明提供之電源供應器在間歇供電模式時，可計算第一指示信號中的脈波群組時間間距，當第一指示信號持續在低電壓位準的時間過長，可以強制於第一指示信號中加入電壓脈衝，使得提供給脈衝寬度調變電路的第二指示信號的頻率升高。因此，本發明提供之電源供應器在輕載時，可保持脈衝寬度調變電路的切換頻率始終高於音頻，而不生噪音的問題。In summary, the power supply provided by the present invention can calculate the pulse group time interval in the first indication signal when the power supply mode is intermittent, and the time when the first indication signal continues to be at the low voltage level is too long. A voltage pulse is forcibly added to the first indication signal such that the frequency of the second indication signal supplied to the pulse width modulation circuit is increased. Therefore, the power supply provided by the present invention can keep the switching frequency of the pulse width modulation circuit always higher than the audio at the time of light load without causing noise.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉本發明之較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;
[電源供應器之實施例][Embodiment of Power Supply]
請參見圖1，圖1係繪示依據本發明一實施例之電源供應器之方塊圖。如圖1所示，本實施例之電源供應器1具有功率開關電路10、負載判斷電路12、脈衝寬度調變電路14以及控制電路16。在此，功率開關電路10分別耦接脈衝寬度調變電路14以及負載(未繪示於圖式)，負載判斷電路12分別耦接負載以及控制電路16，而脈衝寬度調變電路14以及控制電路16互相連接。以下分別就電源供應器1的各部元件做詳細的說明。Please refer to FIG. 1. FIG. 1 is a block diagram of a power supply according to an embodiment of the present invention. As shown in FIG. 1, the power supply 1 of the present embodiment has a power switching circuit 10, a load judging circuit 12, a pulse width modulation circuit 14, and a control circuit 16. Here, the power switch circuit 10 is coupled to the pulse width modulation circuit 14 and the load (not shown), the load determination circuit 12 is coupled to the load and control circuit 16, respectively, and the pulse width modulation circuit 14 and The control circuits 16 are connected to each other. The components of the power supply 1 will be described in detail below.
功率開關電路10受控於脈衝寬度調變電路14產生的脈衝寬度調變信號，用以轉換輸入電壓Vin成為輸出電壓Vout。於實務上，功率開關電路10係為一個場效電晶體，而脈衝寬度調變信號係為場效電晶體的閘極信號。在此，功率開關電路10可在脈衝寬度調變信號位於高電壓位準時，將其輸入端接收的輸入電壓Vin轉換成輸出端送出的輸出電壓Vout。在脈衝寬度調變信號位於低電壓位準時，功率開關電路10即可停止送出輸出電壓Vout。The power switching circuit 10 is controlled by a pulse width modulation signal generated by the pulse width modulation circuit 14 for converting the input voltage Vin into an output voltage Vout. In practice, the power switch circuit 10 is a field effect transistor, and the pulse width modulation signal is the gate signal of the field effect transistor. Here, the power switch circuit 10 can convert the input voltage Vin received at its input terminal into the output voltage Vout sent from the output terminal when the pulse width modulation signal is at a high voltage level. When the pulse width modulation signal is at the low voltage level, the power switching circuit 10 can stop sending the output voltage Vout.
以實際電路上的例子來說，功率開關電路10的輸入端可耦接於功率因數校正(power factor correction，PFC)電路的輸出端，而功率開關電路10的輸出端在連接到負載之前，更可具有整流器、濾波器等電路元件，使得本實施例之電源供應器1輸出給負載的電壓更穩定。換句話說，本實施例所述之功率開關電路10可以是一個功率級(power stage)電路中的一個主要元件，所述功率級電路可以搭配有其他的電路元件。當然，本發明在此並不限制功率開關電路10的實施方式或者功率開關電路10搭配的電路元件，於所屬技術領域具有通常知識者可以視需要而做適當的設計。In an actual circuit example, the input of the power switch circuit 10 can be coupled to the output of a power factor correction (PFC) circuit, and the output of the power switch circuit 10 is connected to the load, Circuit elements such as rectifiers and filters may be provided, so that the voltage outputted to the load by the power supply 1 of the present embodiment is more stable. In other words, the power switch circuit 10 of the present embodiment can be a main component in a power stage circuit, and the power stage circuit can be matched with other circuit components. Of course, the present invention does not limit the implementation of the power switching circuit 10 or the circuit components of the power switching circuit 10, and those skilled in the art can make appropriate designs as needed.
負載判斷電路12用以判斷負載所乘載的工作電流之數值是否小於第一門限值，據以產生對應的第一指示信號。舉例來說，負載判斷電路12可藉由負載所乘載的工作電流判斷負載的使用狀態。一般來說，當負載在待機或者是輕載狀態時，工作電流相對較小，而當負載在重載狀態時，工作電流相對較大。於實務上，第一門限值是用來輔助負載判斷電路12判斷工作電流究竟屬於大或小，使用者可以依據不同的負載自行設定合適的第一門限值，本發明在此不加以限制。此外，負載判斷電路12更可以在所述工作電流產生對應的電壓之後，再行判斷負載所乘載的工作電流對應產生的電壓之數值是否小於第一門限值。也就是說，所述工作電流可以經過電阻或其他阻抗轉換成電壓的形式，負載判斷電路12再由工作電流對應產生的電壓，來判斷負載屬於待機或者輕載狀態。The load determining circuit 12 is configured to determine whether the value of the operating current carried by the load is less than the first threshold value, thereby generating a corresponding first indication signal. For example, the load judging circuit 12 can judge the use state of the load by the operating current loaded by the load. Generally speaking, when the load is in the standby or light load state, the operating current is relatively small, and when the load is in the heavy load state, the operating current is relatively large. In practice, the first threshold is used to assist the load judging circuit 12 to determine whether the operating current is large or small. The user can set a suitable first threshold according to different loads, and the present invention does not limit the present invention. . In addition, the load judging circuit 12 may further determine whether the value of the voltage corresponding to the operating current loaded by the load is less than the first threshold value after the corresponding current is generated by the operating current. That is to say, the operating current can be converted into a voltage form by a resistor or other impedance, and the load judging circuit 12 determines whether the load belongs to a standby or light load state by a voltage corresponding to the operating current.
當負載判斷電路12判斷負載在待機或輕載狀態時，所輸出的第一指示信號會在低電壓位準與高電壓位準之間進行週期性地切換，使得本實施例之電源供應器1進入間歇供電模式。另一方面，當負載判斷電路12判斷負載在重載狀態時，所輸出的第一指示信號則持續在高電壓位準，即不會進入間歇供電模式。換句話說，負載判斷電路12係可為一種回授級(feedback stage)電路，其可依據負載上的工作電流判斷負載的使用狀態，並即時地決定本實施例之電源供應器1是否進入間歇供電模式。When the load judging circuit 12 judges that the load is in the standby or light load state, the outputted first indication signal is periodically switched between the low voltage level and the high voltage level, so that the power supply 1 of the embodiment Enter the intermittent power mode. On the other hand, when the load judging circuit 12 judges that the load is in the heavy load state, the output first indication signal continues at the high voltage level, that is, does not enter the intermittent power supply mode. In other words, the load judging circuit 12 can be a feedback stage circuit that can judge the use state of the load according to the operating current on the load, and instantly determine whether the power supply 1 of the embodiment enters the interval. Power mode.
請繼續參見圖1，脈衝寬度調變電路14受控於第二指示信號，據以產生控制功率開關電路10的脈衝寬度調變信號。在此，所述第二指示信號係為控制電路16所輸出的，可以視為控制電路16適當地調整過第一指示信號而產生的結果。所述脈衝寬度調變信號是用來控制功率開關電路10的導通與否，於所屬技術領域具有通常知識者應可輕易的明白脈衝寬度調變電路14的實做方式，本實施例在此不加以贅述。With continued reference to FIG. 1, the pulse width modulation circuit 14 is controlled by a second indication signal to generate a pulse width modulation signal that controls the power switching circuit 10. Here, the second indication signal is output by the control circuit 16, and can be regarded as a result of the control circuit 16 appropriately adjusting the first indication signal. The pulse width modulation signal is used to control the conduction of the power switching circuit 10. The general knowledge of the pulse width modulation circuit 14 can be easily understood by those skilled in the art. This embodiment is here. Do not repeat them.
控制電路16用以接收並轉換第一指示信號成為第二指示信號。特別是，其中控制電路可具有計時器(未繪示於圖1)，所述計時器累計第一指示信號位於低電壓位準之持續時間，若控制電路16判斷持續時間之數值達到第二門限值，則強制輸出至少一電壓脈衝給脈衝寬度調變電路14，使得第二指示信號實際上可為電壓脈衝與第一指示信號之合成信號。於實務上，當負載判斷電路12判斷負載是重載時，負載判斷電路12所輸出的第一指示信號始終保持在高電壓位準，因此控制電路16的計時器不會啟動，也不會輸出任何的電壓脈衝給脈衝寬度調變電路14。也就是說，在負載是重載時，控制電路16並未啟動調整第一指示信號的機制，故第一指示信號與第二指示信號實際上是一樣的信號。The control circuit 16 is configured to receive and convert the first indication signal into a second indication signal. In particular, wherein the control circuit can have a timer (not shown in FIG. 1), the timer accumulates the duration of the first indication signal at a low voltage level, and if the control circuit 16 determines that the duration value reaches the second gate The limit value forcibly outputs at least one voltage pulse to the pulse width modulation circuit 14, so that the second indication signal may actually be a composite signal of the voltage pulse and the first indication signal. In practice, when the load judging circuit 12 judges that the load is a heavy load, the first indication signal output by the load judging circuit 12 is always maintained at a high voltage level, so the timer of the control circuit 16 does not start and does not output. Any voltage pulse is applied to the pulse width modulation circuit 14. That is to say, when the load is a heavy load, the control circuit 16 does not initiate the mechanism for adjusting the first indication signal, so the first indication signal and the second indication signal are actually the same signal.
另一方面，在負載的狀態在待機或輕載時，由於負載判斷電路12所輸出的第一指示信號會在低電壓位準與高電壓位準之間進行週期性地切換，控制電路16的計時器便會在第一指示信號為低電壓位準時啟動，而開始計算第一指示信號位於低電壓位準之持續時間。若計時器判斷持續時間過久，則控制電路16才會輸出電壓脈衝給脈衝寬度調變電路14，並在輸出電壓脈衝後重新計算所述持續時間。請注意，本實施例的計時器並不是在啟動之後一定會促使控制電路16產生電壓脈衝。在此，若所述持續時間之數值未達到第二門限值，而第一指示信號即切換回高電壓位準時，計時器便會結束這次的計算並將所述持續時間歸零，待下一次第一指示信號位於低電壓位準時，再次計算新的持續時間。On the other hand, when the state of the load is in standby or light load, since the first indication signal outputted by the load judging circuit 12 is periodically switched between the low voltage level and the high voltage level, the control circuit 16 The timer is started when the first indication signal is at a low voltage level, and begins to calculate the duration during which the first indication signal is at a low voltage level. If the timer determines that the duration is too long, the control circuit 16 outputs a voltage pulse to the pulse width modulation circuit 14, and recalculates the duration after the voltage pulse is output. Please note that the timer of this embodiment does not necessarily cause the control circuit 16 to generate a voltage pulse after startup. Here, if the value of the duration does not reach the second threshold, and the first indication signal is switched back to the high voltage level, the timer ends the calculation and zeros the duration. When the first indication signal is at the low voltage level, the new duration is calculated again.
以實際例子來說，當所述持續時間的單位是微秒的時候，所述第二門限值可以被對應在40到60之間。也就是說，當持續時間達到40微秒(μs)到60微秒之間時，控制電路16便強制輸出電壓脈衝給脈衝寬度調變電路14。特別是，持續時間達到恰好50微秒(也就是所述第二門限值對應在50)時，控制電路16便強制輸出電壓脈衝給脈衝寬度調變電路14。舉例來說，由於正常人可以聽見大約在20到20000赫茲範圍內的頻率，若所述持續時間長於50微秒時，則此信號的頻率將會落入20000赫茲之內，因而產生可被聽到的噪音。然而，本實施例的控制電路16可在所述持續時間恰好達到50微秒時，即時產生電壓脈衝，相當於將信號頻率擋在20000赫茲左右，不使其向下落入人的聽覺頻率中，顯見本實施例之電源供應器1有防止噪音的功效。In a practical example, when the unit of duration is microseconds, the second threshold may be corresponding between 40 and 60. That is, when the duration reaches between 40 microseconds (μs) and 60 microseconds, the control circuit 16 forces the output voltage pulse to the pulse width modulation circuit 14. In particular, the control circuit 16 forces the output voltage pulse to the pulse width modulation circuit 14 when the duration reaches exactly 50 microseconds (i.e., the second threshold corresponds to 50). For example, since a normal person can hear a frequency in the range of about 20 to 20,000 Hz, if the duration is longer than 50 microseconds, the frequency of this signal will fall within 20,000 Hz, thus producing audible The noise. However, the control circuit 16 of the present embodiment can generate a voltage pulse immediately when the duration is exactly 50 microseconds, which is equivalent to blocking the signal frequency at about 20,000 Hz, so that it does not fall into the human auditory frequency. It is apparent that the power supply 1 of the present embodiment has an effect of preventing noise.
當然，由於每個人的聽覺頻率上限並不是固定數值(例如有些人可以聽到的頻率上限較高，而有些人較低)，因此本實施例並不限定第二門限值僅對應到50微秒，而是可以選自一個區間範圍(例如40微秒到60微秒之間)中的數值。於所屬技術領域具有通常知識者可以視需要而適當的設計第二門限值的數值。Of course, since the upper limit of the auditory frequency of each person is not a fixed value (for example, the upper limit of the frequency that some people can hear is higher, and some people are lower), the embodiment does not limit the second threshold to only correspond to 50 microseconds. Instead, it can be selected from values in a range of intervals (eg, between 40 microseconds and 60 microseconds). Those having ordinary skill in the art can appropriately design values of the second threshold value as needed.
為了更詳細說明本發明之內容，請繼續參見圖2A、圖2B與圖2C。圖2A係繪示依據本發明一實施例之電源供應器之電路示意圖，圖2B說明間歇供電模式下的訊號波形，而圖2C係繪示依據本發明一實施例之第一指示信號與第二指示信號之波形圖。請注意，雖然本發明繪示了如圖2A所示的電路圖，但圖2A只是用以作為一實施的態樣，並不代表本發明所有電路結構僅限制在圖2A的內容。如圖所示，功率開關電路10可以透過一電感L自前級電路(例如功率因數校正電路)接收輸入電壓Vin後，再經由整流二極體D1與電容C1耦接負載RLoad，使得負載接收輸出電壓Vout且具有工作電流ILoad。In order to explain the contents of the present invention in more detail, please continue to refer to FIGS. 2A, 2B and 2C. 2A is a schematic circuit diagram of a power supply according to an embodiment of the invention, FIG. 2B illustrates a signal waveform in an intermittent power supply mode, and FIG. 2C illustrates a first indication signal and a second according to an embodiment of the invention. A waveform diagram of the indication signal. It should be noted that although the present invention is shown in FIG. 2A, FIG. 2A is only used as an embodiment, and does not mean that all circuit configurations of the present invention are limited only to the contents of FIG. 2A. As shown in the figure, the power switch circuit 10 can receive the input voltage Vin from the pre-stage circuit (for example, the power factor correction circuit) through an inductor L, and then couple the load R Load to the load C1 via the rectifying diode D1 and the capacitor C1, so that the load receives the output. The voltage Vout has an operating current I Load .
由圖2A可知，負載判斷電路12更可具有回授電路122以及比較電路124。於所述回授電路122中，主要是利用電阻R1與R2感測負載的使用狀態，接著感測結果Vfb饋入誤差放大器OTA與一參考電壓值Vref做比較，誤差放大器OTA產生的輸出結果為電壓Vcomp。此外，補償電路(包含電阻Rc與電容Cc)可耦接在誤差放大器OTA的輸出端，使得誤差放大器OTA輸出的電壓Vcomp可饋入比較電路124與對應指示第一門限值之電壓Vburst做比較。As can be seen from FIG. 2A, the load determination circuit 12 can further have a feedback circuit 122 and a comparison circuit 124. In the feedback circuit 122, the use state of the load is mainly sensed by the resistors R1 and R2, and then the sensing result Vfb is fed into the error amplifier OTA and compared with a reference voltage value Vref, and the output result of the error amplifier OTA is Voltage Vcomp. In addition, the compensation circuit (including the resistor Rc and the capacitor Cc) can be coupled to the output of the error amplifier OTA such that the voltage Vcomp output by the error amplifier OTA can be fed to the comparison circuit 124 to be compared with the voltage Vburst corresponding to the first threshold value. .
於實務上，當負載RLoad的工作電流ILoad較大時，對應產生的電壓Vcomp較高，在已取得適當的對應指示第一門限值之電壓Vburst的情況下，即可判斷電壓Vcomp大於(或不小於)電壓Vburst，也就是負載處在重載狀態。此時，比較電路124輸出的比較結果(也就是第一指示信號Vgroup)可持續在高電壓位準。相反的，當負載RLoad的工作電流ILoad較小時，對應產生的電壓Vcomp較低，在已取得適當的電壓Vburst的情況下，即可判斷電壓Vcomp小於電壓Vburst，也就是負載處在輕載狀態。此時，第一指示信號Vgroup便會在低電壓位準與高電壓位準之間進行週期性地切換，而進入間歇供電模式。In practice, when the operating current I Load of the load R Load is large, the corresponding generated voltage Vcomp is high. When the appropriate voltage Vburst corresponding to the first threshold value has been obtained, the voltage Vcomp can be determined to be greater than (or not less than) the voltage Vburst, that is, the load is in a heavy load state. At this time, the comparison result output by the comparison circuit 124 (that is, the first indication signal Vgroup) can be maintained at a high voltage level. Conversely, when the operating current I Load of the load R Load is small, the corresponding generated voltage Vcomp is low. When the appropriate voltage Vburst has been obtained, it can be judged that the voltage Vcomp is smaller than the voltage Vburst, that is, the load is light. Load status. At this time, the first indication signal Vgroup periodically switches between the low voltage level and the high voltage level, and enters the intermittent power supply mode.
請繼續參見圖2A，脈衝寬度調變電路14至少具有一閂鎖器142與一震盪器144，震盪器144耦接控制電路16，閂鎖器142耦接於震盪器144與功率開關電路10之間，震盪器144用以接收並轉換第二指示信號Vgroup1成震盪信號fosc，而閂鎖器142至少根據震盪信號144產生脈衝寬度調變信號Vgate以控制功率開關電路10。在此，脈衝寬度調變電路14又可以包括斜率補償電路146以及比較器comp2等元件，而與傳統的脈衝寬度調變電路不同之處在於，所述震盪信號fosc更可反饋至控制電路16控制電壓脈衝的產生過程。2A, the pulse width modulation circuit 14 has at least one latch 142 and an oscillator 144. The oscillator 144 is coupled to the control circuit 16. The latch 142 is coupled to the oscillator 144 and the power switch circuit 10. The oscillator 144 is configured to receive and convert the second indication signal Vgroup1 into an oscillating signal fosc, and the latch 142 generates a pulse width modulation signal Vgate according to at least the oscillating signal 144 to control the power switching circuit 10. Here, the pulse width modulation circuit 14 may further include components such as the slope compensation circuit 146 and the comparator comp2, and is different from the conventional pulse width modulation circuit in that the oscillation signal fosc is more feedbackable to the control circuit. 16 control voltage pulse generation process.
請一併參見圖2A與圖2B，圖2B係繪示依據本發明一實施例之電源供應器於間歇供電模式下的訊號波形圖。在此，圖2A中繪示的比較器comp1於實務上可以是一遲滯比較器，而電壓Vburst實際上可以是一個數值或是一個範圍，其中所述範圍的下限係以電壓Vburst-表示，且所述範圍的上限係以電壓Vburst+表示。當負載RLoad的工作電流ILoad變小時，誤差放大器輸出電壓Vcomp會隨著工作電流ILoad變低。假使電壓Vcomp小於電壓Vburst-，則比較器comp1輸出的第一指示信號Vgroup會從高電壓位準變成低電壓位準，並使得脈衝寬度調變信號Vgate停止切換。當Vgate停止切換時，Vout電壓會慢慢下降，Vfb就會降低，誤差放大器的輸出電壓Vcomp上升，假使Vcomp電壓上升大於Vburst+，比較器comp1輸出Vgroup會從低電壓位準變成高電壓位準，脈衝寬度調變信號Vgate開始切換。當Vgate持續切換，Vout電壓會慢慢上升，Vfb就會上升，誤差放大器的輸出電壓Vcomp下降，等到Vcomp小於電壓Vburst-，則比較器comp1輸出的第一指示信號Vgroup會從高電壓位準變成低電壓位準。這個過程反覆持續下去，使得Vgroup在低電壓位準和高電壓位準之間切換。Please refer to FIG. 2A and FIG. 2B together. FIG. 2B is a diagram showing signal waveforms of the power supply in the intermittent power supply mode according to an embodiment of the invention. Here, the comparator comp1 illustrated in FIG. 2A may be a hysteresis comparator in practice, and the voltage Vburst may actually be a value or a range, wherein the lower limit of the range is represented by a voltage Vburst-, and The upper limit of the range is represented by the voltage Vburst+. When the operating current I Load of the load R Load becomes small, the error amplifier output voltage Vcomp becomes lower as the operating current I Load . If the voltage Vcomp is less than the voltage Vburst-, the first indication signal Vgroup output by the comparator comp1 will change from the high voltage level to the low voltage level, and the pulse width modulation signal Vgate will stop switching. When Vgate stops switching, the Vout voltage will slowly drop, Vfb will decrease, and the output voltage Vcomp of the error amplifier will rise. If the Vcomp voltage rises above Vburst+, the comparator comp1 output Vgroup will change from the low voltage level to the high voltage level. The pulse width modulation signal Vgate starts switching. When Vgate continues to switch, Vout voltage will rise slowly, Vfb will rise, and the output voltage Vcomp of the error amplifier will drop. When Vcomp is less than voltage Vburst-, the first indication signal Vgroup output by comparator comp1 will change from high voltage level. Low voltage level. This process continues incessantly, causing the Vgroup to switch between low voltage levels and high voltage levels.
從圖2C來看，由於第一指示信號Vgroup會在低電壓位準與高電壓位準之間進行週期性地切換，控制電路16中的計時器主要是用來偵測第一指示信號Vgroup在低電壓位準的持續時間T1，當持續時間T1未達到第二門限值時，控制電路16是不會動作的。然而，如果負載RLoad的工作電流ILoad太小，第一指示信號Vgroup會在低電壓準位維持較久的時間，一旦持續時間T1過長，將會使得脈衝寬度調變信號Vgate進入音頻產生噪音。換句話說，若持續時間T1超過了第二門限值之時間T2的界限時，控制電路16便會在第一指示信號Vgroup中強制加入電壓脈衝，使得控制電路16輸出的第二指示信號Vgroup1，與原本的第一指示信號Vgroup略有不同。本發明在此不限制電壓脈衝的數量，於所屬技術領域具有通常知識者可以自行設定。As seen from FIG. 2C, since the first indication signal Vgroup is periodically switched between the low voltage level and the high voltage level, the timer in the control circuit 16 is mainly used to detect the first indication signal Vgroup. The duration T1 of the low voltage level, when the duration T1 does not reach the second threshold, the control circuit 16 does not operate. However, if the operating current I Load of the load R Load is too small, the first indication signal Vgroup will remain at a low voltage level for a long time. Once the duration T1 is too long, the pulse width modulation signal Vgate will enter the audio generation. noise. In other words, if the duration T1 exceeds the limit of the time T2 of the second threshold, the control circuit 16 forcibly adds a voltage pulse to the first indication signal Vgroup, so that the second indication signal Vgroup1 output by the control circuit 16 It is slightly different from the original first indication signal Vgroup. The invention does not limit the number of voltage pulses here, and can be set by one of ordinary skill in the art.
針對控制電路16的部分，為了使所屬技術領域具有通常知識者更清楚明瞭其一種實施的例子，請繼續參見圖3A與圖3B。圖3A係繪示依據本發明一實施例之控制電路於重載時之電路示意圖，而圖3B係繪示依據本發明一實施例之控制電路於輕載時之電路示意圖。For the portion of the control circuit 16, in order to make the example of one implementation more clear to those skilled in the art, please continue to refer to Figures 3A and 3B. 3A is a schematic diagram of a circuit of a control circuit during heavy load according to an embodiment of the invention, and FIG. 3B is a schematic diagram of a circuit of the control circuit at light load according to an embodiment of the invention.
如圖3A所示，當電壓Vcomp大於(或不小於)第一門限值Vburst時，第一指示信號Vgroup會保持在高電壓位準(在此以1表示)。此時，由於計時器162中的電晶體M1導通，使得電容C2不處在充電狀態(即電壓Vcap無法提高)，而電壓Vcap小於計時電壓VR。因此，於所屬技術領域具有通常知識者可看出第二指示信號Vgroup1與第一指示信號Vgroup並無不同，實質上都是保持在高電壓位準。As shown in FIG. 3A, when the voltage Vcomp is greater than (or not less than) the first threshold value Vburst, the first indication signal Vgroup will remain at a high voltage level (here denoted by 1). At this time, since the transistor M1 in the timer 162 is turned on, the capacitor C2 is not in the charging state (ie, the voltage Vcap cannot be increased), and the voltage Vcap is less than the timing voltage VR. Therefore, those skilled in the art can see that the second indication signal Vgroup1 is not different from the first indication signal Vgroup, and is substantially maintained at a high voltage level.
另一方面，如圖3B所示，當電壓Vcomp小於第一門限值Vburst時，第一指示信號Vgroup一開始是會保持在低電壓位準(在此以0表示)，同時震盪信號fosc初始也應在低電壓位準。此時，由於計時器162中的電晶體M1截止，使得電流源對電容C2持續充電，進而讓電壓Vcap提高。在此，由於電流源的電流值以及電容C2的電容值是使用者可以預先設計的，當然可以計算推估電壓Vcap達到計時電壓VR的時間。如前所述，電壓Vcap達到計時電壓VR的時間應被設定約莫在50微秒左右。於所屬技術領域具有通常知識者可知，電壓Vcap達到計時電壓VR的時間並不僅僅與計時電壓VR的大小有關，更與電流源的電流值以及電容C2的電容值相關。On the other hand, as shown in FIG. 3B, when the voltage Vcomp is less than the first threshold value Vburst, the first indication signal Vgroup will initially remain at a low voltage level (here denoted by 0), and the initial oscillation signal fosc It should also be at a low voltage level. At this time, since the transistor M1 in the timer 162 is turned off, the current source continuously charges the capacitor C2, thereby increasing the voltage Vcap. Here, since the current value of the current source and the capacitance value of the capacitor C2 can be pre-designed by the user, it is of course possible to calculate the time during which the estimated voltage Vcap reaches the timing voltage VR. As previously mentioned, the time at which the voltage Vcap reaches the timing voltage VR should be set at about 50 microseconds. It is known to those skilled in the art that the time at which the voltage Vcap reaches the timing voltage VR is not only related to the magnitude of the timing voltage VR, but also to the current value of the current source and the capacitance value of the capacitor C2.
本發明在此並不限制使用者應調整計時電壓VR的大小、電流源的電流值或是電容C2的電容值，只要計時器162在50微秒左右可以被觸發一次，即符合本發明所稱之計時器162的精神。當然，本發明同樣不限制計時器162的實施方式，圖3A與圖3B僅僅做為一個可能的例子，而不是用以限制本案的權利範圍。The invention does not limit the user to adjust the magnitude of the timing voltage VR, the current value of the current source or the capacitance value of the capacitor C2, as long as the timer 162 can be triggered once in about 50 microseconds, that is, according to the invention. The spirit of the timer 162. Of course, the present invention also does not limit the implementation of the timer 162. Figures 3A and 3B are only one possible example and are not intended to limit the scope of the present invention.
承接上述，當電壓Vcap達到計時電壓VR後，計時器162的輸出電壓便會被切換成高電壓位準(也就是0變成1)，而控制電路16的閂鎖器的R(reset)便會被觸發，使得原本在低電壓位準的第二指示信號Vgroup1被切換成高電壓位準。然而，當圖2A中的震盪器144接收了高電壓位準的第二指示信號Vgroup1後，便會對應開始產生震盪信號fosc。因此回到圖3B，當震盪信號fosc變成高電壓位準後，電晶體M1再次被導通，使得電容C2停止充電狀態(即電壓Vcap釋放歸零)，進而使第二指示信號Vgroup1轉回低電壓位準並停止震盪信號fosc，也就是重新進入下一個持續時間的計算過程。In response to the above, when the voltage Vcap reaches the timing voltage VR, the output voltage of the timer 162 is switched to the high voltage level (that is, 0 becomes 1), and the R (reset) of the latch of the control circuit 16 is Triggered so that the second indication signal Vgroup1 originally at the low voltage level is switched to a high voltage level. However, when the oscillator 144 in FIG. 2A receives the second indication signal Vgroup1 of the high voltage level, the oscillation signal fosc is started to be generated correspondingly. Therefore, returning to FIG. 3B, after the oscillating signal fosc becomes a high voltage level, the transistor M1 is turned on again, so that the capacitor C2 stops charging (ie, the voltage Vcap is released to zero), thereby turning the second indication signal Vgroup1 back to the low voltage. The level stops and stops the oscillating signal fosc, which is the process of re-entering the next duration.
從信號的角度來說，請參見圖4，圖4係繪示依據本發明一實施例之信號波形圖。由圖4可看出，當電壓Vcomp仍高於第一門限值Vburst時，第一指示信號Vgroup與第二指示信號Vgroup1並無差異。當電壓Vcomp小於第一門限值Vburst時，電壓Vcap便開始逐漸升高，待電壓Vcap達到計時電壓VR時，控制電路16觸發了一個電壓脈衝。藉此，使得第二指示信號Vgroup1的頻率向上提升，避免第二指示信號Vgroup1控制的脈衝寬度調變電路14產生落入音頻的脈衝寬度調變信號Vgate。另外，從圖4中亦可看出，控制電路16輸出的第二指示信號Vgroup1相當於在第一指示信號Vgroup中加入一個電壓脈衝，也就是第二指示信號Vgroup1相當於電壓脈衝與第一指示信號Vgroup之合成信號。From a signal point of view, please refer to FIG. 4. FIG. 4 is a diagram showing signal waveforms according to an embodiment of the present invention. As can be seen from FIG. 4, when the voltage Vcomp is still higher than the first threshold value Vburst, the first indication signal Vgroup has no difference from the second indication signal Vgroup1. When the voltage Vcomp is less than the first threshold value Vburst, the voltage Vcap begins to gradually increase. When the voltage Vcap reaches the timing voltage VR, the control circuit 16 triggers a voltage pulse. Thereby, the frequency of the second indication signal Vgroup1 is raised upward, and the pulse width modulation circuit 14 controlled by the second indication signal Vgroup1 is prevented from generating the pulse width modulation signal Vgate falling into the audio. In addition, as can be seen from FIG. 4, the second indication signal Vgroup1 output by the control circuit 16 is equivalent to adding a voltage pulse to the first indication signal Vgroup, that is, the second indication signal Vgroup1 is equivalent to the voltage pulse and the first indication. The composite signal of the signal Vgroup.
綜上所述，本發明實施例提供的電源供應器在間歇供電模式時，可計算第一指示信號在低電壓位準的時間，當第一指示信號持續在低電壓位準的時間過長，可以先將控制電路輸出的第二指示信號強制切換成高電壓位準，再切換回低電壓位準。相當於強制輸出一個電壓脈衝，使得提供給脈衝寬度調變電路的第二指示信號的頻率升高。因此，本發明提供之電源供應器在輕載時，可保持脈衝寬度調變電路的切換頻率始終高於音頻，而不生噪音的問題。In summary, the power supply provided by the embodiment of the present invention can calculate the time when the first indication signal is at the low voltage level in the intermittent power supply mode, and the time when the first indication signal continues to be at the low voltage level is too long. The second indication signal outputted by the control circuit can be forcibly switched to a high voltage level, and then switched back to the low voltage level. Equivalent to forcibly outputting a voltage pulse such that the frequency of the second indication signal supplied to the pulse width modulation circuit rises. Therefore, the power supply provided by the present invention can keep the switching frequency of the pulse width modulation circuit always higher than the audio at the time of light load without causing noise.
以上所述僅為本發明之實施例，其並非用以侷限本發明之專利範圍。The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.
1．．．電源供應器1. . . Power Supplier
10．．．功率開關電路10. . . Power switch circuit
12．．．負載判斷電路12. . . Load judgment circuit
14．．．脈衝寬度調變電路14. . . Pulse width modulation circuit
16．．．控制電路16. . . Control circuit
122．．．回授電路122. . . Feedback circuit
124．．．比較電路124. . . Comparison circuit
142．．．閂鎖器142. . . Latch
144．．．震盪器144. . . Oscillator
146．．．斜率補償電路146. . . Slope compensation circuit
L．．．電感L. . . inductance
D1．．．整流二極體D1. . . Rectifier diode
RLoad．．．負載R Load . . . load
ILoad．．．工作電流I Load . . . Working current
R1、R2、Rc．．．電阻R1, R2, Rc. . . resistance
C1、C2、Cc．．．電容C1, C2, Cc. . . capacitance
comp1、comp2．．．比較器Comp1, comp2. . . Comparators
OTA．．．誤差放大器OTA. . . Error amplifier
M1．．．電晶體M1. . . Transistor
Vin、Vout、Vfb、Vref、Vcomp、Vgate．．．電壓Vin, Vout, Vfb, Vref, Vcomp, Vgate. . . Voltage
Vgroup、Vgroup1、Vcap、VR、fosc．．．電壓Vgroup, Vgroup1, Vcap, VR, fosc. . . Voltage
圖1係繪示依據本發明一實施例之電源供應器之方塊圖。1 is a block diagram of a power supply in accordance with an embodiment of the present invention.
圖2A係繪示依據本發明一實施例之電源供應器之電路示意圖。2A is a circuit diagram of a power supply according to an embodiment of the invention.
圖2B係繪示依據本發明一實施例之電源供應器於間歇供電模式下的訊號波形圖。2B is a diagram showing signal waveforms of a power supply in an intermittent power supply mode according to an embodiment of the invention.
圖2C係繪示依據本發明一實施例之第一指示信號與第二指示信號之波形圖。2C is a waveform diagram of a first indication signal and a second indication signal according to an embodiment of the invention.
圖3A係繪示依據本發明一實施例之控制電路於重載時之電路示意圖。FIG. 3A is a schematic diagram of a circuit of a control circuit under heavy load according to an embodiment of the invention.
圖3B係繪示依據本發明一實施例之控制電路於輕載時之電路示意圖。FIG. 3B is a schematic diagram of a circuit of a control circuit at light load according to an embodiment of the invention.
圖4係繪示依據本發明一實施例之信號波形圖。4 is a diagram showing signal waveforms in accordance with an embodiment of the present invention.
1．．．電源供應器1. . . Power Supplier
10．．．功率開關電路10. . . Power switch circuit
12．．．負載判斷電路12. . . Load judgment circuit
14．．．脈衝寬度調變電路14. . . Pulse width modulation circuit
16．．．控制電路16. . . Control circuit
Vin、Vout．．．電壓Vin, Vout. . . Voltage
Claims (8)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100142890A TWI434502B (en) | 2011-11-23 | 2011-11-23 | Power supply |
| CN201110396548.9A CN103138593B (en) | 2011-11-23 | 2011-11-29 | Power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100142890A TWI434502B (en) | 2011-11-23 | 2011-11-23 | Power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201322610A true TW201322610A (en) | 2013-06-01 |
| TWI434502B TWI434502B (en) | 2014-04-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100142890A TWI434502B (en) | 2011-11-23 | 2011-11-23 | Power supply |
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| Country | Link |
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| CN (1) | CN103138593B (en) |
| TW (1) | TWI434502B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI662789B (en) * | 2018-11-19 | 2019-06-11 | 國家中山科學研究院 | Pressure switch filter |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106208620A (en) * | 2015-04-29 | 2016-12-07 | 群光电能科技股份有限公司 | Pulse interval mode power Supply Method and pulse interval mode power feeding mechanism |
| CN106208671A (en) * | 2015-04-29 | 2016-12-07 | 群光电能科技股份有限公司 | Avoid power supply method and the power supply device of audio frequency noise |
| CN113556028B (en) * | 2021-08-10 | 2022-10-28 | 上海壁仞智能科技有限公司 | Ripple voltage control method, ripple voltage control system, electronic device, and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW523225U (en) * | 2002-02-08 | 2003-03-01 | Richtek Technology Corp | Pulse width modulation circuit |
| TWI275232B (en) * | 2002-04-25 | 2007-03-01 | Quanta Comp Inc | Dual frequency pulse-width-modulation voltage regulation device |
| US9148060B2 (en) * | 2008-03-03 | 2015-09-29 | System General Corp. | Switching controller with burst mode management circuit to reduce power loss and acoustic noise of power converter |
| CN101667782B (en) * | 2009-09-01 | 2011-09-28 | 成都芯源***有限公司 | Switching power supply and control method thereof |
-
2011
- 2011-11-23 TW TW100142890A patent/TWI434502B/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI662789B (en) * | 2018-11-19 | 2019-06-11 | 國家中山科學研究院 | Pressure switch filter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103138593A (en) | 2013-06-05 |
| TWI434502B (en) | 2014-04-11 |
| CN103138593B (en) | 2015-04-22 |
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