TW201322577A - Power switching circuit and power switch method thereof - Google Patents
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本發明係關於一種電源切換電路，特別是關於一種防止瞬間湧入電流之電源切換電路。The present invention relates to a power switching circuit, and more particularly to a power switching circuit that prevents instantaneous inrush current.
近年來科技發展迅速，電子產品的種類及產量也隨之而越來越多，如筆記型電腦、無線分享器、PDA、數位相機以及行動電話等，在多數之電子產品或系統單晶片(system on chip；SOC)之設計中，為有效使用電源，雙電源設計(dual power)普遍應用於各種電子設備中。In recent years, technology has developed rapidly, and the variety and output of electronic products have also increased, such as notebook computers, wireless sharing devices, PDAs, digital cameras, and mobile phones. In most electronic products or system single-chip (system) In the design of on chip; SOC), in order to effectively use the power supply, dual power is commonly used in various electronic devices.
請參考圖1，係顯示一具有雙電源設計之電源管理系統100架構圖。電源管理系統100包括一第一電源101、一第二電源102、一電源切換電路103及一負載104。其中，當第一電源存在時，由第一電源供電，當二組電源同時存在時，也由第一電源供電，當第一電源移除時，第二電源接著供電。Referring to FIG. 1, a power management system 100 architecture diagram with dual power supply design is shown. The power management system 100 includes a first power source 101, a second power source 102, a power switching circuit 103, and a load 104. Wherein, when the first power source is present, the first power source is powered. When the two groups of power sources are simultaneously present, the first power source is also powered. When the first power source is removed, the second power source is subsequently powered.
然而，習知的電源管理系統在啟動第一電源101時，第一電源101供電至負載104，其瞬間湧入電流會損壞負載104端的電子裝置。另外，以軟體方式控制電源管理系統來切換電源，會佔據電源管理系統部分的記憶體空間，以及消耗微處理器的工作時間，使整體效能降低。例如，在一台數位相機中，記憶體內除了資料庫程式來管理存檔，與影像程式來管理鏡頭之外，如果還使用電源管理程式來管理電源供應，無疑地會佔用更多的記憶體空間，而微處理器在處理多個程式的同時，電源管理程式也會佔據微處理器部份的工作時間，並造成其它程式反應較緩慢的情形。詳細而言，當電源管理系統100連接筆記型電腦供電給行動電話，並使用USB介面來作資料傳輸，除了要管理資料傳輸外，還需要同時兼顧充電的功能，因此，電源管理系統100的軟體程式設計的複雜度較高，且開發執行上會較困難，更遑論於筆記型電腦中有更多程式在同時執行，該電源管理程式對系統資源的消耗，與對其它程式的影響將更加顯著。However, when the conventional power management system starts the first power source 101, the first power source 101 supplies power to the load 104, and its instantaneous inrush current can damage the electronic device at the end of the load 104. In addition, controlling the power management system in software to switch the power supply will occupy the memory space of the power management system and consume the working time of the microprocessor, which will reduce the overall performance. For example, in a digital camera, in addition to the database program to manage the archives and the image program to manage the lens, if you use a power management program to manage the power supply, it will undoubtedly take up more memory space. While the microprocessor is processing multiple programs, the power management program also takes up part of the microprocessor's working time and causes other programs to react slowly. In detail, when the power management system 100 is connected to the notebook computer to supply power to the mobile phone, and uses the USB interface for data transmission, in addition to managing data transmission, it is also necessary to simultaneously charge the charging function. Therefore, the software of the power management system 100 The complexity of programming is high, and development and implementation will be more difficult. Moreover, more programs in the notebook are executed at the same time. The power management program will consume more system resources and other programs. .
本發明提供一種電源切換電路與其電源切換方法，其電源切換電路具有緩啟動電路能防止瞬間湧入電流，並以硬體電路設計方式降低電源管理系統佔用軟體資源。The invention provides a power switching circuit and a power switching method thereof. The power switching circuit has a slow start circuit to prevent instantaneous inrush current, and reduces the software resources occupied by the power management system by using a hardware circuit design manner.
本發明提供一種電源切換電路，用於切換一第一電源與一第二電源，電源切換電路包含：一第一開關電路、一第二開關電路與一緩啟動電路。第一開關電路耦接於第一電源，根據第一電源的電壓位準決定導通或關閉。第二開關電路耦接於第一開關電路、第二電源端與負載之間，根據第一電源與第二電源的電壓位準決定導通或關閉；緩啟動電路耦接於第一開關電路與負載之間；其中，當第一電源的電壓位準大於一預設值時，第一開關電路導通且第二開關電路關閉；當第一電源的電壓位準小於該預設值時，第一開關電路關閉且第二開關電路導通，其中緩啟動電路在第一開關電路導通一預設時間後導通。The present invention provides a power switching circuit for switching a first power source and a second power source. The power switching circuit includes: a first switch circuit, a second switch circuit, and a slow start circuit. The first switch circuit is coupled to the first power source, and is turned on or off according to a voltage level of the first power source. The second switch circuit is coupled between the first switch circuit, the second power terminal and the load, and is turned on or off according to the voltage level of the first power source and the second power source; the slow start circuit is coupled to the first switch circuit and the load When the voltage level of the first power source is greater than a predetermined value, the first switch circuit is turned on and the second switch circuit is turned off; when the voltage level of the first power source is less than the preset value, the first switch The circuit is turned off and the second switch circuit is turned on, wherein the slow start circuit is turned on after the first switch circuit is turned on for a predetermined time.
在本發明一實施例中，其中第一開關電路包括：一第一P型場效應電晶體、一第一電阻、一第二電阻、一第三電阻、一第四電阻、一第一電容與一第一NPN電晶體。第一P型場效應電晶體的汲極耦接於第一電源。第一電阻耦接於第一電源與接地端之間。第二電阻具有第一端耦接於第一P型場效應電晶體的汲極。第三電阻具有一第一端耦接於第一P型場效應電晶體的閘極。第四電阻，耦接於第一P型場效應電晶體的源極與閘極之間。第一電容耦接於第二電阻的第二端與接地端之間。第一NPN電晶體的集極耦接於第三電阻的第二端，其基極耦接於第二電阻的第二端，其射極耦接於接地端。In an embodiment of the invention, the first switching circuit includes: a first P-type field effect transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first capacitor A first NPN transistor. The drain of the first P-type field effect transistor is coupled to the first power source. The first resistor is coupled between the first power source and the ground. The second resistor has a first end coupled to the drain of the first P-type field effect transistor. The third resistor has a first end coupled to the gate of the first P-type field effect transistor. The fourth resistor is coupled between the source and the gate of the first P-type field effect transistor. The first capacitor is coupled between the second end of the second resistor and the ground. The collector of the first NPN transistor is coupled to the second end of the third resistor, the base of the first NPN transistor is coupled to the second end of the second resistor, and the emitter is coupled to the ground.
在本發明一實施例中，其中第二開關電路包括：一第二P型場效應電晶體、一第一二極體、一第二二極體、一一第五電阻、第六電阻、一第七電阻與一第八電阻。第二P型場效應電晶體的汲極耦接於第五電阻的第二端。第一二極體的陽極耦接於第一電源，其陰極耦接於第二P型場效應電晶體的閘極。第二二極體的陽極耦接於第二P型場效應電晶體的汲極，其陰極耦接於第二P型場效應電晶體的源極。第五電阻具有第一端耦接於第二電源。第六電阻具有第一端耦接於第二P型場效應電晶體的汲極。第七電阻具有第一端耦接於第二P型場效應電晶體的閘極。第八電阻耦接於第二P型場效應電晶體的源極與閘極之間；第二NPN電晶體的集極耦接於第七電阻的第二端，其基極耦接於該第六電阻的第二端，其射極耦接於接地端。In an embodiment of the invention, the second switching circuit includes: a second P-type field effect transistor, a first diode, a second diode, a fifth resistor, a sixth resistor, and a The seventh resistor and an eighth resistor. The drain of the second P-type field effect transistor is coupled to the second end of the fifth resistor. The anode of the first diode is coupled to the first power source, and the cathode of the first diode is coupled to the gate of the second P-type field effect transistor. The anode of the second diode is coupled to the drain of the second P-type field effect transistor, and the cathode is coupled to the source of the second P-type field effect transistor. The fifth resistor has a first end coupled to the second power source. The sixth resistor has a first end coupled to the drain of the second P-type field effect transistor. The seventh resistor has a first end coupled to the gate of the second P-type field effect transistor. The eighth resistor is coupled between the source and the gate of the second P-type field effect transistor; the collector of the second NPN transistor is coupled to the second end of the seventh resistor, and the base is coupled to the first The second end of the six resistors has an emitter coupled to the ground.
在本發明一實施例中，其中緩啟動電路包括：一第三P型場效應電晶體、一第二電容、一第九電阻、一第十電阻與一第十一電阻。第三P型場效應電晶體的源極耦接於第一開關電路的輸出。第二電容耦接於該第三P型場效應電晶體的源極與閘極之間。第九電阻耦接於第一開關電路的輸出與接地端之間。第十電阻耦接於第三P型場效應電晶體的源極與閘極之間。第十一電阻耦接於第三P型場效應電晶體的閘極與該接地端之間。In an embodiment of the invention, the slow start circuit includes: a third P-type field effect transistor, a second capacitor, a ninth resistor, a tenth resistor, and an eleventh resistor. The source of the third P-type field effect transistor is coupled to the output of the first switching circuit. The second capacitor is coupled between the source and the gate of the third P-type field effect transistor. The ninth resistor is coupled between the output of the first switching circuit and the ground. The tenth resistor is coupled between the source and the gate of the third P-type field effect transistor. The eleventh resistor is coupled between the gate of the third P-type field effect transistor and the ground.
在本發明一實施例中，電源切換電路更包括一信號顯示電路，耦接於第一電源，信號顯示電路包括：一第十二電阻、一第十三電阻、一信號指示器與一第三NPN電晶體。第十二電阻具有第一端耦接於第一電源。第十三電阻具有第一端耦接於第三電源。信號指示器耦接於第十三電阻的第二端。第三NPN電晶體的集極耦接於第十三電阻一第二端，其基極耦接於第十二電阻的第二端，其射極耦接於接地端。In an embodiment of the invention, the power switching circuit further includes a signal display circuit coupled to the first power source, the signal display circuit comprising: a twelfth resistor, a thirteenth resistor, a signal indicator, and a third NPN transistor. The twelfth resistor has a first end coupled to the first power source. The thirteenth resistor has a first end coupled to the third power source. The signal indicator is coupled to the second end of the thirteenth resistor. The collector of the third NPN transistor is coupled to the second end of the thirteenth resistor, the base of the third NPN transistor is coupled to the second end of the twelfth resistor, and the emitter is coupled to the ground.
本發明另提供一種電源切換方法，適用上述電源切換電路，本方法會根據第一電源的電壓，決定第一開關電路與第二開關電路的導通時間。當第一電源的電壓位準大於預設值時，導通第一開關電路且關閉第二開關電路，其中緩啟動電路在第一開關電路導通一預設時間後導通。當第一電源的電壓位準小於預設值時，關閉第一開關電路且導通第二開關電路。The invention further provides a power switching method, which is applicable to the power switching circuit, and the method determines the conduction time of the first switching circuit and the second switching circuit according to the voltage of the first power source. When the voltage level of the first power source is greater than a preset value, the first switch circuit is turned on and the second switch circuit is turned off, wherein the slow start circuit is turned on after the first switch circuit is turned on for a predetermined time. When the voltage level of the first power source is less than a preset value, the first switch circuit is turned off and the second switch circuit is turned on.
綜上所述，本發明係透過電源切換電路，即在提供一種藉由硬體電路設計方式來達成電源管理，進而降低系統資源耗損的電源切換電路，藉此提升的整體效能。In summary, the present invention improves the overall performance by transmitting a power switching circuit by providing a power switching circuit that achieves power management by means of a hardware circuit design, thereby reducing system resource consumption.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉本發明之較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;
為了充分瞭解本發明，於下文將例舉較佳實施例並配合附圖作詳細說明，且其並非用以限定本發明。The present invention will be described in detail with reference to the accompanying drawings,
圖2為根據本發明一實施例之電源切換電路之方塊圖。電源切換電路200包括第一開關電路210、第二開關電路220、緩啟動電路230與信號顯示電路240與負載250。電源切換電路200耦接於第一電源201與第二電源202與負載250之間，用以切換第一電源201與第二電源202，以供電至負載250。第一電源201與第二電源202例如為直流電源，用以輸出電壓與電流，可以單獨供電或第一電源201與第二電源202可以為相同電位切換供電。2 is a block diagram of a power switching circuit in accordance with an embodiment of the present invention. The power switching circuit 200 includes a first switching circuit 210, a second switching circuit 220, a slow start circuit 230, and a signal display circuit 240 and a load 250. The power switching circuit 200 is coupled between the first power source 201 and the second power source 202 and the load 250 for switching the first power source 201 and the second power source 202 to supply power to the load 250. The first power source 201 and the second power source 202 are, for example, DC power sources for outputting voltage and current, and may be separately powered or the first power source 201 and the second power source 202 may be switched to supply power at the same potential.
第一開關電路210耦接於第一電源201、第二開關電路220與緩啟動電路230之間，用以根據第一電源201端的電壓位準決定導通或關閉。第二開關電路220耦接於第二電源202、第一開關電路210與負載250之間，並根據第一電源201與第二電源202的電壓位準決定導通或關閉。緩啟動電路230耦接於第一開關電路210與負載250之間，用以防止瞬間湧入電流(Inrush current)。The first switch circuit 210 is coupled between the first power source 201, the second switch circuit 220, and the slow start circuit 230 for determining whether to turn on or off according to the voltage level of the first power source 201 end. The second switch circuit 220 is coupled between the second power source 202, the first switch circuit 210, and the load 250, and is turned on or off according to the voltage levels of the first power source 201 and the second power source 202. The slow start circuit 230 is coupled between the first switch circuit 210 and the load 250 to prevent an instantaneous inrush current.
具體而言，當第一電源201端的電壓位準大於一預設值時，第一開關電路210導通且第二開關電路220關閉，當第一電源201端的電壓位準低於該預設值時，第一開關電路210關閉且第二開關電路220導通，其中緩啟動電路230在第一開關電路210導通一預設時間後導通。另外，信號顯示電路240耦接於第一開關電路210與第二開關電路220之間，用以顯示電源切換信號。Specifically, when the voltage level of the first power source 201 is greater than a preset value, the first switch circuit 210 is turned on and the second switch circuit 220 is turned off, when the voltage level of the first power source 201 is lower than the preset value. The first switch circuit 210 is turned off and the second switch circuit 220 is turned on, wherein the slow start circuit 230 is turned on after the first switch circuit 210 is turned on for a predetermined time. In addition, the signal display circuit 240 is coupled between the first switch circuit 210 and the second switch circuit 220 for displaying a power switching signal.
圖3繪示本發明一實施例的電源切換電路200的電路圖。第一開關電路210，包括第一P型場效應電晶體Q1、第一電阻R1、第二電阻R2、第三電阻R3、第四電阻R4、第一電容C1與第一NPN電晶體NT1。第一P型場效應電晶體Q1例如為P channel MOSFET或增強型P channel MOSFET，其中第一P型場效應電晶體Q1的閘極G耦接第三電阻R3第一端、第四電阻R4；第一P型場效應電晶體Q1的源極S耦接第四電阻R4；第一P型場效應電晶體Q1的汲極D耦接第二電阻R2第一端。FIG. 3 is a circuit diagram of a power switching circuit 200 in accordance with an embodiment of the present invention. The first switching circuit 210 includes a first P-type field effect transistor Q1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1 and a first NPN transistor NT1. The first P-type field effect transistor Q1 is, for example, a P channel MOSFET or an enhanced P channel MOSFET, wherein the gate G of the first P-type field effect transistor Q1 is coupled to the first end of the third resistor R3 and the fourth resistor R4; The source S of the first P-type field effect transistor Q1 is coupled to the fourth resistor R4; the drain D of the first P-type field effect transistor Q1 is coupled to the first end of the second resistor R2.
第一電阻R1耦接於第一電源201與接地端GND之間。第四電阻R4耦接於第一P型場效應電晶體Q1的源極S與閘極G之間，用以調整該第一P型場效應電晶體Q1閘極G與源極S間的電壓，避免閘極G與源極S間的電壓過高而設計。第一電容C1耦接於第二電阻R2第二端與接地端GND之間，用以穩定電流與防止不穩定的電流回灌至第一P型場效應電晶體Q1。The first resistor R1 is coupled between the first power source 201 and the ground GND. The fourth resistor R4 is coupled between the source S and the gate G of the first P-type field effect transistor Q1 for adjusting the voltage between the gate G and the source S of the first P-type field effect transistor Q1. , to avoid the voltage between the gate G and the source S is too high and designed. The first capacitor C1 is coupled between the second end of the second resistor R2 and the ground GND for stabilizing the current and preventing the unstable current from being recharged to the first P-type field effect transistor Q1.
第一NPN電晶體NT1例如為NPN雙極接面電晶體(NPN bipolar junction transistor)，其基極耦接於第二電阻R2第二端，其集極耦接於第三電阻R3的第二端，其射極耦接於接地端GND。The first NPN transistor NT1 is, for example, an NPN bipolar junction transistor, the base of which is coupled to the second end of the second resistor R2, and the collector is coupled to the second end of the third resistor R3. The emitter is coupled to the ground GND.
第二開關電路220包括第二P型場效應電晶體Q2、第一二極體D1、第二二極體D2、第五電阻R5、第六電阻R6、第七電阻R7、第八電阻R8、第二NPN電晶體NT2。第二P型場效應電晶體Q2例如為P channel MOSFET或增強型P channel MOSFET，其中第二P型場效應電晶體Q2的閘極G耦接第七電阻R7第一端與第一二極體D1的陰極，第二P型場效應電晶體Q2的源極S耦接第八電阻R8、第二二極體D2的陰極與負載250，第二P型場效應電晶體Q2的汲極D耦接第五電阻R5第二端、第六電阻R6第一端與第二二極體D2的陽極。The second switching circuit 220 includes a second P-type field effect transistor Q2, a first diode D1, a second diode D2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The second NPN transistor NT2. The second P-type field effect transistor Q2 is, for example, a P channel MOSFET or an enhanced P channel MOSFET, wherein the gate G of the second P-type field effect transistor Q2 is coupled to the first end of the seventh resistor R7 and the first diode The cathode of D1, the source S of the second P-type field effect transistor Q2 is coupled to the eighth resistor R8, the cathode of the second diode D2 and the load 250, and the drain D of the second P-type field effect transistor Q2 The second end of the fifth resistor R5, the first end of the sixth resistor R6 and the anode of the second diode D2.
第一二極體D1的陽極耦接於第一電源201與第一開關電路210，其陰極耦接於第二P型場效應電晶體Q2的閘極G，用以根據第一電源201與第一開關電路210的電壓位準決定導通或關閉。第二二極體D2耦接於第二P型場效應電晶體Q2的源極S與汲極D，當第一電源201的電壓位準低於該預設值時，第二二極體D2將瞬間導通，用以防止系統斷電，其中第一二極體D1例如為一般二極體，第二二極體D2例如為蕭特基二極體(Schottky diode)。The anode of the first diode D1 is coupled to the first power source 201 and the first switch circuit 210, and the cathode of the first diode D1 is coupled to the gate G of the second P-type field effect transistor Q2 for The voltage level of a switching circuit 210 determines whether it is turned on or off. The second diode D2 is coupled to the source S and the drain D of the second P-type field effect transistor Q2. When the voltage level of the first power source 201 is lower than the preset value, the second diode D2 The moment is turned on to prevent the system from being powered off, wherein the first diode D1 is, for example, a general diode, and the second diode D2 is, for example, a Schottky diode.
接下來，第五電阻R5第一端耦接於第二電源202。第八電阻R8耦接於第二P型場效應電晶體Q2的閘極G與源極S之間，用以調整第二P型場效應電晶體Q2閘極G與源極S間的電壓，避免該閘極G與該源極S間的電壓過高而設計。第二NPN電晶體NT2例如為NPN雙極接面電晶體(NPN bipolar junction transistor)，第二NPN電晶體NT2的基極耦接於第六電阻R6第二端，其集極耦接於第七電阻R7第二端，與其射極耦接於接地端GND。Next, the first end of the fifth resistor R5 is coupled to the second power source 202. The eighth resistor R8 is coupled between the gate G and the source S of the second P-type field effect transistor Q2 for adjusting the voltage between the gate G and the source S of the second P-type field effect transistor Q2. The voltage between the gate G and the source S is prevented from being too high. The second NPN transistor NT2 is, for example, an NPN bipolar junction transistor, and the base of the second NPN transistor NT2 is coupled to the second end of the sixth resistor R6, and the collector is coupled to the seventh The second end of the resistor R7 is coupled to the ground terminal GND with its emitter.
其中，第二開關電路220受控於第二P型場效應電晶體Q2的閘極G與源極S間的電壓決定導通或關閉，例如為第二P型場效應電晶體Q2的閘極G與源極S間的電壓大於一臨限值(threshhold)後電流導通。值得注意的是，第二P型場效應電晶體Q2的閘極G與源極S間的電壓受控於該第一二極體D1的電壓位準，第一二極體D1根據第一開關電路210的電壓位準決定導通或關閉。The second switching circuit 220 is controlled by the voltage between the gate G and the source S of the second P-type field effect transistor Q2 to be turned on or off, for example, the gate G of the second P-type field effect transistor Q2. The current is turned on after the voltage between the source S and the source S is greater than a threshold. It should be noted that the voltage between the gate G and the source S of the second P-type field effect transistor Q2 is controlled by the voltage level of the first diode D1, and the first diode D1 is according to the first switch. The voltage level of circuit 210 determines whether it is turned on or off.
換句話說，當第一開關電路210導通時，第一二極體D1亦導通，第二P型場效應電晶體Q2的閘極G與源極S間的電壓為0，第二開關電路220為關閉，相反的，當第一開關電路210關閉時，第一二極體D1亦關閉，第二P型場效應電晶體Q2的閘極G與源極S間的電壓大於一臨限值後電流導通，即第二開關電路220為導通。In other words, when the first switching circuit 210 is turned on, the first diode D1 is also turned on, and the voltage between the gate G and the source S of the second P-type field effect transistor Q2 is 0, and the second switching circuit 220 is turned on. In order to turn off, on the contrary, when the first switching circuit 210 is turned off, the first diode D1 is also turned off, and the voltage between the gate G and the source S of the second P-type field effect transistor Q2 is greater than a threshold value. The current is turned on, that is, the second switching circuit 220 is turned on.
請繼續參見圖3，緩啟動電路230包括：第三P型場效應電晶體Q3、第九電阻R9、第十電阻R10、第十一電阻R11、第二電容C2。第三P型場效應電晶體Q3包括閘極G、源極S與汲極D，該閘極G耦接第十電阻R10、第十一電阻R11與第二電容C2，該源極S耦接於第一開關電路210、第九電阻R9、第十電阻R10與第二電容C2，該汲極D耦接於負載250。Referring to FIG. 3, the slow start circuit 230 includes a third P-type field effect transistor Q3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a second capacitor C2. The third P-type field effect transistor Q3 includes a gate G, a source S and a drain D. The gate G is coupled to the tenth resistor R10, the eleventh resistor R11 and the second capacitor C2, and the source S is coupled. The first switch circuit 210, the ninth resistor R9, the tenth resistor R10 and the second capacitor C2 are coupled to the load 250.
接下來，第二電容C2耦接於該第九電阻R9、第十電阻R10與第十一電阻R11之間，其中緩啟動電路230受控於第二電容C2達飽和電壓之一預設時間後導通，用以將電流儲存至第二電容C2，作為防止瞬間電流之緩啟動裝置，另於第二電容C2達飽和電壓後，透過第九電阻R9將第二電容C2之飽和電流導至接地端GND，例如在一個使用固定直流電壓源的電路中，第二電容C2兩端的電壓不會超過電源的電壓，當第二電容C2兩端的電壓已不再變動，流過第二電容C2的電流為零時，即達第二電容C2之飽和電壓，當直流電壓源消失時，此時第二電容C2之電流會經第九電阻R9導至接地端GND。Next, the second capacitor C2 is coupled between the ninth resistor R9, the tenth resistor R10 and the eleventh resistor R11, wherein the slow start circuit 230 is controlled by the second capacitor C2 to reach a saturation voltage for a preset time. Turning on to store current to the second capacitor C2 as a slow start device for preventing instantaneous current. After the second capacitor C2 reaches a saturation voltage, the saturation current of the second capacitor C2 is conducted to the ground through the ninth resistor R9. GND, for example, in a circuit using a fixed DC voltage source, the voltage across the second capacitor C2 does not exceed the voltage of the power supply. When the voltage across the second capacitor C2 does not change any more, the current flowing through the second capacitor C2 is At zero hour, the saturation voltage of the second capacitor C2 is reached. When the DC voltage source disappears, the current of the second capacitor C2 is led to the ground GND via the ninth resistor R9.
第九電阻R9耦接於第一開關電路210與接地端GND之間。第十電阻R10耦接於第三P型場效應電晶體Q3的閘極G與源極S之間，用以調整該第三P型場效應電晶體Q3閘極G與源極S間的電壓，避免閘極G與源極S間的電壓過高而設計。其中，緩啟動電路230受控於該第三P型場效應電晶體Q3的源極S與閘極G間的電壓導通或關閉，例如為第三P型場效應電晶體Q3的閘極G與源極S間的電壓大於一臨限值後電流導通。The ninth resistor R9 is coupled between the first switch circuit 210 and the ground GND. The tenth resistor R10 is coupled between the gate G and the source S of the third P-type field effect transistor Q3 for adjusting the voltage between the gate G and the source S of the third P-type field effect transistor Q3. , to avoid the voltage between the gate G and the source S is too high and designed. The slow start circuit 230 is controlled by the voltage between the source S and the gate G of the third P-type field effect transistor Q3 being turned on or off, for example, the gate G of the third P-type field effect transistor Q3 and The current between the source S is greater than a threshold and the current is turned on.
請繼續參見圖3，信號顯示電路240包括：第三電源203、第十二電阻R12、第十三電阻R13、信號指示器241與第三NPN電晶體NT3，用以顯示第一電源201或第二電源202供電狀態。第十二電阻R12第一端耦接於第一電源201、第二電源202、第一開關電路210與第二開關電路220之間。第十三電阻R13第一端耦接於第三電源203。信號指示器241耦接於第十三電阻R13第二端。第三NPN電晶體NT3的基極耦接於第十二電阻R12第二端，其集極耦接於第十三電阻R13第二端與該信號指示器241，與其射極耦接於接地端GND之間。其中，信號指示器241受控於第三電源203的電壓位準決定導通或關閉。Referring to FIG. 3, the signal display circuit 240 includes: a third power source 203, a twelfth resistor R12, a thirteenth resistor R13, a signal indicator 241, and a third NPN transistor NT3 for displaying the first power source 201 or the first The second power supply 202 is powered. The first end of the twelfth resistor R12 is coupled between the first power source 201, the second power source 202, and the first switch circuit 210 and the second switch circuit 220. The first end of the thirteenth resistor R13 is coupled to the third power source 203. The signal indicator 241 is coupled to the second end of the thirteenth resistor R13. The base of the third NPN transistor NT3 is coupled to the second end of the twelfth resistor R12, and the collector is coupled to the second end of the thirteenth resistor R13 and the signal indicator 241, and the emitter is coupled to the ground. Between GND. Wherein, the signal indicator 241 is controlled to be turned on or off by the voltage level of the third power source 203.
本發明提出一種電源切換電路200，用於切換的第一電源201與第二電源202，且第一電源201可以為主電源，第二電源202可以為輔助電源，其電源切換電路200工作模式可以包括下列：The present invention provides a power switching circuit 200 for switching the first power source 201 and the second power source 202, and the first power source 201 can be a main power source, and the second power source 202 can be an auxiliary power source, and the power switching circuit 200 can operate in a mode. Includes the following:
模式一：當第一電源201單獨供電時，第一開關電路210將導通，再由緩啟動電路240於一預設時間後導通，第一電源201透過第一開關電路210與緩啟動電路240供電至負載250端。Mode 1: When the first power source 201 is separately powered, the first switch circuit 210 will be turned on, and then turned on by the slow start circuit 240 after a predetermined time, and the first power source 201 is powered by the first switch circuit 210 and the slow start circuit 240. To the load 250 end.
模式二：當第二電源202單獨供電時，第二開關電路220將導通，第二電源202透過第二開關電路220供電至負載250端。Mode 2: When the second power source 202 is separately powered, the second switch circuit 220 will be turned on, and the second power source 202 is powered to the load 250 terminal through the second switch circuit 220.
模式三：當第二電源202供電時，再以第一電源201供電，第二開關電路220之第一二極體D1將控制第二P型場效應電晶體Q2之閘極G與源極S間之電壓，使第二開關電路220關閉導通電流。Mode 3: When the second power source 202 is powered, the first power source 201 is powered, and the first diode D1 of the second switch circuit 220 controls the gate G and the source S of the second P-type field effect transistor Q2. The voltage between the two switches circuit 220 turns off the on current.
模式四：當第一電源201與第二電源202同時供電，再將第一電源201關閉時，第二開關電路220之第二二極體D2將瞬間提供第二P型場效應電晶體Q2輸出端一略低於第二電源202之電壓，以防止斷電，並再將第二P型場效應電晶體Q2導通。Mode 4: When the first power source 201 and the second power source 202 are simultaneously powered, and then the first power source 201 is turned off, the second diode D2 of the second switch circuit 220 will instantaneously provide the second P-type field effect transistor Q2 output. The terminal is slightly lower than the voltage of the second power source 202 to prevent power interruption, and the second P-type field effect transistor Q2 is turned on again.
模式五：當第一電源201供電後，再以第二電源202供電時，第一開關電路210與緩啟動電路230維持導通電流，第二開關電路220關閉導通電流。Mode 5: When the first power source 201 is powered, and then powered by the second power source 202, the first switch circuit 210 and the slow start circuit 230 maintain the on current, and the second switch circuit 220 turns off the on current.
由上述可知，本實施例之電源切換電路200用於切換第一電源201與第二電源202。其中第一開關電路210根據第一電源201的電壓位準決定導通或關閉，當第一電源201的電壓位準大於預設值時，第一開關電路210導通，第二開關電路220關閉，且緩啟動電路230在第一開關電路210導通一預設時間後導通。在另一狀況下，當第一電源201的電壓位準小於預設值時，第二電源202會啟動供電，第一開關電路210關閉且第二開關電路220導通。As can be seen from the above, the power switching circuit 200 of the present embodiment is configured to switch the first power source 201 and the second power source 202. The first switch circuit 210 is turned on or off according to the voltage level of the first power source 201. When the voltage level of the first power source 201 is greater than a preset value, the first switch circuit 210 is turned on, the second switch circuit 220 is turned off, and The slow start circuit 230 is turned on after the first switch circuit 210 is turned on for a predetermined time. In another case, when the voltage level of the first power source 201 is less than a preset value, the second power source 202 initiates power supply, the first switch circuit 210 is turned off and the second switch circuit 220 is turned on.
當第一電源201透過電源切換電路200供電至負載250端時，第一開關電路210導通，緩啟動電路230透過第二電容C2與第三P型場效應電晶體Q3等元件先關閉一預設時間後導通，因此，緩啟動電路230可防止瞬間湧入電流。當第一電源201停止供電至負載250時，第二電源202會透過電源切換電路200供電至負載250，此時，第一開關電路210關閉且第二開關電路220導通。接下來，配合圖2~圖4說明電源切換電路200的電源切換方法。圖4為根據本實施例之電源切換方法流程圖，其包括步驟如下：When the first power source 201 is powered to the load 250 terminal through the power switching circuit 200, the first switch circuit 210 is turned on, and the slow start circuit 230 first turns off a preset through the second capacitor C2 and the third P-type field effect transistor Q3. The time is turned on, and therefore, the slow start circuit 230 prevents an instantaneous inrush of current. When the first power source 201 stops supplying power to the load 250, the second power source 202 is powered to the load 250 through the power switching circuit 200. At this time, the first switch circuit 210 is turned off and the second switch circuit 220 is turned on. Next, a power supply switching method of the power supply switching circuit 200 will be described with reference to FIGS. 2 to 4. 4 is a flow chart of a power switching method according to this embodiment, which includes the following steps:
步驟S401：判斷第一電源的電壓位準是否大於預設值，如是，則進行步驟S402，如否，則進行步驟S404。Step S401: determining whether the voltage level of the first power source is greater than a preset value, if yes, proceeding to step S402, and if not, proceeding to step S404.
步驟S402：第一開關電路210導通且第二開關電路220關閉，進行步驟S403。Step S402: The first switch circuit 210 is turned on and the second switch circuit 220 is turned off, and step S403 is performed.
步驟S403：於一預設時間後，緩啟動電路230導通，進行步驟S405。Step S403: After a predetermined time, the slow start circuit 230 is turned on, and step S405 is performed.
步驟S404：第一開關電路210關閉且第二開關電路220導通，進行步驟S405。Step S404: the first switch circuit 210 is turned off and the second switch circuit 220 is turned on, and step S405 is performed.
步驟S405：供電至負載250端。Step S405: Power is supplied to the load 250 terminal.
所以在上述說明中，本發明之電源切換電路200透過二極體與電晶體等元件作為硬體電路設計，可防止電路導通之瞬間湧入電流損壞負載端的電子裝置。電源切換電路200為硬體電路設計，可降低佔用電源管理系統的記憶體空間與微處理器的工作時間，並避免使用軟體控制電源切換的問題發生。在實際運作上，如果需要強制使用第一電源201或第二電源202來供電，也可以透過軟體經由微處理器的控制達到此功能。因此，一般狀態下能藉由硬體電路自動切換的方式來降低資源耗損，並也能符合原來用軟體控制的使用需求。Therefore, in the above description, the power supply switching circuit 200 of the present invention transmits a component such as a diode and a transistor as a hardware circuit design, and prevents an electronic device that inrush current from damaging the load terminal when the circuit is turned on. The power switching circuit 200 is designed as a hardware circuit, which can reduce the memory space occupied by the power management system and the working time of the microprocessor, and avoid the problem of using the software to control the power switching. In actual operation, if it is necessary to force the first power source 201 or the second power source 202 to supply power, the function can also be achieved through the control of the microprocessor through the software. Therefore, in the normal state, the hardware power can be automatically switched by the hardware circuit to reduce the resource consumption, and can also meet the original use of software control.
值得一提的是，該第一電源201/第二電源202除了可以適用直流電源外，實際上也可以使用USB電源、乾電池組、太陽能電池組，以及車用電源來供電，本發明一樣可以達到自動電源切換供應的使用要求。It is worth mentioning that the first power source 201 / the second power source 202 can be powered by a USB power source, a dry battery pack, a solar battery pack, and a vehicle power source, in addition to the DC power source. Automatic power switching supply usage requirements.
綜上所述，本發明之電源切換電路可應用於無線分享器或其他電子設備切換電源使用，其利用硬體電路替代軟體控制，藉此簡化電路操作流程與資源，並提高的電源切換電路效率與穩定度。In summary, the power switching circuit of the present invention can be applied to a wireless sharer or other electronic device switching power supply, which uses hardware circuits instead of software control, thereby simplifying circuit operation flow and resources, and improving power switching circuit efficiency. And stability.
雖然本發明之較佳實施例已揭露如上，然本發明並不受限於上述實施例，任何所屬技術領域中具有通常知識者，在不脫離本發明所揭露之範圍內，當可作些許之更動與調整，因此本發明之保護範圍應當以後附之申請專利範圍所界定者為準。Although the preferred embodiments of the present invention have been disclosed as above, the present invention is not limited to the above-described embodiments, and any one of ordinary skill in the art can make some modifications without departing from the scope of the present invention. The scope of protection of the present invention should be determined by the scope of the appended claims.
100．．．電源管理系統100. . . Power management system
101、201．．．第一電源101, 201. . . First power supply
102、202．．．第二電源102, 202. . . Second power supply
103、200．．．電源切換電路103, 200. . . Power switching circuit
104、250．．．負載104, 250. . . load
203．．．第三電源203. . . Third power supply
210．．．第一開關電路210. . . First switching circuit
220．．．第二開關電路220. . . Second switching circuit
230．．．緩啟動電路230. . . Slow start circuit
240．．．信號顯示電路240. . . Signal display circuit
241．．．信號指示器241. . . Signal indicator
R1~R13．．．電阻R1~R13. . . resistance
C1、C2．．．電容C1, C2. . . capacitance
NT1、NT2、NT3．．．NPN電晶體NT1, NT2, NT3. . . NPN transistor
Q1、Q2、Q3．．．P型場效應電晶體Q1, Q2, Q3. . . P-type field effect transistor
D1．．．第一二極體D1. . . First diode
D2．．．第二二極體D2. . . Second diode
D．．．汲極D. . . Bungee
S．．．源極S. . . Source
G．．．閘極G. . . Gate
圖1為根據習知技術之雙電源設計之電子系統架構圖。1 is an electronic system architecture diagram of a dual power supply design in accordance with the prior art.
圖2為根據本發明一實施例之電源切換電路之方塊圖。2 is a block diagram of a power switching circuit in accordance with an embodiment of the present invention.
圖3繪示本發明一實施例之電源切換電路的電路圖。3 is a circuit diagram of a power switching circuit according to an embodiment of the present invention.
圖4繪示本發明一實施例之電源切換方法之流程圖。4 is a flow chart of a power switching method according to an embodiment of the invention.
201．．．第一電源201. . . First power supply
202．．．第二電源202. . . Second power supply
203．．．第三電源203. . . Third power supply
210．．．第一開關電路210. . . First switching circuit
220．．．第二開關電路220. . . Second switching circuit
230．．．緩啟動電路230. . . Slow start circuit
240．．．信號顯示電路240. . . Signal display circuit
241．．．信號指示器241. . . Signal indicator
250．．．負載250. . . load
R1~R13．．．電阻R1~R13. . . resistance
C1、C2．．．電容C1, C2. . . capacitance
NT1、NT2、NT3．．．NPN電晶體NT1, NT2, NT3. . . NPN transistor
Q1、Q2、Q3．．．P型場效應電晶體Q1, Q2, Q3. . . P-type field effect transistor
D1．．．第一二極體D1. . . First diode
D2．．．第二二極體D2. . . Second diode
D．．．汲極D. . . Bungee
S．．．源極S. . . Source
G．．．閘極G. . . Gate
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100143315A TWI429159B (en) | 2011-11-25 | 2011-11-25 | Power switching circuit and power switch method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100143315A TWI429159B (en) | 2011-11-25 | 2011-11-25 | Power switching circuit and power switch method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201322577A true TW201322577A (en) | 2013-06-01 |
| TWI429159B TWI429159B (en) | 2014-03-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100143315A TWI429159B (en) | 2011-11-25 | 2011-11-25 | Power switching circuit and power switch method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI429159B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242473A (en) * | 2013-06-17 | 2014-12-24 | 纬创资通股份有限公司 | Power supply system and method and electronic device |
| TWI712924B (en) * | 2019-03-25 | 2020-12-11 | 瑞納瑟科技股份有限公司 | Stylus pen apparatus with dual power sources |
-
2011
- 2011-11-25 TW TW100143315A patent/TWI429159B/en active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242473A (en) * | 2013-06-17 | 2014-12-24 | 纬创资通股份有限公司 | Power supply system and method and electronic device |
| TWI712924B (en) * | 2019-03-25 | 2020-12-11 | 瑞納瑟科技股份有限公司 | Stylus pen apparatus with dual power sources |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI429159B (en) | 2014-03-01 |
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