TW201322368A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- TW201322368A TW201322368A TW100142905A TW100142905A TW201322368A TW 201322368 A TW201322368 A TW 201322368A TW 100142905 A TW100142905 A TW 100142905A TW 100142905 A TW100142905 A TW 100142905A TW 201322368 A TW201322368 A TW 201322368A
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Abstract
Description
本發明是有關於一種半導體結構及其製作方法，且特別是有關於一種具有共接點結構之半導體結構及其製作方法。The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a common junction structure and a method of fabricating the same.
在積體電路的製作中，晶片(chip)是經由晶圓(wafer)製作、形成積體電路以及切割晶圓(wafer sawing)等步驟而完成。當晶圓內部之積體電路完成之後，可將一線路層配置於晶圓的表面上，並透過形成多個連接晶圓之表面與背面之貫孔的方式，來分別暴露出線路層的多個接墊。然而，由於這些接墊彼此分離，因此最終由晶圓切割所形成的晶片無法直接經由這些貫孔所暴露出的這些接墊直接與一外部電路電性連接。In the fabrication of an integrated circuit, a chip is completed by a process of fabricating a wafer, forming an integrated circuit, and wafer sawing. After the integrated circuit inside the wafer is completed, a circuit layer can be disposed on the surface of the wafer, and the plurality of circuit layers are respectively exposed by forming a plurality of through holes connecting the surface and the back surface of the wafer. Pads. However, since the pads are separated from each other, the wafers formed by the wafer dicing cannot be directly electrically connected to an external circuit directly through the pads exposed by the through holes.
本發明提供一種半導體結構及其製作方法，其製程步驟簡單，可減少製程時間及生產成本。The invention provides a semiconductor structure and a manufacturing method thereof, which have simple process steps and can reduce process time and production cost.
本發明提出一種半導體結構，其包括一半導體基底、一線路層、多個導電通孔以及一導電層。半導體基底具有一正面與一背面以及至少一連接正面與背面的貫孔。線路層配置於半導體基底的正面上，且具有多個接墊，其中這些貫孔分別暴露出部分這些接墊。這些導電通孔分別配置於這些貫孔內。導電層配置於半導體基底的背面上，且覆蓋背面，其中這些導電通孔分別連接電性連接這些接墊與導電層。The present invention provides a semiconductor structure including a semiconductor substrate, a wiring layer, a plurality of conductive vias, and a conductive layer. The semiconductor substrate has a front side and a back side and at least one through hole connecting the front side and the back side. The circuit layer is disposed on the front surface of the semiconductor substrate and has a plurality of pads, wherein the through holes respectively expose a portion of the pads. These conductive vias are respectively disposed in the through holes. The conductive layer is disposed on the back surface of the semiconductor substrate and covers the back surface, wherein the conductive vias are respectively connected to electrically connect the pads and the conductive layer.
本發明還提出一種半導體結構的製作方法，其包括以下步驟。提供一半導體基底以及一線路層。半導體基底具有一正面與一背面，且線路層配置於半導體基底的正面上。線路層具有至少一位在正面上的接墊。形成至少一個連接半導體基底之正面與背面的貫孔，其中貫孔暴露出部分接墊。形成一導電膠以填滿貫孔且覆蓋半導體基底的背面，而構成至少一分別位於貫孔內的導電通孔以及一位於背面上的導電層，其中導電通孔電性連接接墊與導電層。The present invention also provides a method of fabricating a semiconductor structure that includes the following steps. A semiconductor substrate and a wiring layer are provided. The semiconductor substrate has a front side and a back side, and the wiring layer is disposed on the front surface of the semiconductor substrate. The circuit layer has at least one pad on the front side. Forming at least one through hole connecting the front side and the back side of the semiconductor substrate, wherein the through hole exposes a portion of the pad. Forming a conductive paste to fill the through hole and covering the back surface of the semiconductor substrate, and forming at least one conductive via hole respectively located in the through hole and a conductive layer on the back surface, wherein the conductive via is electrically connected to the conductive pad .
基於上述，本發明是透過網版印刷的方式來同時形成這些導電通孔及連接這些導電通孔的導電層，其中這些導電通孔分別連接線路層的這些接墊。因此，本發明之半導體結構可具有共接點結構(即導電層與這些導電通孔)的設計，而本發明之半導體結構的製作方法可具有製程步驟簡單及可減少製程時間及生產成本之優勢。Based on the above, the present invention simultaneously forms the conductive vias and the conductive layers connecting the conductive vias by screen printing, wherein the conductive vias are respectively connected to the pads of the circuit layer. Therefore, the semiconductor structure of the present invention can have a design of a common contact structure (ie, a conductive layer and the conductive vias), and the method for fabricating the semiconductor structure of the present invention can have the advantages of simple process steps and reduced process time and production cost. .
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1G為本發明之一實施例之一種半導體結構的製作方法的剖面示意圖。依照本實施例之半導體結構的製作方法，首先，請參考圖1A，提供一半導體基底110以及一線路層120，其中半導體基底110具有彼此相對之一正面112與一背面114，且線路層120配置於半導體基底110的正面112上。1A to 1G are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to an embodiment of the present invention. According to the manufacturing method of the semiconductor structure of the present embodiment, first, referring to FIG. 1A, a semiconductor substrate 110 and a wiring layer 120 are provided. The semiconductor substrate 110 has a front surface 112 and a back surface 114 opposite to each other, and the circuit layer 120 is disposed. On the front side 112 of the semiconductor substrate 110.
需說明的是，在本實施例中，線路層120是由現行之半導體積體電路製程所製作，且線路層120可由至少一介電層、至少一線路層以及至少一電子元件，其中電子元件例如是一主動元件(active device)、一被動元件(passive device)或一微機電系統元件(Microelectromechanical system device,MEMS device)，於此並不加以限制。It should be noted that, in this embodiment, the circuit layer 120 is fabricated by the current semiconductor integrated circuit process, and the circuit layer 120 may be composed of at least one dielectric layer, at least one circuit layer, and at least one electronic component, wherein the electronic component For example, an active device, a passive device, or a MEMS device is not limited herein.
接著，請參考圖1B，利用乾式蝕刻方式或是雷射切割方式形成至少一個連接半導體基底110之正面112與背面114的貫孔116(圖1B中僅示意地繪示三個)，其中這些貫孔116分別暴露出線路層120的至少一個接墊122(圖1B中僅示意地繪示三個)，且這些接墊122是位在半導體基底110的正面112上。Next, referring to FIG. 1B, at least one through hole 116 connecting the front surface 112 and the back surface 114 of the semiconductor substrate 110 is formed by dry etching or laser cutting (only three are schematically shown in FIG. 1B). The holes 116 respectively expose at least one pad 122 of the circuit layer 120 (only three are schematically shown in FIG. 1B), and the pads 122 are located on the front surface 112 of the semiconductor substrate 110.
接著，進行一網版印刷步驟，其中網版印刷步驟包括以下步驟。首先，請參考圖1C，放置一網版(stencil)150於半導體基底110的背面114上，其中網版150暴露出半導體基底110的部分背面114。接著，請參考圖1D，使一導電膠130填滿這些貫孔116並覆蓋未被網版150所覆蓋之半導體基底110的背面114。之後，請參考圖1E，移除網版150以暴露出半導體基底110之部分背面114，並對導電膠130進行一真空烘烤步驟，以移除導電膠130內的溶劑，而形成至少一個分別位於這些貫孔116內的導電通孔140以及一位於半導體基底110之背面114上的導電層145。Next, a screen printing step is performed, wherein the screen printing step includes the following steps. First, referring to FIG. 1C, a stencil 150 is placed on the back surface 114 of the semiconductor substrate 110, wherein the screen 150 exposes a portion of the back surface 114 of the semiconductor substrate 110. Next, referring to FIG. 1D, a conductive paste 130 fills the through holes 116 and covers the back surface 114 of the semiconductor substrate 110 not covered by the screen 150. Thereafter, referring to FIG. 1E, the screen 150 is removed to expose a portion of the back surface 114 of the semiconductor substrate 110, and a vacuum baking step is performed on the conductive paste 130 to remove the solvent in the conductive paste 130 to form at least one respectively. Conductive vias 140 located in the vias 116 and a conductive layer 145 on the back side 114 of the semiconductor substrate 110.
特別是，在本實施例中，這些導電通孔140分別連接這些貫孔116所暴露出之線路層120的這些接墊122，而導電層145連接這些導電通孔140。換言之，這些接墊122可透過這些導電通孔140而結構性且電性連接至導電層145。再者，導電層145的厚度與網版150(請參考圖1C)的厚度實質上相同。也就是說，可依據所需之導電層145的厚度來選擇網板150的厚度。In particular, in the present embodiment, the conductive vias 140 respectively connect the pads 122 of the circuit layer 120 exposed by the vias 116, and the conductive layer 145 connects the conductive vias 140. In other words, the pads 122 can be structurally and electrically connected to the conductive layer 145 through the conductive vias 140 . Furthermore, the thickness of the conductive layer 145 is substantially the same as the thickness of the screen 150 (please refer to FIG. 1C). That is, the thickness of the stencil 150 can be selected depending on the thickness of the desired conductive layer 145.
最後，請同時參考圖1F與圖1G，沿著半導體基底110被暴露出的部分背面114透過一刀具160切割半導體基底110與線路層120，而形成至少一半導體結構100(圖1E中僅示意地繪示一個)。於此，是以網版150(請參考圖1C)的位置來定義出刀具160進行切割的位置，但並不以此為限。至此，已完成半導體結構100的製作。Finally, referring to FIG. 1F and FIG. 1G, at least one semiconductor structure 100 is formed by cutting a portion of the back surface 114 of the semiconductor substrate 110 through a cutter 160 to form a semiconductor substrate 110 (FIG. 1E only schematically) Show one). Here, the position of the cutter 160 for cutting is defined by the position of the screen 150 (please refer to FIG. 1C), but is not limited thereto. So far, the fabrication of the semiconductor structure 100 has been completed.
值得一提的是，圖1C、圖1D及圖1E所繪示的網版印刷步驟僅是作為舉例說明之用。於其他實施例中，亦可採用塗佈的方式來形成導電膠130a。詳細來說，請參考圖2A，可於圖1B之步驟後，即形成這些連接半導體基底110之正面112與背面114的貫孔116之後，透過塗佈的方式使導電膠130a填滿該些貫孔116並覆蓋該半導體基底110的背面112。接著，請參考圖2B，對導電膠130a進行一薄化程序，以減少導電膠130a的厚度，而形成具有較薄厚度之導電膠130b。最後，再對導電膠130b進行圖1E之真空烘烤步驟，以移除導電膠130b內的溶劑，而形成這些分別位於這些貫孔116內的導電通孔140以及位於半導體基底110之背面114上的導電層145。上述圖2A至圖2B採用塗佈步驟來形成導電膠130a此仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。It is worth mentioning that the screen printing steps illustrated in Figures 1C, 1D and 1E are for illustrative purposes only. In other embodiments, the conductive paste 130a may also be formed by coating. In detail, referring to FIG. 2A, after the steps of FIG. 1B are formed, after the through holes 116 connecting the front surface 112 and the back surface 114 of the semiconductor substrate 110 are formed, the conductive paste 130a is filled through the coating manner. The hole 116 covers the back surface 112 of the semiconductor substrate 110. Next, referring to FIG. 2B, a thinning process is performed on the conductive paste 130a to reduce the thickness of the conductive paste 130a to form a conductive paste 130b having a relatively thin thickness. Finally, the vacuum baking step of FIG. 1E is performed on the conductive paste 130b to remove the solvent in the conductive paste 130b to form the conductive vias 140 respectively located in the through holes 116 and on the back surface 114 of the semiconductor substrate 110. Conductive layer 145. The above-mentioned FIG. 2A to FIG. 2B adopts a coating step to form the conductive paste 130a. This is still a technical solution that can be employed in the present invention without departing from the scope of the present invention.
在結構上，請再參考圖1G，本實施例之半導體結構100包括半導體基底110、線路層120、這些導電通孔140以及導電層145。半導體基底110具有彼此相對之正面112與背面114以及這些連接正面112與背面114的貫孔116。線路層120配置於半導體基底110的正面112上，且具有這些接墊122，其中這些貫孔116分別暴露出線路層120的部分這些接墊122。這些導電通孔140分別配置於這些貫孔116內。導電層145配置於半導體基底110的背面114上，且覆蓋背面114，其中這些導電通孔140分別連接線路層120的這些接墊122，而導電層145連接這些導電通孔140，且導電層145與這些導電通孔140皆是由一導電膠130所構成。換言之，導電層145與這些導電通孔140實質上一體成形。此外，導電層145與這些導電通孔140構成一共接點結構C。Structurally, referring again to FIG. 1G, the semiconductor structure 100 of the present embodiment includes a semiconductor substrate 110, a wiring layer 120, the conductive vias 140, and a conductive layer 145. The semiconductor substrate 110 has a front side 112 and a back side 114 opposite to each other and the through holes 116 connecting the front side 112 and the back side 114. The circuit layer 120 is disposed on the front surface 112 of the semiconductor substrate 110 and has the pads 122. The through holes 116 respectively expose portions of the pads 122 of the circuit layer 120. The conductive vias 140 are disposed in the through holes 116, respectively. The conductive layer 145 is disposed on the back surface 114 of the semiconductor substrate 110 and covers the back surface 114. The conductive vias 140 are respectively connected to the pads 122 of the circuit layer 120, and the conductive layer 145 is connected to the conductive vias 140, and the conductive layer 145 is The conductive vias 140 are formed of a conductive paste 130. In other words, the conductive layer 145 is substantially integrally formed with the conductive vias 140. In addition, the conductive layer 145 and the conductive vias 140 form a common contact structure C.
由於本實施例是透過網版印刷的方式來同時形成這些導電通孔140及連接這些導電通孔140的導電層145，因此本實施例之半導體結構100的製作方法具有製程步驟簡單及可減少製程時間及生產成本之優勢。再者，由於線路層120的這些接墊122可透過這些導電通孔140而結構性且電性連接至導電層145。意即，這些接墊122分別經由這些導電通孔140連接至同一接點(即導電層145)。因此，所形成之半導體結構100可透過此共接點結構C(即導電層145與這些導電通孔140)的設計與一外部電路(未繪示)電性連接，亦或，可將此導電層145視為一接地層，可有效擴充半導體結構100的應用範圍。In this embodiment, the conductive vias 140 and the conductive layers 145 connecting the conductive vias 140 are formed by screen printing. Therefore, the manufacturing method of the semiconductor structure 100 of the embodiment has a simple manufacturing process and can reduce the process. The advantage of time and production cost. Moreover, since the pads 122 of the circuit layer 120 can be electrically and electrically connected to the conductive layer 145 through the conductive vias 140. That is, the pads 122 are respectively connected to the same contact (ie, the conductive layer 145) via the conductive vias 140. Therefore, the formed semiconductor structure 100 can be electrically connected to an external circuit (not shown) through the design of the common contact structure C (ie, the conductive layer 145 and the conductive vias 140), or Layer 145 is considered a ground plane and can effectively expand the range of applications of semiconductor structure 100.
綜上所述，本發明是透過網版印刷的方式來同時形成這些導電通孔及連接這些導電通孔的導電層，其中這些導電通孔分別連接線路層的這些接墊。因此，本發明之半導體結構可具有共接點結構(即導電層與這些導電通孔)的設計，而本發明之半導體結構的製作方法可具有製程步驟簡單及可減少製程時間及生產成本之優勢。In summary, the present invention simultaneously forms the conductive vias and the conductive layers connecting the conductive vias by screen printing, wherein the conductive vias are respectively connected to the pads of the circuit layer. Therefore, the semiconductor structure of the present invention can have a design of a common contact structure (ie, a conductive layer and the conductive vias), and the method for fabricating the semiconductor structure of the present invention can have the advantages of simple process steps and reduced process time and production cost. .
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．半導體結構100. . . Semiconductor structure
110．．．半導體基底110. . . Semiconductor substrate
112．．．正面112. . . positive
114．．．背面114. . . back
116．．．貫孔116. . . Through hole
120．．．線路層120. . . Circuit layer
122．．．接墊122. . . Pad
130、130a、130b．．．導電膠130, 130a, 130b. . . Conductive plastic
140．．．導電通孔140. . . Conductive through hole
145．．．導電層145. . . Conductive layer
150．．．網板150. . . Stencil
160．．．刀具160. . . Tool
C．．．共接點結構C. . . Common contact structure
圖1A至圖1G為本發明之一實施例之一種半導體結構的製作方法的剖面示意圖。1A to 1G are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to an embodiment of the present invention.
圖2A至圖2B為本發明之另一實施例之一種半導體結構的製作方法的局部步驟的剖面示意圖。2A-2B are cross-sectional views showing a partial step of a method of fabricating a semiconductor structure in accordance with another embodiment of the present invention.
100．．．半導體結構100. . . Semiconductor structure
110．．．半導體基底110. . . Semiconductor substrate
112．．．正面112. . . positive
114．．．背面114. . . back
116．．．貫孔116. . . Through hole
120．．．線路層120. . . Circuit layer
122．．．接墊122. . . Pad
140．．．導電通孔140. . . Conductive through hole
145．．．導電層145. . . Conductive layer
Claims (13)
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| TW100142905A TW201322368A (en) | 2011-11-23 | 2011-11-23 | Semiconductor structure and manufacturing method thereof |
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