TW201310236A - Program method for memory and flash memory device using the same - Google Patents
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本發明是有關於一種記憶體編程方法及應用其之快閃記憶體裝置,且特別是有關於一種針對資料編程錯誤進行錯誤回覆之記憶體編程方法及應用其之快閃記憶體裝置。The present invention relates to a memory programming method and a flash memory device using the same, and more particularly to a memory programming method for error rewriting of data programming errors and a flash memory device using the same.
在科技發展日新月異的現今時代,非揮發性記憶體裝置係被廣泛地應用在多種電子產品中;舉例來說,快閃記憶體為最為廣泛使用之非揮發性記憶體之一。一般來說,快閃記憶體中之記憶胞係具有可編程的臨界電壓,此可編程的臨界電壓係用以指示此記憶胞中儲存的資料數值。In today's fast-changing world of technology, non-volatile memory devices are widely used in a variety of electronic products; for example, flash memory is one of the most widely used non-volatile memories. Generally, the memory cell in the flash memory has a programmable threshold voltage, and the programmable threshold voltage is used to indicate the value of the data stored in the memory cell.
在快閃記憶體的資料編程操作中,偶發地會發生編程失敗的情形。據此,需執行諸如錯誤更正碼(Error Correction Code,ECC),以進行相關的回覆操作。然而在一些嚴重的編程錯誤中,即便執行ECC仍無法對編程失敗的資料進行回覆,而將導致資料損失。據此,如何針對快閃記憶體提出更完善的編程方法,以在編程失敗發生時有效地對編程失敗的資料進行回覆,為業界不斷致力方向之一。In the data programming operation of the flash memory, the programming failure occasionally occurs. Accordingly, an Error Correction Code (ECC), such as an Error Correction Code (ECC), needs to be performed to perform a related reply operation. However, in some serious programming errors, even if ECC is executed, it is impossible to reply to the data that failed in programming, which will result in data loss. Based on this, how to provide a more perfect programming method for flash memory to effectively reply to the failed programming data when programming failure occurs is one of the direction of the industry.
本發明有關於一種記憶體編程方法及應用其之快閃記憶體裝置,其係應用於具有第一及第二記憶體層面(Memory Plane)之快閃記憶體中。本發明相關之記憶體編程方法及應用其之快閃記憶體裝置更在此快閃記憶體操作於隨取操作(Random Access)模式時,則建立第一邏輯至實體(Logic-to-Physical,L2P)對照表來將接收之編程邏輯位址對應至第一記憶體層面中之主記憶空間、建立第二L2P對照表來將編程邏輯位址對應至第二記憶體層面中之備份記憶空間並據以同時將編程資料寫入此主記憶空間及此備份記憶空間中。當主記憶空間發生編程失敗時,本發明相關之記憶體編程方法及應用其之快閃記憶體裝置可將對應至主記憶空間之位址指向備份記憶空間,藉此對快閃記憶體進行錯誤修補。據此,相較於傳統快閃記憶體,本發明相關之記憶體編程方法及應用其之快閃記憶體裝置據此可有效地對編程失敗之資料進行回覆之優點。The invention relates to a memory programming method and a flash memory device using the same, which is applied to a flash memory having first and second memory planes. The memory programming method and the flash memory device using the same according to the present invention establish a first logic-to-physical (Logic-to-Physical) when the flash memory is operated in a random access mode (Random Access mode). L2P) a table matching the received programming logic address to the main memory space in the first memory level, establishing a second L2P comparison table to map the programming logic address to the backup memory space in the second memory level and According to the same, the programming data is written into the main memory space and the backup memory space. When the programming failure of the main memory space occurs, the memory programming method and the flash memory device using the same can point the address corresponding to the main memory space to the backup memory space, thereby making an error to the flash memory. repair. Accordingly, compared with the conventional flash memory, the memory programming method and the flash memory device using the same according to the present invention can effectively reply to the data of the failed programming.
根據本發明之第一方面,提出一種記憶體編程方法,應用於快閃記憶體,其中快閃記憶體包括第一及第二記憶體層面(Plane),記憶體編程方法包括下列步驟。首先接收包括編程邏輯位址之編程指令。接著建立第一邏輯至實體(Logic-to-Physical,L2P)對照表將編程邏輯位址對應至第一記憶體層面中之主記憶空間。然後判斷快閃記憶體是否操作於隨取操作(Random Access)模式;若是,建立第二L2P對照表將編程邏輯位址對應至第二記憶體層面中之備份記憶空間。接著對第一及第二記憶體層面同時進行編程以將編程資料寫入主記憶空間及第二記憶體層面之備份記憶空間。然後判斷主記憶空間是否編程成功;若否,將對應至主記憶空間之位址指向備份記憶空間。According to a first aspect of the present invention, a memory programming method is provided for use in a flash memory, wherein the flash memory includes first and second memory levels, and the memory programming method comprises the following steps. The programming instructions including the programming logic address are first received. A first Logic-to-Physical (L2P) lookup table is then established to map the programmed logical address to the primary memory space in the first memory level. Then, it is determined whether the flash memory operates in a random access mode; if so, the second L2P comparison table is established to map the programming logical address to the backup memory space in the second memory level. The first and second memory levels are simultaneously programmed to write programming data to the backup memory space of the main memory space and the second memory level. Then, it is judged whether the main memory space is successfully programmed; if not, the address corresponding to the main memory space is directed to the backup memory space.
根據本發明之第二方面,提出一種快閃記憶體裝置,回應於編程指令進行資料編程操作,編程指令包括編程邏輯位址。快閃記憶體裝置包括快閃記憶體、暫存器及記憶體控制器。快閃記憶體包括第一及第二記憶體層面。暫存器暫存對應至編程指令之編程資料。記憶體控制器回應於編程指令建立第一L2P對照表,以將編程邏輯位址對應至第一記憶體層面之主記憶空間;記憶體控制器更判斷該快閃記憶體是否操作於隨取操作模式;若是,則建立第二L2P對照表,將編程邏輯位址對應至第二記憶體層面之備份記憶空間。記憶體控制器更對第一及第二記憶體層面同時進行編程,以將編程資料寫入主記憶空間及備份記憶空間。記憶體控制器更判斷主記憶空間是否編程成功,若否,則將對應至主記憶空間之位址指向備份記憶空間。According to a second aspect of the present invention, a flash memory device is provided for performing a data program operation in response to a program instruction, the program instruction including a program logic address. The flash memory device includes a flash memory, a scratchpad, and a memory controller. The flash memory includes first and second memory levels. The scratchpad temporarily stores the programming data corresponding to the programming instruction. The memory controller establishes a first L2P comparison table in response to the programming instruction to correspond the programming logic address to the main memory space of the first memory level; the memory controller further determines whether the flash memory is operated by the fetch operation Mode; if yes, a second L2P lookup table is created, and the programming logic address is mapped to the backup memory space of the second memory level. The memory controller simultaneously programs the first and second memory levels to write programming data into the main memory space and the backup memory space. The memory controller further determines whether the main memory space is successfully programmed, and if not, points the address corresponding to the main memory space to the backup memory space.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
請參照第1圖,其繪示依照本發明實施例之快閃記憶體裝置的方塊圖。本實施例之快閃記憶體裝置1回應於主機2提供之編程指令CMD進行資料編程操作,編程指令CMD包括編程邏輯位址Addr_P。快閃記憶體裝置1包括快閃記憶體10、暫存器20及記憶體控制器30。暫存器20暫存對應至編程指令CMD之編程資料Data。Referring to FIG. 1, a block diagram of a flash memory device in accordance with an embodiment of the present invention is shown. The flash memory device 1 of the present embodiment performs a data program operation in response to a program command CMD provided by the host 2, and the program command CMD includes a program logic address Addr_P. The flash memory device 1 includes a flash memory 10, a scratchpad 20, and a memory controller 30. The register 20 temporarily stores the programming data Data corresponding to the programming command CMD.
快閃記憶體10包括記憶體層面(Plane)10_P1及10_P2。舉例來說,記憶體層面10_P1包括多個記憶區塊(Block),而各記憶區塊包括記憶分頁(Page);記憶體層面10_P2包括備份記憶區塊。進一步來說,記憶區塊係為反及閘(NAND)快閃記憶體之清除操作(Erase)的操作單位,而記憶分頁係為NAND快閃記憶體之編程操作(Program)及讀取操作(Read)的操作單元。The flash memory 10 includes memory levels 10_P1 and 10_P2. For example, the memory level 10_P1 includes a plurality of memory blocks, and each memory block includes a memory page; the memory level 10_P2 includes a backup memory block. Further, the memory block is an operation unit of an anti-gate (NAND) flash memory erase operation (Erase), and the memory page is a program operation and a read operation of the NAND flash memory ( Read) operating unit.
記憶體控制器30回應於編程指令CMD建立邏輯至實體(Logic-to-Physical,L2P)對照表L2P_1,以將編程邏輯位址Addr_P對應至記憶體層面10_P1中之主記憶空間。舉例來說,L2P對照表L2P_1係對應至區塊操作模式(Block Mode),其用以將編程邏輯位址Addr_P對應至特定的記憶區塊中之主記憶分頁Page_M。The memory controller 30 establishes a Logic-to-Physical (L2P) look-up table L2P_1 in response to the program instruction CMD to map the program logic address Addr_P to the main memory space in the memory level 10_P1. For example, the L2P comparison table L2P_1 corresponds to a block operation mode (Block Mode) for mapping the program logic address Addr_P to the main memory page Page_M in a specific memory block.
舉例來說,對應至區塊操作模式之L2P對照表L2P_1係以區塊為單位,來將邏輯層面之分頁位址對應至實體記憶體分頁,如第2圖所示。進一步來說,對於邏輯層面同屬一個邏輯記憶體區塊B(L)之多個邏輯記憶體分頁P(L_N)、P(L_N+1)、...、P(L_N+M)來說,其於實體層面中亦對應至一個相同的實體記憶體區塊B(P)中之多個實體記憶體分頁P(P_N)、P(P_N+1)、...、P(P_N+M),其中N及M為自然數。For example, the L2P lookup table L2P_1 corresponding to the block operation mode is in block units to map the logical level paging address to the physical memory page, as shown in FIG. Further, for a plurality of logical memory pages P(L_N), P(L_N+1), ..., P(L_N+M) of a logical memory block B(L) belonging to a logical memory block B(L) It also corresponds to a plurality of physical memory pages P(P_N), P(P_N+1), ..., P(P_N+M in the same physical memory block B(P) at the entity level. ), where N and M are natural numbers.
記憶體控制器30更判斷快閃記憶體10是否操作於隨取操作(Random Access)模式。舉例來說,記憶體控制器30係參考編程指令CMD及記憶體層面10_P1及10_P2的容量,來判斷快閃記憶體10是否操作於隨取操作模式中。The memory controller 30 further determines whether the flash memory 10 is operating in a Random Access mode. For example, the memory controller 30 refers to the capacity of the programming command CMD and the memory levels 10_P1 and 10_P2 to determine whether the flash memory 10 is operating in the fetch mode.
當快閃記憶體10操作於隨取操作模式時,記憶體控制器30建立L2P對照表L2P_2,以將編程邏輯位址CMD對應至記憶體層面10_P2中之備份記憶空間。舉例來說,L2P對照表L2P_2係對應至分頁操作模式(Page Mode),其用以將編程邏輯位址Addr_P對應至記憶體層面10_P2中一個暫存區塊Block_T中之暫存記憶分頁Page_T。在建立L2P對照表L2P_1及LTP_2之後,記憶體控制器30更對記憶體層面10_P1及10_P2同時進行編程,以將編程資料Data寫入記憶體層面10_P1之主記憶分頁Page_M及寫入記憶體層面10_p2之備份記憶分頁Page_T。When the flash memory 10 is operated in the fetch mode, the memory controller 30 establishes the L2P lookup table L2P_2 to correspond the program logic address CMD to the backup memory space in the memory level 10_P2. For example, the L2P comparison table L2P_2 corresponds to a page operation mode (Page Mode) for mapping the program logic address Addr_P to the temporary memory page Page_T in a temporary storage block Block_T in the memory level 10_P2. After the L2P comparison table L2P_1 and LTP_2 are established, the memory controller 30 simultaneously programs the memory levels 10_P1 and 10_P2 to write the programming data Data to the main memory page Page_M of the memory level 10_P1 and write to the memory level 10_p2. The backup memory page Page_T.
舉例來說,對應至分頁操作模式之L2P對照表L2P_2係以分頁為單位,來將邏輯層面之分頁位址對應至實體記憶體分頁,如第3圖所示。進一步來說,對於邏輯層面同屬一個邏輯記憶體區塊B_L之多個邏輯記憶體分頁P(L_N)、P(L_N+1)、...、P(L_N+M)來說,其於實體層面中可能對應至不同的記憶體區塊B(P_X)、B(P_Y)及B(P_Z)中之部份分頁P(L_N+1)、P(L_N+2)、...、P(L_N+M),其中N及M為自然數。For example, the L2P lookup table L2P_2 corresponding to the paged mode of operation is in page-by-page order to map the logical level paged address to the physical memory page, as shown in FIG. Further, for a plurality of logical memory pages P(L_N), P(L_N+1), ..., P(L_N+M) of a logical memory block B_L, the logical level is At the entity level, it may correspond to partial pages P(L_N+1), P(L_N+2), ..., P in different memory blocks B(P_X), B(P_Y), and B(P_Z). (L_N+M), where N and M are natural numbers.
在對主記憶分頁Page_M及備份記憶分頁Page_T之編程操作後,記憶體控制器30更判斷主記憶分頁Page_M是否編程成功。舉例來說,記憶體控制器30參考狀態旗標Status,以判斷主記憶空間Page_M及備份記憶空間Page_T之編程操作是否失敗。當狀態旗標Status指示主記憶空間Page_M及備份記憶空間Page_T其中之部分或全部之編程操作為失敗時,記憶體控制器30進一步判斷主記憶空間Page_M之操作是否失敗。After the programming operation of the main memory page Page_M and the backup memory page Page_T, the memory controller 30 further determines whether the main memory page Page_M is successfully programmed. For example, the memory controller 30 refers to the status flag Status to determine whether the programming operation of the main memory space Page_M and the backup memory space Page_T has failed. When the status flag Status indicates that some or all of the programming operations of the main memory space Page_M and the backup memory space Page_T are failed, the memory controller 30 further determines whether the operation of the main memory space Page_M has failed.
當主記憶分頁Page_M編程失敗時,記憶體控制器30將對應至主記憶分頁Page_T之位址指向備份記憶分頁Page_T。換言之,記憶體控制器30係在主記憶分頁Page_M的編程操作失敗時,將存取主記憶分頁Page_M之指令對應至存取備份記憶分頁Page_T之指令,藉此提供備份記憶分頁Page_T中儲存之編程資料Data來對快閃記憶體10進行錯誤修補。When the main memory page Page_M programming fails, the memory controller 30 points the address corresponding to the main memory page Page_T to the backup memory page Page_T. In other words, the memory controller 30 associates the instruction of accessing the main memory page Page_M with the instruction of accessing the backup memory page Page_T when the programming operation of the main memory page Page_M fails, thereby providing the programming stored in the backup memory page Page_T. Data Data is used to perform error repair on the flash memory 10.
相似於前述之操作,記憶體控制器30可根據L2P對照表L2P_1及L2p_2,來對記憶體層面10_P1及10_P2同時進行編程,以將對應至記憶體層面10_P1之其他主記憶分頁之編程資料Data同時寫入此其他主記憶分頁及對應之備份記憶分頁中,並於此其他主記憶分頁發生編程失敗時,以對應之備份記憶分頁中儲存之資料來對其進行錯誤修補。Similar to the foregoing operation, the memory controller 30 can simultaneously program the memory levels 10_P1 and 10_P2 according to the L2P comparison tables L2P_1 and L2p_2 to simultaneously simultaneously program the data of the other main memory pages corresponding to the memory level 10_P1. When the other main memory page and the corresponding backup memory page are written, and the programming fails in the other main memory pages, the data stored in the corresponding backup memory page is used for error repair.
在其他操作實例中,當快閃記憶體10非操作於隨取操作模式,而例如操作於序列操作(Sequential Access)模式時,記憶體控制器30將編程資料Data寫入記憶體層面10_P1之主記憶空間Page_M,而不執行針對備份記憶分頁進行編程之操作。In other operation examples, when the flash memory 10 is not operating in the fetch mode, for example, in the Sequential Access mode, the memory controller 30 writes the program data Data to the memory layer 10_P1. The memory space Page_M is not executed for programming the backup memory page.
請參照第4圖,其繪示依照本發明實施例之記憶體編程方法的流程圖。首先如步驟(a),記憶體控制器30接收編程指令CMD,其中包括編程邏輯位址Addr_P。接著如步驟(b),記憶體控制器30建立L2P對照表L2P_1,以將編程邏輯位址CMD對應至記憶體層面10_P1中之主記憶分頁Page_M。Please refer to FIG. 4, which is a flow chart of a memory programming method according to an embodiment of the invention. First, as in step (a), the memory controller 30 receives the programming command CMD, which includes the programming logic address Addr_P. Next, as in step (b), the memory controller 30 establishes the L2P lookup table L2P_1 to correspond the program logic address CMD to the main memory page Page_M in the memory level 10_P1.
然後如步驟(c),記憶體控制器30判斷快閃記憶體10是否操作於隨取操作模式;若是執行步驟(d),記憶體控制器30建立L2P對照表L2P_2,以將編程邏輯位址Addr_P對應至記憶體層面10_P2中之備份記憶分頁Page_T。Then, as in step (c), the memory controller 30 determines whether the flash memory 10 is operating in the fetch mode; if the step (d) is performed, the memory controller 30 establishes the L2P lookup table L2P_2 to program the logical address. Addr_P corresponds to the backup memory page Page_T in the memory level 10_P2.
接著如步驟(e),記憶體控制器30對記憶體層面10_P1及10_P2同時進行編程,以將編程資料Data寫入記憶體層面10_P1之主記憶分頁Page_M及寫入記憶體層面10_P2之備份記憶分頁Page_T。Then, as in step (e), the memory controller 30 simultaneously programs the memory levels 10_P1 and 10_P2 to write the programming data Data to the main memory page Page_M of the memory level 10_P1 and the backup memory page of the memory level 10_P2. Page_T.
然後如步驟(f),記憶體控制器30判斷主記憶分頁Page_M是否編程成功。舉例來說,步驟(f)包括子步驟(f1)及(f2),如第5圖所示。於步驟(f1)中,記憶體控制器30參考狀態旗標Status,判斷主記憶分頁Page_M及備份記憶分頁Page_T之編程操作是否失敗;若是執行步驟(f2),記憶體控制器30進一步地判斷主記憶分頁Page_M之操作是否失敗。Then, as in step (f), the memory controller 30 determines whether the main memory page Page_M is successfully programmed. For example, step (f) includes sub-steps (f1) and (f2) as shown in FIG. In step (f1), the memory controller 30 refers to the status flag Status to determine whether the programming operation of the main memory page Page_M and the backup memory page Page_T fails; if the step (f2) is performed, the memory controller 30 further determines the main Whether the operation of paging Page_M fails.
當主記憶分頁Page_M編程失敗時執行步驟(g),記憶體控制器30將對應至主記憶分頁Page_M之位址指向備份記憶分頁Page_T,藉此對快閃記憶體10進行錯誤修補。When the main memory page Page_M programming fails, step (g) is performed, and the memory controller 30 points the address corresponding to the main memory page Page_M to the backup memory page Page_T, thereby performing error repair on the flash memory 10.
在步驟(c)之後,當快閃記憶體10非操作於隨取操作模式時,執行步驟(h),記憶體控制器30將編程資料Data寫入記憶體層面10_P1之主記憶分頁Page_M中,而不執行對備份記憶分頁Page_T編程之操作。After the step (c), when the flash memory 10 is not operating in the fetch mode, step (h) is performed, and the memory controller 30 writes the program data Data into the main memory page Page_M of the memory level 10_P1. The operation of paging the Page_T programming for backup memory is not performed.
本發明實施例之記憶體編程方法及應用其之快閃記憶體裝置係應用於具有第一及第二記憶體層面之快閃記憶體中。本發明實施例之記憶體編程方法及應用其之快閃記憶體裝置更在此快閃記憶體操作於隨取操作模式時,則建立第一L2P對照表來將接收之編程邏輯位址對應至第一記憶體層面中之主記憶空間、建立第二L2P對照表來將編程邏輯位址對應至第二記憶體層面中之備份記憶空間並據以同時將編程資料寫入此主記憶空間及此備份記憶空間中。當主記憶空間發生編程失敗時,本發明實施例之記憶體編程方法及應用其之快閃記憶體裝置可將對應至主記憶空間之位址指向備份記憶空間,藉此對快閃記憶體進行錯誤修補。據此,相較於傳統快閃記憶體,本發明實施例之記憶體編程方法及應用其之快閃記憶體裝置據此可有效地對編程失敗之資料進行回覆之優點。。The memory programming method and the flash memory device using the same according to embodiments of the present invention are applied to flash memory having first and second memory levels. The memory programming method and the flash memory device using the same according to the embodiment of the present invention further establish a first L2P comparison table to correspond to the received programming logic address when the flash memory operates in the fetch operation mode. a main memory space in the first memory level, establishing a second L2P comparison table to map the programming logic address to the backup memory space in the second memory level and simultaneously writing programming data to the main memory space and Back up the memory space. When the main memory space fails to be programmed, the memory programming method and the flash memory device of the embodiment of the present invention can point the address corresponding to the main memory space to the backup memory space, thereby performing the flash memory. Error patching. Accordingly, compared with the conventional flash memory, the memory programming method and the flash memory device using the same according to the present invention can effectively reply to the data of the failed programming. .
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
1...快閃記憶體裝置1. . . Flash memory device
2...主機2. . . Host
10...快閃記憶體10. . . Flash memory
20...暫存器20. . . Register
30...記憶體控制器30. . . Memory controller
10_P1、10_P2...記憶體層面10_P1, 10_P2. . . Memory level
Page_M...主記憶分頁Page_M. . . Main memory paging
Page_T...備份記憶分頁Page_T. . . Backup memory page
B(L)...邏輯記憶體區塊B(L). . . Logical memory block
P(L_N)-P(L_N+M)...邏輯記憶體分頁P(L_N)-P(L_N+M). . . Logical memory paging
B(P)、B(P_X)-B(P_Z)...實體記憶體區塊B(P), B(P_X)-B(P_Z). . . Physical memory block
P(P_N)-P(P_N+M)...實體記憶體分頁P(P_N)-P(P_N+M). . . Physical memory paging
第1圖繪示依照本發明實施例之快閃記憶體裝置的方塊圖。1 is a block diagram of a flash memory device in accordance with an embodiment of the present invention.
第2圖繪示依照邏輯至實體對照表L2P_1的操作示意圖。FIG. 2 is a schematic diagram showing the operation according to the logical to entity comparison table L2P_1.
第3圖繪示依照邏輯至實體對照表L2P_2的操作示意圖。FIG. 3 is a schematic diagram showing the operation according to the logic to entity comparison table L2P_2.
第4圖繪示依照本發明實施例之記憶體編程方法的流程圖。FIG. 4 is a flow chart showing a memory programming method according to an embodiment of the invention.
第5圖繪示依照本發明實施例之記憶體編程方法的部份流程圖。FIG. 5 is a partial flow chart of a memory programming method according to an embodiment of the invention.
(a)-(h)...流程步驟(a)-(h). . . Process step
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