TW201306001A - Display device - Google Patents
Display device Download PDFInfo
- Publication number
- TW201306001A TW201306001A TW100125465A TW100125465A TW201306001A TW 201306001 A TW201306001 A TW 201306001A TW 100125465 A TW100125465 A TW 100125465A TW 100125465 A TW100125465 A TW 100125465A TW 201306001 A TW201306001 A TW 201306001A
- Authority
- TW
- Taiwan
- Prior art keywords
- voltage
- driving
- driving voltage
- display data
- parameter
- Prior art date
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
本發明是有關於一種顯示裝置，且特別是有關於一種具有電荷分享功能的顯示裝置。The present invention relates to a display device, and more particularly to a display device having a charge sharing function.
隨著光電與半導體技術的發展，帶動了平面顯示器之蓬勃發展，而諸多平面顯示器中，液晶顯示器由於因具有高空間利用效率、低消耗功率、無輻射以及低電磁干擾等優越特性，因而成為市場之主流。由於平面顯示器的解析度及更新頻率不斷提高，使得掃描線的更新頻率也越來越快，而這方面的要求又與系統設計工程師節省系統用電的設計互相衝突。因此，就有了電荷分享(Charge Sharing)的技術發展出來。With the development of optoelectronics and semiconductor technology, the development of flat panel displays has been promoted. Among many flat panel displays, liquid crystal displays have become the market due to their superior characteristics such as high space utilization efficiency, low power consumption, no radiation and low electromagnetic interference. The mainstream. As the resolution and update frequency of the flat panel display continue to increase, the update frequency of the scan line is also faster and faster, and this requirement conflicts with the design of the system design engineer to save system power. Therefore, there is a technology of charge sharing (Charge Sharing) developed.
一般而言，電荷分享技術的運作原理，就是將儲存各資料線內的能量(電荷)重新分配，並且無需耗用電力便可驅動各資料線的電壓接近其目標電壓。然而，在多列反轉的驅動方式下，電荷分享技術可能使資料線的電壓遠離其目標電壓，以致於提高平面顯示器的耗電量。In general, the principle of charge sharing technology is to redistribute the energy (charge) stored in each data line, and drive the voltage of each data line to its target voltage without using power. However, in the multi-column inversion driving mode, the charge sharing technique may shift the voltage of the data line away from its target voltage, so as to increase the power consumption of the flat panel display.
本發明提供一種顯示裝置，可避免電荷分享造成電耗增加。The present invention provides a display device that can avoid an increase in power consumption caused by charge sharing.
本發明提出一種顯示裝置，包括顯示面板、源極驅動器、電荷分享開關單元、控制單元、電壓比較電路及邏輯運算單元。源極驅動器包括第一資料通道及第二資料通道。第一資料通道耦接顯示面板，依據多個第一顯示資料依序輸出多個第一驅動電壓至顯示面板，其中每一第一驅動電壓的極性至少相同於兩相鄰的第一驅動電壓的其中之一的極性。第二資料通道耦接顯示面板，依據多個第二顯示資料依序輸出多個第二驅動電壓至該顯示面板，每一第二驅動電壓的極性至少相同於兩相鄰的第二驅動電壓的其中之一的極性。電荷分享開關單元具有第一端、第二端及控制端，第一端耦接第一資料通道的輸出端，第二端耦接第二資料通道的輸出端。控制單元輸出電荷分享信號。電壓比較電路接收這些第一顯示資料及及這些第二顯示資料，依據這些第一顯示資料的當下第一顯示資料及這些第二顯示資料的當下第二顯示資料計算中和電壓，並依據中和電壓與這些第一驅動電壓中的目標第一驅動電壓的第一壓差、中和電壓與這些第二驅動電壓中的目標第二驅動電壓的第二壓差、這些第一驅動電壓中的當下第一驅動電壓與目標第一驅動電壓的第三壓差及這些第二驅動電壓中的當下第二驅動電壓與目標第二驅動電壓的第四壓差產生電壓比較信號。邏輯運算單元耦接控制單元、電壓比較電路及該電荷分享開關單元的控制端，依據電壓比較信號與電荷分享信號控制電壓分享開關單元導通其第一端及第二端。The invention provides a display device comprising a display panel, a source driver, a charge sharing switch unit, a control unit, a voltage comparison circuit and a logic operation unit. The source driver includes a first data channel and a second data channel. The first data channel is coupled to the display panel, and sequentially outputs a plurality of first driving voltages to the display panel according to the plurality of first display materials, wherein each of the first driving voltages has a polarity at least equal to two adjacent first driving voltages. One of the polarities. The second data channel is coupled to the display panel, and sequentially outputs a plurality of second driving voltages to the display panel according to the plurality of second display materials, wherein each of the second driving voltages has a polarity at least equal to two adjacent second driving voltages. One of the polarities. The charge sharing switch unit has a first end, a second end, and a control end. The first end is coupled to the output end of the first data channel, and the second end is coupled to the output end of the second data channel. The control unit outputs a charge sharing signal. The voltage comparison circuit receives the first display data and the second display data, calculates a neutralization voltage according to the current first display data of the first display data and the current second display data of the second display materials, and according to the neutralization a first voltage difference between a voltage and a target first driving voltage of the first driving voltages, a neutral voltage difference between the voltage and a target second driving voltage of the second driving voltages, and a current one of the first driving voltages A third voltage difference between the first driving voltage and the target first driving voltage and a fourth voltage difference between the current second driving voltage and the target second driving voltage of the second driving voltages generate a voltage comparison signal. The logic operation unit is coupled to the control unit, the voltage comparison circuit and the control end of the charge sharing switch unit, and controls the voltage sharing switch unit to conduct the first end and the second end according to the voltage comparison signal and the charge sharing signal.
在本發明之一實施例中，中和電壓為當下第一驅動電壓及當下第二驅動電壓的平均值。In an embodiment of the invention, the neutralization voltage is an average of the current first driving voltage and the current second driving voltage.
在本發明之一實施例中，當目標第一驅動電壓小於中和電壓時，電壓比較電路設定第一參數為零；當目標第一驅動電壓大於等於中和電壓時，電壓比較電路設定第一參數為第一壓差。當目標第二驅動電壓小於中和電壓時，電壓比較電路設定第二參數為零；當目標第二驅動電壓大於等於中和電壓時，電壓比較電路設定第二參數為第二壓差。當目標第一驅動電壓小於當下第一驅動電壓時，電壓比較電路設定第三參數為零；當目標第一驅動電壓大於等於當下第一驅動電壓時，電壓比較電路設定第三參數為第三壓差。當目標第二驅動電壓小於當下第二驅動電壓時，電壓比較電路設定第四參數為零；當目標第二驅動電壓大於等於當下第二驅動電壓時，電壓比較電路設定第四參數為第四壓差。當第一參數與第二參數的總和小於第三參數與第四參數的總和時，電壓比較電路輸出致能的電壓比較信號。當第一參數與第二參數的總和大於等於第三參數與第四參數的總和時，電壓比較電路輸出禁能的電壓比較信號。In an embodiment of the invention, when the target first driving voltage is less than the neutralization voltage, the voltage comparison circuit sets the first parameter to be zero; when the target first driving voltage is greater than or equal to the neutralization voltage, the voltage comparison circuit sets the first The parameter is the first differential pressure. When the target second driving voltage is less than the neutralization voltage, the voltage comparison circuit sets the second parameter to be zero; when the target second driving voltage is greater than or equal to the neutralization voltage, the voltage comparison circuit sets the second parameter to the second voltage difference. When the target first driving voltage is lower than the current first driving voltage, the voltage comparison circuit sets the third parameter to be zero; when the target first driving voltage is greater than or equal to the current first driving voltage, the voltage comparison circuit sets the third parameter to the third voltage. difference. When the target second driving voltage is lower than the current second driving voltage, the voltage comparison circuit sets the fourth parameter to be zero; when the target second driving voltage is greater than or equal to the current second driving voltage, the voltage comparison circuit sets the fourth parameter to the fourth voltage. difference. When the sum of the first parameter and the second parameter is less than the sum of the third parameter and the fourth parameter, the voltage comparison circuit outputs the enabled voltage comparison signal. When the sum of the first parameter and the second parameter is greater than or equal to the sum of the third parameter and the fourth parameter, the voltage comparison circuit outputs the disabled voltage comparison signal.
在本發明之一實施例中，控制單元為時序控制器，用以產生閂鎖信號，其中電荷分享信號為閂鎖信號。In an embodiment of the invention, the control unit is a timing controller for generating a latch signal, wherein the charge sharing signal is a latch signal.
在本發明之一實施例中，源極驅動器更包括線緩衝器。線緩衝器耦接時序控制器，以從時序控制器接收這些第一顯示資料及這些第二顯示資料，並將這些第一顯示資料傳送至第一資料通道，將這些第二顯示資料傳送至第二資料通道。電壓比較電路從線緩衝器接收這些第一顯示資料及這些第二顯示資料，以依據當下第一顯示資料計算當下第一驅動電壓，依據這些第一顯示資料的目標第一顯示資料計算目標第一驅動電壓，依據當下第二顯示資料計算當下第二驅動電壓，以及依據這些第二顯示資料的目標第二顯示資料計算目標第二驅動電壓。In an embodiment of the invention, the source driver further includes a line buffer. The line buffer is coupled to the timing controller to receive the first display data and the second display data from the timing controller, and transmit the first display data to the first data channel, and send the second display data to the first data Two data channels. The voltage comparison circuit receives the first display data and the second display data from the line buffer to calculate the current first driving voltage according to the current first display data, and calculates the target first according to the target first display data of the first display data. The driving voltage calculates a current second driving voltage according to the current second display data, and calculates a target second driving voltage according to the target second display data of the second display materials.
在本發明之一實施例中，當下第一顯示資料及當下第二顯示資料對應第一列顯示資料，目標第一顯示資料及目標第二顯示資料對應第二列顯示資料。In an embodiment of the present invention, the first first display data and the current second display data correspond to the first column display data, and the target first display data and the target second display data correspond to the second column display data.
在本發明之一實施例中，第一通道依據閂鎖信號依序輸出這些第一驅動電壓，第二通道依據閂鎖信號依序輸出這些第二驅動電壓。In an embodiment of the invention, the first channel sequentially outputs the first driving voltages according to the latch signal, and the second channel sequentially outputs the second driving voltages according to the latch signals.
在本發明之一實施例中，邏輯運算單元包括及閘，及閘的第一輸入端耦接控制單元，及閘的第二輸入端耦接電壓比較電路，及閘的輸出端耦接電荷分享開關單元的控制端。In an embodiment of the invention, the logic operation unit includes a gate, and the first input end of the gate is coupled to the control unit, and the second input end of the gate is coupled to the voltage comparison circuit, and the output end of the gate is coupled to the charge sharing The control terminal of the switching unit.
在本發明之一實施例中，電荷分享開關單元包括MOS電晶體，MOS電晶體的第一源/汲極端作為電荷分享開關單元的第一端，MOS電晶體的第二源/汲極端作為電荷分享開關單元的第二端，MOS電晶體的閘極端作為電荷分享開關單元的控制端。In an embodiment of the invention, the charge sharing switch unit comprises a MOS transistor, the first source/汲 terminal of the MOS transistor acts as the first end of the charge sharing switch unit, and the second source/汲 terminal of the MOS transistor acts as the charge The second end of the sharing switch unit shares the gate terminal of the MOS transistor as the control terminal of the charge sharing switch unit.
在本發明之一實施例中，第一資料通道相鄰於第二資料通道。In an embodiment of the invention, the first data channel is adjacent to the second data channel.
在本發明之一實施例中，每一第一驅動電壓的極性相反於對應的第二驅動電壓的極性。In an embodiment of the invention, the polarity of each of the first driving voltages is opposite to the polarity of the corresponding second driving voltage.
基於上述，本發明實施例的顯示裝置，其增加電壓比較電路及邏輯運算單元。電壓比較電路依據當下第一驅動電壓、當下第二驅動電壓、目標第一驅動電壓及目標第二驅動電壓判斷進行電荷分享會增加電耗或減少電耗，在進行電荷分享會增加電耗的情況下透過邏輯運算單元遮罩閂鎖信號(即電荷分享信號)，以使電荷分享不會被執行。藉此，可避免電荷分享造成電耗增加。Based on the above, the display device of the embodiment of the invention increases the voltage comparison circuit and the logic operation unit. The voltage comparison circuit determines that the charge sharing according to the current first driving voltage, the current second driving voltage, the target first driving voltage, and the target second driving voltage increases power consumption or reduces power consumption, and increases power consumption when performing charge sharing. The latch signal (ie, charge sharing signal) is masked through the logic unit so that charge sharing is not performed. Thereby, the electric power consumption caused by the charge sharing can be avoided.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1為依據本發明一實施例的顯示裝置的系統示意圖。請參照圖1，在本實施例中，顯示裝置100包括時序控制器110、閘極驅動器120、源極驅動器130及顯示面板150。閘極驅動器120耦接時序控制器110，並受控於時序控制器110依序輸出多個掃描信號SC以驅動顯示面板150。源極驅動器130耦接時序控制器110，並依據時序控制器110的列顯示資料RDD及閂鎖信號LP依序輸出多個驅動電壓(如VP1及VP2)至顯示面板150。顯示面板150依據掃描信號SC接收驅動電壓(如VP1及VP2)，據此顯示畫面。1 is a system diagram of a display device in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the display device 100 includes a timing controller 110 , a gate driver 120 , a source driver 130 , and a display panel 150 . The gate driver 120 is coupled to the timing controller 110 and controlled by the timing controller 110 to sequentially output a plurality of scan signals SC to drive the display panel 150. The source driver 130 is coupled to the timing controller 110 and sequentially outputs a plurality of driving voltages (such as VP1 and VP2) to the display panel 150 according to the column display data RDD and the latch signal LP of the timing controller 110. The display panel 150 receives driving voltages (such as VP1 and VP2) according to the scan signal SC, and displays a picture accordingly.
進一步來說，源極驅動器130可包括線緩衝器131、多個資料通道(如133、137)、多個電壓比較電路(如135)、多個邏輯運算單元(如139)及多個電荷分享開關單元(如141)。在本實施例中，電壓比較電路(如135)、邏輯運算單元(如139)及電荷分享開關單元(如141)為配置於源極驅動器130中，但在其他實施例中，電壓比較電路(如135)、邏輯運算單元(如139)及電荷分享開關單元(如141)的其中之一、部分或全部可配置於源極驅動器之外，本發明實施例不以此為限。Further, the source driver 130 may include a line buffer 131, a plurality of data channels (such as 133, 137), a plurality of voltage comparison circuits (such as 135), a plurality of logic operation units (such as 139), and a plurality of charge sharing. Switch unit (such as 141). In this embodiment, the voltage comparison circuit (such as 135), the logic operation unit (such as 139), and the charge sharing switch unit (such as 141) are disposed in the source driver 130, but in other embodiments, the voltage comparison circuit ( For example, 135), one of the logical operation unit (such as 139), and a part or all of the charge-sharing switch unit (such as 141) may be disposed outside the source driver, and the embodiment of the present invention is not limited thereto.
線緩衝器131耦接時序控制器110，以從時序控制器110接收列顯示資料RDD。資料通道(如133、137)及電壓比較電路(如135)耦接線緩衝器131，以從線緩衝器131接收對應的顯示資料(如D1及D2)。在本實施例中，線緩衝器131為選擇性的元件，亦即在其他實施例中，可透過其他元件替代線緩衝器131。並且，資料通道(如133、137)會依據閂鎖信號LP輸出對應所接收的顯示資料(如D1及D2)的驅動電壓(如VP1及VP2)，電壓比較電路(如135)則依據所接收的顯示資料(如D1及D2)來判斷電荷分享是否能節省電力，並據此產生電壓比較信號VCS。The line buffer 131 is coupled to the timing controller 110 to receive the column display material RDD from the timing controller 110. A data channel (e.g., 133, 137) and a voltage comparison circuit (e.g., 135) are coupled to the line buffer 131 to receive corresponding display data (e.g., D1 and D2) from the line buffer 131. In the present embodiment, the line buffer 131 is an optional component, that is, in other embodiments, the line buffer 131 can be replaced by other components. Moreover, the data channel (such as 133, 137) outputs a driving voltage (such as VP1 and VP2) corresponding to the received display data (such as D1 and D2) according to the latch signal LP, and the voltage comparison circuit (such as 135) is received according to the received signal. The display data (such as D1 and D2) to determine whether charge sharing can save power, and accordingly generate a voltage comparison signal VCS.
電荷分享開關單元(如141)具有第一端(如141a)、第二端(如141b)及控制端(如141c)。第一端(如141a)耦接一資料通道(如133)的輸出端，第二端(如141b)耦接另一資料通道(如137)的輸出端。邏輯運算單元(如139)耦接時序控制器110、電壓比較電路(如135)及電荷分享開關單元(如141)的控制端(如141c)，並且依據電壓比較信號VCS與閂鎖信號LP(即電荷分享信號)控制電壓分享開關單元(如141)導通其第一端(如141a)及第二端(如141b)。The charge sharing switch unit (e.g., 141) has a first end (e.g., 141a), a second end (e.g., 141b), and a control end (e.g., 141c). The first end (such as 141a) is coupled to the output of a data channel (such as 133), and the second end (such as 141b) is coupled to the output of another data channel (such as 137). The logic operation unit (such as 139) is coupled to the timing controller 110, the voltage comparison circuit (such as 135), and the control terminal (such as 141c) of the charge sharing switch unit (such as 141), and according to the voltage comparison signal VCS and the latch signal LP ( That is, the charge sharing signal) controls the voltage sharing switch unit (such as 141) to turn on its first end (such as 141a) and the second end (such as 141b).
在本實施例中，線緩衝器131會持續自時序控制器110接收列顯示資料RDD，以將顯示資料(如D1及D2)持續提供至對應的資料通道(如133、137)及對應的電壓比較電路(如135)，而每一資料通道(如133、137)會依據閂鎖LP持續輸出對應所接收的顯示資料(如D1及D2)的驅動電壓(如VP1及VP2)，每一電壓比較電路(如135)則依據持續接收的這些顯示資料(如D1及D2)輸出電壓比較信號VCS以決定是否透過邏輯運算單元(如139)遮罩閂鎖信號LP。In this embodiment, the line buffer 131 continuously receives the column display data RDD from the timing controller 110 to continuously provide the display data (such as D1 and D2) to the corresponding data channel (such as 133, 137) and the corresponding voltage. Comparing circuits (such as 135), and each data channel (such as 133, 137) continuously outputs driving voltages (such as VP1 and VP2) corresponding to the received display data (such as VP1 and VP2) according to the latch LP, each voltage The comparison circuit (such as 135) outputs a voltage comparison signal VCS according to the continuously received display data (such as D1 and D2) to determine whether to block the latch signal LP through the logic operation unit (such as 139).
每一邏輯運算單元(如139)包括及閘A1，及閘A1的第一輸入端a耦接時序控制器110以接收閂鎖信號LP，及閘A1的第二輸入端b耦接電壓比較電路(如135)以接收電壓比較信號VCS，及閘A1的輸出端c耦接電荷分享開關單元(如141)的控制端(如141c)。每一電荷分享開關單元(如141)包括電晶體M1，電晶體M1的源極作為電荷分享開關單元(如141)的第一端(如141a)，電晶體M1的汲極作為電荷分享開關單元(如141)的第二端(如141b)，電晶體M1的閘極作為電荷分享開關單元(如141)的控制端(如141c)。在本實施例中，電晶體M1以NMOS電晶體為例，但在其他實施例中，電晶體M1可以為PMOS電晶體，而邏輯運算單元則對應地配置反及閘。Each logic operation unit (such as 139) includes a gate A1, and a first input terminal a of the gate A1 is coupled to the timing controller 110 to receive the latch signal LP, and a second input terminal b of the gate A1 is coupled to the voltage comparison circuit. (eg, 135) to receive the voltage comparison signal VCS, and the output terminal c of the gate A1 is coupled to the control terminal (such as 141c) of the charge sharing switch unit (such as 141). Each charge sharing switch unit (such as 141) includes a transistor M1 having a source as a first end of a charge sharing switch unit (such as 141) (such as 141a) and a drain of the transistor M1 as a charge sharing switch unit. At the second end (e.g., 141b), the gate of transistor M1 acts as the control terminal (e.g., 141c) of the charge sharing switch unit (e.g., 141). In the present embodiment, the transistor M1 is exemplified by an NMOS transistor, but in other embodiments, the transistor M1 may be a PMOS transistor, and the logic operation unit is correspondingly configured with a NAND gate.
圖2為圖1依據本發明一實施例的顯示裝置的驅動時序示意圖。請參照圖1及圖2，在本實施例中，是以資料通道133(即第一資料通道)、相鄰於資料通道133的資料通道137(即第二資料通道)、電壓比較電路135、邏輯運算單元139及電荷分享開關單元141為例來說明。並且，本實施例是以兩列反轉的技術來驅動顯示面板150，但在其他實施例中可以為多列反轉技術或1+N列反轉技術，其中N為大於1的正整數。FIG. 2 is a schematic diagram showing the driving sequence of the display device according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the embodiment, the data channel 133 (ie, the first data channel), the data channel 137 adjacent to the data channel 133 (ie, the second data channel), the voltage comparison circuit 135, The logic operation unit 139 and the charge sharing switch unit 141 are described as an example. Moreover, the present embodiment drives the display panel 150 in a two-column inversion technique, but in other embodiments may be a multi-column inversion technique or a 1+N column inversion technique, where N is a positive integer greater than one.
依據圖2所示，資料通道133依據對應列顯示資料RDD1的前一列顯示資料(未繪示)的顯示資料D1而輸出驅動電壓VP11，資料通道137依據對應列顯示資料RDD1的前一列顯示資料(未繪示)的顯示資料D2而輸出驅動電壓VP21。According to FIG. 2, the data channel 133 outputs the driving voltage VP11 according to the display data D1 of the previous column display data (not shown) of the corresponding column display data RDD1, and the data channel 137 displays the data according to the previous column of the corresponding column display data RDD1 ( The display data D2 is outputted by the display data D2 (not shown).
當線緩衝器131接收到列顯示資料RDD1時，會分別輸出對應列顯示資料RDD1的顯示資料D1及D2至資料通道133及137，並且輸出對應列顯示資料RDD1的顯示資料D1及D2至電壓比較電路135。當線緩衝器131完全接收列顯示資料RDD1且經過時間T1時，閂鎖信號LP會致能(例如為高電壓準位)，其中時間T1約為100奈秒(ns)，並且閂鎖信號LP的致能期間T2約為200奈秒(ns)。並且，於致能期間T2結束且閂鎖信號LP由致能改變為禁能(例如為低電壓準位)時，資料通道133及137會分別輸出驅動電壓VP12及VP22。When the line buffer 131 receives the column display data RDD1, the display data D1 and D2 of the corresponding column display data RDD1 are respectively output to the data channels 133 and 137, and the display data D1 and D2 of the corresponding column display data RDD1 are output to the voltage comparison. Circuit 135. When the line buffer 131 completely receives the column display material RDD1 and elapses time T1, the latch signal LP is enabled (eg, at a high voltage level), wherein the time T1 is approximately 100 nanoseconds (ns), and the latch signal LP The enabling period T2 is approximately 200 nanoseconds (ns). Moreover, when the enable period T2 ends and the latch signal LP is changed from enabled to disabled (eg, low voltage level), the data channels 133 and 137 output the drive voltages VP12 and VP22, respectively.
依據圖2所示，基於共同電壓Vcom，驅動電壓VP12的極性相同於驅動電壓VP11的極性，驅動電壓VP22的極性相同於驅動電壓VP21的極性，而驅動電壓VP11及VP12的極性相反於驅動電壓VP21及VP22的極性，但在其他實施例中，驅動電壓VP11及VP12的極性可相同於驅動電壓VP21及VP22的極性。According to FIG. 2, based on the common voltage Vcom, the polarity of the driving voltage VP12 is the same as the polarity of the driving voltage VP11, the polarity of the driving voltage VP22 is the same as the polarity of the driving voltage VP21, and the polarities of the driving voltages VP11 and VP12 are opposite to the driving voltage VP21. And the polarity of VP22, but in other embodiments, the driving voltages VP11 and VP12 may have the same polarity as the driving voltages VP21 and VP22.
在致能期間T2中，電晶體M1是否導通決定於電壓比較電路135輸出的電壓比較信號VCS是否為致能。在電壓比較電路135接收到對應列顯示資料RDD1的顯示資料D1及D2後，會執行下列程式以判斷在閂鎖信號LP致能的期間T2進行電荷分享是否能節省電力，以決定電壓比較信號VCS為致能(即”H”)或禁能(即”L”)。In the enable period T2, whether or not the transistor M1 is turned on depends on whether or not the voltage comparison signal VCS output from the voltage comparison circuit 135 is enabled. After the voltage comparison circuit 135 receives the display data D1 and D2 of the corresponding column display data RDD1, the following program is executed to determine whether the charge sharing during the period T2 when the latch signal LP is enabled can save power to determine the voltage comparison signal VCS. To enable (ie "H") or disable (ie "L").
PAR1=IF((VP12-(VP11+VP21)/2)<0,0,VP12-(VP11+VP21)/2)─(1)PAR1=IF((VP12-(VP11+VP21)/2)<0,0,VP12-(VP11+VP21)/2)─(1)
PAR2=IF((VP22-(VP11+VP21)/2)<0,0,VP22-(VP11+VP21)/2)─(2)PAR2=IF((VP22-(VP11+VP21)/2)<0,0, VP22-(VP11+VP21)/2)-(2)
PAR3=IF((VP12-VP11)<0,0,VP12-VP11)─(3)PAR3=IF((VP12-VP11)<0,0,VP12-VP11)-(3)
PAR4=IF((VP22-VP21)<0,0,VP22-VP21)─(4)PAR4=IF((VP22-VP21)<0,0,VP22-VP21)-(4)
(PAR1+PAR2)<(PAR3+PAR4)=>”H”─(5)(PAR1+PAR2)<(PAR3+PAR4)=>"H"-(5)
(PAR1+PAR2)≧(PAR3+PAR4)=>”L”─(6)(PAR1+PAR2)≧(PAR3+PAR4)=>”L”—(6)
其中，驅動電壓VP11(即當下第一驅動電壓)及VP21(即當下第二驅動電壓)的平均值即為中和電壓VA1(即(VP11+VP21)/2)。The average value of the driving voltage VP11 (ie, the current first driving voltage) and the VP21 (ie, the current second driving voltage) is the neutralization voltage VA1 (ie, (VP11+VP21)/2).
在本實施例中，電壓比較電路135可依據對應列顯示資料RDD1的前一列顯示資料(未繪示)的顯示資料D1計算出驅動電壓VP11，依據對應列顯示資料RDD1的前一列顯示資料(未繪示)的顯示資料D1計算出驅動電壓VP21，依據對應列顯示資料RDD1的顯示資料D1計算出驅動電壓VP12，依據對應列顯示資料RDD1的顯示資料D2計算出驅動電壓VP22。在其他實施例中，電壓比較電路135可透過資料通道133及137取得驅動電壓VP11、VP12、VP21及VP22，在本發明實施例不以此為限。In this embodiment, the voltage comparison circuit 135 can calculate the driving voltage VP11 according to the display data D1 of the previous column display data (not shown) of the corresponding column display data RDD1, and display the data according to the previous column of the corresponding column display data RDD1 (not The display data D1 of the drawing) calculates the driving voltage VP21, calculates the driving voltage VP12 based on the display data D1 of the corresponding column display data RDD1, and calculates the driving voltage VP22 based on the display data D2 of the corresponding column display data RDD1. In other embodiments, the voltage comparison circuit 135 can obtain the driving voltages VP11, VP12, VP21, and VP22 through the data channels 133 and 137, which are not limited thereto.
在程式(1)中，驅動電壓VP12(即目標第一驅動電壓)小於中和電壓VA1時，電壓比較電路135設定第一參數PAR1為零；當驅動電壓VP12大於等於中和電壓VA1時，電壓比較電路135設定第一參數PAR1為驅動電壓VP12與中和電壓VA1的壓差(即第一壓差)。依據圖2所示，驅動電壓VP12大於中和電壓VA1，因此第一參數PAR1設定為驅動電壓VP12與中和電壓VA1的壓差。In the program (1), when the driving voltage VP12 (ie, the target first driving voltage) is less than the neutralization voltage VA1, the voltage comparison circuit 135 sets the first parameter PAR1 to be zero; when the driving voltage VP12 is greater than or equal to the neutralization voltage VA1, the voltage The comparison circuit 135 sets the first parameter PAR1 to the voltage difference between the driving voltage VP12 and the neutralization voltage VA1 (ie, the first voltage difference). According to FIG. 2, the driving voltage VP12 is greater than the neutralization voltage VA1, so the first parameter PAR1 is set to the voltage difference between the driving voltage VP12 and the neutralization voltage VA1.
在程式(2)中，當驅動電壓VP22(即目標第二驅動電壓)小於中和電壓VA1時，電壓比較電路135設定第二參數PAR2為零；當驅動電壓VP22大於等於中和電壓VA1時，電壓比較電路135設定第二參數PAR2為驅動電壓VP22與中和電壓VA1的壓差(即第二壓差)。依據圖2所示，驅動電壓VP22小於中和電壓VA1，因此第二參數PAR2設定為零。In the program (2), when the driving voltage VP22 (ie, the target second driving voltage) is less than the neutralization voltage VA1, the voltage comparison circuit 135 sets the second parameter PAR2 to be zero; when the driving voltage VP22 is greater than or equal to the neutralization voltage VA1, The voltage comparison circuit 135 sets the second parameter PAR2 to the voltage difference between the driving voltage VP22 and the neutralization voltage VA1 (ie, the second voltage difference). According to FIG. 2, the driving voltage VP22 is smaller than the neutralization voltage VA1, so the second parameter PAR2 is set to zero.
在程式(3)中，當驅動電壓VP12小於驅動電壓VP11時，電壓比較電路135設定第三參數PAR3為零；當驅動電壓VP12大於等於當下驅動電壓VP11時，電壓比較電路135設定第三參數PAR3為驅動電壓VP12與驅動電壓VP11的壓差(即第三壓差)。依據圖2所示，驅動電壓VP22大於驅動電壓VP11，因此第三參數PAR3設定為驅動電壓VP12與驅動電壓VP11的壓差。In the routine (3), when the driving voltage VP12 is smaller than the driving voltage VP11, the voltage comparison circuit 135 sets the third parameter PAR3 to be zero; when the driving voltage VP12 is greater than or equal to the current driving voltage VP11, the voltage comparison circuit 135 sets the third parameter PAR3. It is the voltage difference between the driving voltage VP12 and the driving voltage VP11 (ie, the third voltage difference). According to FIG. 2, the driving voltage VP22 is greater than the driving voltage VP11, so the third parameter PAR3 is set to the voltage difference between the driving voltage VP12 and the driving voltage VP11.
在程式(4)中，當驅動電壓VP22小於驅動電壓VP21時，電壓比較電路135設定第四參數PAR4為零；當驅動電壓VP22大於等於驅動電壓VP21時，電壓比較電路135設定第四參數PAR4為驅動電壓VP22與驅動電壓VP21的壓差(即第四壓差)。依據圖2所示，驅動電壓VP22小於驅動電壓VP21，因此第四參數PAR4設定為零。In the program (4), when the driving voltage VP22 is smaller than the driving voltage VP21, the voltage comparison circuit 135 sets the fourth parameter PAR4 to be zero; when the driving voltage VP22 is greater than or equal to the driving voltage VP21, the voltage comparison circuit 135 sets the fourth parameter PAR4 to The voltage difference between the driving voltage VP22 and the driving voltage VP21 (ie, the fourth voltage difference). According to FIG. 2, the driving voltage VP22 is smaller than the driving voltage VP21, so the fourth parameter PAR4 is set to zero.
在程式(5)中，當第一參數PAR1與第二參數PAR2的總和小於第三參數PAR3與第四參數PAR4的總和時，電壓比較電路135設定電壓比較信號VCS為致能，亦即輸出致能的電壓比較信號VCS。在程式(6)中，當第一參數PAR1與第二參數PAR2的總和大於等於第三參數PAR3與第四參數PAR4的總和時，電壓比較電路135設定電壓比較信號VCS為禁能，亦即輸出禁能的電壓比較信號VCS。依據圖2所示，驅動電壓VP12與中和電壓VA1的壓差大於驅動電壓VP12與驅動電壓VP11的壓差，因此第一參數PAR1與第二參數PAR2的總和大於等於第三參數PAR3與第四參數PAR4的總和，據此電壓比較電路135會輸出禁能的電壓比較信號VCS。依據上述，在致能期間T2中不會進行電荷分享，亦即電晶體M1不會導通，以避免電荷分享造成電耗增加。In the routine (5), when the sum of the first parameter PAR1 and the second parameter PAR2 is smaller than the sum of the third parameter PAR3 and the fourth parameter PAR4, the voltage comparison circuit 135 sets the voltage comparison signal VCS to enable, that is, outputs The voltage can compare the signal VCS. In the routine (6), when the sum of the first parameter PAR1 and the second parameter PAR2 is greater than or equal to the sum of the third parameter PAR3 and the fourth parameter PAR4, the voltage comparison circuit 135 sets the voltage comparison signal VCS to be disabled, that is, the output. The disabled voltage compares the signal VCS. According to FIG. 2, the voltage difference between the driving voltage VP12 and the neutralization voltage VA1 is greater than the voltage difference between the driving voltage VP12 and the driving voltage VP11, so the sum of the first parameter PAR1 and the second parameter PAR2 is greater than or equal to the third parameter PAR3 and the fourth. The sum of the parameters PAR4, according to which the voltage comparison circuit 135 outputs the disabled voltage comparison signal VCS. According to the above, charge sharing is not performed during the enable period T2, that is, the transistor M1 is not turned on to avoid an increase in power consumption due to charge sharing.
簡單來說，依據程式(1)至(5)所述，電壓比較電路135會依據中和電壓VA1與驅動電壓VP12的壓差、中和電壓VA1與驅動電壓VP22的壓差、驅動電壓VP11與驅動電壓VP12的壓差及驅動電壓VP21與驅動電壓VP22的壓差產生電壓比較信號VCS。Briefly, according to the programs (1) to (5), the voltage comparison circuit 135 is based on the voltage difference between the neutralization voltage VA1 and the driving voltage VP12, the voltage difference between the neutralization voltage VA1 and the driving voltage VP22, and the driving voltage VP11. The voltage difference of the driving voltage VP12 and the voltage difference between the driving voltage VP21 and the driving voltage VP22 generate a voltage comparison signal VCS.
當線緩衝器131接收到列顯示資料RDD2時，會分別輸出對應列顯示資料RDD2的顯示資料D1及D2至資料通道133及137，並且輸出對應列顯示資料RDD2的顯示資料D1及D2至電壓比較電路135。並且，於致能期間T3結束時，資料通道133及137會分別輸出驅動電壓VP13及VP23。依據上述，將驅動電壓VP12替代程式(1)及(3)的驅動電壓VP11，將驅動電壓VP13替代程式(1)及(3)的驅動電壓VP12，將驅動電壓VP22替代程式(2)及(4)的驅動電壓VP21，將驅動電壓VP23替代程式(2)及(4)的驅動電壓VP22。When the line buffer 131 receives the column display data RDD2, the display data D1 and D2 of the corresponding column display data RDD2 are respectively output to the data channels 133 and 137, and the display data D1 and D2 of the corresponding column display data RDD2 are output to the voltage comparison. Circuit 135. Moreover, at the end of the enable period T3, the data channels 133 and 137 output the drive voltages VP13 and VP23, respectively. According to the above, the driving voltage VP12 is substituted for the driving voltages VP11 of the programs (1) and (3), and the driving voltage VP13 is substituted for the driving voltages VP12 of the programs (1) and (3), and the driving voltage VP22 is substituted for the programs (2) and ( The driving voltage VP21 of 4) replaces the driving voltage VP23 of the programs (2) and (4) with the driving voltage VP23.
依據圖2所示，第一參數PAR1會設定為零，第二參數PAR2會設定為驅動電壓VP23與中和電壓VA2(即驅動電壓VP12與VP22的平均值)的壓差，第三參數PAR3會設定為零，第四參數PAR4會設定為驅動電壓VP23與驅動電壓VP22的壓差。由於驅動電壓VP23與中和電壓VA2的壓差小於驅動電壓VP23與驅動電壓VP22的壓差，因此程式(5)會被執行，藉此電壓比較電路135會輸出致能的電壓比較信號VCS。依據上述，在致能期間T3中會進行電荷分享，亦即電晶體M1會導通，以透過電荷分享降低電耗。According to FIG. 2, the first parameter PAR1 is set to zero, and the second parameter PAR2 is set to the voltage difference between the driving voltage VP23 and the neutralization voltage VA2 (ie, the average value of the driving voltages VP12 and VP22), and the third parameter PAR3 will be Set to zero, the fourth parameter PAR4 is set to the voltage difference between the driving voltage VP23 and the driving voltage VP22. Since the voltage difference between the driving voltage VP23 and the neutralization voltage VA2 is smaller than the voltage difference between the driving voltage VP23 and the driving voltage VP22, the routine (5) is executed, whereby the voltage comparison circuit 135 outputs the enabled voltage comparison signal VCS. According to the above, charge sharing is performed during the enable period T3, that is, the transistor M1 is turned on to reduce power consumption through charge sharing.
依此類推，在致能期間T4結束時，資料通道133及137會分別輸出對應列顯示資料RDD3的顯示資料D1及D2的驅動電壓VP14及VP24。由於驅動電壓VP24與中和電壓VA3的壓差等於驅動電壓VP14與驅動電壓VP13的壓差與驅動電壓VP24與驅動電壓VP23的壓差的總和，因此電壓比較電路135會輸出禁能的電壓比較信號VCS。依據上述，在致能期間T4中不會進行電荷分享，亦即電晶體M1不會導通，以避免電荷分享造成電耗增加。Similarly, at the end of the enabling period T4, the data channels 133 and 137 respectively output the driving voltages VP14 and VP24 of the display data D1 and D2 of the corresponding column display data RDD3. Since the voltage difference between the driving voltage VP24 and the neutralization voltage VA3 is equal to the sum of the voltage difference between the driving voltage VP14 and the driving voltage VP13 and the voltage difference between the driving voltage VP24 and the driving voltage VP23, the voltage comparison circuit 135 outputs the disabled voltage comparison signal. VCS. According to the above, charge sharing is not performed during the enable period T4, that is, the transistor M1 is not turned on to avoid an increase in power consumption due to charge sharing.
在致能期間T5結束時，資料通道133及137會分別輸出對應列顯示資料RDD4的顯示資料D1及D2的驅動電壓VP15及VP25。由於驅動電壓VP15與中和電壓VA4的壓差小於驅動電壓VP25與驅動電壓VP24的壓差，因此電壓比較電路135會輸出致能的電壓比較信號VCS。依據上述，在致能期間T5中會進行電荷分享，亦即電晶體M1會導通，以透過電荷分享降低電耗。At the end of the enable period T5, the data channels 133 and 137 respectively output the drive voltages VP15 and VP25 of the display data D1 and D2 of the corresponding column display data RDD4. Since the voltage difference between the driving voltage VP15 and the neutralization voltage VA4 is smaller than the voltage difference between the driving voltage VP25 and the driving voltage VP24, the voltage comparison circuit 135 outputs the enabled voltage comparison signal VCS. According to the above, charge sharing is performed during the enable period T5, that is, the transistor M1 is turned on to reduce power consumption through charge sharing.
綜上所述，本發明實施例的顯示裝置，其增加電壓比較電路及邏輯運算單元。電壓比較電路可判斷進行電荷分享會增加電耗或減少電耗，在進行電荷分享會增加電耗的情況下透過邏輯運算單元遮罩閂鎖信號(即電荷分享信號)，以使電荷分享不會被執行。藉此，可避免電荷分享造成電耗增加。In summary, the display device of the embodiment of the invention adds a voltage comparison circuit and a logic operation unit. The voltage comparison circuit can determine that performing charge sharing increases power consumption or reduces power consumption, and masks a latch signal (ie, a charge sharing signal) through a logic operation unit when charge sharing increases power consumption, so that charge sharing does not occur. Executed. Thereby, the electric power consumption caused by the charge sharing can be avoided.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．顯示裝置100. . . Display device
110．．．時序控制器110. . . Timing controller
120．．．閘極驅動器120. . . Gate driver
130．．．源極驅動器130. . . Source driver
131．．．線緩衝器131. . . Line buffer
133、137．．．資料通道133, 137. . . Data channel
135．．．電壓比較電路135. . . Voltage comparison circuit
139．．．邏輯運算單元139. . . Logical unit
141．．．電荷分享開關單元141. . . Charge sharing switch unit
141a．．．第一端141a. . . First end
141b．．．第二端141b. . . Second end
141c．．．控制端141c. . . Control terminal
150．．．顯示面板150. . . Display panel
A1．．．及閘A1. . . Gate
a．．．第一輸入端a. . . First input
b．．．第二輸入端b. . . Second input
c．．．輸出端c. . . Output
D1、D2．．．顯示資料D1, D2. . . Display data
LP．．．閂鎖信號(電荷分享信號)LP. . . Latch signal (charge sharing signal)
M1．．．電晶體M1. . . Transistor
RDD、RDD1~RDD4．．．列顯示資料RDD, RDD1~RDD4. . . Column display data
SC．．．掃描信號SC. . . Scanning signal
T1．．．時間T1. . . time
T2~T5．．．致能期間T2~T5. . . During the enablement period
VA1~VA4．．．中和電壓VA1~VA4. . . Neutralization voltage
Vcom．．．共同電壓Vcom. . . Common voltage
VP1、VP2、VP11~VP15、VP21~VP25．．．驅動電壓VP1, VP2, VP11~VP15, VP21~VP25. . . Driving voltage
圖1為依據本發明一實施例的顯示裝置的系統示意圖。1 is a system diagram of a display device in accordance with an embodiment of the present invention.
圖2為圖1依據本發明一實施例的顯示裝置的驅動時序示意圖。FIG. 2 is a schematic diagram showing the driving sequence of the display device according to an embodiment of the invention.
100．．．顯示裝置100. . . Display device
110．．．時序控制器110. . . Timing controller
120．．．閘極驅動器120. . . Gate driver
130．．．源極驅動器130. . . Source driver
131．．．線緩衝器131. . . Line buffer
133、137．．．資料通道133, 137. . . Data channel
135．．．電壓比較電路135. . . Voltage comparison circuit
139．．．邏輯運算單元139. . . Logical unit
141．．．電荷分享開關單元141. . . Charge sharing switch unit
141a．．．第一端141a. . . First end
141b．．．第二端141b. . . Second end
141c．．．控制端141c. . . Control terminal
150．．．顯示面板150. . . Display panel
A1．．．及閘A1. . . Gate
a．．．第一輸入端a. . . First input
b．．．第二輸入端b. . . Second input
c．．．輸出端c. . . Output
D1、D2．．．顯示資料D1, D2. . . Display data
LP．．．閂鎖信號(電荷分享信號)LP. . . Latch signal (charge sharing signal)
M1．．．電晶體M1. . . Transistor
RDD．．．列顯示資料RDD. . . Column display data
SC．．．掃描信號SC. . . Scanning signal
VP1、VP2．．．驅動電壓VP1, VP2. . . Driving voltage
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125465A TWI435312B (en) | 2011-07-19 | 2011-07-19 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125465A TWI435312B (en) | 2011-07-19 | 2011-07-19 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201306001A true TW201306001A (en) | 2013-02-01 |
| TWI435312B TWI435312B (en) | 2014-04-21 |
Family
ID=48169240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100125465A TWI435312B (en) | 2011-07-19 | 2011-07-19 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI435312B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI464721B (en) * | 2012-03-27 | 2014-12-11 | Novatek Microelectronics Corp | Display driving optimization method and display driver |
| CN109389930A (en) * | 2017-08-04 | 2019-02-26 | 硅工厂股份有限公司 | For showing the low-power drive system and sequence controller of equipment |
-
2011
- 2011-07-19 TW TW100125465A patent/TWI435312B/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI464721B (en) * | 2012-03-27 | 2014-12-11 | Novatek Microelectronics Corp | Display driving optimization method and display driver |
| CN109389930A (en) * | 2017-08-04 | 2019-02-26 | 硅工厂股份有限公司 | For showing the low-power drive system and sequence controller of equipment |
| CN109389930B (en) * | 2017-08-04 | 2023-08-15 | 硅工厂股份有限公司 | Low power driving system and timing controller for display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI435312B (en) | 2014-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10916213B2 (en) | Shift register and method for driving the same, gate driving circuit, and display device | |
| US10074330B2 (en) | Scan driver and display panel using the same | |
| US9779646B2 (en) | Shift register, method and system for operating shift register | |
| US10403222B2 (en) | Gate driver on array circuit having clock-controlled inverter and LCD panel | |
| US9892703B2 (en) | Output circuit, data driver, and display device | |
| US11373613B2 (en) | Shift register unit including pull-up node state maintenance circuit, driving method thereof, gate driving circuit and display device | |
| KR100596091B1 (en) | Driver circuit and shift register of display device and display device | |
| JP4480944B2 (en) | Shift register and display device using the same | |
| US9824658B2 (en) | GOA circuit and liquid crystal display device | |
| US20180108320A1 (en) | Gate driving circuit, display panel and display apparatus having the same, and driving method thereof | |
| US20170169780A1 (en) | Scan driving circuit and liquid crystal display device having the circuit | |
| TWI411989B (en) | Display driving circuit and method | |
| TWI434254B (en) | Gate pulse modulation circuit and angle modulating method thereof | |
| US20180040273A1 (en) | Shift register unit, driving method, gate driving circuit and display apparatus | |
| TWI681380B (en) | Gate driver and display apparatus thereof | |
| CN102262850B (en) | Display device | |
| TW201417082A (en) | Self-detection charge sharing module | |
| US9805638B2 (en) | Shift register, array substrate and display apparatus | |
| US9159448B2 (en) | Shift register unit, shift register and scanning method thereof, and display device | |
| TWI518666B (en) | Display apparatus and common voltage generator thereof | |
| TWI435312B (en) | Display device | |
| US11322063B2 (en) | Scan driving circuit and driving method thereof, and display device | |
| JP2013041029A (en) | Liquid crystal drive circuit | |
| TWI515709B (en) | Display device and discharge control circuit thereof | |
| US10140943B2 (en) | Thin film transistor drive circuit and drive method thereof and liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |