TW201304104A - TSV structure and method for forming the same - Google Patents
TSV structure and method for forming the same Download PDFInfo
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本發明係關於一種矽穿孔結構以及形成矽穿孔結構的方法。本發明特別是關於一種在製作互補金氧半導體之前，先製作穿孔洞介電層，然後在完成互補金氧半導體之後才著手製作矽穿孔結構之方法，以避免後段製程(BEOL)影響矽穿孔結構而產生電阻劣化(pumping)的問題，同時還可以避免晶圓薄化時銅污染的問題。The present invention relates to a ruthenium perforated structure and a method of forming a ruthenium perforated structure. More particularly, the present invention relates to a method for fabricating a via dielectric layer prior to fabrication of a complementary gold oxide semiconductor, and then completing the fabrication of the tantalum via structure after completion of the complementary gold oxide semiconductor to prevent the back end of the process (BEOL) from affecting the tantalum perforated structure. The problem of resistance degradation occurs, and at the same time, the problem of copper contamination during wafer thinning can be avoided.
矽穿孔技術(TSV)是一種新穎的半導體技術。矽貫通電極技術主要在於解決晶片間互連的問題，屬於一種新的三度空間立體封裝技術。當紅的矽穿孔技術藉由三度空間的堆疊、經由矽穿孔創造出更符合輕、薄、短、小之市場需求產品，提供微機電系統(MEMS)、光電及電子元件等晶圓級封裝所需之封裝製程技術。Tantalum Perforation Technology (TSV) is a novel semiconductor technology.矽Through-electrode technology mainly solves the problem of interconnection between wafers, and belongs to a new three-dimensional space three-dimensional packaging technology. The popular 矽 矽 技术 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉 藉Packaging process technology required.
矽穿孔技術是在晶圓上以蝕刻或雷射的方式鑽孔，再將導電材料如銅、多晶矽、鎢等填入導孔(Via)形成導電的通道(即連接內、外部的接合線路)。最後則將晶圓或晶粒(die)薄化再加以堆疊、結合(bonding)，而成為三度空間的堆疊積體電路(3D IC)。如此一來，就可以去除打線連結(wire bonding)方式。改以蝕刻或雷射的方式鑽孔(Via)並導通電極，不僅可以省去打線空間，也可以縮小了電路板的使用面積與封裝件的體積。The boring technique is to etch holes on the wafer by etching or laser, and then electrically conductive materials such as copper, polysilicon, tungsten, etc. are filled into the vias (Via) to form conductive channels (ie, internal and external bonding lines). . Finally, the wafer or die is thinned and then stacked and bonded to form a three-dimensional stacked integrated circuit (3D IC). In this way, the wire bonding method can be removed. By etching or lasering the Via and turning on the electrodes, not only can the wiring space be eliminated, but also the area of the board and the size of the package can be reduced.
由於採用矽穿孔技術的構裝內部接合距離，即為薄化後之晶圓或晶粒的厚度，相較於採取打線連結的傳統堆疊封裝，三度空間堆疊積體電路的內部連接路徑更短，相對可使晶片間的傳輸電阻更小、速度更快、雜訊更小、效能更佳。尤其在中央處理器(CPU)與快取記憶體，以及記憶卡應用中的資料傳輸上，更能突顯矽穿孔技術的短距離內部接合路徑所帶來的效能優勢。此外，三度空間堆疊積體電路封裝後的尺寸等同於晶粒尺寸。在強調多功能、小尺寸的可攜式電子產品領域，三度空間堆疊積體電路的小型化特性更是市場導入的首要因素。Due to the internal bonding distance of the boring perforation technology, that is, the thickness of the thinned wafer or the die, the internal connection path of the three-dimensional space-stacked integrated circuit is shorter than that of the conventional stacked package with wire bonding. Relatively, the transmission resistance between the wafers can be made smaller, the speed is faster, the noise is smaller, and the performance is better. Especially in the central processing unit (CPU) and cache memory, as well as data transfer in memory card applications, it can highlight the performance advantages of the short-distance internal bonding path of the perforation technology. In addition, the dimensions of the three-dimensional space-stacked integrated circuit package are equivalent to the grain size. In the field of portable electronic products that emphasize multi-function and small size, the miniaturization of three-dimensional space-stacked integrated circuits is the primary factor in market introduction.
以目前開發的技術及製程的先後順序而言，矽穿孔技術可以分為先鑽孔(via first)與後鑽孔(via last)兩大態樣。其中先鑽孔製程又可分為在金氧半導體前(before CMOS)與在金氧半導體後(after CMOS)兩種變化。在金氧半導體前的先鑽孔製程步驟，是在進行金氧半導體製程前，先行在矽晶圓基材上形成矽穿孔通道，並填入導電材料。為顧及後續金氧半導體步驟中的高溫製程，導電材料的選擇目前以較可承受後續金氧半導體高溫製程的多晶矽為主。而導電性更佳的銅等金屬，則會因為導電金屬在反覆接受高溫製程後(thermal process)會影響其電阻，而造成電阻劣化(pumping)的問題。就整體而言，在考慮到填導電材料後晶圓薄化製程的困難度時，此等在金氧半導體前進行的先鑽孔製程步驟，與傳統半導體製程技術的整合度與相容度較高，但是會有銅汙染與導電材料必需承受後續金氧半導體高溫製程的考量。In terms of the current development of technology and process sequence, the helium perforation technology can be divided into two aspects: first first and last last. The first drilling process can be divided into two types: before (before CMOS) and after CMOS. The first drilling process in front of the MOS semiconductor is to form a ruthenium perforation channel on the enamel wafer substrate and fill the conductive material before performing the MOS process. In order to take into account the high-temperature process in the subsequent MOS process, the selection of the conductive material is currently dominated by polycrystalline germanium which can withstand the subsequent high-temperature process of the MOS semiconductor. Metals such as copper, which are more conductive, cause a problem of resistance degradation because the conductive metal affects its resistance after repeated high-temperature processes. On the whole, when considering the difficulty of the wafer thinning process after filling the conductive material, the integration process and compatibility of the prior drilling process steps before the MOS semiconductor and the traditional semiconductor process technology are compared. High, but there will be copper pollution and conductive materials must be subject to the subsequent high-temperature process of MOS semiconductor.
而在金氧半導體後的先鑽孔製程步驟，則是在完成金氧半導體製程後，才開始進行導孔的成形製程並填入導電金屬。目前採用的導電金屬材料以導電特性優良的銅為多。而由於銅在填孔時容易產生底部未填滿但頂部已封口的現象，導致通道內出現空洞(void)而失效，因此亦有部份製造商以鎢(W)金屬為導電材料。總體來說，在金氧半導體後的先鑽孔製程步驟，由於金氧半導體已經完成，將銅填入導孔後的平坦化製程會特別困難，而且也有銅汙染的問題，這樣會增加此等製程步驟與傳統半導體製程技術整合與相容的困難度。In the first drilling process after the MOS, the forming process of the via hole is started and the conductive metal is filled after the MOS process is completed. The conductive metal materials currently used are mostly copper having excellent electrical conductivity. However, since copper is likely to be filled at the bottom of the hole but the top is sealed, voids in the channel are disabled, and some manufacturers use tungsten (W) metal as the conductive material. In general, in the first drilling process after MOS, since the MOS has been completed, the planarization process after copper is filled into the via hole is particularly difficult, and there is also a problem of copper contamination, which will increase this. The difficulty of integrating and compatible process steps with traditional semiconductor process technology.
另外，化學機械拋光步驟也會對於層間介電層造成影響。因此，仍然需要一種新穎的矽穿孔結構，以及製作矽穿孔結構的方法。既可以使用具有較佳導電性的銅來取代多晶矽作為矽穿孔結構中的導電材料，又不會礙於金氧半導體已經完成，反而造成將銅填入矽穿孔結構後，平坦化製程特別困難的問題。In addition, the chemical mechanical polishing step also affects the interlayer dielectric layer. Therefore, there is still a need for a novel perforated structure and a method of making a perforated structure. It is possible to use polysilicon with better conductivity instead of polysilicon as the conductive material in the perforated structure, without hindering the completion of the MOS, but the flattening process is particularly difficult after the copper is filled into the perforated structure. problem.
本發明於是提出一種新穎的矽穿孔結構，以及製作矽穿孔結構的方法。本發明新穎的矽穿孔結構，是一種無縫的矽穿孔結構。穿孔洞中的導電層與穿孔洞壁之間沒有習知矽材料的阻隔，所以在相同導電層尺寸而不影響元件電性的前提下，可以得到更小的矽穿孔結構尺寸。本發明新穎的矽穿孔結構，雖然使用具有較佳導電性的銅來取代多晶矽作為導電材料，但是不會有礙於金氧半導體已經完成，反而造成將銅填入矽貫通電極通道後，晶圓薄化製程特別困難與銅汙染的問題。另外，矽穿孔結構中的銅材料還可以避免因為反覆接受高溫製程，而造成電阻劣化(pumping)的問題。The present invention thus proposes a novel perforated structure and a method of making a perforated structure. The novel perforated structure of the present invention is a seamless perforated structure. There is no barrier between the conductive layer in the perforated hole and the wall of the perforated hole, so that the size of the same conductive layer can be obtained without affecting the electrical properties of the element. The novel ruthenium perforation structure of the present invention uses a copper having better conductivity instead of polysilicon as a conductive material, but does not hinder the completion of the MOS, but causes the copper to be filled into the 矽 through electrode channel. The thinning process is particularly difficult and the problem of copper contamination. In addition, the copper material in the perforated structure can also avoid the problem of resistance degradation due to repeated high temperature processes.
本發明首先提出一種新穎的矽穿孔結構。本發明的矽穿孔結構包含晶圓、穿孔洞、穿孔洞介電層、導電層、第一介電層與第二介電層。晶圓包含有基材、第一面與第二面，而穿孔洞位於晶圓中，並連通第一面與第二面。穿孔洞介電層則覆蓋穿孔洞之內壁。填入穿孔洞中之導電層係由單一導電材料所組成，而成為無縫的矽穿孔結構。第一介電層覆蓋第一面並環繞導電層，第二介電層則覆蓋第二面與部份之穿孔洞介電層，又部分為導電層所覆蓋。The present invention first proposes a novel perforated structure. The germanium perforated structure of the present invention comprises a wafer, a via hole, a via dielectric layer, a conductive layer, a first dielectric layer and a second dielectric layer. The wafer includes a substrate, a first side and a second side, and the through hole is located in the wafer and communicates with the first side and the second side. The perforated hole dielectric layer covers the inner wall of the perforated hole. The conductive layer filled in the perforated hole is composed of a single conductive material and becomes a seamless perforated structure. The first dielectric layer covers the first surface and surrounds the conductive layer, and the second dielectric layer covers the second surface and a portion of the via dielectric layer, and is partially covered by the conductive layer.
本發明其次提出一種矽穿孔結構。本發明的矽穿孔結構包含晶圓、穿孔洞、穿孔洞介電層、導電層、第一介電層、內連線結構與插塞。晶圓包含有基材、第一面與第二面，而穿孔洞位於晶圓中，並連通第一面與第二面。穿孔洞介電層則覆蓋穿孔洞之內壁。導電層填入穿孔洞中。第一介電層覆蓋第一面。內連線結構則位於第一介電層中並覆蓋導電層。另外，插塞穿過第一介電層，用來電連接導電層與內連線結構。The present invention secondly proposes a crucible perforation structure. The ruthenium perforated structure of the present invention comprises a wafer, a via hole, a via dielectric layer, a conductive layer, a first dielectric layer, an interconnect structure and a plug. The wafer includes a substrate, a first side and a second side, and the through hole is located in the wafer and communicates with the first side and the second side. The perforated hole dielectric layer covers the inner wall of the perforated hole. The conductive layer is filled into the perforated holes. The first dielectric layer covers the first side. The interconnect structure is located in the first dielectric layer and covers the conductive layer. In addition, the plug passes through the first dielectric layer for electrically connecting the conductive layer and the interconnect structure.
本發明又提出一種矽穿孔結構。本發明的矽穿孔結構包含晶圓、穿孔洞、基材柱、穿孔洞介電環、第一導電環與第一介電環。晶圓包含有第一面與第二面，而穿孔洞位於晶圓中，並連通第一面與第二面。基材柱填滿穿孔洞，而使得穿孔洞介電環得以直接接觸並圍繞基材柱。第一導電環直接接觸並圍繞穿孔洞介電環。第一介電環直接接觸並圍繞第一導電環，並又被晶圓所圍繞。The invention further proposes a crucible perforation structure. The crucible perforation structure of the present invention comprises a wafer, a perforation hole, a substrate post, a perforated hole dielectric ring, a first conductive ring and a first dielectric ring. The wafer includes a first side and a second side, and the perforated hole is located in the wafer and communicates with the first side and the second side. The substrate column fills the perforation holes so that the perforated hole dielectric ring is in direct contact and surrounds the substrate column. The first conductive ring directly contacts and surrounds the via hole dielectric ring. The first dielectric ring directly contacts and surrounds the first conductive ring and is surrounded by the wafer.
本發明再提出一種矽穿孔結構。本發明的矽穿孔結構包含晶圓、主動區域、穿孔洞、導電層、介電層、至少一主動元件、內連線結構與整體接觸。晶圓包含有第一面與第二面，而主動區域位於第一面上。穿孔洞位於晶圓中，並連通第一面與第二面。導電層填入穿孔洞中。介電層則覆蓋第一面。至少一主動元件位於主動區域中、介電層上與導電層之正上方。內連線結構則位於層間介電層中並位在至少一主動元件之上方。另外，整體接觸位於主動區域中、穿過介電層，以電連接導電層與內連線結構。The invention further proposes a crucible perforation structure. The ruthenium perforated structure of the present invention comprises a wafer, an active region, a via hole, a conductive layer, a dielectric layer, at least one active component, and an interconnect structure in overall contact. The wafer includes a first side and a second side, and the active area is on the first side. The perforated hole is located in the wafer and communicates with the first side and the second side. The conductive layer is filled into the perforated holes. The dielectric layer covers the first side. At least one active component is located in the active region, directly above the dielectric layer and the conductive layer. The interconnect structure is located in the interlayer dielectric layer and above the at least one active component. In addition, the overall contact is located in the active region through the dielectric layer to electrically connect the conductive layer to the interconnect structure.
本發明另外提出一種矽穿孔結構。本發明的矽穿孔結構包含晶圓、穿孔洞、穿孔洞介電層、導電層、介電層、導電帽蓋、內連線結構與插塞。晶圓包含有第一面與第二面，而穿孔洞位於晶圓中，並連通第一面與第二面。穿孔洞介電層則覆蓋穿孔洞之內壁。導電層填入穿孔洞中。介電層部分覆蓋第一面。導電帽蓋位於第一面上、介電層中、而且直接接觸並完全覆蓋導電層。內連線結構則位於介電層中並覆蓋導電帽蓋。另外，插塞位於介電層中，用來電連接導電帽蓋與內連線結構。The invention further provides a meandering perforation structure. The ruthenium perforated structure of the present invention comprises a wafer, a via hole, a via dielectric layer, a conductive layer, a dielectric layer, a conductive cap, an interconnect structure and a plug. The wafer includes a first side and a second side, and the perforated hole is located in the wafer and communicates with the first side and the second side. The perforated hole dielectric layer covers the inner wall of the perforated hole. The conductive layer is filled into the perforated holes. The dielectric layer partially covers the first side. The conductive cap is located on the first side, in the dielectric layer, and directly contacts and completely covers the conductive layer. The interconnect structure is located in the dielectric layer and covers the conductive cap. Additionally, the plug is located in the dielectric layer for electrically connecting the conductive cap to the interconnect structure.
本發明首先提供一種形成矽穿孔結構的新穎方法。本發明的新穎方法，是在金氧半導體已經完成之後，才將銅填入矽穿孔通道中，所以本發明不但使用導電性遠勝於多晶矽的銅來作為導電材料，又不會有礙於金氧半導體已經完成，反而造成將銅填入矽貫通電極通道後，晶圓薄化製程特別困難與銅汙染的問題。另外，矽穿孔結構中的銅材料在金氧半導體已經完成之後才形成，還可以避免因為反覆接受高溫製程，而造成電阻劣化(pumping)的問題。The present invention first provides a novel method of forming a perforated structure. The novel method of the present invention is to fill the copper perforation channel after the MOS has been completed, so the invention not only uses copper having conductivity much better than polysilicon as a conductive material, but also does not hinder gold. The oxygen semiconductor has been completed, which in turn causes the wafer thinning process to be particularly difficult and copper contamination after filling the copper through the via electrode channel. In addition, the copper material in the ruthenium perforated structure is formed after the MOS has been completed, and it is also possible to avoid the problem of resistance degradation due to the repeated acceptance of the high temperature process.
請參考第1-10圖，繪示本發明形成矽穿孔結構方法的示意圖。由於本發明形成矽穿孔結構的方法可以形成多種不同之矽穿孔結構，所以下述之方法可以有多種不同之實施方式。首先，請參考第1圖，首先提供晶圓103。晶圓103將用於形成矽穿孔結構，本身包含一半導體基材106，並具有相對之第一面101與第二面102，其中第一面101為半導體基材106的正面，用來製備各式半導體元件與金屬內連線，而第二面102則為半導體基材106的底面。半導體基材106可以為矽。Please refer to FIG. 1-10 for a schematic diagram of a method for forming a perforated structure according to the present invention. Since the method of forming a perforated structure of the present invention can form a plurality of different perforated structures, the following methods can be implemented in a variety of different ways. First, referring to FIG. 1, the wafer 103 is first provided. The wafer 103 will be used to form a tantalum perforated structure, itself comprising a semiconductor substrate 106, and having a first side 101 and a second side 102 opposite thereto, wherein the first side 101 is the front side of the semiconductor substrate 106 for preparing each The semiconductor component is interconnected with a metal and the second side 102 is the bottom surface of the semiconductor substrate 106. The semiconductor substrate 106 can be germanium.
其次，在本發明之第一實施態樣之中，可以在晶圓103中形成一環狀介電層110。環狀介電層110可以在淺溝渠隔離(圖未示)之形成步驟時一併完成。例如，可以使用微影與蝕刻步驟，在晶圓103中形成凹穴(圖未示)，以及用來分別界定環狀介電層110與淺溝渠(圖未示)，且可利用遮罩的開口大小與蝕刻條件來控制凹穴與淺溝渠的深度，較佳者，凹穴的深度大於淺溝渠的深度。隨後，使用一種介電材料，例如氧化矽，填入凹穴與淺溝渠之中再加以平坦化而分別得到所需之環狀介電層110與淺溝渠隔離(圖未示)。視情況需要，環狀介電層110之厚度可以為2微米-3微米。Next, in the first embodiment of the present invention, an annular dielectric layer 110 can be formed in the wafer 103. The annular dielectric layer 110 can be completed in the formation of shallow trench isolation (not shown). For example, a lithography and etching step can be used to form recesses (not shown) in the wafer 103, and to define the annular dielectric layer 110 and the shallow trenches (not shown), respectively, and can utilize a mask. The opening size and etching conditions are used to control the depth of the pockets and shallow trenches. Preferably, the depth of the pockets is greater than the depth of the shallow trenches. Subsequently, a dielectric material, such as yttria, is filled into the recesses and shallow trenches and planarized to provide the desired annular dielectric layer 110 from the shallow trenches (not shown). The thickness of the annular dielectric layer 110 may range from 2 microns to 3 microns, as desired.
請參考第1A圖，在本發明之第二實施態樣之中，可以在晶圓103中蝕刻出凹穴(圖未示)，用來容置後續形成之穿孔洞介電環、第一導電環與第一介電環。凹穴(圖未示)可以在淺溝渠隔離(圖未示)之形成步驟時一併完成。在凹穴(圖未示)形成後，即可以在凹穴側壁上形成一層絕緣層104，並繼續在凹穴(圖未示)之中填滿一導電材料而成為一導電層150，例如使用沉積的方式，填滿凹穴(圖未示)之中。俟絕緣層104與導電層150完成之後，晶圓103中部份之基材即位於絕緣層104與導電層150之間。Referring to FIG. 1A, in a second embodiment of the present invention, a cavity (not shown) may be etched into the wafer 103 for accommodating a subsequently formed via hole dielectric ring and a first conductive layer. The ring is connected to the first dielectric ring. The pockets (not shown) can be completed simultaneously in the formation of shallow trench isolation (not shown). After the recess (not shown) is formed, an insulating layer 104 may be formed on the sidewall of the recess, and a conductive material may be filled in the recess (not shown) to form a conductive layer 150, for example, The way of deposition fills the pocket (not shown). After the insulating layer 104 and the conductive layer 150 are completed, a portion of the substrate in the wafer 103 is located between the insulating layer 104 and the conductive layer 150.
在導電層150填滿凹穴(圖未示)之前，視情況需要，可以在絕緣層104之內壁上先形成障壁層(圖未示)與晶種層(圖未示)其中之至少一者，而覆蓋絕緣層104的表面。當導電層150為銅時，障壁層(圖未示)可以避免銅原子不良的擴散。晶種層(圖未示)則是可以誘導導電層150的沉積。Before the conductive layer 150 fills the recess (not shown), at least one of a barrier layer (not shown) and a seed layer (not shown) may be formed on the inner wall of the insulating layer 104 as occasion demands. The surface of the insulating layer 104 is covered. When the conductive layer 150 is copper, the barrier layer (not shown) can avoid poor diffusion of copper atoms. A seed layer (not shown) can induce deposition of the conductive layer 150.
視情況需要，請參考第1A圖，還可以在絕緣層104與導電層150的外圍再形成同心之至少一組導電層與介電層。例如，形成第二導電層150b與第二絕緣層104b。此時，也可以形成障壁層151與晶種層152。第二導電層150b會被絕緣層104所圍繞。第二絕緣層104b則會圍繞並直接接觸第二導電層150b，又為晶圓103所圍繞。形成同心之導電層與絕緣層的方法，可以參考前述之說明，在此故不多加贅述。If necessary, please refer to FIG. 1A, and at least one set of conductive layers and dielectric layers concentric may be formed on the periphery of the insulating layer 104 and the conductive layer 150. For example, the second conductive layer 150b and the second insulating layer 104b are formed. At this time, the barrier layer 151 and the seed layer 152 may also be formed. The second conductive layer 150b is surrounded by the insulating layer 104. The second insulating layer 104b then surrounds and directly contacts the second conductive layer 150b, which is again surrounded by the wafer 103. For the method of forming the concentric conductive layer and the insulating layer, reference may be made to the foregoing description, and thus no further description is provided herein.
然後，請參考第2圖，進行一半導體製程。此等半導體製程可以為任何適當之半導體製程，例如，經由此半導體製程而在第一面101上之主動區域中形成一半導體元件120，例如，半導體元件120其為至少一種主動元件。並在半導體元件120上形成覆蓋半導體元件120之層間介電層124，以及位於層間介電層124之上、而與半導體元件120電連接之內連線結構125。Then, please refer to Figure 2 for a semiconductor process. These semiconductor processes can be any suitable semiconductor process, for example, by forming a semiconductor component 120 in the active region on the first face 101 via the semiconductor process, for example, the semiconductor component 120 is at least one active component. An interlayer dielectric layer 124 covering the semiconductor device 120 and an interconnect structure 125 electrically connected to the semiconductor device 120 are formed on the semiconductor device 120.
在本實施例中，半導體元件120可包含閘極123與位於閘極123兩側之源極121與汲極122等。視情況需要，還可以在半導體元件120上形成蝕刻停止層或是應力層，然後再形成層間介電層124。內連線結構125即經由接觸插塞126，穿過層間介電層124而分別與位於第一面上相對應之閘極123、源極121與汲極122電連接。在形成源極121、汲極122、閘極123、層間介電層124、內連線結構125與接觸插塞126之過程中，會進行至少一次溫度高於380℃之高溫步驟，例如380℃-410℃之高溫步驟。層間介電層124可以包含一種介電材料，例如氧化矽。內連線結構125可以為經由鑲嵌步驟所形成之銅鑲嵌導電結構。接觸插塞126通常會包含鎢。In the present embodiment, the semiconductor device 120 may include a gate 123 and a source 121 and a drain 122 on both sides of the gate 123. An etch stop layer or a stress layer may be formed on the semiconductor device 120 as needed, and then the interlayer dielectric layer 124 may be formed. The interconnect structure 125 is electrically connected to the gate 123, the source 121 and the drain 122 corresponding to the first surface via the contact plug 126 via the interlayer dielectric layer 124. During the formation of the source 121, the drain 122, the gate 123, the interlayer dielectric layer 124, the interconnect structure 125 and the contact plug 126, at least one high temperature step of temperature above 380 ° C, such as 380 ° C, is performed. -410 ° C high temperature step. The interlayer dielectric layer 124 may comprise a dielectric material such as hafnium oxide. The interconnect structure 125 can be a copper damascene conductive structure formed via a damascene step. Contact plug 126 will typically contain tungsten.
接下來，請參考第3圖，待第一面101完成所需的各式半導體元件與金屬內連線之後，接著進行一晶圓薄化製程，以經由第二面102薄化晶圓103而暴露出環狀介電層110，使得環狀介電層110成為一穿孔洞介電層110。其可以使用研磨等的方式，移除部份之晶圓103而暴露出環狀介電層110。例如，請參考第3圖，可以使用有機材料，像是黏膠130，將晶圓103的第一面101與一載體131貼合，再進行研磨步驟，來移除部份之晶圓103而暴露出環狀介電層110。Next, referring to FIG. 3, after the first surface 101 completes various required semiconductor components and metal interconnections, a wafer thinning process is subsequently performed to thin the wafer 103 via the second surface 102. The annular dielectric layer 110 is exposed such that the annular dielectric layer 110 becomes a via dielectric layer 110. It is possible to remove a portion of the wafer 103 to expose the annular dielectric layer 110 by means of grinding or the like. For example, referring to FIG. 3, an organic material such as a glue 130 may be used to bond the first side 101 of the wafer 103 to a carrier 131, and then a grinding step is performed to remove a portion of the wafer 103. The annular dielectric layer 110 is exposed.
請參考第3A圖，例示第1A圖之結構進行過一晶圓薄化製程。在本發明之矽穿孔結構100中，基材106成為基材柱107、絕緣層104成為一穿孔洞介電環110與第一介電環114，而導電層150成為第一導電環113。在此矽穿孔結構100中，使用第一導電環113圍繞基材柱107而非導電層150位於同心結構的中心，以減低導電層150在受熱步驟中可能的膨脹變形。Please refer to FIG. 3A to illustrate the structure of FIG. 1A for a wafer thinning process. In the crucible structure 100 of the present invention, the substrate 106 becomes the substrate pillar 107, the insulating layer 104 becomes a via hole dielectric ring 110 and the first dielectric ring 114, and the conductive layer 150 becomes the first conductive ring 113. In this ruthenium perforated structure 100, a first conductive ring 113 is used around the substrate pillar 107 rather than the conductive layer 150 at the center of the concentric structure to reduce the possible expansion deformation of the conductive layer 150 during the heating step.
如果第1A圖之結構具有障壁層151及/或晶種層152，第3A圖中亦可見障壁層151與晶種層152。其可以使用研磨等的方式，移除部份之晶圓103、絕緣層104、導電層150而暴露出第一導電環113。If the structure of FIG. 1A has the barrier layer 151 and/or the seed layer 152, the barrier layer 151 and the seed layer 152 are also visible in FIG. 3A. It may remove a portion of the wafer 103, the insulating layer 104, and the conductive layer 150 to expose the first conductive ring 113 by means of grinding or the like.
第3B圖例示第二導電層150b與第二絕緣層104b進行過晶圓薄化製程之結果。第3B圖例示同心之圓環結構，其繪示晶圓103、穿孔洞111、基材柱107、穿孔洞介電環110、第一導電環113、第一介電環114、第二導電環115與第二介電環116。第二導電層150成為第二導電環115，而第二絕緣層104b成為第二介電環116。在本發明之矽穿孔結構100中，基材柱107填滿連通第一面101與第二面102之穿孔洞111。第二導電環115圍繞第一介電環114，而第二介電環116直接接觸並圍繞第二導電環115，又為晶圓103所圍繞。FIG. 3B illustrates the result of the wafer thinning process performed by the second conductive layer 150b and the second insulating layer 104b. FIG. 3B illustrates a concentric annular structure, which shows the wafer 103, the through hole 111, the substrate pillar 107, the through hole dielectric ring 110, the first conductive ring 113, the first dielectric ring 114, and the second conductive ring. 115 and the second dielectric ring 116. The second conductive layer 150 becomes the second conductive ring 115, and the second insulating layer 104b becomes the second dielectric ring 116. In the crucible perforation structure 100 of the present invention, the substrate post 107 fills the perforation hole 111 connecting the first side 101 and the second side 102. The second conductive ring 115 surrounds the first dielectric ring 114, and the second dielectric ring 116 directly contacts and surrounds the second conductive ring 115, which is again surrounded by the wafer 103.
隨後，請參考第4圖，形成第二介電層140。第二介電層140不但會覆蓋第二面102，並同時暴露出環狀介電層110。形成第二介電層140的步驟可以是，先使用一介電材料，例如氮化矽或是氧化矽，在低溫環境下，例如低於200℃，全面性地覆蓋第二面102，然後再使用微影配合蝕刻步驟選擇性移除部份之介電材料，目的是精準地暴露出環狀介電層110。Subsequently, referring to FIG. 4, a second dielectric layer 140 is formed. The second dielectric layer 140 not only covers the second side 102 but also exposes the annular dielectric layer 110. The second dielectric layer 140 may be formed by first covering a second surface 102 with a dielectric material, such as tantalum nitride or tantalum oxide, in a low temperature environment, for example, below 200 ° C, and then A portion of the dielectric material is selectively removed using a lithography and etching step in order to accurately expose the annular dielectric layer 110.
請注意，由於微影步驟的對準誤差，第二介電層140通常不會完整地覆蓋環狀介電層110的外表面。第二介電層140既不需要完整地覆蓋環狀介電層110的外表面，亦不是完全不覆蓋環狀介電層110的外表面。此外，如果介電材料是在低溫環境下覆蓋第二面102時，還可以避免傷害貼合晶圓103與載體131之有機材料。Please note that the second dielectric layer 140 typically does not completely cover the outer surface of the annular dielectric layer 110 due to alignment errors in the lithography step. The second dielectric layer 140 does not need to completely cover the outer surface of the annular dielectric layer 110, nor does it completely cover the outer surface of the annular dielectric layer 110. In addition, if the dielectric material covers the second side 102 in a low temperature environment, the organic material adhering to the wafer 103 and the carrier 131 can be avoided.
繼續，請參考第5圖，環狀介電層110中間被裸露之半導體基材106需要被完全移除，而形成穿孔洞111。在移除環狀介電層110中間之半導體基材106時，還需要一併移除對應之層間介電層124，使得穿孔洞111之兩端能同時連通第一面101與第二面102。由於環狀介電層110中間之半導體基材106會被完全移除，中空之環狀介電層110成為穿孔洞介電層110，而同時覆蓋穿孔洞111之內壁112。可以使用適當之蝕刻法，例如乾蝕刻及/或濕蝕刻，來移除基材106與對應之層間介電層124。Continuing, referring to FIG. 5, the exposed semiconductor substrate 106 in the middle of the annular dielectric layer 110 needs to be completely removed to form the via hole 111. When the semiconductor substrate 106 in the middle of the annular dielectric layer 110 is removed, the corresponding interlayer dielectric layer 124 needs to be removed together, so that both ends of the through hole 111 can simultaneously connect the first surface 101 and the second surface 102. . Since the semiconductor substrate 106 in the middle of the annular dielectric layer 110 is completely removed, the hollow annular dielectric layer 110 becomes the via hole dielectric layer 110 while covering the inner wall 112 of the via hole 111. The substrate 106 and the corresponding interlayer dielectric layer 124 can be removed using a suitable etching process, such as dry etching and/or wet etching.
視情況需要，穿孔洞111可以無需暴露內連線結構125，避免穿孔洞111在最後的蝕刻步驟中將銅暴露出來而造成污染。本實施例亦可以考慮使用接觸插塞126作為間接的媒介。例如，請參考第6圖。在形成接觸插塞126時，即預先設計部分之接觸插塞126對應於穿孔洞111的位置；然後於完全移除環狀介電層110中間的半導體基材106形成穿孔洞111時，曝露此等對應的接觸插塞126。較佳者，請參考第6圖，半導體元件120上設置有蝕刻停止層127或是應力層127，因此在形成接觸插塞126時，即預先設計部分之接觸插塞126對應於穿孔洞111的位置，並貫穿層間介電層124與蝕刻停止層127或是應力層127，而穿孔洞111最後的蝕刻步驟便可以停止在蝕刻停止層127或是應力層127上，如此，穿孔洞111在蝕刻完成時，即會暴露出部分之蝕刻停止層127或是應力層127，以及鑲嵌在蝕刻停止層127或是應力層127中之接觸插塞126，其直接接觸內連線結構125。As desired, the perforation 111 may eliminate the need to expose the interconnect structure 125, preventing the perforation 111 from exposing the copper during the final etching step to cause contamination. This embodiment can also be considered to use the contact plug 126 as an indirect medium. For example, please refer to Figure 6. When the contact plug 126 is formed, that is, the pre-designed portion of the contact plug 126 corresponds to the position of the through hole 111; then, when the through hole 111 is formed by completely removing the semiconductor substrate 106 in the middle of the annular dielectric layer 110, the exposure is exposed. Corresponding contact plugs 126. Preferably, referring to FIG. 6, the semiconductor device 120 is provided with an etch stop layer 127 or a stress layer 127. Therefore, when the contact plug 126 is formed, the pre-designed portion of the contact plug 126 corresponds to the through hole 111. Positioning, and penetrating the interlayer dielectric layer 124 and the etch stop layer 127 or the stress layer 127, and the last etching step of the via hole 111 can be stopped on the etch stop layer 127 or the stress layer 127, and thus, the via hole 111 is etched. Upon completion, a portion of the etch stop layer 127 or stress layer 127, and contact plugs 126 embedded in the etch stop layer 127 or the stressor layer 127 are exposed, which directly contact the interconnect structure 125.
請參考第7圖，接著就可以將導電層150，例如使用沉積的方式，填滿穿孔洞111之中，並且與內連線結構125直接或是間接電連接。視情況需要，導電層150不但會填滿穿孔洞111還會向周圍延伸，於是覆蓋部份之第二介電層140，形成預定圖案之電連接墊154。導電層150通常由單一之導電材料所組成，較佳為銅。導電層150與環狀介電層110之間完全沒有晶圓103之基材，而成為一無縫的矽穿孔結構100。構成矽穿孔結構100的導電層150可以為直徑約為18-22微米之一柱形結構。較佳者，曝露出第二面102的導電層150不具有帽蓋結構。Referring to FIG. 7, the conductive layer 150 can then be filled into the via hole 111, for example, by deposition, and electrically connected directly or indirectly to the interconnect structure 125. As needed, the conductive layer 150 not only fills the via hole 111 but also extends around, thus covering a portion of the second dielectric layer 140 to form a predetermined pattern of electrical connection pads 154. Conductive layer 150 is typically comprised of a single electrically conductive material, preferably copper. There is no substrate of the wafer 103 between the conductive layer 150 and the annular dielectric layer 110, and it becomes a seamless 矽 perforated structure 100. The conductive layer 150 constituting the tantalum perforated structure 100 may be a cylindrical structure having a diameter of about 18-22 microns. Preferably, the conductive layer 150 exposing the second side 102 does not have a cap structure.
當導電層150直接與內連線結構125電連接時，可以是在蝕刻完成時穿孔洞111直接暴露內連線結構125，所以所形成之導電層150可以直接接觸內連線結構125，同時部份之導電層150也會被層間介電層124所環繞，而其他部份之導電層150則會被環狀介電層110所環繞。如果是導電層150間接與內連線結構125電連接時，可以如第7A圖所示，預先在內連線結構125與穿孔洞111之間先形成接觸插塞126，於是導電層150即可以透過接觸插塞126間接與內連線結構125電連接。蝕刻停止層127或是應力層127並非必要，所以接觸插塞126視情況需要可以位於蝕刻停止層127或是應力層127中。When the conductive layer 150 is directly electrically connected to the interconnect structure 125, the via hole 111 may directly expose the interconnect structure 125 when the etching is completed, so that the formed conductive layer 150 may directly contact the interconnect structure 125, and at the same time The conductive layer 150 is also surrounded by the interlayer dielectric layer 124, while the other portions of the conductive layer 150 are surrounded by the annular dielectric layer 110. If the conductive layer 150 is indirectly electrically connected to the interconnect structure 125, the contact plug 126 may be formed in advance between the interconnect structure 125 and the via hole 111 as shown in FIG. 7A, so that the conductive layer 150 can be Indirectly connected to the interconnect structure 125 via the contact plug 126. The etch stop layer 127 or the stress layer 127 is not necessary, so the contact plug 126 may be located in the etch stop layer 127 or the stress layer 127 as occasion demands.
第7B圖繪示晶圓103是一種絕緣層覆矽(SOI)的結構，因此晶圓103進一步會包含位於第一面101上之一介電層105。如果在晶圓103的第一面101上之主動區域108中形成有至少一種主動元件，例如電晶體120，則本發明之矽穿孔結構100中之主動元件即剛好位在介電層105上與導電層150之正上方。導電層150的尺寸，通常比主動元件120要大上許多。例如，主動元件之總面積不大於導電層150截面積之十分之一。另外，導電層150與基材106之間還可以有絕緣層104。FIG. 7B illustrates that the wafer 103 is a structure of an insulating layer (SOI), and thus the wafer 103 further includes a dielectric layer 105 on the first side 101. If at least one active component, such as transistor 120, is formed in active region 108 on first side 101 of wafer 103, the active component in germanium via structure 100 of the present invention is positioned just on dielectric layer 105. Directly above the conductive layer 150. The size of the conductive layer 150 is typically much larger than the active component 120. For example, the total area of the active components is no more than one tenth of the cross-sectional area of the conductive layer 150. In addition, an insulating layer 104 may be further disposed between the conductive layer 150 and the substrate 106.
內連線結構125即可以經由位於主動區域中106、穿過介電層105之整體接觸126與導電層150電連接。整體接觸126可以視為前述接觸插塞126的一種變化，而較一般導電插塞(conductive plugs)之截面積面積為大。較佳者，多個整體接觸126還可以形成一導電插塞矩陣126’，例如n*m之矩陣。整體接觸126之形成方式可以參閱接觸插塞126之相關說明。The interconnect structure 125 can be electrically coupled to the conductive layer 150 via an integral contact 126 located in the active region 106 through the dielectric layer 105. The overall contact 126 can be considered as a variation of the aforementioned contact plug 126, which is larger than the cross-sectional area of a typical conductive plug. Preferably, the plurality of integral contacts 126 may also form a matrix of conductive plugs 126', such as a matrix of n*m. The manner in which the integral contact 126 is formed can be referred to the relevant description of the contact plug 126.
第7C圖繪示使用在第2圖中進行之半導體製程之閘極123之材料作為蝕刻停止層之實施方式。如果想要確實控制完全移除基材106而形成穿孔洞111之蝕刻步驟，則可以使用半導體製程中閘極123之材料作為蝕刻停止層。例如，預先將閘極123之材料形成在日後將要建立矽穿孔結構的位置上。閘極123之材料可以是金屬或是矽。另外，導電帽蓋129的下方亦不排除會有淺溝渠隔離128。層間介電層124會部分覆蓋第一面101。FIG. 7C illustrates an embodiment in which the material of the gate 123 of the semiconductor process performed in FIG. 2 is used as an etch stop layer. If it is desired to control the etching step of completely removing the substrate 106 to form the via hole 111, the material of the gate 123 in the semiconductor process can be used as the etch stop layer. For example, the material of the gate 123 is formed in advance at a position where a perforated structure is to be established in the future. The material of the gate 123 may be metal or tantalum. In addition, shallow trench isolation 128 is not excluded below the conductive cap 129. The interlayer dielectric layer 124 partially covers the first side 101.
之後，請參閱第7C圖，如果想要確實控制完全移除基材106而形成穿孔洞111之蝕刻步驟，而避免蝕刻不足、過蝕刻或是蝕刻劑損傷插塞126的缺點時，即可以使用閘極123之材料作為蝕刻停止層以避免以上之缺點。如果淺溝渠隔離128存在時，穿孔洞111可能會部份穿過淺溝渠隔離128。隨後在矽穿孔結構100完成時，與閘極123導體相同之材料部分即成為一導電帽蓋129。導電帽蓋129可以作為一電子系統層級(electronic system-level，ESL)之一閘電極。導電帽蓋129位於第一面101上、層間介電層124中、並且完全覆蓋並直接接觸導電層150。因此，導電帽蓋129之面積大於導電層150之面積。因為接觸插塞126電連接導電帽蓋129與內連線結構125，使得導電層150得以電連接內連線結構125。導電帽蓋129可以包含多晶矽與金屬材料其中之至少一者。Thereafter, referring to FIG. 7C, if it is desired to surely control the etching step of completely removing the substrate 106 to form the via hole 111, and avoid the disadvantages of insufficient etching, over-etching or etchant damage plug 126, it can be used. The material of the gate 123 serves as an etch stop layer to avoid the above disadvantages. If the shallow trench isolation 128 is present, the perforation 111 may partially pass through the shallow trench isolation 128. Then, when the crucible perforation structure 100 is completed, the portion of the material that is the same as the conductor of the gate 123 becomes a conductive cap 129. The conductive cap 129 can serve as a gate electrode of an electronic system-level (ESL). The conductive cap 129 is located on the first side 101, in the interlayer dielectric layer 124, and completely covers and directly contacts the conductive layer 150. Therefore, the area of the conductive cap 129 is larger than the area of the conductive layer 150. Because the contact plug 126 electrically connects the conductive cap 129 to the interconnect structure 125, the conductive layer 150 is electrically connected to the interconnect structure 125. The conductive cap 129 can comprise at least one of a polysilicon and a metallic material.
視情況需要，如第8圖所示。在導電層150填滿穿孔洞111之前，可以在穿孔洞介電層110之上先形成障壁層151與晶種層152其中之至少一者，而覆蓋穿孔洞介電層110與第二介電層140的表面。當導電層150為銅時，障壁層151可以避免銅原子不良的擴散。晶種層152則是可以誘導導電層150的沉積。或是，在形成障壁層151與晶種層152之後而形成導電層150前，又在障壁層151與晶種層152之上形成圖案化之線路重佈層遮罩153，如第8圖所示。線路重佈層遮罩153可以是乾膜(dry film)，並且使用微影配合蝕刻步驟來定義所需之圖案。As needed, as shown in Figure 8. Before the conductive layer 150 fills the via hole 111, at least one of the barrier layer 151 and the seed layer 152 may be formed on the via hole dielectric layer 110, and the via hole dielectric layer 110 and the second dielectric layer are covered. The surface of layer 140. When the conductive layer 150 is copper, the barrier layer 151 can avoid poor diffusion of copper atoms. The seed layer 152 is then capable of inducing deposition of the conductive layer 150. Alternatively, before the formation of the conductive layer 150 after forming the barrier layer 151 and the seed layer 152, a patterned line redistribution mask 153 is formed over the barrier layer 151 and the seed layer 152, as shown in FIG. Show. The line redistribution mask 153 can be a dry film and uses a lithography fit etching step to define the desired pattern.
如果有使用障壁層151、晶種層152或線路重佈層遮罩153，在導電層150填滿穿孔洞110之後，即可以移除線路重佈層遮罩153、障壁層151與晶種層152，而得到如第7A圖所示無縫的矽穿孔結構100。視情況需要，還可以在導電層150上之適當位置形成焊球(bump)155，作為向外電連接之媒介。If the barrier layer 151, the seed layer 152 or the line redistribution layer mask 153 is used, after the conductive layer 150 fills the perforation hole 110, the line redistribution layer mask 153, the barrier layer 151 and the seed layer can be removed. 152, resulting in a seamless perforated structure 100 as shown in Figure 7A. A bump 155 may also be formed at a suitable location on the conductive layer 150 as a medium for electrical interconnection, as desired.
經過以上方法步驟之後，即可以得到本發明無縫的矽穿孔結構100，如第7圖所示。晶圓103包含有基材106、第一面101與第二面102，而穿孔洞111即位於晶圓103中，而連通第一面101與第二面102。穿孔洞111中有穿孔洞介電層110，而覆蓋穿孔洞111之內壁112。填入穿孔洞111中之導電層150係由單一導電材料所組成，例如銅。導電層150可以為直徑約為18-22微米之柱形結構。較小之柱形結構有利於增加晶圓之元件密度。較佳者，導電層150不具有帽蓋結構。視情況需要，穿孔洞介電層110之厚度可以為2微米-3微米。After the above method steps, the seamless crucible perforation structure 100 of the present invention can be obtained, as shown in FIG. The wafer 103 includes a substrate 106, a first surface 101 and a second surface 102, and the through hole 111 is located in the wafer 103 to communicate the first surface 101 and the second surface 102. The perforated hole 111 has a perforated hole dielectric layer 110 covering the inner wall 112 of the perforated hole 111. The conductive layer 150 filled in the via hole 111 is composed of a single conductive material such as copper. Conductive layer 150 can be a cylindrical structure having a diameter of about 18-22 microns. The smaller cylindrical structure helps to increase the component density of the wafer. Preferably, the conductive layer 150 does not have a cap structure. The thickness of the via dielectric layer 110 can range from 2 microns to 3 microns, as desired.
第一介電層124與第二介電層140分別覆蓋晶圓103之第一面101與第二面102。第一介電層124還可以環繞部份之導電層150。第二介電層140則覆蓋第二面102與部份之穿孔洞介電層110，但是不完全覆蓋穿孔洞介電層110之底表面。導電層150還可以向四周延伸，而覆蓋住部分之第二介電層140。請注意，以上之結構係建立在晶圓(wafer)中，而非晶片(chip)中。換句話說，本發明是一種晶圓層級之矽穿孔結構，而不是封裝層級之結構。導電層150上之適當位置還有焊球155，作為向外電連接之媒介。The first dielectric layer 124 and the second dielectric layer 140 cover the first side 101 and the second side 102 of the wafer 103, respectively. The first dielectric layer 124 can also surround a portion of the conductive layer 150. The second dielectric layer 140 covers the second surface 102 and a portion of the via dielectric layer 110, but does not completely cover the bottom surface of the via dielectric layer 110. The conductive layer 150 may also extend to the periphery to cover a portion of the second dielectric layer 140. Please note that the above structure is built in the wafer, not in the chip. In other words, the present invention is a wafer-level perforated structure rather than an encapsulation level structure. A solder ball 155 is also present on the conductive layer 150 as a medium for electrical interconnection.
視情況需要，穿孔洞111之內表面上可以有障壁層151與晶種層152之至少一者，而覆蓋穿孔洞介電層110，如第8圖所示。當導電層150為銅時，障壁層151可以覆蓋穿孔洞介電層110並直接接觸穿孔洞介電層110，使得障壁層151圍繞導電層150並直接接觸導電層150，避免銅原子不良的擴散。晶種層152則是可以誘導導電層150的沉積。如果穿孔洞111之內表面上沒有障壁層151與晶種層152時，穿孔洞介電層110便會直接接觸導電層150。導電層150還可以向四周延伸，形成圖案化之線路重佈層153，形成預定圖案之電連接墊154，如第7或7A圖所示。Optionally, at least one of the barrier layer 151 and the seed layer 152 may be disposed on the inner surface of the through hole 111 to cover the via hole dielectric layer 110, as shown in FIG. When the conductive layer 150 is copper, the barrier layer 151 can cover the via dielectric layer 110 and directly contact the via dielectric layer 110, so that the barrier layer 151 surrounds the conductive layer 150 and directly contacts the conductive layer 150 to avoid poor diffusion of copper atoms. . The seed layer 152 is then capable of inducing deposition of the conductive layer 150. If the barrier layer 151 and the seed layer 152 are not present on the inner surface of the via hole 111, the via dielectric layer 110 directly contacts the conductive layer 150. The conductive layer 150 may also extend circumferentially to form a patterned circuit redistribution layer 153 to form a predetermined pattern of electrical connection pads 154, as shown in FIG. 7 or 7A.
在晶圓103的第一面101上，有半導體元件120、覆蓋半導體元件120之層間介電層124，以及位於層間介電層124之上、而與半導體元件120電連接之內連線結構125。半導體元件120通常包含閘極123與位於閘極123兩側之源極121與汲極122等。內連線結構125即經由接觸插塞126，穿過層間介電層124而分別與位於第一面上之閘極123、源極121與汲極122電連接。On the first side 101 of the wafer 103, there are a semiconductor device 120, an interlayer dielectric layer 124 covering the semiconductor device 120, and an interconnect structure 125 on the interlayer dielectric layer 124 and electrically connected to the semiconductor device 120. . The semiconductor device 120 generally includes a gate 123 and a source 121 and a drain 122 on both sides of the gate 123. The interconnect structure 125 is electrically connected to the gate 123, the source 121 and the drain 122 on the first surface via the contact plug 126 through the interlayer dielectric layer 124, respectively.
內連線結構125亦可即經由接觸插塞126間接與導電層150電連接。層間介電層124可以包含一種介電材料，例如氧化矽。內連線結構125可以為經由鑲嵌步驟所形成之銅鑲嵌導電結構。接觸插塞126通常會包含鎢。導電層150可以穿過層間介電層124與內連線結構125直接電連接，如第7圖所示，或是經由接觸插塞126間接與內連線結構125電連接，如第7A圖所示。當使用接觸插塞126時，接觸插塞126在第一面101上之佈局可以為方形(square)之棋盤狀(check board)，或是條狀(slot)(圖未示)。The interconnect structure 125 may also be indirectly electrically coupled to the conductive layer 150 via the contact plugs 126. The interlayer dielectric layer 124 may comprise a dielectric material such as hafnium oxide. The interconnect structure 125 can be a copper damascene conductive structure formed via a damascene step. Contact plug 126 will typically contain tungsten. The conductive layer 150 can be directly electrically connected to the interconnect structure 125 through the interlayer dielectric layer 124, as shown in FIG. 7, or indirectly connected to the interconnect structure 125 via the contact plug 126, as shown in FIG. 7A. Show. When the contact plug 126 is used, the layout of the contact plug 126 on the first side 101 may be a square check board or a slot (not shown).
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．矽穿孔結構100. . . Perforated structure
101．．．第一面101. . . First side
102．．．第二面102. . . Second side
103．．．晶圓103. . . Wafer
104．．．絕緣層104. . . Insulation
104b．．．第二絕緣層104b. . . Second insulating layer
105．．．介電層105. . . Dielectric layer
106．．．半導體基材106. . . Semiconductor substrate
107．．．基材柱107. . . Substrate column
108．．．主動區域108. . . Active area
110．．．環狀介電層/穿孔洞介電層/穿孔洞介電環110. . . Annular dielectric layer / perforated hole dielectric layer / perforated hole dielectric ring
111．．．穿孔洞111. . . Perforated hole
112．．．內壁112. . . Inner wall
113．．．第一導電環113. . . First conductive ring
114．．．第一介電環114. . . First dielectric ring
115．．．第二導電環115. . . Second conductive ring
116．．．第二介電環116. . . Second dielectric ring
120．．．半導體元件120. . . Semiconductor component
121．．．源極121. . . Source
122．．．汲極122. . . Bungee
123．．．閘極123. . . Gate
124．．．層間介電層124. . . Interlayer dielectric layer
124．．．第一介電層124. . . First dielectric layer
125．．．內連線結構125. . . Inline structure
126．．．接觸插塞/整體接觸126. . . Contact plug / overall contact
126’．．．導電插塞矩陣126’. . . Conductive plug matrix
127．．．蝕刻停止層/應力層127. . . Etch stop layer/stress layer
128．．．淺溝渠隔離128. . . Shallow trench isolation
129．．．導電帽蓋129. . . Conductive cap
130．．．黏膠130. . . Viscose
131．．．載體131. . . Carrier
140．．．第二介電層140. . . Second dielectric layer
150．．．導電層150. . . Conductive layer
150b．．．第二導電層150b. . . Second conductive layer
151．．．障壁層151. . . Barrier layer
152．．．晶種層152. . . Seed layer
153．．．線路重佈層遮罩153. . . Line redistribution mask
154．．．電連接墊154. . . Electrical connection pad
155．．．焊球155. . . Solder ball
第1-8圖繪示本發明形成矽穿孔結構方法的示意圖。1-8 are schematic views showing a method of forming a perforated structure of the present invention.
101．．．第一面101. . . First side
102．．．第二面102. . . Second side
103．．．晶圓103. . . Wafer
110．．．環狀介電層/穿孔洞介電層110. . . Annular dielectric layer/perforated dielectric layer
111．．．穿孔洞111. . . Perforated hole
112．．．內壁112. . . Inner wall
120．．．半導體元件120. . . Semiconductor component
121．．．源極121. . . Source
122．．．汲極122. . . Bungee
123．．．閘極123. . . Gate
124．．．層間介電層124. . . Interlayer dielectric layer
125．．．內連線結構125. . . Inline structure
126．．．接觸插塞126. . . Contact plug
140．．．第二介電層140. . . Second dielectric layer
150．．．導電層150. . . Conductive layer
154．．．電連接墊154. . . Electrical connection pad
155．．．焊球155. . . Solder ball
Claims (20)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9349803B2 (en) | 2013-07-30 | 2016-05-24 | Micron Technology, Inc. | Semiconductor graphene structures, semiconductor devices including such structures, and related methods |
| US9978638B2 (en) | 2013-09-03 | 2018-05-22 | Realtek Semiconductor Corp. | Metal trench de-noise structure and method for forming the same |
| TWI680533B (en) * | 2018-01-18 | 2019-12-21 | 新加坡商格羅方德半導體私人有限公司 | Devices and methods of forming thereof by post single layer transfer fabrication of device isolation structures |
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2011
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9349803B2 (en) | 2013-07-30 | 2016-05-24 | Micron Technology, Inc. | Semiconductor graphene structures, semiconductor devices including such structures, and related methods |
| US9978638B2 (en) | 2013-09-03 | 2018-05-22 | Realtek Semiconductor Corp. | Metal trench de-noise structure and method for forming the same |
| TWI680533B (en) * | 2018-01-18 | 2019-12-21 | 新加坡商格羅方德半導體私人有限公司 | Devices and methods of forming thereof by post single layer transfer fabrication of device isolation structures |
| US10522393B2 (en) | 2018-01-18 | 2019-12-31 | Globalfoundries Singapore Pte. Ltd. | Devices and methods of forming thereof by post single layer transfer fabrication of device isolation structures |
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