TW201302600A - 矽奈米線陣列之製作方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title abstract description 9
- 229910052710 silicon Inorganic materials 0.000 title abstract description 9
- 239000010703 silicon Substances 0.000 title abstract description 9
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 28
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- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 2
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Abstract
本發明揭露一種大面積矽奈米線陣列之製作方法，其包括利用一鍍膜製程在一表面具有矽材料之基材上形成一預定厚度之金屬層，該金屬層係選自由銀、金、鉑所組成的群組；及選用一蝕刻溶液對該矽材料進行金屬誘發化學蝕刻作用。藉此克服習知奈米銀粒子在進行金屬誘發化學蝕刻作用時之不均勻的問題。
Description
本發明係與一種矽奈米線之製作方法有關，特別係與一種大面積的矽奈米線陣列之製作方法有關。
矽奈米線(Silicon nanowires,SiNWs)陣列所形成之表面係具有良好抗反射率，將其應用在太陽能電池表面上，可以有效提升太陽光之吸收效果。傳統上，矽奈米線陣列係透過微影製程來製作，但是其之製作成本較高，且難以製作出如太陽能面板一般之大面積矽奈米線陣列。因此，大面積矽奈米線陣列的製作方法逐漸轉為以非微影製程方式來製作，例如以成長矽奈米線或是以金屬誘發矽蝕刻(metal-induced silicon etching)等方式來製作。
現有以金屬誘發矽蝕刻作用來製作大面積矽奈米線(silicon microwires)陣列的方法，係將矽基材泡在具有例如硝酸銀(AgNO3)混合氫氟酸(HF)溶液之奈米銀懸浮粒子的溶液中，以使得奈米銀粒子沈積在矽基材表面上。接著，再對該具有奈米銀粒子的矽基材進行濕式蝕刻(wet etching)，例如將具有奈米銀粒子的矽基材泡在氫氟酸與過氧化氫(H2O2)混合溶液裡，其中奈米銀粒子係作為催化劑，使得於其上局部具有奈米銀粒子的矽材料部分被蝕刻，在其往下蝕刻到一預定深度時，再將矽基材拿出以停止蝕刻。最後，再利用硝酸(HNO3)將奈米銀粒子洗去，以形成矽奈米線陣列。
然而，傳統利用金屬誘發矽蝕刻技術製作矽奈米線陣列時，因為所沈積的金屬粒子大小和沈積位置皆為隨機的，故所產生之矽奈米線陣列的均勻性並不好且會有叢聚現象，因而無法達到生產出大面積且排列均勻之矽奈米線陣列的目標。
有鑑於此，有必要對現有技術進行改良，以克服改善傳統金屬誘發矽蝕刻技術之缺點。
本發明之目的在於提供一種矽奈米線陣列之製作方法，其在表面具有矽材料之基材上鍍上一層極薄的金屬，再對矽材料進行金屬誘發化學蝕刻作用，根據本方法可製作出大面積且高均勻度之矽奈米線陣列。
為達成上述之目的，本發明提供一種矽奈米線陣列之製作方法，其包括：利用一鍍膜製程在一表面具有矽材料之基材上形成一預定厚度之金屬層，該金屬層係選自由銀、金、鉑所組成群組，該基材為矽基材或表面具有矽薄膜之矽或其他基材；選用一蝕刻溶液對該矽材料進行金屬誘發化學蝕刻作用；以及洗去殘留於基材表面的金屬層。
在一較佳實施例中，該鍍膜製程係為一電子束蒸鍍、一物理蒸鍍、一化學蒸鍍、或一濺鍍作用。在此較佳實施例中，該金屬層係為銀，且該金屬層的預定厚度係介於5奈米至50奈米。此外，該蝕刻溶液係為氟化氫加上過氧化氫之水溶液，且氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.7至0.99。在此較佳實施例中，蝕刻的速率與該蝕刻溶液的溫度呈正比。進一步而言，在一預定溫度下，該矽奈米線的長度與蝕刻時間係呈正比。
值得一提的是，所生成之矽奈米線的長度係小於等於該矽材料的蝕刻深度。當該金屬層在該矽材料表面的區域越小，該矽奈米線的長度與總蝕刻深度的差距就越大，蝕刻生成矽奈米線的速率亦隨之降低。
依據本發明之矽奈米線陣列之製作方法，其可以取代習知以銀奈米粒子沈積在矽材料表面之作法，而改以鍍膜技術來鍍上一層極薄的銀，使得銀自然在矽材料表面形成多孔網狀結構，然後再進行金屬誘發化學蝕刻作用，進而蝕刻出大面積且高均勻度之矽奈米線陣列。
為讓本發明之上述內容能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。
以下將配合附圖來詳細說明本發明的矽奈米線陣列之製作方法的較佳實施例。請參照第1圖及第2圖，第1圖繪示本發明較佳實施例的矽奈米線陣列之製作方法的流程圖，第2圖繪示進行步驟S10時表面具有矽材料之基材的剖面示意圖。該製作方法係用於在一表面具有矽材料之基材10(簡稱為基材10)上，製作出高均勻度之矽奈米線陣列，其中該矽材料可為單晶矽(mono-crystalline silicon)，例如晶格方向為(100)、(110)、或(111)者。該矽材料亦可為多晶矽(polysilicon)或非晶矽(amorphous silicon,a-Si)，該矽材料可為本質(intrinsic)矽或摻雜(doped)矽。
在步驟S10中，利用一鍍膜製程在一表面具有矽材料之基材10上形成一預定厚度之金屬層20，該金屬層20係選自由銀(Ag)、金(Au)、鉑(Pt)所組成群組，其中銀(Ag)、金(Au)、鉑(Pt)係為對矽具有催化效果之金屬。具體而言，該鍍膜製程係為電子束蒸鍍(electron beam evaporation)、物理蒸鍍(physical vapor deposition)、化學蒸鍍(chemical vapor deposition)、或濺鍍(sputtering)等等製程。然而，本發明並不限於上述幾種鍍膜製程。在此較佳實施例中，該金屬層20係為銀，且該金屬層20的預定厚度係介於5奈米(nm)至50奈米(nm)之間。在此一厚度下，銀會自然在表面具有矽材料之基材10上形成規律的多孔網狀結構。因此，該金屬層20的鍍膜厚度需被加以控制。如果金屬層20厚度太薄，則最終將會形成多孔隙矽結構而非所欲矽奈米線陣列；如果金屬層20厚度太厚會使蝕刻溶液不易滲入金屬層20，而較難形成均勻之矽奈米線陣列。以此較佳實施例來說，金屬層20之最佳厚度為20奈米(nm)。
請參考第1圖及第3圖，第2圖繪示進行步驟S20時表面具有矽材料之基材的剖面示意圖。選用一蝕刻溶液30來對該矽材料進行金屬誘發化學蝕刻(metal-induced chemical etching)作用。在此較佳實施例中，該步驟S20即為將該表面具有矽材料之基材10，浸入具有該蝕刻溶液30的容器32中，以進行濕蝕刻作用。
具體而言，該蝕刻溶液30係為氟化氫(HF)加上過氧化氫(H2O2)之水溶液，即氫氟酸加上雙氧水。由於金屬層20之厚度極薄(5nm至50nm)，因此該蝕刻溶液30可以很容易地浸潤至該基材10表面。進一步地說，該表面具有矽材料之基材10上具有銀的局部區域，係以銀作為催化劑往下蝕刻，而不被銀所覆蓋的區域則不會被往下蝕刻。其中該過氧化氫(H2O2)之作用係將矽氧化成二氧化矽(SiO2)，然後氫氟酸再蝕刻掉該二氧化矽(SiO2)，並據此往下蝕刻。
值得注意的是，氟化氫(HF)與過氧化氫(H2O2)之間的比例也會影響所形成的矽奈米線陣列之型態。以該金屬層20(銀)來說，氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.7至0.99，即[HF]/([HF]+[H2O2])係介於0.7至0.99，才可得較均勻之矽奈米線陣列。
請參照第4a圖、第4b圖、第5a圖及第5b圖，第4a圖為氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.89時，所蝕刻出之矽奈米線陣列的電子顯微鏡上視圖；第4b圖為第4a圖之側視圖；第5a圖為氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.68時，所蝕刻出之矽奈米線陣列的電子顯微鏡上視圖；第5b圖為第5a圖之側視圖。在此較佳實施例中，由實驗可得知[HF]/([HF]+[H2O2])之數值在介於0.87至0.95之間時，可得一較為均勻之矽奈米線陣列。如第4a圖及第4b圖所示，在([HF]/([HF]+[H2O2])為0.89(介於0.87至0.95之間)時，此參數所形成的矽奈米線陣列，較第5a圖及第5b圖之([HF]/([HF]+[H2O2])為0.68(非介於0.87至0.95之間)時之矽奈米線陣列來得整齊。且參數在[HF]/([HF]+[H2O2])為0.68時之矽奈米線陣列，較易於產生叢聚之情形。
在此較佳實施例中，矽蝕刻的速率與該蝕刻溶液30的溫度係呈正比。也就是該蝕刻溶液30的溫度越高，則蝕刻作用越強，且蝕刻速率與該蝕刻溶液30的溫度為一線性關係。請再參考第3圖，進一步而言，在一預定溫度下，該矽奈米線的長度15與蝕刻時間呈正比，據此即可根據蝕刻速率乘上時間而得到矽奈米線的長度。
請參照第6圖，在此較佳實施例中，所生成之矽奈米線12的長度15，係小於等於該矽材料的蝕刻深度17。具體而言，即是在金屬誘發化學蝕刻時，會先蝕刻掉一些許厚度19的矽材料後，才會開始蝕刻出矽奈米線12。此外，該矽奈米線12的長度15係與該金屬層20在該基材10表面的區域大小有關，如果金屬層20僅形成在區域I，則蝕刻矽奈米線12的深度d與總蝕刻深度D的差距會變大。即當該金屬層20在該基材10表面的區域越小，該矽奈米線12的長度d與總蝕刻深度D的差距就越大。在一預定蝕刻時間下，在區域I中生成之矽奈米線12的長度d會小於在開放空間中生成之矽奈米線12的長度15。
請參照第1圖及第7圖，第7圖繪示進行步驟S30時表面具有矽材料之基材的剖面示意圖。在步驟S30中，將殘留於基材10上的金屬層20洗去。舉例而言，可利用硝酸(HNO3)溶液40將殘留的銀洗去，最後形成大面積且均勻的矽奈米線陣列。
綜上所述，本發明之矽奈米線陣列之製作方法，其可以取代習知以銀奈米粒子沈積在矽基材之作法，而以鍍膜技術來鍍上一層極薄的銀，使得銀自然在表面具有矽材料之基材上形成多孔網狀結構，然後再進行金屬誘發化學蝕刻，藉此蝕刻出大面積且高均勻度之矽奈米線陣列。因此本發明克服了習知奈米銀粒子，於進行金屬誘發化學蝕刻作用所製作而成的矽奈米線陣列中，所產生之不均勻、倒塌、叢聚等缺點。而具有均勻的矽奈米線陣列的表面將可有極低之反射率，而可增加其光吸收效率。
雖然本發明已用較佳實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
S10．．．步驟
S20．．．步驟
S30．．．步驟
10．．．表面具有矽材料之基材
20．．．金屬層
30．．．蝕刻溶液
32．．．容器
12．．．矽奈米線
15．．．長度
17．．．蝕刻深度
19．．．厚度
d．．．深度
D．．．總蝕刻深度
I．．．區域
第1圖繪示本發明較佳實施例的矽奈米線陣列之製作方法的流程圖。
第2圖繪示進行步驟S10時表面具有矽材料之基材之剖面示意圖。
第3圖繪示進行步驟S20時表面具有矽材料之基材之剖面示意圖。
第4a圖為氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.89所蝕刻出之矽奈米線陣列的電子顯微鏡上視圖。
第4b圖為第4a圖之側視圖。
第5a圖為氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.68所蝕刻出之矽奈米線陣列的電子顯微鏡上視圖。
第5b圖為第5a圖之側視圖。
第6圖繪示在不同大小蝕刻區域之矽奈米線陣列的剖面示意圖。
第7圖繪示進行步驟S30時表面具有矽材料之基材之剖面示意圖。
S10．．．步驟
S20．．．步驟
S30．．．步驟
Claims (10)
- 一種矽奈米線陣列之製作方法，其包括：利用一鍍膜製程在一表面具有矽材料之基材上，形成一預定厚度之金屬層，該金屬層係選自由銀、金、鉑所組成群組；選用一蝕刻溶液對該矽材料進行金屬誘發化學蝕刻作用；以及洗去殘留於基材上的金屬層。
- 如申請專利範圍第1項所述之矽奈米線陣列之製作方法，其中該鍍膜製程係為一電子束蒸鍍、一物理蒸鍍、一化學蒸鍍、或一濺鍍作用。
- 如申請專利範圍第1項所述之矽奈米線陣列之製作方法，其中該表面具有矽材料之基材係為矽基材、表面具有矽薄膜之矽基材或表面具有矽薄膜之基材。
- 如申請專利範圍第3項所述之矽奈米線陣列之製作方法，其中該矽材料可為單晶矽、多晶矽或非晶矽，且該矽材料可為本質矽或摻雜矽。
- 如申請專利範圍第1項所述之矽奈米線陣列之製作方法，其中該金屬層係為銀。
- 如申請專利範圍第5項所述之矽奈米線陣列之製作方法，其中該預定厚度係介於5奈米至50奈米之間。
- 如申請專利範圍第1項所述之矽奈米線陣列之製作方法，其中該蝕刻溶液係為氟化氫加上過氧化氫之水溶液。
- 如申請專利範圍第7項所述之矽奈米線陣列之製作方法，其中氟化氫在氟化氫加上過氧化氫的溶液中所佔比例為0.7至0.99。
- 如申請專利範圍第1項所述之矽奈米線陣列之製作方法，其中矽蝕刻的速率與該蝕刻溶液的溫度呈正比，且在一預定溫度下，該矽奈米線的長度與蝕刻時間呈正比。
- 如申請專利範圍第1項所述之矽奈米線陣列之製作方法，其中當該金屬層在該矽材料表面的區域越小，該矽奈米線的長度與總蝕刻深度的差距就越大，蝕刻生成矽奈米線的速率亦隨之降低。
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| WO2014008663A1 (en) * | 2012-07-13 | 2014-01-16 | Empire Technology Development Llc | Fabrication of nano-structure electrodes for ultra-capacitor |
| CN103147125A (zh) * | 2013-02-27 | 2013-06-12 | 中国科学院半导体研究所 | 廉价粉末多晶硅基纳米线的制备方法 |
| EP3033788A1 (en) * | 2013-08-14 | 2016-06-22 | Board of Regents, The University of Texas System | Methods of fabricating silicon nanowires and devices containing silicon nanowires |
| US9529126B2 (en) * | 2014-01-09 | 2016-12-27 | Wisconsin Alumni Research Foundation | Fresnel zone plate |
| CN103950889B (zh) * | 2014-05-08 | 2015-08-19 | 清华大学 | 一种场发射性能优良具有尖端结构的硅纳米线阵列的制备方法 |
| KR102139217B1 (ko) * | 2014-09-25 | 2020-07-29 | 삼성전자주식회사 | 안테나 장치 |
| US9893046B2 (en) * | 2016-07-08 | 2018-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Thinning process using metal-assisted chemical etching |
| CN108882845B (zh) | 2016-12-31 | 2022-05-03 | 鲁姆斯有限公司 | 基于经由光导光学元件的视网膜成像的眼动追踪器 |
| AT519922B1 (de) * | 2017-05-11 | 2020-01-15 | Univ Wien Tech | SERS-Substrat |
| IL259518B2 (en) | 2018-05-22 | 2023-04-01 | Lumus Ltd | Optical system and method for improving light field uniformity |
| CN109509839A (zh) * | 2018-11-05 | 2019-03-22 | 深圳清华大学研究院 | 杂化太阳能电池的制备方法及杂化太阳能电池 |
| TW202026685A (zh) | 2018-11-08 | 2020-07-16 | 以色列商魯姆斯有限公司 | 具有反射鏡的光導顯示器 |
| CN112028077B (zh) * | 2020-09-15 | 2022-04-05 | 北京师范大学 | 一种在硅纳米线及其阵列中形成裂纹的方法 |
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