TW201301445A - Memory structure and fabricating method thereof - Google Patents
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本發明是有關於一種記憶體結構及其製造方法，且特別是有關於一種具有多個實體上分離的電荷儲存單元的記憶體結構及其製造方法。The present invention relates to a memory structure and a method of fabricating the same, and more particularly to a memory structure having a plurality of physically separated charge storage units and a method of fabricating the same.
記憶體為設計來儲存資訊或資料之半導體元件。當電腦微處理器之功能變得越來越強，軟體所進行的程式與運算也隨之增加。因此，記憶體的容量需求也就越來越高。在各式的記憶體產品中，非揮發性記憶體，例如可電抹除可程式化唯讀記憶體（Electrically Erasable Programmable Read Only Memory，EEPROM）允許多次的資料程式化、讀取及抹除操作，且其中儲存的資料即使在記憶體被斷電後仍可以保存。基於上述優點，可電抹除可程式化唯讀記憶體已成為個人電腦和電子設備所廣泛採用的一種記憶體。A memory is a semiconductor component designed to store information or data. As the functions of computer microprocessors become stronger and stronger, the programs and operations performed by the software increase. Therefore, the capacity requirements of the memory are getting higher and higher. Among various types of memory products, non-volatile memory, such as Electrically Erasable Programmable Read Only Memory (EEPROM), allows multiple data to be programmed, read, and erased. Operation, and the stored data can be saved even after the memory is powered off. Based on the above advantages, the erasable programmable read-only memory has become a memory widely used in personal computers and electronic devices.
典型的可電抹除且可程式化唯讀記憶體係以摻雜的多晶矽製作浮置閘極（floating gate）與控制閘極（control gate）。當記憶體進行程式化（program）時，注入浮置閘極的電子會均勻分布於整個多晶矽浮置閘極之中。然而，當多晶矽浮置閘極下方的穿隧氧化層有缺陷存在時，就容易造成元件的漏電流，影響元件的可靠度。A typical electrically erasable and programmable read only memory system fabricates a floating gate and a control gate with doped polysilicon. When the memory is programmed, the electrons injected into the floating gate are evenly distributed throughout the polysilicon floating gate. However, when there is a defect in the tunneling oxide layer under the floating gate of the polysilicon, it is easy to cause leakage current of the element and affect the reliability of the element.
因此，為了解決可電抹除可程式化唯讀記憶體漏電流之問題，目前習知的一種方法是採用含有非導體的電荷儲存層之閘極結構來取代多晶矽浮置閘極。以電荷儲存層取代多晶矽浮置閘極的另一項優點是，在元件程式化時，僅會將電子局部性地儲存在接近源極或汲極上方的電荷儲存層中。因此，在進行程式化時，可以分別對堆疊式閘極一端的源極區與控制閘極施加電壓，而在接近於源極區的電荷儲存層中產生高斯分布的電子，並且也可以分別對堆疊式閘極一端的汲極區與控制閘極施加電壓，而在接近於汲極區的電荷儲存層中產生高斯分布的電子。故而，藉由改變控制閘極與其兩側之源極/汲極區所施加電壓，可以在單一的電荷儲存層之中存在兩群具有高斯分布的電子、單一群具有高斯分布的電子或是不存在電子。因此，此種以電荷儲存層取代浮置閘極的快閃記憶體，可以在單一的記憶胞之中寫入四種狀態，為一種單一記憶胞二位元（2 bits/cell）儲存之快閃記憶體。Therefore, in order to solve the problem of electrically erasing the leakage current of the programmable read-only memory, a conventional method is to replace the polysilicon floating gate with a gate structure containing a non-conductor charge storage layer. Another advantage of replacing the polysilicon floating gate with a charge storage layer is that when the component is programmed, only electrons are locally stored in the charge storage layer near the source or drain. Therefore, when programming, a voltage can be applied to the source region and the control gate of one end of the stacked gate, and a Gaussian distribution of electrons can be generated in the charge storage layer close to the source region, and can also be respectively The drain region of one end of the stacked gate and the control gate apply a voltage, and a Gaussian distribution of electrons is generated in the charge storage layer close to the drain region. Therefore, by changing the voltage applied to the source/drain region of the control gate and its two sides, there can be two groups of electrons having a Gaussian distribution, a single group of Gaussian distribution electrons or not in a single charge storage layer. There is electrons. Therefore, such a flash memory in which a floating gate is replaced by a charge storage layer can write four states in a single memory cell, and is stored as a single memory cell (2 bits/cell). Flash memory.
然而，隨著半導體元件積集度（integrity）之增加，非揮發性記憶體的尺寸也不斷地微縮。由於閘極長度(gate length)的微縮讓同一記憶胞中的左右兩個電荷儲存單元越來越靠近，而導致嚴重的第二位元效應(second bit effect)的問題，因此容易產生讀取錯誤。此外，由於源極區與汲極區的微縮，所以源極區與汲極區阻擋不了由程式化選定的記憶胞時所產生的二次熱電子(secondary hot electron)，而造成二次熱電子注入到相鄰的記憶胞中，進而產生程式化干擾(program disturbance)的問題，而降低記憶體元件之可靠度。However, as the degree of integration of semiconductor components increases, the size of non-volatile memory is also constantly shrinking. Since the miniaturization of the gate length causes the left and right charge storage cells in the same memory cell to get closer and closer, resulting in a serious second bit effect problem, it is easy to generate a read error. . In addition, due to the miniaturization of the source region and the drain region, the source region and the drain region can not block the secondary hot electron generated by the stylized selected memory cell, thereby causing secondary thermal electrons. Injection into adjacent memory cells creates a problem of program disturbance and reduces the reliability of the memory components.
有鑑於此，本發明的一實施例提供一種記憶體結構，其可解決由第二位元效應所造成的讀取錯誤。In view of this, an embodiment of the present invention provides a memory structure that can solve a read error caused by a second bit effect.
本發明的另一實施例提供一種記憶體結構的製造方法，其可降低由二次熱電子所造成的程式化干擾。Another embodiment of the present invention provides a method of fabricating a memory structure that reduces stylized interference caused by secondary hot electrons.
本發明的一實施例提出一種記憶體結構，包括記憶胞，而記憶胞包括下列構件。第一閘極設置於基底上。堆疊結構包括設置於第一閘極上的第一介電結構、通道層、第二介電結構與第二閘極、設置於第一介電結構中的第一電荷儲存結構、及設置於第二介電結構中第二電荷儲存結構。其中，第一電荷儲存結構與第二電荷儲存結構中的至少一者包括實體上分離設置的兩個電荷儲存單元。第一介電層設置於堆疊結構兩側的第一閘極上。第一源極與汲極及第二源極與汲極設置於第一介電層上且位於通道層的兩側。One embodiment of the present invention provides a memory structure including a memory cell, and the memory cell includes the following components. The first gate is disposed on the substrate. The stack structure includes a first dielectric structure disposed on the first gate, a channel layer, a second dielectric structure and a second gate, a first charge storage structure disposed in the first dielectric structure, and a second A second charge storage structure in the dielectric structure. Wherein at least one of the first charge storage structure and the second charge storage structure comprises two charge storage units physically separated. The first dielectric layer is disposed on the first gates on both sides of the stacked structure. The first source and the drain and the second source and the drain are disposed on the first dielectric layer and on both sides of the channel layer.
依照本發明的一實施例所述，在上述之記憶體結構中，第一電荷儲存結構與第二電荷儲存結構例如皆為實體上分離設置的兩個電荷儲存單元。According to an embodiment of the invention, in the memory structure, the first charge storage structure and the second charge storage structure are, for example, two charge storage units that are physically separated.
依照本發明的一實施例所述，在上述之記憶體結構中，第一電荷儲存結構例如是單一個電荷儲存單元，第二電荷儲存結構例如是實體上分離設置的兩個電荷儲存單元。According to an embodiment of the invention, in the memory structure, the first charge storage structure is, for example, a single charge storage unit, and the second charge storage structure is, for example, two charge storage units physically separated.
依照本發明的一實施例所述，在上述之記憶體結構中，第一電荷儲存結構例如是實體上分離設置的兩個電荷儲存單元，第二電荷儲存結構例如是單一個電荷儲存單元。According to an embodiment of the invention, in the memory structure, the first charge storage structure is, for example, two charge storage units physically separated, and the second charge storage structure is, for example, a single charge storage unit.
依照本發明的一實施例所述，在上述之記憶體結構中，當記憶體結構包括多個記憶胞時，這些記憶胞堆疊設置。According to an embodiment of the invention, in the memory structure described above, when the memory structure includes a plurality of memory cells, the memory cells are stacked.
本發明的另一實施例提出一種記憶體結構的製造方法，包括下列步驟。首先，於基底上形成第一閘極。接著，於第一閘極上形成堆疊結構。堆疊結構包括設置於第一閘極上的第一介電結構、通道層、第二介電結構與第二閘極、設置於第一介電結構中的第一電荷儲存結構、及設置於第二介電結構中第二電荷儲存結構。其中，第一電荷儲存結構包括實體上分離設置的兩個第一電荷儲存單元，且第二電荷儲存結構包括實體上分離設置的兩個第二電荷儲存單元。然後，於堆疊結構兩側的第一閘極上形成第一介電層。接下來，於第一介電層上形成位在通道層兩側的第一源極與汲極及第二源極與汲極。Another embodiment of the present invention provides a method of fabricating a memory structure comprising the following steps. First, a first gate is formed on the substrate. Next, a stacked structure is formed on the first gate. The stack structure includes a first dielectric structure disposed on the first gate, a channel layer, a second dielectric structure and a second gate, a first charge storage structure disposed in the first dielectric structure, and a second A second charge storage structure in the dielectric structure. The first charge storage structure includes two first charge storage units that are physically separated, and the second charge storage structure includes two second charge storage units that are physically separated. Then, a first dielectric layer is formed on the first gates on both sides of the stacked structure. Next, a first source and a drain and a second source and a drain are formed on the first dielectric layer on both sides of the channel layer.
依照本發明的另一實施例所述，在上述之記憶體結構的製造方法中，第一閘極的形成方法例如是離子植入法或化學氣相沉積法。According to another embodiment of the present invention, in the method of fabricating the memory structure described above, the method of forming the first gate is, for example, an ion implantation method or a chemical vapor deposition method.
依照本發明的另一實施例所述，在上述之記憶體結構的製造方法中，堆疊結構的形成方法可包括下列步驟。首先，於第一閘極上依序形成第二介電材料層、半導體材料層、第三介電材料層與閘極材料層。接著，圖案化第二介電材料層、半導體材料層、第三介電材料層與閘極材料層，而於第一閘極上依序形成第二介電層、通道層、第三介電層與第二閘極。然後，移除第二介電層的兩側部分與第三介電層的兩側部分，而於通道層與第一閘極之間形成兩個第一開口，且於第二閘極與通道層之間形成兩個第二開口。接下來，於第一開口的表面與第二開口的表面上形成第四介電層。之後，於第四介電層上形成填入第一開口的第一電荷儲存單元與填入第二開口的第二電荷儲存單元。According to another embodiment of the present invention, in the above method of fabricating a memory structure, the method of forming the stacked structure may include the following steps. First, a second dielectric material layer, a semiconductor material layer, a third dielectric material layer, and a gate material layer are sequentially formed on the first gate. Then, the second dielectric material layer, the semiconductor material layer, the third dielectric material layer and the gate material layer are patterned, and the second dielectric layer, the channel layer and the third dielectric layer are sequentially formed on the first gate With the second gate. Then, both side portions of the second dielectric layer and both side portions of the third dielectric layer are removed, and two first openings are formed between the channel layer and the first gate, and the second gate and the channel are formed Two second openings are formed between the layers. Next, a fourth dielectric layer is formed on the surface of the first opening and the surface of the second opening. Thereafter, a first charge storage unit filled in the first opening and a second charge storage unit filled in the second opening are formed on the fourth dielectric layer.
依照本發明的另一實施例所述，在上述之記憶體結構的製造方法中，第一源極與汲極及第二源極與汲極的形成方法可包括下列步驟。首先，於第一介電層上形成導體層，且導體層覆蓋堆疊結構。接著，移除部分導體層，而形成位於通道層兩側的第一源極與汲極及第二源極與汲極，且第一源極與汲極、第二源極與汲極與通道層的厚度例如是實質上相同。According to another embodiment of the present invention, in the above method for fabricating a memory structure, the method of forming the first source and the drain and the second source and the drain may include the following steps. First, a conductor layer is formed on the first dielectric layer, and the conductor layer covers the stacked structure. Then, a part of the conductor layer is removed to form a first source and a drain and a second source and a drain on both sides of the channel layer, and the first source and the drain, the second source and the drain and the channel The thickness of the layers is, for example, substantially the same.
依照本發明的另一實施例所述，在上述之記憶體結構的製造方法中，更可包括於第一源極與汲極及第二源極與汲極上形成位於第二閘極兩側的第五介電層。According to another embodiment of the present invention, in the method for fabricating the memory structure, the method further includes: forming a first source and a drain and a second source and a drain on both sides of the second gate The fifth dielectric layer.
基於上述，在本發明的一實施例所提出之記憶體結構中，由於第一電荷儲存結構與第二電荷儲存結構中的至少一者包括實體上分離設置的兩個電荷儲存單元，因此可解決由第二位元效應所造成的讀取錯誤，且可降低由二次熱電子所造成的程式化干擾。Based on the above, in the memory structure of an embodiment of the present invention, since at least one of the first charge storage structure and the second charge storage structure includes two charge storage units that are physically separated, the solution can be solved. Read errors caused by the second bit effect and can reduce stylized interference caused by secondary hot electrons.
此外，本發明的另一實施例所提出之記憶體結構的製造方法可與現行製程進行整合，因此能有效地降低製程複雜度。In addition, the method for fabricating the memory structure proposed by another embodiment of the present invention can be integrated with the current process, thereby effectively reducing process complexity.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1H所繪示為本發明之第一實施例的記憶體結構的製造流程剖面圖。1A to 1H are cross-sectional views showing a manufacturing process of a memory structure according to a first embodiment of the present invention.
請參照圖1A，首先，於基底100上形成閘極102。閘極102例如是N型摻雜區，而基底100例如是P型基底。N型的閘極102與P型的基底100為相反的摻雜型態，因此具有阻擋電荷在其間流通的功效。在另一實施例中，基底100也可具有在N型井區(未繪示)中的P型井區(未繪示)，而使閘極102形成於基底100的P型井區上。當閘極102為N型摻雜區時，閘極102的形成方法例如是利用離子植入法於基底100中植入掺質所形成。Referring to FIG. 1A, first, a gate 102 is formed on a substrate 100. The gate 102 is, for example, an N-type doped region, and the substrate 100 is, for example, a P-type substrate. The N-type gate 102 and the P-type substrate 100 have opposite doping types, and thus have the effect of blocking charges flowing therebetween. In another embodiment, the substrate 100 may also have a P-type well region (not shown) in an N-type well region (not shown), and the gate 102 is formed on the P-type well region of the substrate 100. When the gate 102 is an N-type doped region, the method of forming the gate 102 is formed, for example, by implanting a dopant into the substrate 100 by ion implantation.
在另一實施例中，閘極102可為摻雜多晶矽閘極。當閘極102為摻雜多晶矽閘極時，更可形成於基底100與閘極102之間形成隔離介電層，以隔離基底100與閘極102。In another embodiment, the gate 102 can be a doped polysilicon gate. When the gate 102 is a doped polysilicon gate, an isolation dielectric layer can be formed between the substrate 100 and the gate 102 to isolate the substrate 100 from the gate 102.
接著，於閘極102上依序形成介電材料層104、半導體材料層106、介電材料層108與閘極材料層110。介電材料層104的材料例如是氧化矽。半導體材料層106的材料例如是磊晶矽、多晶矽或非晶矽。介電材料層108的材料例如是氧化矽。閘極材料層110的材料例如是摻雜多晶矽或金屬等導體材料。介電材料層104、半導體材料層106、介電材料層108與閘極材料層110的形成方法例如是化學氣相沉積法或物理氣相沉積法。Next, a dielectric material layer 104, a semiconductor material layer 106, a dielectric material layer 108, and a gate material layer 110 are sequentially formed on the gate 102. The material of the dielectric material layer 104 is, for example, ruthenium oxide. The material of the semiconductor material layer 106 is, for example, epitaxial germanium, polycrystalline germanium or amorphous germanium. The material of the dielectric material layer 108 is, for example, ruthenium oxide. The material of the gate material layer 110 is, for example, a conductive material such as doped polysilicon or metal. The method of forming the dielectric material layer 104, the semiconductor material layer 106, the dielectric material layer 108, and the gate material layer 110 is, for example, a chemical vapor deposition method or a physical vapor deposition method.
然後，請參照圖1B，圖案化介電材料層104、半導體材料層106、介電材料層108與閘極材料層110，而於閘極102上依序形成介電層112、通道層114、介電層116與閘極118。介電材料層104、半導體材料層106、介電材料層108與閘極材料層110的圖案化方法例如是對上述膜層進行微影製程與蝕刻製程而形成。Then, referring to FIG. 1B, the dielectric material layer 104, the semiconductor material layer 106, the dielectric material layer 108, and the gate material layer 110 are patterned, and the dielectric layer 112 and the channel layer 114 are sequentially formed on the gate 102. Dielectric layer 116 and gate 118. The patterning method of the dielectric material layer 104, the semiconductor material layer 106, the dielectric material layer 108, and the gate material layer 110 is formed, for example, by performing a lithography process and an etching process on the film layer.
接下來，請參照圖1C，移除介電層112的兩側部分與介電層116的兩側部分，而於通道層114與閘極102之間形成開口120，且於閘極118與通道層114之間形成開口122。部分介電層112與部分介電層116的移除方法例如是濕式蝕刻法。Next, referring to FIG. 1C, both side portions of the dielectric layer 112 and both side portions of the dielectric layer 116 are removed, and an opening 120 is formed between the channel layer 114 and the gate 102, and the gate 118 and the channel are formed. An opening 122 is formed between the layers 114. The method of removing the portion of the dielectric layer 112 and the portion of the dielectric layer 116 is, for example, a wet etching method.
之後，請參照圖1D，於閘極102、介電層112、通道層114、介電層116與閘極118的表面上形成介電材料層124。介電材料層124的材料例如是氧化矽。介電材料層124的形成方法例如是熱氧化法。Thereafter, referring to FIG. 1D, a dielectric material layer 124 is formed on the surface of the gate 102, the dielectric layer 112, the channel layer 114, the dielectric layer 116, and the gate 118. The material of the dielectric material layer 124 is, for example, ruthenium oxide. The method of forming the dielectric material layer 124 is, for example, a thermal oxidation method.
隨後，於介電材料層124上形成填滿開口120與開口122的電荷儲存材料層126。電荷儲存材料層126的材料例如是氮化矽、摻雜多晶矽或奈米晶粒。電荷儲存材料層126的形成方法例如是化學氣相沉積法。Subsequently, a layer of charge storage material 126 filling the opening 120 and the opening 122 is formed on the dielectric material layer 124. The material of the charge storage material layer 126 is, for example, tantalum nitride, doped polysilicon or nanocrystalline grains. The method of forming the charge storage material layer 126 is, for example, a chemical vapor deposition method.
繼之，請參照圖1E，移除位於開口120外部與位於開口122外部的電荷儲存材料層126，而於介電材料層124上形成填入開口120的電荷儲存單元128、130與填入開口122的電荷儲存單元132、134。在此實施例中，由實體上分離設置電荷儲存單元128、130形成電荷儲存結構136，且由實體上分離設置電荷儲存單元132、134形成電荷儲存結構138。部分電荷儲存材料層126的移除方法例如是乾式蝕施法、濕式蝕刻法或上述方法的組合。Then, referring to FIG. 1E, the charge storage material layer 126 located outside the opening 120 and outside the opening 122 is removed, and the charge storage units 128, 130 filling the opening 120 and the filling opening are formed on the dielectric material layer 124. Charge storage unit 132, 134 of 122. In this embodiment, the charge storage structures 136 are formed by physically disposing the charge storage units 128, 130, and the charge storage structures 138 are formed by physically separating the charge storage units 132, 134. The method of removing the portion of the charge storage material layer 126 is, for example, a dry etching method, a wet etching method, or a combination of the above methods.
接著，於介電材料層124表面上形成介電材料層140。介電材料層140的材料例如是氧化矽。介電材料層140的形成方法例如是化學氣相沉積法。Next, a dielectric material layer 140 is formed on the surface of the dielectric material layer 124. The material of the dielectric material layer 140 is, for example, ruthenium oxide. The method of forming the dielectric material layer 140 is, for example, a chemical vapor deposition method.
然後，請參照圖1F，移除位於開口120外部與位於開口122外部的介電材料層140及介電材料層124，在開口120外部與開口122外部留下位於閘極102上方的介電材料層124及介電材料層140而形成介電層148，而由位於開口120的表面與開口122的表面上的介電材料層124形成介電層142。部分介電材料層140與部分介電材料層124的移除方法例如是乾式蝕刻法。此時，可能會有部份介電材料層124及部分介電材料層140殘留在閘極118上方。Then, referring to FIG. 1F, the dielectric material layer 140 and the dielectric material layer 124 outside the opening 120 and outside the opening 122 are removed, and the dielectric material above the gate 102 is left outside the opening 120 and outside the opening 122. The dielectric layer 148 is formed by the layer 124 and the dielectric material layer 140, while the dielectric layer 142 is formed by the dielectric material layer 124 on the surface of the opening 120 and the surface of the opening 122. The method of removing the portion of the dielectric material layer 140 and the portion of the dielectric material layer 124 is, for example, a dry etching method. At this time, a portion of the dielectric material layer 124 and a portion of the dielectric material layer 140 may remain above the gate 118.
其中，位於開口120表面的介電層142與介電層112形成介電結構144，可用以隔離電荷儲存結構136中的電荷儲存單元128、130，且可使電荷儲存結構136與通道層114及閘極102進行隔離。位於開口122表面的介電層142與介電層116形成介電結構146，可用以隔離電荷儲存結構136中的電荷儲存單元132、134，且可使電荷儲存結構138與通道層114及閘極118進行隔離。The dielectric layer 142 on the surface of the opening 120 and the dielectric layer 112 form a dielectric structure 144, which can be used to isolate the charge storage units 128, 130 in the charge storage structure 136, and can cause the charge storage structure 136 and the channel layer 114 and The gate 102 is isolated. The dielectric layer 142 on the surface of the opening 122 and the dielectric layer 116 form a dielectric structure 146 that can be used to isolate the charge storage cells 132, 134 in the charge storage structure 136, and can cause the charge storage structure 138 and the channel layer 114 and the gate 118 for isolation.
此外，由介電結構144、通道層114、介電結構146與閘極118、設置於介電結構144中的電荷儲存結構136、及設置於介電結構146中電荷儲存結構138形成設置於閘極102上的堆疊結構150。雖然堆疊結構150是以上述方法所製作，然而堆疊結構150及其中的各構件的製造方法並不以此為限。In addition, a dielectric structure 144, a channel layer 114, a dielectric structure 146 and a gate 118, a charge storage structure 136 disposed in the dielectric structure 144, and a charge storage structure 138 disposed in the dielectric structure 146 are formed in the gate. Stack structure 150 on pole 102. Although the stacked structure 150 is fabricated in the above manner, the method of manufacturing the stacked structure 150 and each of the members thereof is not limited thereto.
另外，位於堆疊結構150兩側的閘極102上的介電層148，用以隔離閘極102與後續形成於介電層148上的源極與汲極。介電層148的厚度只要是可用以隔離閘極102與後續形成於介電層148上的源極與汲極即可。舉例來說，介電層148的厚度例如是約等於介電結構144的厚度。In addition, a dielectric layer 148 on the gates 102 on both sides of the stacked structure 150 is used to isolate the gates 102 from the source and drain electrodes formed on the dielectric layer 148. The thickness of the dielectric layer 148 may be used to isolate the gate 102 from the source and drain subsequently formed on the dielectric layer 148. For example, the thickness of the dielectric layer 148 is, for example, approximately equal to the thickness of the dielectric structure 144.
接下來，於介電層148上形成導體層152，且導體層152覆蓋堆疊結構150。導體層152的材料例如是摻雜多晶矽或金屬。導體層152的形成方法例如是化學氣相沉積法。Next, a conductor layer 152 is formed over the dielectric layer 148, and the conductor layer 152 covers the stacked structure 150. The material of the conductor layer 152 is, for example, doped polysilicon or metal. The method of forming the conductor layer 152 is, for example, a chemical vapor deposition method.
之後，請參照圖1G，移除部分導體層152，而形成位於通道層114兩側的源極與汲極154及源極與汲極156，且源極與汲極154、源極與汲極156與通道層114的厚度例如是實質上相同。部分導體層152的移除方法例如是乾式蝕刻法。此時，位於通道層114側壁上的導體層152會被移除，以防止閘極118與源極與汲極154及源極與汲極156相互導通。此外，可能會有部分導體層152殘留在介電材料層140上。Thereafter, referring to FIG. 1G, a portion of the conductor layer 152 is removed to form a source and a drain 154 and a source and a drain 156 on both sides of the channel layer 114, and a source and a drain 154, a source and a drain The thickness of 156 and channel layer 114 is, for example, substantially the same. The method of removing the partial conductor layer 152 is, for example, a dry etching method. At this time, the conductor layer 152 on the sidewall of the channel layer 114 is removed to prevent the gate 118 from being electrically connected to the source and drain 154 and the source and drain 156. In addition, a portion of the conductor layer 152 may remain on the dielectric material layer 140.
再者，可於源極與汲極154及源極與汲極156上形成介電材料層158，且介電材料層158覆蓋堆疊結構150。介電材料層158的材料例如是氧化矽。介電材料層158的形成方法例如是化學氣相沉積法。Furthermore, a dielectric material layer 158 can be formed over the source and drain 154 and the source and drain 156, and the dielectric material layer 158 overlies the stacked structure 150. The material of the dielectric material layer 158 is, for example, yttrium oxide. The method of forming the dielectric material layer 158 is, for example, a chemical vapor deposition method.
隨後，請參照圖1H，移除部分介電材料層158，直到暴露出閘極118，以於源極與汲極154及源極與汲極156上形成位於閘極118兩側的介電層160。移除部分介電材料層158的同時，會一併移除位於閘極118上方的介電材料層124、介電材料層140與殘留在介電材料層140上的導體層152。部分介電材料層158、介電材料層140、介電材料層124與殘留在介電材料層140上的部分導體層152的移除方法例如是化學機械研磨法。Subsequently, referring to FIG. 1H, a portion of the dielectric material layer 158 is removed until the gate 118 is exposed to form a dielectric layer on both sides of the gate 118 on the source and drain 154 and the source and drain 156. 160. While removing a portion of the dielectric material layer 158, the dielectric material layer 124, the dielectric material layer 140, and the conductor layer 152 remaining on the dielectric material layer 140 are removed together. The method of removing a portion of the dielectric material layer 158, the dielectric material layer 140, the dielectric material layer 124, and the portion of the conductor layer 152 remaining on the dielectric material layer 140 is, for example, a chemical mechanical polishing method.
繼之，可於閘極118上形成連接導線162，且閘極118與連接導線162形成字元線164。連接導線162的形成方法例如是先利用化學汽相沉積法於閘極118上形成導體層(未繪示)，在對導體層進行圖案化而形成。導體層的材料例如是摻雜多晶矽或金屬。Next, a connection wire 162 can be formed on the gate 118, and the gate 118 and the connection wire 162 form a word line 164. The connecting wire 162 is formed by, for example, forming a conductor layer (not shown) on the gate 118 by chemical vapor deposition, and patterning the conductor layer. The material of the conductor layer is, for example, doped polysilicon or metal.
基於上述可知，上述實施例所提出之記憶體結構的製造方法可與現行製程進行整合，因此能有效地降低製程複雜度。Based on the above, the method for manufacturing the memory structure proposed in the above embodiments can be integrated with the current process, thereby effectively reducing the process complexity.
以下，藉由圖1H來說明第一實施例所提出之記憶體結構。圖2所繪示為圖1H的上視圖，圖1H為圖2中沿I-I'剖面線的剖面圖。Hereinafter, the memory structure proposed in the first embodiment will be described with reference to Fig. 1H. 2 is a top view of FIG. 1H, and FIG. 1H is a cross-sectional view taken along line II' of FIG. 2.
請同時參照圖1H及圖2，記憶體結構包括記憶胞166。各記憶胞166包括閘極102、堆疊結構150、介電層148、源極與汲極154及源極與汲極156。此外，記憶體結構更可包括介電層160、連接導線162及通道接出線170。連接導線162用以連接堆疊結構150中的閘極118，而形成字元線164。字元線164之間利用隔離結構168進行隔離。其中，一條字元線164對應一條由閘極102所形成的字元線，而由閘極102所形成的字元線之間利用隔離結構(未繪示)進行隔離。字元線164可不需對準由閘極102所形成的字元線。通道接出線170連接至通道層114，可將通道層114中所累積的電洞導出，以防止產生浮置基體效應(floating-body effect)，進而避免因通道層的電位提高而不易程式化的問題。通道接出線170的材料例如是金屬等導體材料。此外，記憶體結構中之其他構件的配置方式、材料、製造方法及功效已於上述實施例中進行詳盡地說明，故於此不再贅述。Referring to FIG. 1H and FIG. 2 simultaneously, the memory structure includes a memory cell 166. Each memory cell 166 includes a gate 102, a stacked structure 150, a dielectric layer 148, a source and drain 154, and a source and drain 156. In addition, the memory structure may further include a dielectric layer 160, a connecting wire 162, and a channel connecting line 170. Connecting wires 162 are used to connect the gates 118 in the stacked structure 150 to form word lines 164. The word lines 164 are isolated by an isolation structure 168. One word line 164 corresponds to one word line formed by the gate 102, and the word lines formed by the gate 102 are isolated by an isolation structure (not shown). The word line 164 may not need to be aligned with the word line formed by the gate 102. The channel connection line 170 is connected to the channel layer 114, and the holes accumulated in the channel layer 114 can be led out to prevent a floating-body effect, thereby avoiding the difficulty of stylizing due to the potential increase of the channel layer. The problem. The material of the channel connection line 170 is, for example, a conductor material such as metal. In addition, the arrangement, materials, manufacturing methods, and effects of other components in the memory structure have been described in detail in the above embodiments, and thus will not be described herein.
基於上述實施例可知，由於電荷儲存結構136中的電荷儲存單元128、130實體上分離設置，且電荷儲存結構138中的電荷儲存單元132、134實體上分離設置，所以當閘極長度進行微縮時，可防止在記憶胞166中的左右兩個電荷儲存單元128、130(或132、134)之間產生第二位元效應，因此可避免產生讀取錯誤。此外，由於電荷儲存結構136中的電荷儲存單元128、130實體上分離設置，且電荷儲存結構138中的電荷儲存單元132、134實體上分離設置，所以當源極與汲極154、156微縮時，可減少二次熱電子注入到相鄰的記憶胞166中的數量，進而降低程式化干擾的問題，而提升記憶體元件之可靠度。Based on the above embodiments, since the charge storage units 128, 130 in the charge storage structure 136 are physically disposed apart, and the charge storage units 132, 134 in the charge storage structure 138 are physically separated, when the gate length is reduced. The second bit effect can be prevented from occurring between the left and right charge storage units 128, 130 (or 132, 134) in the memory cell 166, thus avoiding read errors. Moreover, since the charge storage units 128, 130 in the charge storage structure 136 are physically separated and the charge storage units 132, 134 in the charge storage structure 138 are physically separated, when the source and drain 154, 156 are miniature The number of secondary hot electrons injected into the adjacent memory cells 166 can be reduced, thereby reducing the problem of stylized interference and improving the reliability of the memory components.
以下，藉由圖1H來說明第一實施例所提出之記憶體結構的操作方法。Hereinafter, an operation method of the memory structure proposed in the first embodiment will be described with reference to FIG. 1H.
在對記憶胞166中的電荷儲存單元134進行程式化操作時，會在閘極118施加第一電壓、在閘極102施加第二電壓、在源極與汲極154施加第三電壓、且在源極與汲極156施加第四電壓，其中第一電壓大於第二電壓，且第四電壓大於第三電壓。第一電壓例如是11V、第二電壓例如是0V、第三電壓例如是0V、且第四電壓例如是4V，但本發明程式化操作的操作電壓並不以此為限。When the charge storage unit 134 in the memory cell 166 is programmed, a first voltage is applied to the gate 118, a second voltage is applied to the gate 102, a third voltage is applied to the source and the drain 154, and The source and drain 156 apply a fourth voltage, wherein the first voltage is greater than the second voltage and the fourth voltage is greater than the third voltage. The first voltage is, for example, 11 V, the second voltage is, for example, 0 V, the third voltage is, for example, 0 V, and the fourth voltage is, for example, 4 V. However, the operating voltage of the program operation of the present invention is not limited thereto.
在對記憶胞166中的電荷儲存單元134進行讀取操作時，會在閘極118施加第五電壓、在閘極102施加第六電壓、在源極與汲極154施加第七電壓、且在源極與汲極156施加第八電壓，其中第五電壓大於第六電壓，且第七電壓大於第八電壓。第五電壓例如是3V、第六電壓例如是0V、第七電壓例如是1.6V、且第八電壓例如是0V，但本發明讀取操作的操作電壓並不以此為限。When a read operation is performed on the charge storage unit 134 in the memory cell 166, a fifth voltage is applied to the gate 118, a sixth voltage is applied to the gate 102, a seventh voltage is applied to the source and the drain 154, and The source and drain 156 apply an eighth voltage, wherein the fifth voltage is greater than the sixth voltage and the seventh voltage is greater than the eighth voltage. The fifth voltage is, for example, 3V, the sixth voltage is, for example, 0V, the seventh voltage is, for example, 1.6V, and the eighth voltage is, for example, 0V, but the operating voltage of the read operation of the present invention is not limited thereto.
在對記憶胞166中的電荷儲存單元134進行抹除操作時，會在閘極118施加第九電壓、在閘極102施加第十電壓、在源極與汲極154施加第十一電壓、且在源極與汲極156施加第十二電壓，其中第十電壓大於第九電壓、第十二電壓大於第十一電壓、且第九電壓與第十二電壓的電性相反。第九電壓例如是-6V、第十電壓例如是0V、第十一電壓例如是0V、且第十二電壓例如是4V，但本發明抹除操作的操作電壓並不以此為限。When an erase operation is performed on the charge storage unit 134 in the memory cell 166, a ninth voltage is applied to the gate 118, a tenth voltage is applied to the gate 102, and an eleventh voltage is applied to the source and the drain 154, and A twelfth voltage is applied to the source and drain 156, wherein the tenth voltage is greater than the ninth voltage, the twelfth voltage is greater than the eleventh voltage, and the ninth voltage is opposite to the electrical property of the twelfth voltage. The ninth voltage is, for example, -6V, the tenth voltage is, for example, 0V, the eleventh voltage is, for example, 0V, and the twelfth voltage is, for example, 4V, but the operating voltage of the erasing operation of the present invention is not limited thereto.
此外，於此技術領域具有通常知識者參照上述實施例所揭露的操作方法可得知對記憶胞166中的電荷儲存單元128、130、134的操作方式，故於此不再贅述。In addition, the operation of the charge storage unit 128, 130, 134 in the memory cell 166 can be known by those skilled in the art with reference to the operation methods disclosed in the above embodiments, and thus will not be described herein.
圖3及圖4所繪示分別為本發明之第二實施例及第三實施例的記憶體結構的剖面圖。3 and 4 are cross-sectional views showing the memory structure of the second embodiment and the third embodiment of the present invention, respectively.
在第一實施例中，記憶體結構是以記憶胞166中的電荷儲存結構136、138分別為實體上分離設置的兩個電荷儲存單元128、130及132、134為例進行說明。然而，本發明的範圍並不以此為限，只要電荷儲存結構136、138中的至少一者為實體上分離設置的兩個電荷儲存單元即屬於本發明所保護的範圍。In the first embodiment, the memory structure is exemplified by two charge storage units 128, 130 and 132, 134 which are physically separated and separated by the charge storage structures 136, 138 in the memory cell 166, respectively. However, the scope of the present invention is not limited thereto, as long as at least one of the charge storage structures 136, 138 is physically separated from the two charge storage units, which is within the scope of the present invention.
舉例來說，請同時參照圖1H及圖3，第一實施例與第二實施例中的記憶體結構的差異在於：在第二實施例的記憶體結構中，電荷儲存結構136'為單一個電荷儲存單元，且介電結構144'包括介電層172與介電層174，其中介電層172設置於閘極102與電荷儲存結構136'之間，且介電層174設置於電荷儲存結構136'與通道層114之間。電荷儲存結構136'的材料例如是氮化矽、摻雜多晶矽或奈米晶粒。介電層172與介電層174的材料例如分別是氧化矽。第二實施例中的其他構件與第一實施例相似，故於此不再贅述。For example, referring to FIG. 1H and FIG. 3 simultaneously, the difference between the memory structures in the first embodiment and the second embodiment is that in the memory structure of the second embodiment, the charge storage structure 136' is a single one. a charge storage unit, and the dielectric structure 144' includes a dielectric layer 172 and a dielectric layer 174, wherein the dielectric layer 172 is disposed between the gate 102 and the charge storage structure 136', and the dielectric layer 174 is disposed on the charge storage structure Between 136' and the channel layer 114. The material of the charge storage structure 136' is, for example, tantalum nitride, doped polysilicon or nanocrystalline grains. The material of the dielectric layer 172 and the dielectric layer 174 is, for example, yttrium oxide, respectively. Other members in the second embodiment are similar to the first embodiment, and thus will not be described again.
此外，請同時參照圖1H及圖4，第一實施例與第三實施例中的記憶體結構的差異在於：在第三實施例的記憶體結構中，電荷儲存結構138'為單一個電荷儲存單元，且介電結構146'包括介電層176與介電層178，其中介電層176設置於通道層114與電荷儲存結構138'之間，且介電層178設置於電荷儲存結構138'與閘極118之間。電荷儲存結構138'的材料例如是氮化矽、摻雜多晶矽或奈米晶粒。介電層176與介電層178的材料例如分別是氧化矽。第三實施例中的其他構件與第一實施例相似，故於此不再贅述。In addition, referring to FIG. 1H and FIG. 4 simultaneously, the difference between the memory structures in the first embodiment and the third embodiment is that in the memory structure of the third embodiment, the charge storage structure 138' is a single charge storage. The dielectric structure 146' includes a dielectric layer 176 and a dielectric layer 178, wherein the dielectric layer 176 is disposed between the channel layer 114 and the charge storage structure 138', and the dielectric layer 178 is disposed on the charge storage structure 138'. Between the gate 118 and the gate. The material of the charge storage structure 138' is, for example, tantalum nitride, doped polysilicon or nanocrystalline grains. The material of the dielectric layer 176 and the dielectric layer 178 is, for example, yttrium oxide, respectively. Other members in the third embodiment are similar to the first embodiment, and thus will not be described again.
圖5所繪示為本發明之第四實施例的記憶體結構的剖面圖。Fig. 5 is a cross-sectional view showing the structure of a memory according to a fourth embodiment of the present invention.
第一實施例與第四實施例中的記憶體結構的差異在於：第四實施例中的記憶體結構具有堆疊設置的多個記憶胞166，垂直相鄰的兩個記憶胞166共用一條字元線。第四實施例中的其他構件與第一實施例相似，故於此不再贅述。The difference between the first embodiment and the memory structure in the fourth embodiment is that the memory structure in the fourth embodiment has a plurality of memory cells 166 arranged in a stack, and two vertically adjacent memory cells 166 share one character. line. Other members in the fourth embodiment are similar to the first embodiment, and thus will not be described again.
在第四實施例中，由於記憶體結構具有堆疊設置的多個記憶胞166，因此可以進一步地提升記憶體元件的積集度。In the fourth embodiment, since the memory structure has a plurality of memory cells 166 arranged in a stack, the degree of accumulation of the memory elements can be further improved.
綜上所述，上述實施例至少具有下列優點：In summary, the above embodiment has at least the following advantages:
1.上述實施例所提出之記憶體結構可解決由第二位元效應所造成的讀取錯誤，且可降低由二次熱電子所造成的程式化干擾。1. The memory structure proposed in the above embodiment can solve the reading error caused by the second bit effect and can reduce the stylized interference caused by the secondary hot electrons.
2.上述實施例所提出之記憶體結構的製造方法可與現行製程進行整合，因此能有效地降低製程複雜度。2. The method for fabricating the memory structure proposed in the above embodiments can be integrated with the current process, thereby effectively reducing the process complexity.
3.上述實施例所提出之記憶體結構可以進一步地提升記憶體元件的積集度。3. The memory structure proposed in the above embodiments can further enhance the accumulation of memory elements.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．基底100. . . Base
102、118．．．閘極102, 118. . . Gate
104．．．介電材料層104. . . Dielectric material layer
106．．．半導體材料層106. . . Semiconductor material layer
108、124、140、158．．．介電材料層108, 124, 140, 158. . . Dielectric material layer
110．．．閘極材料層110. . . Gate material layer
112、116、142、148、160．．．介電層112, 116, 142, 148, 160. . . Dielectric layer
114．．．通道層114. . . Channel layer
120、122．．．開口120, 122. . . Opening
126．．．電荷儲存材料層126. . . Charge storage material layer
128、130、132、134．．．電荷儲存單元128, 130, 132, 134. . . Charge storage unit
136、136’、138、138’．．．電荷儲存結構136, 136', 138, 138'. . . Charge storage structure
144、144’、146、146’．．．介電結構144, 144', 146, 146'. . . Dielectric structure
150．．．堆疊結構150. . . Stack structure
152．．．導體層152. . . Conductor layer
154、156．．．源極與汲極154, 156. . . Source and bungee
162．．．連接導線162. . . Connecting wire
164．．．字元線164. . . Word line
166．．．記憶胞166. . . Memory cell
168．．．隔離結構168. . . Isolation structure
170．．．通道接出線170. . . Channel output line
172、174、176、178．．．介電層172, 174, 176, 178. . . Dielectric layer
圖1A至圖1H所繪示為本發明之第一實施例的記憶體結構的製造流程剖面圖。1A to 1H are cross-sectional views showing a manufacturing process of a memory structure according to a first embodiment of the present invention.
圖2所繪示為圖1H的上視圖Figure 2 is a top view of Figure 1H
圖3及圖4所繪示分別為本發明之第二實施例及第三實施例的記憶體結構的剖面圖。3 and 4 are cross-sectional views showing the memory structure of the second embodiment and the third embodiment of the present invention, respectively.
圖5所繪示為本發明之第四實施例的記憶體結構的剖面圖。Fig. 5 is a cross-sectional view showing the structure of a memory according to a fourth embodiment of the present invention.
100．．．基底100. . . Base
102、118．．．閘極102, 118. . . Gate
148、160．．．介電層148, 160. . . Dielectric layer
114．．．通道層114. . . Channel layer
128、130、132、134．．．電荷儲存單元128, 130, 132, 134. . . Charge storage unit
136、138．．．電荷儲存結構136, 138. . . Charge storage structure
144、146．．．介電結構144, 146. . . Dielectric structure
150．．．堆疊結構150. . . Stack structure
154、156．．．源極與汲極154, 156. . . Source and bungee
162．．．連接導線162. . . Connecting wire
164．．．字元線164. . . Word line
166．．．記憶胞166. . . Memory cell
Claims (10)
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