201251093 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種太陽能電池的製造方法，特別是 指一種銅銦鎵硒（CIGS)薄膜太陽能電池的製造方法。 【先如技術】 銅銦鎵硒（CIGS)薄膜太陽能電池是以銅銦鎵硒四元合金 作為光吸收層，由於CIGS為直接能隙半導體，可以吸收較 大範圍波長的光線’並且具有高轉換效率、穩定性佳，因 此成為備受囑目的太陽能電池。 參閱圖1’為一種已知CIGS太陽能電池，包含：一基 板11、一彼覆在該基板11上的背電極12、一層由ciGS材 料製成的p型吸收層13、一層n型的緩衝層14，以及一個 由透明導電材料製成的頂電極15。在形成該aGS吸收層 13時，通常是先利用真空鍍膜方式，將銅銦鎵等三種金屬 鍵著在該背電極12的表面而形成—層三元合金層，再於該 三元合金層表面錢著一層砸薄膜，透過高溫砸化製程將該 二元合金層砸化成為該CIGS的吸收層13。 在砸化製程中，砸材料的用量是根據所欲形成的吸收 層U中的材料組成比例而配置，但是當溫度升高到贿 左右時’叫料會朝㈣方向擴散移動，而且邱料的上 =其它：體作為遮播’因此只有部分的栖材料會向下 層中，其餘的，則是往上擴散，而可 或其它形態存在於砸化製程所使用的腔體 致該吸收層13的财量未達預定比例，進而影響太陽能電 201251093 池的品質與轉換效率β 【發明内容】 因此，本發明之目的，即在提供一 丨你捉供種材料比例符合預 定需求、品質佳且轉換效率佳的太陽能電池的製造方法。 於是，本發明太陽能電池的製造方法，包人. (Α)在一基板上形成一第一電極； (Β)披覆一層由銅銦鎵製成的第一合金層在該第一合 金層的表面披覆一層砸薄膜層’再於該碼薄膜層：表面: 覆一層由銅銦鎵製成的第二合金層； (Q進行砸化處理，使該第—合金層、第二合金層皆與 該砸薄膜層反應而騎，該第—合金層、第二合金層及 該石西薄膜層化合形成-層由銅銦鎵砸製成# p型半導體層 (E>)在該p型半導體層的表面形成一 η型半導體層丨及 (Ε)在該半導體層的表面形成一第二電極。 其中，步驟（B)可以只進行一次，也可以進行至少兩次 之後再進行步驟（C)。 本發明之功效··藉由上下設置的第一合金層及第二合 金層將該硒薄膜層夾設在中間’使硒材料無論往上擴散： 彺下擴散’都可以與上方或下方的銅銦鎵合金反應而達到 砸化目的，因此本發明製成# p型半導體層的材料組成比 例與預定比例相同或較接近，使電池有良好品質與轉換效 率。 、 【實施方式】 4 201251093 有關本發明之前述及其他技術内容、特點 以下配合參考圖式之一個較佳實施例的 明效二 清楚的呈現。 ”，將可 參閱圖2,|發明太陽能電池的製造方法之—較佳實施 例’ ^於製造-個銅㈣邮⑽）薄膜太陽能電池，所述電 池包含：-基板2’以及由下往上依序披覆在該基板2上方 的第電極3、-p型半導體層4、一n型半導體層$與 一第二電極6。其中，該ρ型半導體層4是由銅銦鎵师料 製成，用於吸收光能，所述第一電極3及第二電極6則配 合將電能輸出至外部。 參閱圖2、3、4,本發明的製造方法包含下列步驟： (1) 進行步驟71:在該基板2上形成該第一電極3。該 基板2為矽基板、玻璃基板、可撓性基板，或不銹鋼基板 ’該第一電極3的材料為鉬（Mo)金屬。此步驟的具體方式 疋利用物理氣相沉積（Physical Vapor Deposition,簡稱PVD )或化學氣相沉積（Chemical Vapor Deposition, CVD)等真 空鍵膜方式’將Mo鍍著彼覆在該基板2上而形成薄膜狀的 第一電極3。所述PVD包含蒸鍍、濺鍍等方式，所述CVD 包含原子層化學氣相沉積 （Atomic Layer CVD，簡稱 ALCVD)、電聚輔助化學氣相沉積(Plasma-Enhanced CVD, 簡稱PECVD)等方式。 (2) 進行步驟72 :利用PVD或CVD等真空鍍膜方式’ 在該第一電極3的表面沉積彼覆一層由銅銦鎵（CIG)製成的 第一合金層41，接著同樣利用真空鍍膜方式’在該第一合 201251093 金層41的表面沉積披覆—層硒㈣薄膜層42,再於該硒薄 膜層42的表面沉積披覆—層同樣由銅銦鎵製成的第二合金 層43因此，所述硒薄祺層42被夾設在上下兩個合金層之 間而形成三明治結構。其中，該第-合金I 41的厚度為 0.3微米（㈣〜0.8微米，該第二合金層43的厚度為〇3微 米二〇.8微米’該砸薄膜層42的厚度為〇.5微米〜丨5微米 。實際製作日夺’該第一合金層41及第二合金層43的總厚 度約略等於該砸薄膜層42的厚度，冑CIG & Se的組成比 例約為1 : 1。 上述形成該第一合金層41及第二合金層43所使用的 鍍膜靶材，可以為一個包含有銅、銦、鎵金屬的合金靶材 。此外，也可以在真空腔體内分別設置銅、銦、鎵三種金 層的靶材，再利用共濺鍍方式使三種金屬共同沉積而構成 合金層。 (3)進行步驟73 :進行高溫的硒化處理，使該第一合金 層41、第二合金層43皆與該硒薄膜層42反應而硒化，進 而化合形成所述由銅銦鎵硒製成的p型半導體層4。本步驟 疋使用快速熱處理（Rapid Thermal Process,簡稱RTP)方式 ’也就是以較快的速度升溫至45(TC〜550eC，再以較緩慢的 速度降溫冷卻，而且經過數次的快速升溫及緩慢降溫的周 期過程，使硒化反應充分且完全。利用RTp方式使降溫速 度小於升溫速度’其緩慢降溫能避免因溫度改變太快而造 成破片。 其中，硒化處理必需升高溫度至45(TC ~55(TC，是為了 6 201251093 使該砸薄膜層40 _ .. 的硒材料具有足夠的移動動能，進而能朝 43，、進入=第—合金層4〗及朝上擴散進入該第二合金層 。二b &金層41及第二合金層43皆被砸化，當然 〇 &金層的材料擴散移動而與該硒薄膜層42反應201251093 VI. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing a solar cell, and more particularly to a method of manufacturing a copper indium gallium selenide (CIGS) thin film solar cell. [First as technology] Copper indium gallium selenide (CIGS) thin film solar cell is a copper indium gallium selenide quaternary alloy as a light absorbing layer, because CIGS is a direct energy gap semiconductor, can absorb a large range of wavelengths of light 'and has a high conversion With high efficiency and stability, it has become a high-profile solar cell. 1 is a known CIGS solar cell comprising: a substrate 11, a back electrode 12 coated on the substrate 11, a p-type absorber layer 13 made of ciGS material, and an n-type buffer layer. 14. A top electrode 15 made of a transparent conductive material. When the aGS absorber layer 13 is formed, three layers of a metal such as copper indium gallium are bonded to the surface of the back electrode 12 by a vacuum coating method to form a layer of a ternary alloy layer, and then the surface of the ternary alloy layer is formed. The binary alloy layer is deuterated into the absorption layer 13 of the CIGS by a high temperature deuteration process. In the deuteration process, the amount of the crucible material is configured according to the proportion of the material composition in the absorption layer U to be formed, but when the temperature rises to the left and right of the bribe, the material will spread and move in the direction of (four), and the material of the material is Upper = Other: The body acts as an obscuration' so that only part of the habitat material will be in the lower layer, and the rest will be diffused upwards, and other forms may exist in the cavity used in the deuteration process to cause the absorption layer 13 The amount of money does not reach the predetermined ratio, which in turn affects the quality and conversion efficiency of the solar energy 201251093 pool. [Inventive content] Therefore, the object of the present invention is to provide a glimpse of the ratio of the material to be harvested to meet the predetermined demand, good quality and conversion efficiency. A good method of manufacturing solar cells. Thus, in the method of fabricating the solar cell of the present invention, a first electrode is formed on a substrate; (Β) a first alloy layer made of copper indium gallium is coated on the first alloy layer. The surface is covered with a layer of tantalum film' and then the film layer: surface: a second alloy layer made of copper indium gallium; (Q is subjected to deuteration treatment, so that the first alloy layer and the second alloy layer are Riding with the tantalum film layer, the first alloy layer, the second alloy layer, and the litho thin film layer forming layer are made of copper indium gallium germanium, a #p-type semiconductor layer (E>) in the p-type semiconductor Forming an n-type semiconductor layer on the surface of the layer and forming a second electrode on the surface of the semiconductor layer. wherein step (B) may be performed only once, or may be performed at least twice after step (C) The effect of the present invention is that the selenium film layer is sandwiched in the middle by the first alloy layer and the second alloy layer disposed above and below, so that the selenium material diffuses upward: the underarm diffusion can be above or below The copper indium gallium alloy reacts to achieve the purpose of deuteration, so the present invention is made #p The material composition ratio of the semiconductor layer is the same as or close to the predetermined ratio, so that the battery has good quality and conversion efficiency. [Embodiment] 4 201251093 The foregoing and other technical contents and features of the present invention are preferably selected as follows. The clear effect of the embodiment is clearly shown. ", reference will be made to FIG. 2, a method of manufacturing a solar cell of the invention - a preferred embodiment of the invention - a copper (four) mail (10) thin film solar cell, the battery comprising a substrate 2' and a first electrode 3, a p-type semiconductor layer 4, an n-type semiconductor layer $ and a second electrode 6 which are sequentially overlying the substrate 2. The p-type semiconductor The layer 4 is made of a copper indium gallium material for absorbing light energy, and the first electrode 3 and the second electrode 6 cooperate to output electric energy to the outside. Referring to Figures 2, 3 and 4, the manufacturing method of the present invention The method includes the following steps: (1) performing step 71: forming the first electrode 3 on the substrate 2. The substrate 2 is a germanium substrate, a glass substrate, a flexible substrate, or a stainless steel substrate. The material of the first electrode 3 is Molybdenum (Mo) metal. This The specific method of the step is to form a thin film on the substrate 2 by using a vacuum bonding film method such as Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD). The first electrode 3. The PVD includes evaporation, sputtering, etc., and the CVD includes atomic layer chemical vapor deposition (ALCVD), electropolymerization-assisted chemical vapor deposition (Plasma-Enhanced CVD). (PECVD), etc. (2) Performing step 72: using a vacuum coating method such as PVD or CVD, depositing a first alloy layer 41 made of copper indium gallium (CIG) on the surface of the first electrode 3 Then, a vacuum coating method is also used to deposit a clad-selenium (tetra) film layer 42 on the surface of the first layer 201251093 gold layer 41, and then deposit a coating on the surface of the selenium film layer 42. The layer is also made of copper indium gallium. The second alloy layer 43 is thus formed, and the selenium thin layer 42 is sandwiched between the upper and lower alloy layers to form a sandwich structure. Wherein, the thickness of the first alloy I 41 is 0.3 micrometers ((4) to 0.8 micrometers, and the thickness of the second alloy layer 43 is 〇3 micrometers. 8 micrometers. The thickness of the tantalum thin film layer 42 is 〇.5 micrometers~丨 5 μm. The actual thickness of the first alloy layer 41 and the second alloy layer 43 is approximately equal to the thickness of the tantalum film layer 42, and the composition ratio of 胄CIG & Se is about 1:1. The coating target used for the first alloy layer 41 and the second alloy layer 43 may be an alloy target containing copper, indium or gallium metal. Further, copper, indium, or the like may be provided in the vacuum chamber. The target of the three gold layers of gallium is co-sputtered to form the alloy layer by co-sputtering. (3) Step 73: performing high-temperature selenization treatment to make the first alloy layer 41 and the second alloy layer 43 is reacted with the selenium thin film layer 42 to selenize, and then combined to form the p-type semiconductor layer 4 made of copper indium gallium selenide. This step uses a Rapid Thermal Process (RTP) method. Warm up to 45 (TC~550eC) at a faster rate, and then slow down The speed is cooled and cooled, and after several cycles of rapid temperature rise and slow cooling, the selenization reaction is sufficient and complete. The RTp method is used to make the cooling rate lower than the heating rate'. The slow cooling can avoid the fragmentation caused by the temperature changing too fast. Among them, the selenization treatment must raise the temperature to 45 (TC ~ 55 (TC, is for 6 201251093 so that the selenium material of the tantalum film layer 40 _ .. has sufficient moving kinetic energy, and then can go toward 43,, enter = - alloy layer 4 and diffused upward into the second alloy layer. Both b & gold layer 41 and second alloy layer 43 are deuterated, of course, the material of the 〇 & gold layer diffuses and moves with the selenium film layer 42 reaction
化合’但無論如何’最後都會使所述第-合金141、第I 合金層43及号τ g @ μ >3 〇Λ溥膜層42化合形成銅銦鎵硒層，此即為 °亥Ρ型半導體層4 ’其厚度約為1.5微米〜2.5微米。 3月的是，硒化處理時也可以同時在腔體中通入 碰化氫（H2Se)氣體，以提升硒化效果。 一個真空腔體内進 本步驟73肖前述步驟72可以在同 行，使製程步驟流暢並節省製程時間。 此外，前述步驟72也可以連續進行兩次或兩次以上之 後，再進行步驟73。舉例來說，若步驟72進行兩次，則在 該第電極3上方會形成兩組三明治結構，由下往上依序 形成CIG/S=CIG/CIG/Se/CIG，接著進行㈣η _化處 理即可使層薄膜化合成為該p型半導體層心但益論 步驟72進行幾次，都可以藉由控制每一膜層的厚度，使最 後形成的P型半導體層4的總厚度是固定的，例如，若步 驟72進行兩次’此時每一膜層的厚度應為只進行一次時的 膜層厚度的一半。 ⑷進行步驟74··在該p型半導體層4的表面形成該η 型+導體層5’其材料例如硫化锡（Cds)，並且可以利用化 學浸鍵（Chemieal Dip)、健熱解法伽叮py—is)、離子 層氣相反應法（Ion Layer Gas Reaeti〇n，帛稱⑽㈤，或連 201251093 續式離子層吸附反應法（Successive ionic Layer Adsorption and Reaction，簡稱SILAR)等方式形成。 (5)進行步驟75:在該n型半導體層5的表面形成該第 二電極6，該第二電極6為透明導電層，其材料例如氧化鋅 摻雜鋁（ZnO : A1)、氧化鋅摻雜硼（Zn0 : B)，或其它可導電 且可透光的材料，並且可以利用PVD、cVD或融膠凝膠法 (Sol-Gel)等方式形成。 綜上所述’本發明主要是改良該p型半導體層4的製 程，藉由上下設置的第一合金層41及第二合金層43將該 硒薄膜層42夾設在中間，無論硒材料往上擴散或往下擴散 都了以與上方或下方的銅銦錄合金反應而達到砸化目的 。因此’本發明藉由該第二合金層43作為硒薄膜層42的 上方阻障’避免砸材料未進行反應即散逸，改善以往CIGS 層的硒含量未達預定比例的缺點，本發明製成的p型半導 體層4的材料組成比例與預定比例相同或較接近，使電池 具有良好品質與轉換效率。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一種已知太陽能電池的示意圖； 圆2是一示意圖，顯示本發明太陽能電池的製造方法 之一較佳實施例所製作出的太陽能電池； 201251093 圖3是該較佳實施例的步驟流程圖；及 圖4是該較佳實施例各步驟進行時的流程示意圖。 201251093 【主要元件符號說明】 2…… .....基板 43....... ••第一合金層 3…… •…第一電極 5 ........ ••η型半導體層 4…… ••…P型半導體層 6 ........ ••第二電極 41 ····. .....第 合金層 71-75·· ••步驟 42···.. •…硒薄膜層 10The combination 'but in any case' will eventually combine the first alloy 141, the first alloy layer 43 and the τ g @ μ > 3 ruthenium film layer 42 to form a copper indium gallium selenide layer, which is The type semiconductor layer 4' has a thickness of about 1.5 μm to 2.5 μm. In March, it is also possible to simultaneously introduce a hydrogen halide (H2Se) gas into the cavity during selenization to enhance the selenization effect. In a vacuum chamber, step 73 can be performed in the same manner to make the process step smooth and save the process time. Further, the aforementioned step 72 may be carried out two or more times in succession, and then step 73 is performed. For example, if step 72 is performed twice, two sets of sandwich structures are formed above the first electrode 3, and CIG/S=CIG/CIG/Se/CIG is sequentially formed from bottom to top, followed by (iv) η-processing. The film can be thinned into the p-type semiconductor layer core, but the step 72 is performed several times, and the total thickness of the finally formed P-type semiconductor layer 4 can be fixed by controlling the thickness of each film layer. For example, if step 72 is performed twice, then the thickness of each film layer should be half of the film thickness when it is only performed once. (4) Performing step 74: forming the n-type + conductor layer 5' on the surface of the p-type semiconductor layer 4, such as tin sulfide (Cds), and utilizing a chemical dip bond (Chemieal Dip), a thermal solution gamma py —is), ion layer gas phase reaction method (Ion Layer Gas Reaeti〇n, nickname (10) (five), or even 201251093 continuous ion ionic layer adsorption reaction (SILAR), etc. (5) Step 75: forming the second electrode 6 on the surface of the n-type semiconductor layer 5, the second electrode 6 is a transparent conductive layer, such as zinc oxide doped aluminum (ZnO: A1), zinc oxide doped boron ( Zn0 : B), or other electrically conductive and light transmissive material, and can be formed by PVD, cVD or melt-gel method (Sol-Gel), etc. In summary, the present invention mainly improves the p-type. The process of the semiconductor layer 4 is performed by sandwiching the selenium film layer 42 by the first alloy layer 41 and the second alloy layer 43 disposed above and below, regardless of whether the selenium material diffuses upward or diffuses downward to be above or below The copper indium alloy reacts to achieve the purpose of deuteration. The present invention uses the second alloy layer 43 as the upper barrier of the selenium film layer 42 to prevent the ruthenium material from being unreacted or dissipated, thereby improving the disadvantage that the selenium content of the conventional CIGS layer is less than a predetermined ratio. The material composition ratio of the semiconductor layer 4 is the same as or closer to the predetermined ratio, so that the battery has good quality and conversion efficiency. However, the above is only a preferred embodiment of the present invention, and the present invention cannot be limited thereto. The scope of the invention, that is, the simple equivalent changes and modifications made by the invention in the scope of the invention and the description of the invention are still within the scope of the invention. [Fig. 1] A known solar cell A schematic diagram of a circle 2 is a schematic diagram showing a solar cell produced by a preferred embodiment of the method for fabricating a solar cell of the present invention; 201251093 FIG. 3 is a flow chart of the steps of the preferred embodiment; and FIG. 4 is a comparison Schematic diagram of the process of each step of the preferred embodiment 201251093 [Explanation of main component symbols] 2...... ..... Substrate 43....... •• First alloy layer 3... •...first electrode 5 ........ ••n-type semiconductor layer 4...••...P-type semiconductor layer 6 ........ ••second electrode 41 ·· ··· ..... Alloy layer 71-75··••Step 42···.. •...Selenium film layer 10