TW201250705A - Memory chip - Google Patents

Memory chip Download PDF

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TW201250705A
TW201250705A TW101118633A TW101118633A TW201250705A TW 201250705 A TW201250705 A TW 201250705A TW 101118633 A TW101118633 A TW 101118633A TW 101118633 A TW101118633 A TW 101118633A TW 201250705 A TW201250705 A TW 201250705A
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storage unit
unit
capacity
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TW101118633A
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Chul-Sung Park
Joo-Sun Choi
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

A memory chip is provided which includes a storage unit comprising a storage region having an arbitrary capacity greater than a first standard capacity of 2<SP>n</SP> and less than a second standard capacity that is twice greater than the first standard capacity; and a control unit for controlling write and read operations of data into and from the storage unit.

Description

201250705 42676pif 六、發明說明： 【發明所屬之技術領域】 本發明概念是關於記憶體晶片、記憶體系統及存取記 憶體晶片之方法，以及更特別地，是關於具有用最佳化使 儲存容量之記憶體晶片、記憶體系統以及存取記憶體晶片 之方法。 【先前技術】 用來存取記憶體晶片之儲存單元之位址設定為對應記 憶體晶片之儲存單元之儲存容量的位元數。每個位址的位 元可以具有數值0或1。相對應地，記憶體晶片之儲存容 量可以設置如2n標準容量。 【發明内容】 本發明概念提供具有最佳化使用之儲存容量之記憶體 晶片、記憶體系統以及存取記憶體晶片之方法。 根據本發明概念之觀點’提供一種記憶體晶片而包 括·儲存單元包括具有任意容量之儲存區，任意容量大於 具有2n的第一標準容量以及小於第二標準容量，第二標準 容量大於該第一標準容量的兩倍；以及控制單元用來控制 資料到該存單元的寫入操作以及資料從儲存單元的讀取操 作，以及控制單元與儲存單元構成為晶片，其中儲存單元 包括：第一子儲存單元回應於第一選擇信號而啟動且具有 第三標準容#;以及第二子儲存單元回應於第二選擇^號 而啟動且具有第四標準容量，以及其中第三標準容量^第 四標準容量之總和等於任意容量。 3 201250705 42676pif 記憶體晶片可以更進一步包括介面單元，用來回應於 第一選擇信號以傳輸關於第一子儲存單元之資料、位址及 控制信號到外部裝置，或回應於第一選擇信號以從外部裝 置接收關於第-子儲存單元之資料、位址及控制信號，或 疋回應於第一選擇信號以傳輸關於第二子儲存單元之資 料、位址及控制信號到外部裝置，或回應於第二選擇信號 以從外部裝置接收關於第二子儲存單元之資料、位址及控 制信號。 介面單元可以包括第一輸入/輸出單元用來傳輸或接 收關於第-子儲存單元之資料、位土止及控制信號，以及第 二輸入/輸出單元用來傳輸或接收關於第二子儲存單元之 資料、位址及控制信號，且所構成的第二輸入/輸出單元獨 立於第一輸入/輸出單元。 介面單元可以包括共用輸入/輸出單元而用來傳輸或 接收至少一群組，群組由關於第一子儲存單元之資料、位 址及控制信號所構成，以及傳輸或接收至少一群組群組 由關於第二子儲存單元之資料、位址及控制信號所構成。 構成第一子儲存單元之記憶單元的類型可以相同於構 成第二子儲存單元之記憶單元的類型。 構成第一子儲存單元之記憶單元的類型可以不同於構 成第二子儲存單元之記憶單元的類型。 儲存於第一子儲存單元之資料之使用相同於儲存於第 二子儲存單元之資料之使用。 、 儲存於第一子儲存單元之資料之使用不同於儲存於第 4 201250705 42676pif 一子儲存單元之資料之使用。 根據本發明概念之另一觀點’提供一種記憶體晶片而 包括：儲存單元，包括具有任意容量之儲存區，任意容量 大於具有2n的第一標準容量以及小於第二標準容量，第二 才木準谷量大於第一標準容量的兩倍；以及控制單元，用來 控制資料到儲存單元的寫入操作以及資料從儲存單元的讀 取操作，以及控制举元與儲存早元構成為晶片，其中基於 ，有位元數之記憶體位址而存取儲存單元，位元數與關於 第一標準容量之記憶體位址相比大了 1-位元。 〇〇若所接收到的記憶體位址沒有映射到儲存單元，控制 單元處理關於記憶體位址之存取結果可以視為失敗。 。。控制單元可以如此運作，如果對應於記憶體位址之儲 存單7〇為非啟動，或是若未接收到關於記憶體位址之命 令’則處理存取結果視為失敗。 用來存取儲存單元之記憶體位址可以包括用來存取區 、、且之的區組位址，以及關於儲存單元之區組位址可以設 定為比關於第—標準容量之區組位址大了 1-位元。 一用來存取儲存單元之記憶體位址可以包括用來存取列 ί於二於儲存單元之列位址可以設定為與 才不準谷罝之列位址相比大了 1-位元。 用來存取儲存單元之記憶齡址可以包_來存取複 之行位址，以及關於儲存單元之區組位址可以呀 疋為與關於第—標準容量之區組位址相比大了 1·位元/ °己憶體晶片可以為群組中的至少-個，其群組包括了 201250705 42676pif 動態隨機存取記憶體(dynamic random access memory， DRAM)、快取記憶體、電阻式隨機存取記憶體(resistive random access memory，RRAM)、磁電阻式隨機存取記憶 體(magnetoresistive random access memory，MRAM)以及相 變式隨機存取§己憶體（phase-change random access memory，PRAM)。 【實施方式】 此後，本發明概念將藉由解釋本發明之所附圖示之實 施例來詳述之。 然而，本發明概念可以以許多不同的形式來體現，而 此後不應解讀僅限於實施例所記載；此實施例是提供來讓 其揭露更為充分，以及將充分傳達發明構思給所屬技術領 域中具有通常知識者。 在此使用之科技是為了描述特定實施例之目的而不是 用來限制本發明概念。如同在此所使用的單數形式&quot;一，，和,， 此&quot;也用來包括複數形式，除非内容有清楚的表達其他的意 思。其將更進一步了解的是’當”包括”及/或”包含&quot;術語使 用在此說明中，是來詳細說明所述之特徵、數字、步驟、 操作、兀件及/或構件的存在，但不排除存在或增加其他特 徵、數字、步驟、操作、元件、構件及/或其群組 應了解的是，透過第一、第二、第三等術語，可以在 此使用來描述各種不同的元件、構件、區域、層及/或區塊， 而此7G件、構件、區域、層及/或區塊不應該被這些術語限 制。此術語只是用來區分元件、構件、區域、層或區塊間 6 201250705 420/bpif 的彼此。因此在下述稱為第—元件、構件、區域、層或區 塊亦可以第二元件、構件、區域、層或區塊相稱，而不會 違背本發明概念的教義。 曰 此後，本發明概念之實施例將藉由伴隨說明其實施例 之圖示的參考來描述。在圖示中，舉例來說，說明的形狀 可以根據製程之科技及/或容限而有所變形。因此，本發明 概念之實施例不應受限於當前說明的某種表示之形狀，而 可以包括因為製程而導致的形狀之修改或誤差。 如同在此一列元件之前之表達式“至少一的”之使 用’會修改整列元件而不個別修改列中之元件。 圖1為根據本發明概念之實施例的記憶體晶MCIP的 方塊圖。 參閱圖1 ’記憶體晶片MCIP包括儲存單元STU及控 制單元COU。如圖2所示，儲存單元STU可以儲存其容 量大於第一標準容量(2η，η為整數)而小於第二標準容量 (2η+1)的資料。此後，任意容量是指大於第一標準容量而小 於第二標準容量的容量。任意容量表示為ADEN(2n &lt;ADEN&lt;2n+1)。記憶體晶片MCIP可以是揮發性記憶體如 動態隨機存取記憶體(DRAM)，或是非揮發性記憶體如快 閃記憶體，電阻式隨機存取記憶體(RRAM)，磁電阻式隨 機存取記憶體（MRAM)，或相變式隨機存取記憶體 (PRAM)。 第一標準容量為2n。舉例來說，第一標準容量可以是 64Mb、128Mb、256Mb、512Mb、1Gb 或 2Gb。第二標準 7 201250705 42676pif 容量大於第一標準容量的兩倍。例如，若第一標準容量為 1Gb，則第二標準容量為2Gb。 圖3是說明根據標準行動DRAM(DDRx32)之標準容 量中之增加的位址之位元數。參閱圖3，當標準行動 DRAM(DDRx32)之標準容量倍增時，位址之位元數會增加 1位元。舉例來說，如果關於128Mb標準行動 DRAM(DDRx32)之位址設為 20 位元 (BA[1]:0，RA[11:0]，CA[7:0])，則關於 256Mb 標準行動 DRAM(DDRx32)之位址設為 21 位元 (BA[1]:0，RA[11:0]，CA[8:0])。 然而，在需要更高的容量及整合的記憶體晶片中，舉 例來說，由於在製程中的限制，需要更多時間來滿足增加 記憶體晶片之儲存容量以達到更高一級的標準容量之需 求，其容量大於現今商業化或發展中的最大標準容量。不 過’現今個人資訊使用量增加，而因此導致從記憶體晶片 之儲存單元需求的高容量的增加。同樣地，既然電子裝置 變得更為可攜帶，低耗能已是重要的要素。 即使在具有標準容量（如2州)之記憶體晶片的發展之 前’其標準容量大於其現今商業化或發展中的最大標準容 量(如2n)的兩倍’根據本發明概念之實施例之記憶體晶片 可以具有任意容量，其滿足高容量之需求以及能容易的存 取和控制。同樣地，根據本發明概念之實施例之記憶體晶 片可以具有最佳化之容量，來因應使用者考量之耗能或可 以像是易於存取控制資料的儲存與讀取的需求。在此將槔 8 201250705 4ZO/Opif 供細節描述。 存單圖V控制單元C〇U控制資料DTA到儲 的二取操作。^例來說， ' ^ —=、、 = 資料===== 讀取資料DTA顺應他之行及列。碰采寫入或 ϋΤΑ^ϋΑ六及。圖4B所示，儲存在儲存單元STU的資料 ®#/κ：ϋ I早is™讀取出來_#DTAux#料 触及絲科部裝置(未料）。雖在圖4 ^用=存資料DTA到儲存單元stu的位 =號號用來從儲存單元STU讀取資料_的位址以及 嫌5说，也可從外部裝置藉由介面單元ICU來接收位址 3=信L。在此實例中，外部裝置可以是底下將描述 之控制器。其細郎之描述將在底下提供之。 =5所示’記憶體晶片Μαρ可以構成於晶圓醫 儲存3 陰影部份所示’控制單元C〇U可以構成於 = 的外圍。如圖5所示，儲存單元STU可以 勿為預設儲存區(如區組）。在此實例中，控制單元cou可 構成·存單元 _面單二 =二：圖5特別表示201250705 42676pif VI. Description of the Invention: [Technical Field] The present invention relates to a memory chip, a memory system, and a method of accessing a memory chip, and more particularly, to optimizing storage capacity A memory chip, a memory system, and a method of accessing a memory chip. [Prior Art] The address of the storage unit for accessing the memory chip is set to the number of bits corresponding to the storage capacity of the storage unit of the memory chip. The bit of each address can have a value of 0 or 1. Correspondingly, the storage capacity of the memory chip can be set to a standard capacity of 2n. SUMMARY OF THE INVENTION The present inventive concept provides a memory chip, a memory system, and a method of accessing a memory chip having an optimized storage capacity. According to the concept of the present invention, a memory chip is provided, and the storage unit includes a storage area having an arbitrary capacity, the arbitrary capacity being greater than the first standard capacity having 2n and being smaller than the second standard capacity, the second standard capacity being greater than the first Two times the standard capacity; and the control unit is configured to control the writing operation of the data to the storage unit and the reading operation of the data from the storage unit, and the control unit and the storage unit are configured as a wafer, wherein the storage unit includes: the first sub-storage The unit is activated in response to the first selection signal and has a third standard capacity; and the second sub-storage unit is activated in response to the second selection number and has a fourth standard capacity, and wherein the third standard capacity is the fourth standard capacity The sum is equal to any capacity. 3 201250705 The 42676pif memory chip may further comprise an interface unit responsive to the first selection signal for transmitting data, address and control signals regarding the first sub-memory unit to the external device, or in response to the first selection signal to The external device receives the data, the address and the control signal about the first sub-memory unit, or responds to the first selection signal to transmit the data, the address and the control signal about the second sub-storage unit to the external device, or responds to the And selecting a signal to receive data, an address, and a control signal regarding the second sub-storage unit from the external device. The interface unit may include a first input/output unit for transmitting or receiving information about the first sub-memory unit, a bit stop and control signal, and a second input/output unit for transmitting or receiving information about the second sub-storage unit. Data, address and control signals, and the second input/output unit is constructed independently of the first input/output unit. The interface unit may include a shared input/output unit for transmitting or receiving at least one group, the group consisting of data, address and control signals regarding the first sub-storage unit, and transmitting or receiving at least one group of groups It consists of data, address and control signals about the second sub-storage unit. The type of the memory unit constituting the first sub-storage unit may be the same as the type of the memory unit constituting the second sub-storage unit. The type of the memory unit constituting the first sub-storage unit may be different from the type of the memory unit constituting the second sub-storage unit. The use of the data stored in the first sub-storage unit is the same as the use of the data stored in the second sub-storage unit. The use of the data stored in the first sub-storage unit is different from the data stored in the 4 201250705 42676pif sub-storage unit. According to another aspect of the inventive concept, a memory chip includes: a storage unit including a storage area having an arbitrary capacity, and any capacity is greater than a first standard capacity having 2n and a second standard capacity; The amount of valleys is greater than twice the capacity of the first standard; and the control unit is configured to control the writing operation of the data to the storage unit and the reading operation of the data from the storage unit, and the control element and the storage element are formed into a wafer, wherein The memory location is accessed by the memory address of the bit number, and the number of bits is 1-bit larger than the memory address of the first standard capacity. 〇〇If the received memory address is not mapped to the storage unit, the control unit processing the result of the access to the memory address can be regarded as a failure. . . The control unit can operate as such if the memory list corresponding to the memory address is not activated, or if the command for the memory address is not received, then processing the access result is considered a failure. The memory address used to access the storage unit may include a block address for accessing the area, and the block address of the storage unit may be set to be larger than the block address of the first standard capacity. Big one bit. A memory address for accessing the storage unit may include a column address for accessing the storage unit and may be set to be 1-bit larger than the column address of the database. The memory age address used to access the storage unit can be used to access the complex row address, and the block address of the storage unit can be larger than the block address of the first standard capacity. The 1/bit/° memory chip can be at least one of the groups, and the group includes 201250705 42676pif dynamic random access memory (DRAM), cache memory, resistive random Resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and phase-change random access memory (PRAM) . [Embodiment] Hereinafter, the present invention will be described in detail by explaining the embodiments of the accompanying drawings. However, the inventive concept may be embodied in many different forms, and should not be construed as being limited to the embodiments. The embodiments are provided to provide a more complete disclosure and to fully convey the inventive concept to the technical field. Have the usual knowledge. The technology used herein is for the purpose of describing particular embodiments and is not intended to limit the inventive concepts. As used herein, the singular forms &quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot; It will be further understood that the term "and" includes "and/or" includes the <RTI ID=0.0>&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot;&quot; However, it should not be understood that the presence or addition of other features, numbers, steps, operations, components, components, and/or groups thereof should be understood by the first, second, third, etc. Elements, components, regions, layers and/or blocks, and such 7G members, components, regions, layers and/or blocks should not be limited by these terms. This term is only used to distinguish elements, components, regions, layers or regions. Inter-block 6 201250705 420/bpif each other. Therefore, the following elements, components, regions, layers or blocks may also be commensurate with the second element, component, region, layer or block without departing from the inventive concept. The teachings of the present invention will be described by reference to the accompanying drawings which illustrate the embodiments thereof. In the drawings, for example, the illustrated shapes may be based on the technology and/or tolerance of the process. and Variations are therefore made. Therefore, embodiments of the inventive concept should not be limited to the shape of a representation of the present description, but may include modifications or errors in shape due to the process. As in the expression before this column of elements " At least one of the "uses" will modify the entire list of elements without individually modifying the elements in the columns. Figure 1 is a block diagram of a memory crystal MCIP in accordance with an embodiment of the inventive concept. Referring to Figure 1 'The memory chip MCIP includes a memory cell STU and control unit COU. As shown in Fig. 2, the storage unit STU can store data whose capacity is larger than the first standard capacity (2η, η is an integer) and smaller than the second standard capacity (2η+1). Thereafter, any capacity is Refers to a capacity greater than the first standard capacity and less than the second standard capacity. Any capacity is expressed as ADEN (2n &lt; ADEN &lt; 2n + 1). The memory chip MCIP may be a volatile memory such as dynamic random access memory (DRAM) ), or non-volatile memory such as flash memory, resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or phase change random access memory (PRAM) The first standard capacity is 2n. For example, the first standard capacity may be 64Mb, 128Mb, 256Mb, 512Mb, 1Gb or 2Gb. The second standard 7 201250705 42676pif capacity is greater than twice the capacity of the first standard. For example, if the first The standard capacity is 1Gb, and the second standard capacity is 2Gb. Figure 3 is a diagram illustrating the number of bits in the standard capacity of the standard mobile DRAM (DDRx32). See Figure 3, when the standard mobile DRAM (DDRx32) When the standard capacity is multiplied, the number of bits in the address is increased by one bit. For example, if the address of the 128Mb standard mobile DRAM (DDRx32) is set to 20 bits (BA[1]:0, RA[11: 0], CA[7:0]), the address of the 256Mb standard mobile DRAM (DDRx32) is set to 21 bits (BA[1]:0, RA[11:0], CA[8:0]) . However, in memory chips that require higher capacity and integration, for example, due to limitations in the process, more time is required to meet the need to increase the memory capacity of the memory chip to achieve a higher standard capacity. Its capacity is greater than the largest standard capacity in commercialization or development today. However, the amount of personal information used today has increased, thus resulting in a high capacity increase from the storage unit of the memory chip. Similarly, since electronic devices have become more portable, low energy consumption has become an important factor. Even before the development of a memory chip having a standard capacity (such as 2 states), its standard capacity is more than twice the maximum standard capacity (such as 2n) in its current commercialization or development'. Memory according to an embodiment of the inventive concept The bulk wafer can have any capacity that meets the needs of high capacity and can be easily accessed and controlled. Similarly, a memory chip in accordance with an embodiment of the inventive concept can have an optimized capacity to accommodate the energy consumption of the user or to facilitate the storage and reading of control data. Here 槔 8 201250705 4ZO/Opif is described in detail. The deposit order map V control unit C〇U controls the data DTA to store the second take operation. ^ For example, ' ^ —=, , = data ===== Read the data DTA to follow his line and column. Hit and write or ϋΤΑ^ϋΑ6 and. As shown in Fig. 4B, the data stored in the storage unit STU ® # / κ: ϋ I is detected by the isTM _#DTAux# material touches the silk department device (unexpected). Although in FIG. 4, the bit = number used to store the data DTA to the storage unit stu is used to read the address of the data_ from the storage unit STU, and the address can be received from the external device through the interface unit ICU. Address 3 = letter L. In this example, the external device can be a controller as will be described below. The description of its slang will be provided below. The memory chip Μαρ shown in =5 can be formed in the shaded portion of the wafer memory. The control unit C〇U can be formed on the periphery of =. As shown in FIG. 5, the storage unit STU may not be a preset storage area (such as a block). In this example, the control unit cou can constitute a storage unit _ face two = two: Figure 5 shows

曰如圖5所示’具有任意容量及實現為一晶片之記憶體 二片νΓϋ’可以與控制器⑽一同用來實現記憶體系統 圖6所示。如圖1及圖6所示，記憶體系統MSYS 201250705 42676pif 之控制器Ctrl為了寫入資料DTA到記憶體晶片MCIP之 儲存早元STU，而傳輸資料DTA、位址Addr及控制信號 XCON到記憶體晶片MCIP。同樣地，控制器Ctrl為了從 記憶體晶片MCIP之儲存單元STU來讀取資料DTA，而 傳輸位址Addr及控制信號XCON到記憶體晶片MCIP，以 及從記憶體晶片MCIP接收資料DTA。 在此實例中，從控制器Ctrl傳輸到記憶體晶片MCIP 的位址Addr之位元數’可以對應記憶體晶片Μαρ之儲存 容量。舉例來說，記憶體晶片MCIP之儲存單元STU具有 2&quot;之儲存容量’即第一標準容量，位址Addr之位元數可以 為η。同樣地，記憶體晶片MCIP之儲存單元STU具有2n+1 之儲存容量，即第二標準容量，位址Ad(k之位元數可以 為 n+1。 承上述，記憶體晶片MCIP之儲存單元STU具有任意 容量。相對應地，使用了不同於標準容量之存取方法。 圖7是根據本發明概念之另一實施例的記憶體晶片 MCIP之方塊圖。圖8是如圖7所示第一及第二子儲存單 兀SSU1及SSU2之存取方法的流程圖。 ▲，圖1、圖7及圖8所示，存取方法包括回應第一選 擇^號ssi而啟動第一子儲存單元SSU1及存取第一子儲 存單to SSU.1(操作S82G);以及回應第二選擇信號SS2而 啟動第二子儲存單元SSU2及存取第二子儲存單元 SSU2(操作S840)。圖i中所示之儲存單元STU也可包括 如圖7所之第-及第二子儲存單元ssm及SSU2。在此 201250705 4ZO/〇pif 實例中，第一子德左S _ 存容量，以及具有第三標準容量(2X)之儲 紗六六旦子儲存早元SSU2具有第四標準容量(2y) h丨氺:今^里。第二及第四標準容量之和等於任意容量。舉 1及第四容量為3GB，第三標準容量可以為2GB 以及第四私準容量可以為1GB。 回應第-選擇信號SS1而啟動第—子儲存單元 ssm。基於關於第—子儲存料ssm之位址偷1而存 取所啟動=第-子儲存單元ssm。在此實例中，關於第 =儲存單元ssui之位址Addrl之位元數設定為對應於 第三標準容量⑺。資料DTA1及㈣㈣XCQm可以傳 ，到存取的第—子儲存單元SSU1，或是資料DTA1可以 從存取的第-子儲存單元SSU1輸出。 在，實例中，傳輸到第一子儲存單元SSU1關於第一 子儲存單元/SU1之資料DTA卜條Addirl或控制信號 XCON1之操作’或從第一子儲存單元SSU1輸出關於第一 子儲存單元SSU1之資料DTA卜位址A_或控制信號 XC〇N1之操作’用來操作圖1所示之控制單元C0U，^ 操=施加對應資料DTA卜位址Addrl、或關於第一子^ 存單元ssui之控制信號XC0N1的電壓到存取使用之儲 存區(記憶單元）。舉例來說，如果位址Addrl指向第一子 儲存單元SSU1之第一記憶單元（未繪示），控制信蜆 XCON1是寫入命令，以及資料dTA1表示為數值丨，則圖U 1所示之控制單元COU施加電壓對應寫入數值丨之操作’ 到—個連接到第—記憶單元的行與列。此後，傳輪到子儲 11 201250705 42676pifAs shown in Fig. 5, a memory having an arbitrary capacity and implemented as a chip, two νΓϋ's can be used together with the controller (10) to implement a memory system as shown in Fig. 6. As shown in FIG. 1 and FIG. 6, the controller Ctrl of the memory system MSYS 201250705 42676pif transfers the data DTA, the address Addr and the control signal XCON to the memory in order to write the data DTA to the memory chip MCIP storage early STU. Wafer MCIP. Similarly, the controller Ctrl transfers the address Addr and the control signal XCON to the memory chip MCIP and the data DTA from the memory chip MCIP in order to read the data DTA from the memory cell STU of the memory chip MCIP. In this example, the number of bits transmitted from the controller Ctrl to the address of the memory chip MCIP, Addr, may correspond to the storage capacity of the memory chip Μαρ. For example, the storage unit STU of the memory chip MCIP has a storage capacity of 2&quot;, i.e., the first standard capacity, and the number of bits of the address Addr may be η. Similarly, the storage unit STU of the memory chip MCIP has a storage capacity of 2n+1, that is, a second standard capacity, and the address Ad (the number of bits of k can be n+1. According to the above, the storage unit of the memory chip MCIP The STU has an arbitrary capacity. Correspondingly, an access method different from the standard capacity is used. Fig. 7 is a block diagram of a memory chip MCIP according to another embodiment of the inventive concept. A flowchart of an access method for the first and second sub-storage units SSU1 and SSU2. ▲, as shown in FIG. 1, FIG. 7, and FIG. 8, the access method includes starting the first sub-storage unit in response to the first selection ssi ssi SSU1 and accessing the first sub-storage list to SSU.1 (operation S82G); and initiating the second sub-storage unit SSU2 and accessing the second sub-storage unit SSU2 in response to the second selection signal SS2 (operation S840). The illustrated storage unit STU may also include the first and second sub-storage units ssm and SSU2 as shown in Figure 7. In the 201250705 4ZO/〇pif instance, the first sub-left S _ storage capacity, and the third Standard capacity (2X) storage yarn sixty-six-denier storage early SSU2 has a fourth standard capacity (2y h丨氺: This is the current. The sum of the second and fourth standard capacities is equal to any capacity. The 1st and 4th capacities are 3GB, the third standard capacity can be 2GB, and the fourth private capacity can be 1GB. - Selecting the signal SS1 to activate the first sub-storage unit ssm. Accessing the activated = first-sub-storage unit ssm based on the address of the first sub-stock ssm. In this example, regarding the = storage unit ssui The bit number of the address Addrl is set to correspond to the third standard capacity (7). The data DTA1 and (4) (4) XCQm can be transmitted to the accessed first sub-storage unit SSU1, or the data DTA1 can be accessed from the first-sub-storage unit SSU1 output. In the example, the operation to the first sub-storage unit SSU1 regarding the data DTA of the first sub-storage unit /SU1, the operation of the control signal XCON1 or the output of the first sub-storage unit SSU1 The operation of the data unit DSU address A_ or the control signal XC〇N1 of the storage unit SSU1 is used to operate the control unit C0U shown in Fig. 1, and the operation data DTA address Addrl is added, or about the first child ^ Storage unit ssui control signal XC0N1 To access the storage area (memory unit). For example, if the address Addrl points to the first memory unit (not shown) of the first sub-storage unit SSU1, the control signal XCON1 is a write command, and the data dTA1 Expressed as a numerical value, the control unit COU shown in Figure U1 applies a voltage corresponding to the operation of writing the value 丨 to a row and column connected to the first memory unit. Thereafter, the transfer to the sub-store 11 201250705 42676pif

•選擇信號SS1可以直接實施於第一 以啟動電源傳到第一子儲存單元 子儲存單元SSU1 , 料的操作’也如同上述鱗而執行。 如圖7所示，第一選擇信號SS1 jui㉟而本發明概念不受限於此。第—選擇信號⑻ =也藉由啟動及傳輸位址Addr卜控制信號XC0N1或 貝=DTA1到第一子儲存單元ssm來啟動第一子儲存單 凡SSU1。相同的原則將實施到下列描述。 ，次參_ 7，回應第二選擇信號脱而啟動第二子 :子單7L SSU2。基於關於第二子儲存單元SSU2之位址 =·2來存。取第二子儲存單元卿2。在此實例中，關於第 -儲存單70 SSU2之位址Ad(k2之㈣數蚊為對應第 四標準容量⑺。f料DTA2及控制信號 XCON2可以傳輸 子取之第一子儲存單元SSU2 ’或是資料DTA2可以從 存取之第二子儲存單元；581；2輸出。 〇 ，於巧第一及第二選擇信號SS1及SS2之中之啟動信 號面單元ICU可以傳輸或接收關於第一子儲存單元 SSU1之資料DTA1、位址Addrl或控制信號卜或 可以傳輸或接收關於第二子儲存單元SSU2之資料 DTA2、位址Addr2、或控制信號xc〇N2。 、如上述所提，根據本發明概念之實施例的記憶體晶片 可以包括具有任意容量之儲存單元，⑽存單元可以分為 具Ϊ不同標準容量之子儲存單元來分職動及存取其子儲 存單π »在此實例巾，基於具有對應其標準容量之位元數 12 201250705 42676pif 的位址來存取各個子儲存單元。相對應地，雖然標準容量 實現如同任意容量，既然只有簡單地選擇子儲存單元來存 取之附加操作，根據本發明概念之實施例之記憶體晶片可 以簡易地控制其存取。 再次參閱圖7，可以從控制器Ctrl來接收第一及第二 選擇^號SS1及SS2，如圖9所示。當位址Addr輸出， 控制器Ctrl可以基糾立土止Addr之位元數來傳輸第一及第 一選擇4§!虎SS1及SS2的其中之一到記憶體晶片Μαρ。 如圖9所示之介面單元Icu可以包括第一選擇信號輸入單 =ssii來接收第一選擇信號ss卜以及第二選擇信號輸入 單兀SSI2來接收第二選擇信號SS2，如圖1〇所示。可以 獨立地包括第—及第二選擇信號輸人單元觀及s犯。 可以從控制器Ctrl傳輸第一及第二選擇信號SS1及 SS2 ’如® 1〇所不，或如目u所示可以產生於記憶體晶 MCIP中。如圖11所示之介面單元ICU基於接收位址 Addr來啟動第一及第二選擇信號如及脱的其中之一。 。。一對於此，介面單元ICU包括位址輸入單元AI及選擇 早疋SEL。位址輸入單元AI接收從控制器⑽而來的位 ^八她。選擇單元SEL輸出關於位址Addr所指之子儲存 =的選擇信號。舉例來說，控制器㈤可以藉由包括識 二來指，取之子儲存單元是第一子儲存單元ssui或 二子儲存單几SSU2以產生位址Addr。在此實例中選 早疋SEL可以基於包括在位址Addr巾之識別符來啟動 一及第二選擇信號SS1及SS2的其中之一。 13 201250705 42676pif 另外，如圖12所示，介面單元ICU之位址輸入單元 亡I接收關，第-子儲存單元SSU1之位址八細或關於第 -子儲料元SSU2之位址Addl*2。選擇單元SEL基於從 位址輸入單元AI傳輸之位址之位元數來啟動第一及第二 選擇信號SS1及SS2其中之…舉例來說，如果χ_位元之 位址，收’選擇單元SEL可以啟動第一選擇信號如，而 如果是y-位元之位址則可以啟動第二選擇信號SS2。 基於從第一及第二選擇信號SS1及SS2其中之經選擇 信號’啟動第一及第二子儲存單元ssm及SSU2其中之 一。這就是，基於從第一及第二選擇信號SS1及SS2其中 之-之關於第-及第二子错存單元ssm及SSU2其中之 -之，選擇信號’資料、位址或控制信號傳輸騎應之子 儲存單元’或是從子儲存單元輸出關於第—及第二子儲存 單元SSU1及SSU2其中之一之資料。 在圖9到圖12中，在控制器ctrl及記憶體晶片Μαρ 之間傳輸或接收信號(選擇信號、位址、資料及控制信號） 之中’為了方㈣目的’只有需要解釋的健才會說明。 雖然第-及第二選擇㈣SS1&amp;SS2可以藉由利用各種不 同之方法產生，此後為了解釋的方便，將假設其第一及第 二選擇信號SS1及SS2是從外部裝置(例如控制器Qrl)來 傳輪。 介面單元ICU也傳輸或接收如同上述之資料、位址或 控制信號。對於此，如圖13所示，介面單元ICU包括第 -及第二輸入/輸出單元101及1〇2。第一輸入/輸出單元 201250705 4Z676pif ιοί傳輸或接收到或從外部裝置(如控制器Ctrl)之關於第 一子儲存單元SSU1之資料DTA1、位址Addrl或控制信 號 XCON1。 ° 第一輸入/輸出單元101可以包括第一位址輸入單元 All來接收關於第一子儲存單元SSU1之位址Addrl，第一 控制信號輸入單元CI1來接收關於第一子儲存單元SSU1 之控制信號XCON卜以及第一資料輸入/輸出單元DI〇1 來傳輸或接收關於第一子儲存單元SSU1之資料DTA1。 第一位址輸入單元All、第一控制信號輸入單元cn以及 第資料輸入/輸出單元DIOl可以實現如輸入引腳及輸入 /輸出引腳’或輸入引墊及輸入/輸出引墊。 第二輸入/輸出單元102分別於第一輸入/輸出單元 101而單獨構成β第一輸入/輸出單元1〇2傳輸或接收到或 從外部裝置(如控制器Ctrl)之關於第二子儲存單元SSU2資 料DTA2、位址Addr2或控制信號xCON2。第二輸入/輸 出單元102可以包括第二位址輸入單元AI2來接收關於第 =子儲存單元SSU2之位址Addr2，第二控制信號輸入單 元CI2來接收關於第二子儲存單元SSU2之控制信號 XCON2，以及第二資料輸入/輸出單元m〇2來傳輸或接收 ，於第二子儲存單元SSU2之資料DTA2。第二位址輸入 單元AI2、第二控制信號輸入單元α2及第二資料輸入/輸 出單元DI02可以實現如輸入引腳及輸入/輸出引腳，或輸 入引墊及輸入/輸出引墊。 介面單元ICU可以進一步包括上述之第一及第二選擇 15 201250705 42676pif 信號輸入單元SSI1及SSI2。 圖13顯示這樣的例子，當關於第一子儲存單元SSU1 之二料DTA1、位址Addrl及控制信號xc〇Ni，以及關於 ，:子儲存單元SSU2之資料DTA2、位址A她2及控制 5號XC〇N2接收時是透過不同的輸入/輸出單元，如第一 =二輸入/輸出單元101及1〇2。另外，如圖14所示， f Γ及第二子儲存單元SSU1及SSU2可以制輪入/輸出 旱7L。 圖14所示之介面單元ICU可以包括共用位址輸入單 =CAI、共用控制信號輸入單元CCI及共用資料輸入/輸出 早元CDIO。共用位址輸入單元CAI從控制器c⑴接收位 址jdch· ’傳輸_第-子儲存單元ssm之位址Addri到 第-子儲存單元SSm，以及傳輸關於第二子儲存單元 SSU2之位址Addr2到第二子儲存單元ssm。共用控制作 戒輸入單it cci從控制器ctrl接收控制信號xc〇N，傳^ 關於，一子儲存單元SSU1之控制信號XCON1到第一子 儲f單兀SSU卜以及傳輸關於第二子儲存單元SSU2之控 XCON2爿第二子儲存單元SSU2。共用資料輸入/ 」出單το CDIO從控制器Ctrl接收資料DTA，傳輸關於第 一子儲存單元SSU1之資料DTA1到第一子儲存單元 SSU1 ’以及傳輸關於第二子儲存單元之資料OTA〗 到第二子儲存單元SSU2。同樣地，制f料輸人/輸出單 元CDIO分別從第一及第二子儲存單元SSU1及ssu2 輸資料DTA1及DTA2到控制器Ctrl。 201250705 42676pif 介面單元ICU可以進一步包括上述之第一及 信號輸入單元SSI1及SSI2。共用位址輸人單元CAI、、丘 用控制錢輸人單元ca及制資浦人/_單元cm〇 可以回應於從第-選擇信號輸人單元ssn傳輸 擇信號SS1來分別選擇及輸出關於第-子儲存單元SSU1 之位址Addr卜控制信號XCON1及資料DTA1。同樣地， 共用位址輸人單元CAI、共肋繼號輸人單元ccj及庄 可㈣胁料二鄉信號輸 傳輸之第二選擇信號SS2來分別選擇及輸出 關於第一子儲存單元SSU2之資料dta 控制信號XCON2。 诅址Addr2及 元及圖15B顯示圖7所示之第一及第二子儲存單 兀SSU1及SSU2的例子。 ^圖15A，第—及第二子儲存單元ssm及ssu2 同區組數。圖15A特別表示這樣的例子，當第 存單元SSU1及SSU2個別包括4個區組 第三在財财，如果第-讀存單元麵的 容lift里(2)Α於第二子儲存單元SSU2的第四標準 子儲=第二子儲存單元SSU2的該大何則、於第-储存早元ssm的區組大小。 及sstiL如圖15B所示，第—及第二子儲存單元ssin 子，、包括不同區組數。® 15A_表示這樣的例 二子=：：子儲存單元麵包括8區組A到Η，以及第 子早7LSSU2包括4個區組Α到D。在此實例中， 17 201250705 42676pif 如果第Γ子儲存單元SSU1的第三標準容量(2X)大於第二 =儲存單元SSU2的第四標準容量⑺，第一及第 早元ssm及SSU2可以具有_區組大小。• The selection signal SS1 can be directly implemented on the first to initiate power transfer to the first sub-storage unit sub-storage unit SSU1, and the operation of the material is also performed as described above. As shown in FIG. 7, the first selection signal SS1 jui35 and the inventive concept are not limited thereto. The first-selection signal (8) = also activates the first sub-storage SSU1 by starting and transmitting the address Addrb control signal XC0N1 or B1 = DTA1 to the first sub-storage unit ssm. The same principles will be implemented to the following description. , sub-parameter _ 7, in response to the second selection signal off and start the second sub: sub-single 7L SSU2. The address is stored based on the address of the second sub-storage unit SSU2 = 2. Take the second sub-storage unit 2 . In this example, the address of the first storage unit 70 SSU2 is Ad (the number of (4) mosquitoes of k2 is corresponding to the fourth standard capacity (7). The material DTA2 and the control signal XCON2 can transmit the first sub-storage unit SSU2 ' or Is the data DTA2 can be accessed from the second sub-storage unit; 581; 2 output. 〇, the activation signal plane unit ICU among the first and second selection signals SS1 and SS2 can transmit or receive the first sub-storage The data DTA1, the address Addrl or the control signal of the unit SSU1 may transmit or receive the data DTA2, the address Addr2, or the control signal xc〇N2 regarding the second sub-storage unit SSU2. As mentioned above, according to the concept of the present invention The memory chip of the embodiment may include a storage unit having an arbitrary capacity, and (10) the storage unit may be divided into sub-storage units having different standard capacities to divide and access the sub-storage unit π » in this example, based on having Corresponding to the address of the standard capacity of 12 201250705 42676pif to access each sub-storage unit. Correspondingly, although the standard capacity is implemented as arbitrary capacity, since it is simply selected The additional operation of the sub-storage unit for accessing, the memory chip according to the embodiment of the inventive concept can be easily controlled for access. Referring again to FIG. 7, the first and second selections can be received from the controller Ctrl. And SS2, as shown in Figure 9. When the address Addr is output, the controller Ctrl can correct the number of bits of the Addr to transmit the first and first choices 4 §! One of the SS SS1 and SS2 to the memory The body unit Μαρ. The interface unit Icu as shown in FIG. 9 may include a first selection signal input unit=ssii to receive the first selection signal ssb and a second selection signal input unit SSI2 to receive the second selection signal SS2, as shown in the figure. 1〇. It can independently include the first and second selection signals to input the unit and s. The first and second selection signals SS1 and SS2 can be transmitted from the controller Ctrl, such as The unit u can be generated in the memory crystal MCIP. The interface unit ICU shown in FIG. 11 activates one of the first and second selection signals, such as a sum, based on the receiving address Addr. The interface unit ICU includes an address input unit AI and The address input unit AI receives the bit from the controller (10). The selection unit SEL outputs a selection signal regarding the sub-storage= indicated by the address Addr. For example, the controller (5) can be used by Including the second reference, the sub-storage unit is the first sub-storage unit ssui or the two sub-storage SSU2 to generate the address Addr. In this example, the pre-selection SEL can be started based on the identifier included in the address Addr towel. One of the first and second selection signals SS1 and SS2. 13 201250705 42676pif In addition, as shown in FIG. 12, the address input unit of the interface unit ICU is deactivated, and the address of the first sub-memory unit SSU1 is eight or Regarding the address of the first-sub-stock SSU2, Addl*2. The selection unit SEL activates the first and second selection signals SS1 and SS2 based on the number of bits of the address transmitted from the address input unit AI... For example, if the address of the χ_bit is received, the 'selection unit The SEL can initiate the first selection signal, eg, and if it is the address of the y-bit, the second selection signal SS2 can be initiated. One of the first and second sub-storage units ssm and SSU2 is activated based on the selected signal 'from the first and second selection signals SS1 and SS2. That is, based on the among the first and second selection signals SS1 and SS2 regarding the first and second sub-disconnection units ssm and SSU2, the selection signal 'data, address or control signal transmission ride should be The child storage unit 'either outputs information about one of the first and second child storage units SSU1 and SSU2 from the child storage unit. In Figures 9 to 12, among the signals (selection signals, addresses, data, and control signals) transmitted or received between the controller ctrl and the memory chip Μαρ, there is only a need for explanation for the purpose of the (fourth) purpose. Description. Although the first and second choices (4) SS1 &amp; SS2 can be generated by using various methods, for convenience of explanation, it will be assumed that the first and second selection signals SS1 and SS2 are from an external device (for example, the controller Qrl). Passing the wheel. The interface unit ICU also transmits or receives data, address or control signals as described above. For this, as shown in FIG. 13, the interface unit ICU includes first and second input/output units 101 and 1〇2. The first input/output unit 201250705 4Z676pif ιοί transmits or receives data DTA1, address Addrl or control signal XCON1 regarding the first sub-storage unit SSU1 from an external device (such as controller Ctrl). The first input/output unit 101 may include a first address input unit All to receive an address Addrl about the first sub-storage unit SSU1, and a first control signal input unit CI1 to receive a control signal regarding the first sub-storage unit SSU1 The XCON and the first data input/output unit DI〇1 transmit or receive the data DTA1 regarding the first sub-storage unit SSU1. The first address input unit All, the first control signal input unit cn, and the data input/output unit DIO1 can implement, for example, an input pin and an input/output pin ’ or an input pad and an input/output pad. The second input/output unit 102 is separately configured by the first input/output unit 101 in the first input/output unit 101 to transmit or receive or receive from the external device (such as the controller Ctrl) about the second sub-storage unit. SSU2 data DTA2, address Addr2 or control signal xCON2. The second input/output unit 102 may include a second address input unit AI2 to receive an address Addr2 regarding the first sub-storage unit SSU2, and a second control signal input unit CI2 to receive a control signal XCON2 regarding the second sub-storage unit SSU2. And the second data input/output unit m〇2 transmits or receives the data DTA2 of the second sub-storage unit SSU2. The second address input unit AI2, the second control signal input unit α2, and the second data input/output unit DI02 can implement, for example, an input pin and an input/output pin, or an input pad and an input/output pad. The interface unit ICU may further include the first and second selections 15 201250705 42676pif signal input units SSI1 and SSI2 described above. Figure 13 shows an example of the DTA1, the address Addrl and the control signal xc〇Ni for the first sub-storage unit SSU1, and the data DTA2, address A, and control 5 of the sub-storage unit SSU2. The number XC〇N2 is received through different input/output units, such as the first=two input/output units 101 and 1〇2. In addition, as shown in Fig. 14, f Γ and the second sub-storage units SSU1 and SSU2 can make a wheel/intake of 7L. The interface unit ICU shown in FIG. 14 may include a shared address input list = CAI, a shared control signal input unit CCI, and a shared data input/output early element CDIO. The shared address input unit CAI receives the address jdch from the controller c(1), the address of the transmission_first-sub-storage unit ssm, Addri to the first-sub-storage unit SSm, and transmits the address Addr2 to the second sub-storage unit SSU2 to The second sub-storage unit ssm. The common control input command input unit cci receives the control signal xc〇N from the controller ctrl, transmits a control signal XCON1 of a sub-storage unit SSU1 to the first sub-storage unit SSU, and transmits the second sub-storage unit. SSU2 control XCON2 爿 second sub-storage unit SSU2. Shared data input / "Output το CDIO receives data DTA from controller Ctrl, transmits data DTA1 about first sub-storage unit SSU1 to first sub-storage unit SSU1 'and transmits information about second sub-storage unit OTA" to Two sub-storage unit SSU2. Similarly, the input/output unit CDIO transfers the data DTA1 and DTA2 from the first and second sub-storage units SSU1 and ssu2 to the controller Ctrl, respectively. The 201250705 42676pif interface unit ICU may further include the first and signal input units SSI1 and SSI2 described above. The shared address input unit CAI, the Qiu control money input unit ca, and the production Puperson/_ unit cm〇 can respectively select and output the first in response to the selection signal SS1 from the first selection signal input unit ssn. - The address of the sub-storage unit SSU1 Addrb control signal XCON1 and data DTA1. Similarly, the shared address input unit CAI, the common rib succession input unit ccj, and the second selection signal SS2 of the Zhuangke (4) No. 2 signal transmission transmission are respectively selected and outputted with respect to the first sub storage unit SSU2. Dta control signal XCON2. The addresses Addr2 and FIG. 15B show examples of the first and second sub-storage sheets SSU1 and SSU2 shown in FIG. ^ Figure 15A, the first and second sub-storage units ssm and ssu2 are the same number of blocks. FIG. 15A particularly shows such an example, when the storage units SSU1 and SSU2 individually include 4 blocks, the third is in the fortune, if the capacity of the first-read storage unit is in the lift (2) in the second sub-storage unit SSU2 The fourth standard sub-storage = the size of the second sub-storage unit SSU2, and the block size of the first-storage element ssm. And sstiL as shown in FIG. 15B, the first and second sub-storage units ssin sub, including the number of different block groups. ® 15A_ denotes such an example. The second sub ==: sub-storage unit surface includes 8 blocks A to Η, and the first 7 LSSU2 includes 4 blocks Α to D. In this example, 17 201250705 42676pif if the third standard capacity (2X) of the second storage unit SSU1 is greater than the fourth standard capacity (7) of the second = storage unit SSU2, the first and the early elements ssm and SSU2 may have the _ area Group size.

二早提及當第—子儲存單元SSU1之容量大於第 存卓70 SSU2之容量的實例。然而，本發明概念不 二县°如圖15A及圖15B所示，第一子儲存單元SSU1 t可則、於第二子儲存單元SSU2之容量。如圖16A 同果Ϊ 一及第二子儲存單元SSU1及咖2具有相 二’、:第—子儲存單元SSU2之區組大小可以大 i一單元SSU1之區組大小。或如圖16B所示，如果 Ϊ 一子::!儲存單元SSU1及ssu2具有不同區組數， sHt：^SSU2之隨數可以於第—顿存單元 及所示’第一及第二子儲存單元咖 來實現_ 疋使用相同之記憶單元(記憶體)類型(使用） 顯示這樣的例子，當第-及第二子儲存單 樣的例n—Λ i Μ來貫現。圖1 7β顯示這 皆以PRAM:—第一子儲存單元SSU1及SSU2兩者 二子儲存單元圖17c顯示這樣的例子，當第一及第 現。如果第—及m ^咖2兩者皆以快取記憶體來實 暗辨办麻帛及第一子儲存單元SSU1及咖2以快取纪 見=17C所示，第-及第二子儲存單元_ 及SSU2可以以頁或區塊之單位來存取。 另外，如圖㈤到圖17F所示，第—及第 201250705 ^ζο/οριι 元SSU1及SSU2可以是使用不同之記憶單 (使用）來實現。圖17D顯示這樣的例子，當 i j 1士 元SSU1以DRAM來實現而篦一；冲+田 堵存早 不只兄而第一子儲存單元SSU2以 PRAM來貫現。圖17E顯示這樣的例子，當第—子儲 兀ssm a PRAM來實現而第二子儲存單元咖2以 RRAM來貫現。圖17F顯示這樣的例子，當第—子儲存單 兀ssui以快取記憶體來實現而第二子儲存單元聊2以 PRAM來實現。 除了圖17A到圖17C所顯示之例子外，第一及第二子 2單it ssm及SSU2也能以各種抑記㈣之例子來 第-及第二子儲存單元SSU1及SSU2可讀存相同 貧枓之類型’如圖18A及圖18B所示。圖18A顯示這樣 =例子當第-及第二子儲存單元SSU1及SSU2兩者皆儲 存使用者J料UDTA。圖18B _這_鮮#第一及第 -子儲存單兀SSU1及SSU2兩者皆儲存圖像資料IDTA。 另外，第-及第二子儲存單元ssm及SSU2可以儲 存=同資料之類型’如圖18c及圖⑧所示。圖18C顯 =樣的例子當第—子儲存單元ssm儲存使用者資料 JA而第一子儲存單元SSU2儲存元資料mdta。圖 =不這樣的例子當第—子儲存單元ssm儲存圖像資料 TA而第二子儲存單元SSU2儲存文字資料TDTA。 ，了圖18A到圖18D所顯示之例子外，第—及第二子 =子單7GSSU1及SSU2也可儲存各種不同資料之型態。 201250705 42676pif 以上只有描述包括兩個子儲存單元的實例。然而本發 明概念不以此為限。如圖19 A及19B所示，儲存單元s τυ 可以包括3個或更多的子儲存單元。圖19Α中，儲存單元 stu包括k個子儲存單元(k為大於或等於3的整數），例 如’第-到第k具有標準容量之子儲存單元ssm到 SSUk。在此實例中，第-到第k子儲存單元ssm到 之標準容量之和特任意容量。舉例來說，如果儲存單元 STU包括3個子儲存單元而任意容量為7(Jb，3個子儲存 單元可以具有4Gb、2Gb及1Gb之標準容量。 如圖19B所不’第一到第k子儲存單元ssm到SSUk 在不同時間點回應對應之實施於儲存單元STU之選擇信 號而啟動。舉例來說，回應第一選擇信號SS1而啟動第一 子儲，單元ssui，回應第二選擇信號SS2而啟動第二子 儲存單元SSU2。同樣地，第k子儲存單元ssuk回應第k 選擇信號SSk而啟動。 如圖20所示，介面單元ICU可以包括輸入/輸出單元 用來傳輸或接收關於第一到第k子儲存單元ssui到SSUk 之資料、位址及控制信號。參閱圖2〇,介面單元ICU可以 包括第一輸入/輸出單元ΙΟΙ用來傳輸或接收關於第一子 儲存單元SSU1之資料DTA卜位址Addrl或控制信號 XCONl ’第二輸入/輸出單元用來傳輸或接收關於第 ，子儲存單元ssu2之資料DTA2、位址Addr2或控制信 號XCON2，到第k輸入/輸出單元i0k用來傳輸或接收關 於第k子儲存單元SSUk之資料DTAk、位址Addrk或控 20 201250705 42676ρΐί 制信號XCONk。 另外，如圖21所示，介面單元ICU可以包括共用輸 入/輸出單元用來傳輸或接收關於第一到第k子儲存單元 SSU1到SSUk之資料、位址及控制信號。參閱圖21，介 面單兀icu可以包括共用位址輸入單元CAI用來接收關於 第一子儲存單元SSU1之位址Addrl，關於第二子儲存單 元SSU2之位址Addr2’到關於第k子儲存單元之位 址Addrk。同樣地，介面單元ICU可以包括共用控制俨號 輸入單元cci用來接收關於第一子儲存單元SSU1之控制 信號XCON1，關於第二子儲存單元ssm之控制俨號 XCON2 ’細關於第k子儲存單元之控制^號 XCONk。更進-步地’介面單元咖可以包括共用資料輸 入/輸出單元CDIO用來傳輸或接收關於第一子儲存 ssui之資料DTA卜關於第二子儲存單元卿2之 DTA2 ’直到關於第k子儲存單元SSUk之資料〇丁处。 雖=在圖21巾，介面單元ICU包括所有共用位 入早[、共用控制信號輸人單」 /，巧元⑽’介面單元ICU可以僅包括共用 早兀CAI、共用控制信號輸入單元ca 輸:單元_中之-或二。舉例來說，如;=入片/ 之，入/輸出速度完全依賴資料的傳輸或接收，介“ 元:來傳輸或接收關於所; 於子儲存單元之㈣錢或健輪〜輸4單元絲傳輪關 201250705 42676pif 圖22及圖23為根據另一本發明概念之實施例來描述 存取記憶體晶片之方法。 ί〜^圖^2及圖23所示，存取方法包括基於關於第二標 準谷®(2η+1)而設定為具有位元數(η+1)之記憶體位址An example of when the capacity of the first-sub-storage unit SSU1 is larger than the capacity of the first-storage 70 SSU2 is mentioned twice. However, the present invention is not the same as shown in Figs. 15A and 15B, and the first sub-storage unit SSU1 t can be in the capacity of the second sub-storage unit SSU2. As shown in Fig. 16A, the same as the second sub-storage unit SSU1 and the coffee maker 2 have two phases, and the block size of the first sub-storage unit SSU2 can be larger than the block size of the cell SSU1. Or, as shown in FIG. 16B, if the :::! storage units SSU1 and ssu2 have different number of blocks, the sHt:^SSU2 can be stored in the first-storage unit and the first and second sub-stores as shown. Unit coffee to achieve _ 疋 use the same memory unit (memory) type (used) Display such an example, when the first and second sub-storage examples n - Λ i Μ come true. Figure 1 7β shows that all of them are PRAM: - the first sub-storage units SSU1 and SSU2, two sub-storage units, Figure 17c shows such an example, when first and foremost. If both the first and the second sub-storage are in the form of cache memory, the first sub-storage unit SSU1 and the coffee 2 are displayed in the cache memory. Unit_ and SSU2 can be accessed in units of pages or blocks. In addition, as shown in (5) to 17F, the first and the 201250705 ^ζο/οριι SSU1 and SSU2 can be implemented using different memory sheets (used). Fig. 17D shows an example in which the ij 1 SSU1 is implemented in DRAM and the first one; the first sub-storage unit SSU2 is realized in PRAM. Fig. 17E shows an example in which the first sub-storage ssm a PRAM is implemented and the second sub-storage unit 2 is realized in RRAM. Fig. 17F shows an example in which the first sub-storage ssui is implemented in cache memory and the second sub-storage unit 2 is implemented in PRAM. In addition to the examples shown in FIGS. 17A to 17C, the first and second sub-single ssm and SSU2 can also be readable by the first and second sub-storage units SSU1 and SSU2 in the case of various stimuli (4). The type of ' is as shown in FIGS. 18A and 18B. Fig. 18A shows such an example. When both the first and second sub-storage units SSU1 and SSU2 store the user UDTA. The image data IDTA is stored in both the first and the first sub-storage sheets SSU1 and SSU2 in FIG. 18B. Further, the first and second sub-storage units ssm and SSU2 may store the type of the same data as shown in Figs. 18c and 8. Fig. 18C shows an example in which the first sub storage unit ssm stores the user data JA and the first sub storage unit SSU2 stores the metadata mdta. Figure = No such example When the first sub-storage unit ssm stores the image data TA and the second sub-storage unit SSU2 stores the text data TDTA. In addition to the examples shown in Figures 18A through 18D, the first and second sub-sub-segments 7GSSU1 and SSU2 can also store various types of data. 201250705 42676pif The above description only includes examples of two sub-storage units. However, the concept of the present invention is not limited thereto. As shown in Figures 19A and 19B, the storage unit s τ υ may include three or more sub-storage units. In Fig. 19A, the storage unit stu includes k sub-memory units (k is an integer greater than or equal to 3), for example, 'first-to-kth sub-memory units ssm to SSUk having standard capacity. In this example, the sum of the standard capacities of the first to kth sub-storage units ssm to the arbitrary capacity. For example, if the storage unit STU includes 3 sub-storage units and the arbitrary capacity is 7 (Jb, the 3 sub-memory units may have a standard capacity of 4Gb, 2Gb, and 1Gb. As shown in FIG. 19B, the first to k-th sub-storage unit Ssm to SSUk are started at different time points in response to the corresponding selection signal implemented in the storage unit STU. For example, the first sub-store is activated in response to the first selection signal SS1, and the unit ssui is activated in response to the second selection signal SS2. The two sub storage unit SSU2. Similarly, the kth sub storage unit ssuk is activated in response to the kth selection signal SSk. As shown in Fig. 20, the interface unit ICU may include an input/output unit for transmitting or receiving about the first to the kth. The data, address and control signals of the sub-storage unit ssui to SSUk. Referring to FIG. 2A, the interface unit ICU may include a first input/output unit for transmitting or receiving data about the first sub-storage unit SSU1. Addrl or control signal XCON1 'The second input/output unit is used to transmit or receive information about the first, sub-storage unit ssu2 DTA2, address Addr2 or control signal XCON2, to the kth input The output unit i0k is used to transmit or receive the data DTAk, the address Addrk or the control 20 201250705 42676ρΐί signal XCONk for the kth sub-storage unit SSUk. In addition, as shown in FIG. 21, the interface unit ICU may include a shared input/output unit. For transmitting or receiving data, address and control signals regarding the first to kth sub-storage units SSU1 to SSUk. Referring to FIG. 21, the interface unit 兀uu may include a shared address input unit CAI for receiving information about the first sub-storage. The address of the unit SSU1 is Addrl, regarding the address Addr2' of the second sub-storage unit SSU2 to the address Addrk about the k-th sub-memory unit. Similarly, the interface unit ICU may include a shared control nickname input unit cci for receiving The control signal XCON1 of the first sub-storage unit SSU1, the control key XCON2 of the second sub-storage unit ssm is detailed with respect to the control number XCONk of the k-th sub-memory unit. Further, the interface unit may include shared data. The input/output unit CDIO is used to transmit or receive the data about the first sub-storage ssui DTA about the second sub-storage unit 2 DTA2' until about the kth sub The information of the storage unit SSUk is in the shackle. Although in Figure 21, the interface unit ICU includes all the common bits into the early [, shared control signal input list" /, the Qiaoyuan (10) interface unit ICU can only include the shared early CAI , the common control signal input unit ca input: in the unit _ - or two. For example, such as; = into / /, the input / output speed depends entirely on the transmission or reception of data, "met: to transmit or receive about (4) Money or the wheel to the 4th wire transfer wheel 201250705 42676pif FIG. 22 and FIG. 23 are diagrams illustrating a method of accessing a memory chip according to another embodiment of the inventive concept. 〜〜^图^2 and FIG. 23, the access method includes setting a memory address having a bit number (n+1) based on the second standard valley® (2η+1).

Addr ，存取具有任意容量之儲存單元STU(操作，也就 ，，接收讀取或寫入之命令。這也就是，具有任意容量之 s己憶體晶片基於具有位元數(n+1)之記憶體位址Addr, access to the storage unit STU of any capacity (operation, that is, receive read or write commands. That is, the memory of any size of the memory is based on the number of bits (n + 1) Memory address

Addr而存 取，其位址與關於第一標準容量(2,而定之記憶體位址 Addr相比大了 位元。如同上述關於圖丨，任意容量(2n+m) 大於第一標準容量(2Π)而小於第二標準容量(2η·Η)。 因此，如圖24所示，如果具有任意小於第二標準容量 之汜憶體晶片基於具有相同於關於第二標準容量而設定之 。己隐體位址之位元數之記憶體位址而存取，雖然記憶體位 址之值(Addr[DZ])存在，記憶體晶片之儲存區（如圖丨等圖 所示之儲存單元STU)對應於記憶體位址之值可以不存在。 在此，圖24所示之陰影部份，其記憶體位址之值存在 但對應於其值之儲存區不存在指為死區(dead z〇ne)。關於 死區之記憶體位址表示為Addr[DZ]。 如圖1、圖23及圖25A所示，存取方法包括如果死區 之存取請求Req_ACC(Addr[DZ])接收時，即如果關於死區 之讀取或寫入命令接收時，則處理存取結果為失敗(操作 S2340)。在此貫例中，§己憶體晶片MCIP可以傳輪存取失 敗信號Resp_Acc(fail)到控制器Ctd。Access by Addr, the address is larger than the first standard capacity (2, and the memory address Addr is larger than the bit. As mentioned above, any capacity (2n+m) is greater than the first standard capacity (2Π) ) is smaller than the second standard capacity (2η·Η). Therefore, as shown in FIG. 24, if there is any memory cell smaller than the second standard capacity, it is set based on having the same capacity as the second standard. The memory address of the bit number of the address is accessed. Although the value of the memory address (Addr[DZ]) exists, the storage area of the memory chip (the storage unit STU shown in the figure and the like) corresponds to the memory location. The value of the address may not exist. Here, the shaded portion shown in Fig. 24, the value of the memory address exists but the storage area corresponding to the value does not exist as a dead zone (dead z〇ne). The memory address is represented as Addr[DZ]. As shown in FIG. 1, FIG. 23 and FIG. 25A, the access method includes if the access request of the dead zone Req_ACC (Addr[DZ]) is received, that is, if the dead zone is concerned When the read or write command is received, the processing access result is failed (operation S2340). Consistent embodiment, § MCIP wafer can have memory access transfer wheel failure signal Resp_Acc (fail) to the controller Ctd.

如圖26A所不’ s己憶體晶片MCIP之控制單元COU 22 201250705 420/0pif 可以處理死區之存取請求Req_Acc(Addr[DZ])。為了處理 死區之存取請求Req_Acc(Addr[DZ])，控制單元COU可以 在非啟動模式(NonAct)中運作。另外，如圖26B中所示， 如果死區之存取請求Req_Acc(Addr[DZ])接收，控制單元 C〇U可以運作彷彿沒有接收關於記憶體位址Addr[DZ]之 命令(控制信號）（NoCom)。 在此實例中，如圖26A所示，記憶體晶片MCIP可以 運作於非啟動模式(NonAct)中，或如圖26B所示，可以運 作彷彿無命令(控制信號)接收(NoCom)，藉由執行無操作來 對應死區之存取請求Req_Acc(Addr[DZ])(例如’藉由輸出 無資料來對應讀取命令）。在此，如果從記憶體晶片MCIP 沒有接收關於死區之命令(控制信號)之回應，控制器Ctrl 可以將此視為失敗。 同樣地’如圖25B、圖26C及圖26D所示，記憶體系 統MSYS可以在主機Host及控制器Ctrl之間處理死區。 舉例來說，如果死區之存取請求Req_Acc(Addr[DZ])從主 機Host接收，控制器Ctrl可以不傳輸死區之存取請求 Req_Acc(Addr[DZ])到記憶體晶片MCIP以及可以在非啟 動模式(NonAct)中來運作記憶體系統MSYS，或者可以運 作記憶體系統MSYS彷彿無命令(控制信號)接收(N〇c〇m)^ 圖27為實施例來顯示包括在圖丨所示之儲存單元STU 中的區組之配置。 如圖1及圖27所示，儲存單元STU可以包括複數個 區組(請見圖15A、15B、16A及16B)。各區組(例如ΒΑ0) 23 201250705 42676pif 包括複數個列RAO到RAs以及複數個行CAO到CAt。各 區組BA0包括複數個記憶單元(未繪示)連接於RA0到RAs 以及行CAO到CAt。為了儲存資料到任意記憶單元或從任 意記憶單元讀取資料，控制單元COU施加電壓到對應記 憶體位址Addr之列及行。 相對應地，如圖28所示，記憶體位址Addr可以包括 區組位址BA、列位址RA及行位址CA。然而，在記憶體 位址Addr中，列位址RA及行位址CA之位置可以不同於 圖28所示之位置。 如圖29所示，具有第一標準容量2n之記憶體晶片之 η-位元位址可以形成(a+i)_位元區組位址BA，（b+Ι)-位元 列位址RA，及(c+1)-位元行位址CA。區組位址BA、列位 址RA及行位址CA的位元數之和，即(a+l)+(b+l)+(c+l)， 同等於記憶體晶片之位址之位元數，即η。 如同上述關於圖1，具有任意容量ADEN之記憶體晶 片MCIP可以設定為具有η+ι位元之記憶體位址 Addr[n:〇] ’其位址與設定為關於具有第一標準容量2°之記 憶體晶片之記憶體位址Addr之η位元相比大了 1-位元。 舉例來說’如圖30所示，記憶體位址Addr之區組位址ΒΑ 有a+2位元(n+1)’其位址與具有第一標準容量2n之記憶體 晶片之區組位址BA之a+Ι位元相比大了 1-位元。 如圖31所示，如果具有第一標準容量2n之記憶體晶 片之各區組大小相同於具有任意容量之記憶體晶片MCIP 之區組大小，以及任意大於第一標準容量2n的1.5倍之容 24 201250705 4^6/6plf 量’則具有第一標準容量2n之記憶體晶片可以包括區組a 到D ’而具有任意容量之記憶體晶片MCIP可以包括區組 A到F 0 如圖30所示’既然根據本發明概念之實施例之區組位 址BA設定為比關於第一標準容量2n之區組位址BA大了 1-位元’根據本發明概念之實施例對應於區組位址BA之 部分之區組可以不存在於記憶體晶片MCIP上。舉例來 說’如果關於第一標準容量2n之區組位址BA是2位元而 根據本發明概念之實施例之區組位址BA是3位元，區組 G及Η對應區組位址[no]及[in]如圖31所示為不存在於 記憶體晶片MCIP上，以及因此可以處理如同死區dz。 如果關於死區DZ之區組位址ΒΑ接收，如上述關於 圖23、圖25Α及圖25Β，控制單元COU可以處理存取結 果為失敗。如上述關於圖5，控制單元COU可以安置在儲 存區（區組)之外’或在區組A、C及Ε ’以及區組Β、D及 F之間。 如果根據本發明概念之實施例的記憶體晶片為快取記 憶體晶片，區組位址可以為區塊位址。 如圖32所示’根據本發明概念之實施例，（n+1)_位元 之記憶體位址Addr之列位址RA可以與關於具有第一標準 谷置2之s己憶體晶片之列位址RA相比而大了 1 _位元。如 果具有第一標準容量2n之記憶體晶片之各區組大小同等於 具有任意容量之記憶體晶片MCIP之區組大小，具有第一 才示準容量2n之記憶體晶片可以包括對應於列位址RA〇到 25 201250705 42676pif RA2 -1的列’如圖33所示，然而具有任意容量之記憶體 晶片MCIP可以包括對應於列位址RA〇到rat的列。列 位址RAT具有在列位址及〗之間之值。 如圖3 2所示，既然根據本發明概念之實施例之列位址 RA設定為比關於第一標準容量2&quot;之列位址ra大了丨_位 元’根據本發明概念之實施例之對應於列位址之部分 之列可以不存在。如果關於第一標準容量2n之列位址 為(b+1)位元以及根據本發明概念之實施例之列位址RA為 (b+2)位元，如圖32所示’對應於列位址RAT+1到RA2b+1-l 之列不存在於記憶體晶片MCIP之上，如圖33所示，以及 因此可以處理如同死區DZ。 如果關於死區DZ之列位址RA接收的話，如同上述 關於圖23、圖25A及圖25B，控制單元COU可以會處理 存取之結果視為失敗。 圖33說明當用來構成死區DZ之列位址RAT+1到 RA2b+1-l相同地包括在A到D所有的區組中時的例子。然 而’本發明概念並不限於此。如圖34所示，記憶體晶片 MCIP之死區DZ可以只有構成於一些區組之列中。圖34 中’死區DZ可以不構成在區組b及D中，而僅可以對應 於區組A與區組C之列位址RA2ba RA2b+1-l之列處理視 為死區DZ。死區DZ不限於圖34所說明之例子，而可以 構成於圖32所說明之各種不同具有列位址及八之記憶體晶 片MCIP上。 如圖35所示，根據本發明概念之實施例的(n+1)_位元 26 201250705 4ZO/〇pit 之記憶體位址Addr之行位址CA可以比關於具有第一標準 谷ΐ 2之§己憶體晶片之行位址CA大了 1 -位元。如果具有 第一標準容量2η之記憶體晶片之區組大小相等於具有任意 容量之記憶體晶片MCIP之區組大小，具有第一標準容量 2η之記憶體晶片可以包括圖36中所示之對應於行位址 CA0到CA2e之行，然而具有任意容量之記憶體晶片MCIP 可以包括圖36所示中對應於行位址ca〇到CAT之行。行 位址CAT具有行位址CA2c及RA2C+1-1之間之值。 如圖35所示’既然根據本發明概念之實施例的行位址 CA設定為比關於第一標準容量2n之行位址CA大了 1·位 元，根據本發明概念之實施例的對應於行位址CA之部分 之行可以不存在。如圖36所示，如果關於第一標準容量 2之彳亍位址CA為(c+1)位元而根據本發明概念之實施例之 行位址CA為(c+2)位元，則圖36中所示之對應於行位址 CAT+1到CA2c+1-l之行不存在於記憶體晶片Μαρ之上， 而可以因此處理視為死區DZ。 如果關於死區DZ之行位址CA接收’如上述關於圖 23、25A及25B，控制單元C0U可以處理存取結果視為失 敗。 圖36說明這樣的例子，當構成死區Dz之行位址 CAT+1到CA2c+1-l同等於包括在所有區組A到D之中。 然而，本發明概念並不受限於此。如圖37所示，記憶體晶 片MCIP之死區DZ可以僅僅構成於一些區組之行中。圖 37中，死區DZ可以不構成於區組C&amp;D之中，而可以僅 27 201250705 42676pif 僅區組A與區組B之對應於行位址CA2e到CA2c+1-l之行 處理視為死區DZ。死區DZ並不受限於圖3 7所說明之例 子’而可以構成於圖35所示之各種不同具有行位址CA之 記憶體晶片MCIP之上。 圖38是根據本發明概念之實施例的電腦系統csys 之方塊圖。 如圖38所示，電腦系統CSYS包括處理器CPu、使 用者介面UI及記憶體系統MSYS，其電性連接於匯流排 BUS。記憶體系統MSYS包括控制器Ctrl及記憶體晶片 MCIP。記憶體晶片MCIP可以儲存有N-位元之資料(n為 大於或等於1之整數）’其資料藉由處理器CPU或藉由控 制器Ctrl之控制來處理或處理。圖38所示之包括於記憶 體系統MSYS中之記憶體晶片MCIP可以為圖i等所示^ s己憶體系統MSYS，以及可以藉由利用圖2或圖23所示之 存取方法來存取《相對應地，既然記憶體晶片MCIp具有 各種不同儲存容量，電腦系統CSYS可以迅速地滿足高容 量之需求，以及當比較於記憶體晶片具有一樣的儲存容量 的情形時，可以減少封裝厚度及耗能。 電腦系統csys可以進一步包括電源供應器ps。如果 電腦系統CSYS為行動裝置’可以額外提供用來提供電腦 系統CSYS之操作電壓之電池以及如同基帶晶片组 (baseband chipset)之數據機。同樣的，電腦系統csys可 ^進-步包括習知的元件如同應用晶片組、攝影圖像處理 器(CIS)、行動動態隨機存取記憶體(DRAM)等等，而在此 28 201250705 42676pif 不再提供其詳述。 圖39為根據本發明概念之實施例的記憶卡MCRD之 概要圖。 如圖39所示，記憶卡MCRD包括控制器Ctri及記憶 體晶片MCIP。控制器Ctrl控制回應於外部主機(未繪示) 之請求到或從記憶體晶片MCIP之資料之寫入或讀取操 作，其為透過輸入/輸出裝置I/O來接收。為了控制操作， 記憶卡MCRD之控制器Ctrl可以包括了主機及記憶體晶片 MCIP之間的介面（未繪示）以及隨機存取記憶體(ramx未 繪示）。記憶卡MCRD可以實現如同圖6所示之記憶體系 統 MSYS。 §己憶卡MCRD可以為快取記憶卡（compact f]ash card，CFC)、微型硬碟、智能媒體卡（SMC)、多媒體卡 (multimedia card ’ MMC)、安全數位卡（security digital card，SDC)、MS 卡、萬用串列匯流排(universai serial bus， USB)快取記憶體硬碟等等。相對應地，既然記憶體晶片 MCIP具有各種不同儲存容量，記憶卡MCRD可以迅速地 滿足高容量之需求，以及當比較於記憶體晶片具有一樣的 儲存容量的情形時，可以減少封裝厚度及耗能。 圖40為根據本發明概念之實施例之固態硬碟(Ssd)之 方塊圖。 如圖40所示，SSD包括SSD控制器SCTL及記憶體 晶片MCIP。SSD控制器SCTL包括處理器PROS、隨機存 取記憶體RAM、快取緩衝器CBUF及控制器Ctrl，其為透 29 201250705 4^0/Opif 過匯流排BUS來連接。處理器PROS控制控制器Ctrl回應 主機(未繪示)之請求(命令、位址或資料)到及從記憶體晶片 MCIP傳輸及接收資料。SSD之處理器PROS及控制器Ctrl 可以實現如同RAM處理器。請求去運作處理器PR〇s之 資料可以載入到RAM。 主機介面I/F傳輸從主機接收之請求到處理器 PROS，或傳輸從記憶體晶片MCIP接收之資料到主機。主 機介面I/F可以為對於主機之介面，其為藉由利用各種不 同介面協疋之一’如USB、人機通信（man machine communication ’ MMC)、快速周邊組件互連（peripheral component interconnect-express，PCI-E)、串聯高級技術附 件（serial advanced technology attachment，SATA)、並聯高 級技術附件（parallel advanced technology attachment， PATA)、小型電腦系統介面（smau c〇mpUter system interface ’ SCSI)、加強型小裝置介面(enhanced small device interface，ESDI)以及智慧型電子驅動器（intelligent electronics ’ IDE)。傳輸從或傳輸到記憶體晶片MCIP之資 料可以暫時儲存在快取緩衝器CBUF中。舉例來說，快取 緩衝器CBUF可以為靜態ram(SRAM)。 如圖6等所示，SSD可以實現如同包括了記憶體晶片 MCIP的記憶體系統MSYS。相對應地，既然記憶體晶片 MCIP具有各種不同儲存容量，SSD可以迅速地滿足高容 量之需求，以及當比較於記憶體晶片具有一樣的儲存容量 的情形時，可以能減少封裝厚度及耗能。 30 201250705 4ZD/〇pir 圖41為根據本發明概念之實施例包括SSD之伺服器As shown in Fig. 26A, the control unit COU 22 201250705 420/0pif of the memory chip MCIP can handle the dead zone access request Req_Acc (Addr[DZ]). In order to process the dead zone access request Req_Acc(Addr[DZ]), the control unit COU can operate in the non-start mode (NonAct). In addition, as shown in FIG. 26B, if the dead zone access request Req_Acc(Addr[DZ]) is received, the control unit C〇U can operate as if the command (control signal) regarding the memory address Addr[DZ] is not received ( NoCom). In this example, as shown in FIG. 26A, the memory chip MCIP can operate in a non-active mode (NonAct), or as shown in FIG. 26B, can operate as if there is no command (control signal) reception (NoCom), by performing There is no operation to correspond to the dead zone access request Req_Acc(Addr[DZ]) (for example, 'by reading no data to correspond to the read command). Here, if the response from the memory chip MCIP does not receive a command (control signal) regarding the dead zone, the controller Ctrl can regard this as a failure. Similarly, as shown in Figs. 25B, 26C, and 26D, the memory system MSYS can process the dead zone between the host Host and the controller Ctrl. For example, if the dead zone access request Req_Acc(Addr[DZ]) is received from the host Host, the controller Ctrl may not transmit the dead zone access request Req_Acc(Addr[DZ]) to the memory chip MCIP and may Non-boot mode (NonAct) to operate the memory system MSYS, or can operate the memory system MSYS as if there is no command (control signal) reception (N〇c〇m) ^ Figure 27 is an embodiment to display as shown in the figure The configuration of the block in the storage unit STU. As shown in Figures 1 and 27, the storage unit STU can include a plurality of blocks (see Figures 15A, 15B, 16A, and 16B). Each block (for example, ΒΑ0) 23 201250705 42676pif includes a plurality of columns RAO to RAs and a plurality of rows CAO to CAt. Each block BA0 includes a plurality of memory cells (not shown) connected to RA0 to RAs and rows CAO to CAt. In order to store data to or read data from any memory unit, the control unit COU applies a voltage to the column and row of the corresponding memory address Addr. Correspondingly, as shown in FIG. 28, the memory address Addr may include a block address BA, a column address RA, and a row address CA. However, in the memory address Addr, the position of the column address RA and the row address CA may be different from the position shown in FIG. As shown in FIG. 29, the n-bit address of the memory chip having the first standard capacity 2n can form (a+i)_bit block address BA, (b+Ι)-bit column address RA, and (c+1)-bit row address CA. The sum of the number of bits of the block address BA, the column address RA, and the row address CA, that is, (a+l)+(b+l)+(c+l), which is equal to the address of the memory chip. The number of bits, ie η. As described above with respect to FIG. 1, the memory chip MCIP having an arbitrary capacity ADEN can be set to have a memory address of the n+ι bit Addr[n:〇]' whose address is set to be 2° with respect to the first standard capacity. The memory address of the memory chip Addr is 1-bit larger than the η bit of the memory address. For example, as shown in FIG. 30, the block address of the memory address Addr a has a + 2 bits (n+1) 'the address of the block with the first standard capacity 2n. The a+Ι bit of the address BA is 1-bit larger than the bit. As shown in FIG. 31, if the block size of the memory chip having the first standard capacity 2n is the same as the block size of the memory chip MCIP having an arbitrary capacity, and any size larger than 1.5 times the first standard capacity 2n. 24 201250705 4^6/6plf amount 'The memory chip having the first standard capacity 2n may include the blocks a to D' and the memory chip MCIP having any capacity may include the blocks A to F 0 as shown in FIG. 'Since the block address BA according to an embodiment of the inventive concept is set to be 1-bit larger than the block address BA with respect to the first standard capacity 2n', the embodiment according to the inventive concept corresponds to the block address The block of the part of the BA may not exist on the memory chip MCIP. For example, 'If the block address BA with respect to the first standard capacity 2n is 2 bits, and the block address BA according to the embodiment of the inventive concept is 3 bits, the block G and the corresponding block address of the block [no] and [in] are not present on the memory chip MCIP as shown in FIG. 31, and thus can be treated like the dead zone dz. If the block address of the dead zone DZ is received, as described above with respect to Fig. 23, Fig. 25, and Fig. 25, the control unit COU can handle the access result as a failure. As described above with respect to Fig. 5, the control unit COU may be disposed outside the storage area (block) or between the blocks A, C, and ’ and the blocks D, D, and F. If the memory chip according to an embodiment of the inventive concept is a cache memory chip, the block address may be a block address. As shown in FIG. 32, 'in accordance with an embodiment of the inventive concept, the address address RA of the (n+1)_bit memory address Addr can be related to the simon memory chip having the first standard valley 2 The address RA is 1 _ bit larger than the address. If the size of each block of the memory chip having the first standard capacity 2n is equal to the block size of the memory chip MCIP having an arbitrary capacity, the memory chip having the first display capacity 2n may include the column address corresponding to the column address RA. 〇 to 25 201250705 42676pif The column of RA2 -1 ' is as shown in FIG. 33, however, the memory chip MCIP having an arbitrary capacity may include a column corresponding to the column address RA 〇 to rat. The column address RAT has a value between the column address and the 〗. As shown in FIG. 3, since the column address RA according to the embodiment of the inventive concept is set larger than the address address ra of the first standard capacity 2&quot;, the bit is in accordance with an embodiment of the inventive concept. The column corresponding to the portion of the column address may not exist. If the address for the first standard capacity 2n is (b+1) bits and the column address RA according to the embodiment of the inventive concept is (b+2) bits, as shown in FIG. 32, 'corresponds to the column The columns of addresses RAT+1 through RA2b+1-l do not exist above the memory chip MCIP, as shown in Figure 33, and thus can be treated like dead zone DZ. If the address RA of the dead zone DZ is received, as described above with respect to Fig. 23, Fig. 25A and Fig. 25B, the result that the control unit COU can handle the access is regarded as a failure. Figure 33 illustrates an example when the column addresses RAT+1 to RA2b+1-1 used to constitute the dead zone DZ are identically included in all blocks of A to D. However, the concept of the present invention is not limited thereto. As shown in Fig. 34, the dead zone DZ of the memory chip MCIP may be formed only in the columns of some blocks. In Fig. 34, the dead zone DZ may not be formed in the blocks b and D, but may be treated as the dead zone DZ only in the column address R2ba RA2b+1-1 of the block A and the block C. The dead zone DZ is not limited to the example illustrated in Fig. 34, but may be constructed on the various memory chips MCIP having the column address and eight illustrated in Fig. 32. As shown in FIG. 35, the address address CA of the (n+1)_bit 26 201250705 4ZO/〇pit memory address Addr according to an embodiment of the inventive concept may be higher than that regarding the first standard valley 2 The row address CA of the memory chip is 1 bit larger. If the block size of the memory chip having the first standard capacity 2n is equal to the block size of the memory chip MCIP having an arbitrary capacity, the memory chip having the first standard capacity 2n may include the corresponding one shown in FIG. The row addresses CA0 to CA2e, however, the memory chip MCIP having an arbitrary capacity may include the row corresponding to the row address ca〇 to CAT as shown in FIG. The row address CAT has a value between the row address CA2c and RA2C+1-1. As shown in FIG. 35, since the row address CA according to the embodiment of the inventive concept is set to be larger by 1 bit than the row address CA with respect to the first standard capacity 2n, the embodiment according to the inventive concept corresponds to The line of the line address CA may not exist. As shown in FIG. 36, if the address CA of the first standard capacity 2 is (c+1) bits and the row address CA according to the embodiment of the present inventive concept is (c+2) bits, then The row corresponding to the row address CAT+1 to CA2c+1-1 shown in Fig. 36 does not exist on the memory chip Μαρ, but can be treated as the dead zone DZ. If the row address CA for the dead zone DZ is received&apos; as described above with respect to Figures 23, 25A and 25B, the control unit C0U can process the access result as a failure. Fig. 36 illustrates an example in which the row addresses CAT+1 to CA2c+1-1 constituting the dead zone Dz are equivalent to being included in all of the blocks A to D. However, the inventive concept is not limited thereto. As shown in Fig. 37, the dead zone DZ of the memory chip MCIP may be formed only in the rows of some blocks. In FIG. 37, the dead zone DZ may not be formed in the block C&amp;D, but may only be 27 201250705 42676pif only the row A and the block B correspond to the row address CA2e to CA2c+1-l. For the dead zone DZ. The dead zone DZ is not limited to the example illustrated in Fig. 37 and may be formed on the memory chip MCIP having the row address CA shown in Fig. 35. 38 is a block diagram of a computer system csys in accordance with an embodiment of the inventive concept. As shown in FIG. 38, the computer system CSYS includes a processor CPu, a user interface UI, and a memory system MSYS, which are electrically connected to the bus BUS. The memory system MSYS includes a controller Ctrl and a memory chip MCIP. The memory chip MCIP can store N-bit data (n is an integer greater than or equal to 1) whose data is processed or processed by the processor CPU or by control of the controller Ctrl. The memory chip MCIP included in the memory system MSYS shown in FIG. 38 may be the MV system MSYS shown in FIG. 1 and the like, and may be stored by using the access method shown in FIG. 2 or FIG. Correspondingly, since the memory chip MCIp has various storage capacities, the computer system CSYS can quickly meet the demand for high capacity, and when compared with the case where the memory chip has the same storage capacity, the package thickness can be reduced. Energy consumption. The computer system csys may further include a power supply ps. If the computer system CSYS is a mobile device, a battery for supplying the operating voltage of the computer system CSYS and a data machine like a baseband chipset can be additionally provided. Similarly, the computer system csys can include conventional components such as application chipset, photographic image processor (CIS), mobile dynamic random access memory (DRAM), etc., and here 28 201250705 42676pif not Further details are provided. Figure 39 is a schematic diagram of a memory card MCRD in accordance with an embodiment of the inventive concept. As shown in Fig. 39, the memory card MCRD includes a controller Ctri and a memory chip MCIP. The controller Ctrl controls a write or read operation in response to a request from an external host (not shown) to or from the memory chip MCIP, which is received through the input/output device I/O. In order to control the operation, the controller Ctrl of the memory card MCRD may include an interface (not shown) between the host and the memory chip MCIP and a random access memory (ramx not shown). The memory card MCRD can realize the memory system MSYS as shown in Fig. 6. § The memory card MCRD can be a compact memory card (CFC), a mini hard drive, a smart media card (SMC), a multimedia card (MMC), a security digital card (SDC). ), MS card, universal serial bus (USB) cache memory hard disk and so on. Correspondingly, since the memory chip MCIP has various storage capacities, the memory card MCRD can quickly meet the demand for high capacity, and can reduce the package thickness and energy consumption when compared with the case where the memory chip has the same storage capacity. . Figure 40 is a block diagram of a solid state hard disk (Ssd) in accordance with an embodiment of the inventive concept. As shown in Fig. 40, the SSD includes an SSD controller SCTL and a memory chip MCIP. The SSD controller SCTL includes a processor PROS, a random access memory RAM, a cache buffer CBUF, and a controller Ctrl, which are connected by a 2012 20120705 4^0/Opif over bus BUS. The processor PROS control controller Ctrl responds to requests (commands, addresses or data) from the host (not shown) to and from the memory chip MCIP. The SSD processor PROS and controller Ctrl can be implemented like a RAM processor. The data requesting to operate the processor PR〇s can be loaded into the RAM. The host interface I/F transfers the request received from the host to the processor PROS or transfers the data received from the memory chip MCIP to the host. The host interface I/F can be an interface to the host, which utilizes one of a variety of different interface technologies such as USB, man machine communication 'MMC, and peripheral component interconnect-express , PCI-E), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), small computer system interface (smau c〇mpUter system interface 'SCSI), enhanced small The enhanced small device interface (ESDI) and the intelligent electronics 'IDE. The information transferred from or transferred to the memory chip MCIP can be temporarily stored in the cache buffer CBUF. For example, the cache buffer CBUF can be a static ram (SRAM). As shown in FIG. 6 and the like, the SSD can be implemented as the memory system MSYS including the memory chip MCIP. Correspondingly, since the memory chip MCIP has various storage capacities, the SSD can quickly meet the demand for high capacity, and can reduce the package thickness and energy consumption when compared with the case where the memory chip has the same storage capacity. 30 201250705 4ZD/〇pir FIG. 41 is a server including an SSD according to an embodiment of the inventive concept.

系統SSYS ’以及包括伺服器系統SSYS之網路系統NSYS 之概要圖。 如圖41所示，網路系統NSYS可以包括伺服器系統 SSYS及第1到第n終端機ΤΕΜι到TEMn，其透過網路 而連接。祠服器系統SSYS可以包括伺服器SERVER用來 處理從第1到第n終端機TEm到TEMn接收之請求，以 及SSD用來儲存對應於從第1到第η終端機TEM1到 ΤΕΜη接收之請求之資料。在此實例中’如圖41所示之 SSD可以為圖4〇所示之SSD。這也就是圖41所示之SSD 可以包括SSD控制器SCTL及記憶體晶片MCIP，以及記 憶體晶片MCIP可以為圖6等所示之記憶體晶片MCIP。 本發明概念已特別藉由實施例之參考來顯示及描述 之。在此所使用來描述本發明概念之術語僅僅是為了描述 的目的，而本發明概念之範圍並不因此而限制。 舉例來說，雖然圖6等所示之記憶體系統MSYS描述 為2維系統’但本發明概念並不限於此。如圖42A及圖42b 所示，記憶體系統MSYS可以為3維系統，藉由利用在層 之間之矽穿孔(through-silicon vias，TSV)來傳輸或接收信 號’例如在介面晶片ICU及記憶體晶片MCIP之間，或是 在如圖42B所示之記憶體晶片MICP之間。 因此，將了解的是，所屬技術領域中具有通常知識者， 在不脫離本發明的精神和範圍内，當可作些許更動與潤 飾’故本發明的保護範圍當視後附的申請專利範圍所界定 31 201250705 42676pif 者為準。 【圖式簡單說明】 本發明概念之實施例將從下面的所附圖示之詳述的結 合來更加清楚了解’其圖示： 圖1為根據本發明概念之實施例的記憶體晶片的方塊 圖； 圖2是顯示圖1所示之儲存單元的儲存容量； 圖3為顯示在§己憶體晶片中標準容量及位址之位元數 之間的相互關係； 圖4A及圖4B為根據本發明概念之另一實施例的記憶 體晶片的方塊圖； 圖5為根據本發明概念之實施例的記憶體晶片構成於 之晶圓的概要圖； 圖6為根據本發明概念之實施例的記憶體系統的方塊 圖； 圖7為根據本發明概念之另一實施例的記憶體系統的 方塊圖； 圖8為圖7所示之第一及第二子儲 的流程圖； 心妤取万沄 號之各 圖9到圖12顯示圖7所示之第一及第二選擇 種不同的例子； σ 圖13到圖14顯示圖7所示之介面單元的例子. 以及St圖別、圖16Α及圖⑽、圖17Α到圖 及圖18Α到圖18D顯示圖7所示之第一及第二子儲存單 32 201250705 4^b/〇pif 元的例子； 圖19A及圖19B、圖20以及圖21顯示包括3個或更 多子儲存單元之記憶體晶片’以及包括於記憶體晶片之介 面單元的例子； 圖22到圖24為根據本發明概念之另一實施例來描述 存取記憶體晶片的方法； 圖25A及圖25B以及圖26A到圖26D為根據本發明 概念之實施例來描述處理死區的方法； 圖27為顯示包括於圖1所示之儲存單元之區組的示範 配置； 圖28為顯示位址之示範配置； 圖29為顯示具有第一標準容量之記憶體晶片中之位 址之例子； 圖30為根據本發明概念之實施例來顯示記憶體晶片 中之位址之例子； 圖31顯示因圖30所示之位址而導致之死區； 圖32為根據本發明概念之另一實施例來顯示記憶體 晶片中之位址之例子； 圖33及圖34顯示因圖32所示之位址而導致之死區的 例子； 圖35為根據本發明概念之另一實施例來顯示記憶體 晶片中之位址之例子； 圖及圖顯示因圖35所示之位址而導致之死區的 例子； 33 201250705 42676pif 圖38為根據本發明概念之實施例之電腦系統的方塊 圖； 圖39為根據本發明概念之實施例之記憶卡的概要圖； 圖40為根據本發明概念之實施例之固態硬碟(SSD)的 方塊圖； 圖41為根據本發明概念之實施例之包括SSD之伺服 器系統’及包括伺服器系統之網路系統的概要圖；以及 圖42A及圖42B為根據本發明概念之實施例之包括矽 穿孔(TSV)之記憶體系統的概要圖。 【主要元件符號說明】 1〇〇 :記憶單元陣列 110 :列解碼器 120 :行解碼器 130 :緩衝器 140 :緩衝器 ADEN .任意容量A schematic diagram of the system SSYS' and the network system NSYS including the server system SSYS. As shown in Fig. 41, the network system NSYS may include a server system SSYS and first to nth terminals ΤΕΜι to TEMn, which are connected through a network. The server system SSYS may include a server SERVER for processing requests received from the first to nth terminals TEm to TEMn, and the SSD is used to store requests corresponding to reception from the first to the nth terminals TEM1 to ΤΕΜn. data. In this example, the SSD shown in Fig. 41 may be the SSD shown in Fig. 4A. That is, the SSD shown in Fig. 41 may include the SSD controller SCTL and the memory chip MCIP, and the memory chip MCIP may be the memory chip MCIP shown in Fig. 6. The inventive concept has been shown and described with particular reference to the embodiments. The terminology used herein to describe the invention is for the purpose of description, and the scope of For example, although the memory system MSYS shown in Fig. 6 and the like is described as a 2-dimensional system', the inventive concept is not limited thereto. As shown in FIG. 42A and FIG. 42b, the memory system MSYS can be a 3-dimensional system by transmitting or receiving signals by using through-silicon vias (TSVs) between layers, such as in the interface chip ICU and memory. Between the body wafers MCIP, or between the memory chips MCP as shown in FIG. 42B. Therefore, it will be appreciated that those skilled in the art will be able to make a few changes and modifications without departing from the spirit and scope of the invention. The definition of 31 201250705 42676pif shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS [0007] Embodiments of the present invention will be more clearly understood from the following detailed description of the accompanying drawings. FIG. 1 is a block diagram of a memory wafer according to an embodiment of the inventive concept. Figure 2 is a diagram showing the storage capacity of the storage unit shown in Figure 1; Figure 3 is a diagram showing the relationship between the standard capacity and the number of bits in the DDR memory; Figure 4A and Figure 4B are based on FIG. 5 is a schematic diagram of a memory wafer formed on a memory wafer according to an embodiment of the inventive concept; FIG. 6 is a schematic diagram of a memory wafer according to an embodiment of the present invention; Figure 7 is a block diagram of a memory system in accordance with another embodiment of the inventive concept; Figure 8 is a flow chart of the first and second sub-stores shown in Figure 7; 9 to 12 of the apostrophe show different examples of the first and second selections shown in Fig. 7; σ Figs. 13 to 14 show examples of the interface unit shown in Fig. 7. and Fig. Fig. 16 And Figure (10), Figure 17Α to Figure 18 and Figure 18D to Figure 18D show Figure 7 Examples of first and second sub-storage sheets 32 201250705 4^b/〇pif elements; FIGS. 19A and 19B, FIG. 20 and FIG. 21 show memory chips including 3 or more sub-storage units' and including An example of an interface unit for a memory chip; FIGS. 22 through 24 illustrate a method of accessing a memory chip in accordance with another embodiment of the inventive concept; FIGS. 25A and 25B and FIGS. 26A to 26D are diagrams according to the present invention. The embodiment of the concept describes a method of processing a dead zone; FIG. 27 is an exemplary configuration showing a block included in the storage unit shown in FIG. 1. FIG. 28 is an exemplary configuration showing a address; FIG. An example of an address in a memory chip of a capacity; FIG. 30 is an example of displaying an address in a memory chip in accordance with an embodiment of the inventive concept; FIG. 31 shows a dead zone due to the address shown in FIG. 32 is an example of displaying an address in a memory chip in accordance with another embodiment of the inventive concept; and FIGS. 33 and 34 show an example of a dead zone due to the address shown in FIG. 32; Another embodiment in accordance with the inventive concept An example of displaying a address in a memory chip; FIG. and a diagram showing an example of a dead zone due to the address shown in FIG. 35; 33 201250705 42676pif FIG. 38 is a block diagram of a computer system according to an embodiment of the inventive concept. Figure 39 is a block diagram of a memory card in accordance with an embodiment of the inventive concept; Figure 40 is a block diagram of a solid state drive (SSD) in accordance with an embodiment of the inventive concept; A schematic diagram of a server system including an SSD and a network system including a server system; and FIGS. 42A and 42B are schematic diagrams of a memory system including a via via (TSV) according to an embodiment of the inventive concept. [Main component symbol description] 1〇〇: Memory cell array 110: Column decoder 120: Row decoder 130: Buffer 140: Buffer ADEN . Any capacity

Addr、Addrl、Addr2、Addrk、Addrp ·•位址 AI :位址輸入單元 All :第一位址輸入單元 AI2 :第二位址輸入單元 BA :區組位址 CA :行位址 CA0、CA1、CA2、CA3、Cat、CAT :行 CBUF :快取緩衝器 34 201250705 42b/5plf CI1 ··第一控制信號輸入單元 CI2 :第二控制信號輸入單元 CDIO :共用資料輸入/輸出單元 COU :控制單元 CSYS :電腦系統Addr, Addrl, Addr2, Addrk, Addrp · Address AI: Address input unit All: First address input unit AI2: Second address input unit BA: Block address CA: Row address CA0, CA1 CA2, CA3, Cat, CAT: Line CBUF: Cache Buffer 34 201250705 42b/5plf CI1 ··First Control Signal Input Unit CI2: Second Control Signal Input Unit CDIO: Common Data Input/Output Unit COU: Control Unit CSYS :computer system

Ctrl :控制器 CPU :處理器 DI01 :第一資料輸入/輸出單元 DI02:第二資料輸入/輸出單元 DTA、DTA卜 DTA2、DTAk、DTAp :資料 DZ .死^區 ICU :介面單元 I/O :輸入/輸出裝置 101 :第一輸入/輸出單元 102 :第二輸入/輸出單元 MCIP :記憶體晶片 MCRD :記憶卡 MSYS :記憶體系統 NonAct :非啟動模式 NoCom :命令(控制信號） PS :電源供應器 PROS :處理器 RA :列位址 RAM :隨機存取記憶體Ctrl : Controller CPU : Processor DI01 : First data input / output unit DI02 : Second data input / output unit DTA , DTA Bu DTA2 , DTAk , DTAp : Data DZ . Dead zone ICU : Interface unit I / O : Input/output device 101: First input/output unit 102: Second input/output unit MCIP: Memory chip MCRD: Memory card MSYS: Memory system NonAct: Non-start mode NoCom: Command (control signal) PS: Power supply PROS: Processor RA: Column Address RAM: Random Access Memory

RAO、RA 卜 RA2、RA3、RAs、RAT :歹丨J 35 201250705 42b/6pifRAO, RA Bu RA2, RA3, RAs, RAT: 歹丨J 35 201250705 42b/6pif

Req_Acc(Addr[DZ]):存取請求Req_Acc(Addr[DZ]): access request

Resp_Acc(fail):存取失敗信號 SCTL : SSD控制器 SEL :選擇單元 SERVER :伺月艮器 SSU1 :第一子儲存單元 SSU2 :第二子儲存單元 5511 :第一選擇信號輸入單元 5512 :第二選擇信號輸入單元 551 :第一選擇信號 552 :第二選擇信號 SSk :第k選擇信號 SSYS :伺服器系統 STU :儲存單元 S820、S840 :操作 S2320、S2340 :操作 TEM1 :第1終端機 TEM2 :第2終端機 TEM3 :第3終端機 TEMn :第η終端機 TSV :矽穿孔 UI :使用者介面 WAP :晶圓 XCON、XCON1、XCON2、XCONk、XCONp :控制 信號 36Resp_Acc(fail): access failure signal SCTL: SSD controller SEL: selection unit SERVER: server SSU1: first sub-storage unit SSU2: second sub-storage unit 5511: first selection signal input unit 5512: second Selection signal input unit 551: first selection signal 552: second selection signal SSk: kth selection signal SSYS: server system STU: storage unit S820, S840: operation S2320, S2340: operation TEM1: first terminal TEM2: 2 Terminal TEM3: 3rd terminal TEMn: η terminal TSV: 矽 Perforated UI: User interface WAP: Wafer XCON, XCON1, XCON2, XCONk, XCONp: Control signal 36

Claims (1)

201250705 42676pif 七、申請專利範圍： L 一種記憶體晶片，包括： 意容量= 有一任意容量之—儲存區，該任 容量，守I第—標準容量^及小於—第二標準 -^制二準容量A於該P標準容量的兩倍；以及 以及資二:存，資料到該儲存單元的寫入操作 储存;讀取操作’α及該控制單元與該 其中该儲存單元包括： 第子儲存單元，回岸於一第一撰埋•味品 具有-第三標準容量；J^狀《選擇㈣而啟動且 且右=單元，回應於4二選擇信號而啟動且 具有一第四標準容量，以及 其^第三標準容量及該第四鮮容量之總和等於該 任意容|。 2如申5月，利範圍帛1項所述之記憶體晶片，更進一 步包括-介面單元，用來回應於該第—選擇信號以傳輸關 於該第-子儲存單元之:#料、位址及控制信號到一外部裝 置，或回應?該第-選擇信號峨料部I置接收關於該 第-子儲存單7L之資料、位址及控制信號，献回應於該 第二選擇信號以傳輪關於該第二子儲存單元之資料、位址 及控制信制料轉置，或回應_帛二祕信號以從 該外部裝置接收關於第二子儲存單元之資料、位址及控制 信號。 37 201250705 42676pif 介面單Γ包申括月專利範圍第2項所述之記憶體晶片，其令該 儲存；苐輸出單元，用來傳輸或接收關於該第-子 储存：兀之資料、位址及控制信號；以及 錯存輸出單元’用來傳輸或接收關於該第二子 及控制信號，且所構成的該第二輸 入/輸出早喊立於該第—輸人/輸出單元。 4 显如申請專利範圍第2項所述之記憶體晶片 ，其中該 少〖—共用輸人/輸出單元而时傳輸或接收至 該群組由關於該第一子儲存單元之資料、位 群組:關3所:成，以及傳輸或接收至少-該群組’該 成。1於第二子儲存單元之資料、位址及控制信號所構 成該ϋ申請專利範圍第1項所述之記憶體晶片，其中構 «儲存單元之記憶單元的一類型相同於構成該第 -千儲存早元之記憶單元的該類型。 成請專利範圍第1項所述之記憶體晶片，其中構 二ΐ儲;r留儲存單7之記憶單元的一類型不同於構成該第 存單元之記憶單元的該類型。 存於專利範圍第1項所述之記憶體晶片，其中儲 -子:Ϊ苗儲存單元之資料之一使用相同於儲存於該第 -子儲存単元之資料之該使用。 ，如申請專利範圍第i項所述之記憶體晶片，其中 子於。玄第一子儲存單元之資料之一使用不同於儲存於該第 38 201250705 42676pif 子儲存 9. 一 單元之資料之該使用。 種記憶體晶片，包括： 意容量it包括具有一任意容量之-儲存區，該任 容旦^具有2的—第—標準容量以及小於1二標準 里一第=標準容量大於該第一標準容量的兩倍；以及 一控制單元，用來控制資料到該儲存 一及該控 單元其=於位元數之一記憶體位址而存取該儲存 數與關於該第一標準容量之該 比大了 1-位元。 仲 10.如申5月專利範圍第9項所述之記憶體晶片，盆中 若=接收_-記龍位址沒有映射_儲存單元該控 制單元處理_該記憶體位址之—存取結果視為失敗。 39201250705 42676pif VII. Patent application scope: L A memory chip, including: Italian capacity = a certain capacity - storage area, the capacity, the first - standard capacity ^ and less than - the second standard - ^ two standard capacity A is twice the capacity of the P standard; and the second storage: the storage operation of the data to the storage unit; the reading operation 'α and the control unit and the storage unit include: the first storage unit, Back to shore in a first burial • flavor has a - third standard capacity; J ^ "select (four) and start and right = unit, in response to the 4 two selection signal and has a fourth standard capacity, and its ^ The sum of the third standard capacity and the fourth fresh capacity is equal to the arbitrary capacity|. 2, as claimed in claim 5, the memory chip described in paragraph 1, further comprising an interface unit for responding to the first selection signal for transmitting the first sub-storage unit: #料, address And the control signal is sent to an external device, or the first selection signal buffering portion I receives the data, the address and the control signal about the first sub-memory list 7L, and responds to the second selection signal to transmit the wheel Data, address and control signal transposition of the second sub-storage unit, or response to the second sub-signal to receive data, address and control signals for the second sub-storage unit from the external device. 37 201250705 42676pif interface package includes the memory chip described in item 2 of the patent scope of the month, which causes the storage unit; the output unit for transmitting or receiving information about the first-sub-storage: 兀, address and The control signal; and the faulty output unit 'is used to transmit or receive the second sub-control signal, and the second input/output is formed to stand on the first input/output unit. 4 The memory chip according to claim 2, wherein the less--shared input/output unit is transmitted or received to the group by the information about the first sub-storage unit, the bit group : Off 3: Cheng, and transmit or receive at least - the group 'this. The data, the address and the control signal of the second sub-storage unit constitute the memory chip according to the first aspect of the patent application, wherein a type of the memory unit of the storage unit is the same as the first Store this type of memory unit in the early element. A memory chip according to the first aspect of the patent application, wherein the memory cell of the r memory cell 7 is of a different type than the memory cell constituting the memory cell. The memory chip of claim 1, wherein one of the data of the storage: seedling storage unit uses the same data as that stored in the first storage unit. For example, the memory chip described in claim i is in the middle of the patent. One of the materials of the first sub-storage unit is used differently from the data stored in the unit of the 38th 201250705 42676pif sub-storage 9. The memory chip includes: the intended capacity it includes a storage area having an arbitrary capacity, the any capacity has 2 - the first standard capacity and the second standard = the standard capacity is greater than the first standard capacity And a control unit for controlling data to the storage unit 1 and the control unit, wherein the memory number of one of the number of bits is accessed, and the storage number is greater than the ratio of the first standard capacity. Bit. Zhong 10. The memory chip according to item 9 of the patent scope of May 5, if there is no mapping in the basin = receiving _- 记 龙 address _ storage unit processing unit processing _ the memory address - access result For failure. 39
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