201244358 六、發明說明： 【發明所屬之技術領域1 本發明涉及一種用於一次側控制功率轉換器的電路；特別涉及 一種用於一次側控制功率轉換器的適應性電路。 【先前技術】 圖1顯示習知的一次側控制功率轉換器的電路圖。該一次側控 制功率轉換器包含一變壓器10，該變壓器10包含一次側繞組Np、 二次側繞組Ns及一輔助繞組NA。該功率轉換器的一輸入電壓V!N 供應至該一次側繞組NP。一切換控制器100耦合至由電阻51與 57所形成的一分壓器且透過該分壓器取樣該變壓器10的該輔助 繞組NA的一反射電壓VA。該電阻51的一端連接至該變壓器10 的該輔助繞組NA，且該電阻51的另一端連接至該電阻57的一端。 該電阻57的另一端親接至地。該電阻51與該電阻57串聯。基於 該反射電壓VA，一訊號VS產生於該電阻51與該電阻57的連接 處且施與至該切換控制器1〇〇的一偵測端Vs 〇該反射電壓VA與 該訊號Vs關聯於該功率轉換器的一輸出電壓V〇。該一次側控制 功率轉換器進一步包含一整流器40與一電容45。該整流器40的 一陽極連接至該電阻51與該輔助繞組NA。該整流器40的一陰極 連接至該電容45。一供應電壓VCC供應至該切換控制器100的一 供應端VCC，其連接至該整流器40的該陰極與該電容45的連接 處。一整流器60的一陽極連接至該變壓器10的該二次側繞組 201244358 NS，且該整流器60的一陰極連接至一輸出電容65。一負載70與 該輸出電容65並聯，且該輸出電壓VO產生於該負載70的一端。 該切換控制器100接收可視爲一電壓回饋訊號(feedback signal) 的訊號Vs，其關聯於該功率轉換器的該輸出電壓V〇。響應於該電 壓回饋訊號，該切換控制器100產生一切換訊號Sw以切換一功率 晶體管20及該變壓器10 ,進而調節該功率轉換器的該輸出電壓 ν〇。當該切換訊號Sw變爲邏輯高準位(logic-high)，一次側切換電 流Ip將因此產生。耦合至該功率晶體管20的一電流感測電阻30 可作爲一電流感測組件。一電流感測訊號Vcs產生於該電流感測 電阻30與該功率晶體管20的連接處，且被施與至該切換控制器 100的一感測端CS。該一次側控制功率轉換器的詳細描述於以下 專利：美國專利 6,977,824 ’ 發明名稱 “Control circuit for controlling output current at the primary side of a power converter” ；以及美國 專利 7,016,204，發明名稱 “Close-loop PWM controller for primary-side controlled power conveters” 。 該訊號Vs的波形顯示於圖2 〇該訊號Vs於該切換訊號Sw的 截止週期(off-time period)期間產生。過了一遮沒期間(blanking peri〇d)TBUC之後，該訊號Vs將爲穩定且關聯於該輸出電壓V〇。 然而，該變壓器10的漏感與該功率晶體管20的汲極電容造成具 有一振鈴期間Trxng的振鈴訊號Vr!nG於該訊號Vs中。此外因爲 該反射電壓VA包含該振鈴訊號VRING，其將造成不想要的値於該 訊號Vs中。圖3顯示習知的一次側控制功率轉換器的另一電路 201244358 圖。一電容58連接至該等電阻51、57與地的連接處，.以減小該 訊號Vs中的該振鈴訊號VRINC。該等電阻51、57與該電容58形 成一低通濾波器。然而，該低通濾波器造成該訊號VS的失真及取 樣錯誤。圖4顯示在該切換訊號Sw的截止期間該訊號Vs的失真 的波形。因爲該低通濾波器，該訊號Vs波形失真且該訊號Vs的 上升時間延長，其造成當該訊號Vs的脈寬短的時候取樣錯誤。舉 例而言，當該負載爲輕負載或無載情況，因爲該切換訊號Sw的小 脈寬，該訊號Vs的脈寬太短以致無法精準地被該控制器100所取 樣來產生該電壓回饋訊號。取樣錯誤造成不正確的電壓回饋訊號 (該電壓回饋訊號的較低値)且導致該輸出電壓V〇的增量。換言 之，因爲該控制器100感測到不正確的電壓回饋訊號，該輸出電 壓V〇將會太高。再者，該訊號Vs的失真波形與延長的穩定時間 TD限制了該切換訊號SW的最高速度與最高頻率。 【發明內容】 本發明之一目的是濾除振鈴訊號VRIM3而無須延長穩定時間 TD。本發明提供一種用於一次側控制功率轉換器的適應性電路， 以取樣一變壓器的反射電壓。該變壓器的該反射電壓用S舞周節功 率轉換器的輸出電壓與輸出電流。 爲達到上述目的，本發明提供一種用於取樣功率轉換器的變壓 器的一反射電壓的適應性濾波電路，包含：一第一開關，用以接 收該反射電壓；一電阻，具有一第一端與一第二端，該電阻的該 第一端耦合至該第一開關；一電容，耦合至該電阻的該第二端以 201244358 保持該反射電壓以及一第二開關，並聯耦合至該電阻；其中該 電阻與該電容形成一濾波器以取樣該反射電壓；於一切換訊號的 一禁能(disable)期間，該反射電壓於一第一期間未藉由該濾波器濾 波而被取樣；且於該切換訊號的一該禁能期間，該反射電壓於一 第二期間藉由該濾波器濾波而被取樣。 前述適應性濾波電路，該第一期間與該第二期間是藉由開啓與 關閉該第一開關與該第二開關所決定。 前述適應性濾波電路，該第二期間於該第一期間結束後開始。 前述適應性濾波電路，該反射電壓被取樣以產生用於該功率轉 換器的一回饋訊號；該反射電壓關聯於該功率轉換器的一輸出電 壓。. 前述適應性濾波電路，該第一開關於該第一期間與該第二期間 開啓。 前述適應性濾波電路，該第二開關於該第二期間關閉。 前述適應性濾波電路，該回饋訊號爲電壓回饋訊號。 爲達到上述目的，本發明復提供一種用於取樣功率轉換器的變 壓器的一反射電壓的適應性濾波電路，包含：一取樣保持電路， 耦合以取樣該反射電壓；及一電阻，耦合至該取樣保持電路；其 中該電阻與該取樣保持電路的一電容形成一濾波器以取樣該反射 電壓；該反射電壓於一第一期間未藉由該濾波器濾波而被取樣； 該反射電壓於一第二期間藉由該濾波器濾波而被取樣。 爲達到上述目的，本發明還提供一種用於取樣功率轉換器的變· 201244358 壓器的一反射電壓的適應性濾波電路’包含：一第一開關，用以. 接收該反射電壓；一濾波器，耦合至該第一開關且包含一電阻與 一電容，以取樣該反射電壓；及一第二開關，並聯親合至該電阻； 其中於該變壓器的一放電期間，該反射電壓於一第一期間未藉由 該瀘波器濾波而被取樣；且於該變壓器的該放電期間，該反射電 壓於一第二期間藉由該濾波器濾波而被取樣。 爲達到上述目的，本發明還提供一種用於取樣功率轉換器的變 壓器的一反射電壓的方法，包含：於一切換訊號被禁能後，接收 該反射電壓；於一第一期間禁能一振鈴消除模組，且於該第一期 間，該反射電壓包含振鈴訊號；及於一第二期間致能(enable)—振 鈴消除模組，且於該第二期間，該反射電壓的振鈴訊號被消除； 其中該振鈴消除模組耦合至該反射電壓，且該切換訊號用於切換 該變壓器。 【實施方式】 本發明的實施例及其優點藉由參考附圖可被最佳地了解。類似 的組件符號使用於各附圖中相似及對應的組件。 圖5是根據本發明一較佳實施例用於一次側控制功率轉換器的 一控制器100’的方塊圖。該控制器100’具有類似於圖1中該切 換控制器100的功能’但是具有本發明的新穎特徵。該控制器 100’包含一電壓偵測電路(V-DET) 150、一電流偵測電路(I-DET) 200 --積分器250 誤差放大器350 誤差放大器370、一低 201244358 通濾波器(LPF) 400、一低通濾波器(LPF) 450以及一脈寬調變電路 (PWM) 500。 該電壓偵測電路150耦合至顯示於圖1中的該偵測端Vs，以接 收該訊號Vs來產生一電壓回饋訊號VV及一放電時間訊號SDS。 一參考訊號VRV供應至該誤差放大器350的一正輸入，且該電壓 回饋訊號Vv被接收於該誤差放大器350的一負輸入。該誤差放大 器350輸出一放大訊號Ev，以放大該電壓回饋訊號Vv與該參考 訊號VRV間的一誤差且提供一電壓回路增益以響應該參考訊號 VRV。該電壓回路增益用於輸出電壓控制。該放大訊號Ev被該低 通濾波器400所接收以產生一電壓回路訊號Vc〇MV來作該電壓回 路的頻率補償。 該電流偵測電路200耦合至顯示於圖1中的該電流感測端 CS，以接收一電流感測訊號Vcs來產生一電流波形訊號Vw。該積 分器250耦合至該電流偵測電路200與該電壓偵測電路15〇，以根 據該電流波形訊號Vw與該放電時間訊號SDS來產生一電流回饋訊 號％。該電流波形訊號Vw藉由量測顯示於圖3的該一次側切換 電流Ip所產生。該電流回饋訊號^藉由積分該電流波形訊號vw 與該放電時間訊號SDS來產生。該電流回饋訊號％進一步施予至 該誤差放大器370的一負輸入，且一參考訊號VRI施予至該誤差放 大器370的一正輸入。該誤差放大器370產生一放大訊號El，以 放大該電流回饋訊號％與該參考訊號VRI間的一誤差且提供一電 流回路增益以響應該參考訊號VRI。該電流回路增益用於輸出電流 201244358 控制。 該低通濾波器450接收該放大訊號玛以產生一電流回路訊號 VCOMI來作該電流回路的頻率補償。該PWM電路500產生該切換 訊號Sw且控制該切換訊號Sw的脈寬，以響應該電壓回路訊號 Vc〇MV與該電流回路訊號VcOMI 〇因此，該控制器100接收該訊 號Vs以產生該切換訊號sw 〇 圖6是根據本發明一較佳實施例的電壓偵測電路150，其包含 一適應性爐波電路，用來取樣產生顯示於圖1的該偵測端VS的該 訊號Vs。該適應性濾波電路包含由第一開關171與電容172所形 成的一取樣保持電路、一第二開關181、一電阻182、一緩衝放大 器172、一第三開關179以及一電容176。該電阻182與該電容172 架構以形成一濾波器。該訊號Vs關聯於該變壓器10的該反射電 壓VA。該電阻182耦合至該第一開關171與該第二開關181。該 電容172耦合至該電阻182與該緩衝放大器172的一正輸入端。 該第一開關171的一控制端由一取樣訊號SMP所控制。當該取樣 訊號SMP致能且該第一開關171開啓(turned on)，該訊號Vs透過 該電阻182被取樣至該電容172。亦即，一旦該取樣訊號SMP致能 且該第一開關171開啓，該電容172耦合至該第一開關171以保 持該反射電壓VA 〇201244358 VI. Description of the Invention: [Technical Field 1 of the Invention] The present invention relates to a circuit for controlling a power converter on a primary side; and more particularly to an adaptive circuit for controlling a power converter on a primary side. [Prior Art] Fig. 1 shows a circuit diagram of a conventional primary side control power converter. The primary side control power converter includes a transformer 10 including a primary side winding Np, a secondary side winding Ns, and an auxiliary winding NA. An input voltage V!N of the power converter is supplied to the primary side winding NP. A switching controller 100 is coupled to a voltage divider formed by resistors 51 and 57 and samples a reflected voltage VA of the auxiliary winding NA of the transformer 10 through the voltage divider. One end of the resistor 51 is connected to the auxiliary winding NA of the transformer 10, and the other end of the resistor 51 is connected to one end of the resistor 57. The other end of the resistor 57 is in contact with the ground. The resistor 51 is connected in series with the resistor 57. Based on the reflected voltage VA, a signal VS is generated at the junction of the resistor 51 and the resistor 57 and is applied to a detecting terminal Vs of the switching controller 1A. The reflected voltage VA is associated with the signal Vs. An output voltage V〇 of the power converter. The primary side control power converter further includes a rectifier 40 and a capacitor 45. An anode of the rectifier 40 is coupled to the resistor 51 and the auxiliary winding NA. A cathode of the rectifier 40 is coupled to the capacitor 45. A supply voltage VCC is supplied to a supply terminal VCC of the switching controller 100, which is connected to the junction of the cathode of the rectifier 40 and the capacitor 45. An anode of a rectifier 60 is coupled to the secondary winding 201244358 NS of the transformer 10, and a cathode of the rectifier 60 is coupled to an output capacitor 65. A load 70 is coupled in parallel with the output capacitor 65, and the output voltage VO is generated at one end of the load 70. The switching controller 100 receives a signal Vs that can be viewed as a voltage feedback signal associated with the output voltage V〇 of the power converter. In response to the voltage feedback signal, the switching controller 100 generates a switching signal Sw to switch a power transistor 20 and the transformer 10 to adjust the output voltage ν 该 of the power converter. When the switching signal Sw becomes a logic high, the primary side switching current Ip will be generated. A current sense resistor 30 coupled to the power transistor 20 can function as a current sensing component. A current sensing signal Vcs is generated at the junction of the current sensing resistor 30 and the power transistor 20, and is applied to a sensing terminal CS of the switching controller 100. The primary side control power converter is described in detail in U.S. Patent No. 6,977,824, entitled "Control circuit for controlling output current at the primary side of a power converter"; and U.S. Patent 7,016,204, entitled "Close-loop PWM controller". For primary-side controlled power conveters". The waveform of the signal Vs is shown in Figure 2, and the signal Vs is generated during the off-time period of the switching signal Sw. After a blanking period (blanking peri〇d) TBUC, the signal Vs will be stable and associated with the output voltage V〇. However, the leakage inductance of the transformer 10 and the drain capacitance of the power transistor 20 cause a ringing signal Vr!nG having a ringing period Trxng in the signal Vs. In addition, since the reflected voltage VA includes the ringing signal VRING, it will cause unwanted sag in the signal Vs. Figure 3 shows another circuit of the conventional primary side control power converter 201244358. A capacitor 58 is connected to the junction of the resistors 51, 57 and ground to reduce the ringing signal VRINC in the signal Vs. The resistors 51, 57 and the capacitor 58 form a low pass filter. However, the low pass filter causes distortion and sampling errors of the signal VS. Fig. 4 shows the waveform of the distortion of the signal Vs during the off period of the switching signal Sw. Because of the low pass filter, the signal Vs waveform is distorted and the rise time of the signal Vs is prolonged, which causes a sampling error when the pulse width of the signal Vs is short. For example, when the load is light load or no load, because the small pulse width of the switching signal Sw, the pulse width of the signal Vs is too short to be accurately sampled by the controller 100 to generate the voltage feedback signal. . A sampling error results in an incorrect voltage feedback signal (which is lower of the voltage feedback signal) and causes an increase in the output voltage V〇. In other words, because the controller 100 senses an incorrect voltage feedback signal, the output voltage V〇 will be too high. Moreover, the distortion waveform of the signal Vs and the extended settling time TD limit the maximum speed and the highest frequency of the switching signal SW. SUMMARY OF THE INVENTION One object of the present invention is to filter out the ringing signal VRIM3 without extending the settling time TD. The present invention provides an adaptive circuit for a primary side control power converter to sample the reflected voltage of a transformer. The reflected voltage of the transformer uses the output voltage and output current of the S-week power converter. To achieve the above object, the present invention provides an adaptive filter circuit for a reflected voltage of a transformer for sampling a power converter, comprising: a first switch for receiving the reflected voltage; and a resistor having a first end and a second end, the first end of the resistor is coupled to the first switch; a capacitor coupled to the second end of the resistor to maintain the reflected voltage at 201244358 and a second switch coupled to the resistor in parallel; The resistor and the capacitor form a filter to sample the reflected voltage; during a disable of a switching signal, the reflected voltage is not sampled by the filter during a first period; and During a disable period of the switching signal, the reflected voltage is sampled by filtering the filter during a second period. In the adaptive filter circuit, the first period and the second period are determined by turning on and off the first switch and the second switch. In the aforementioned adaptive filter circuit, the second period starts after the end of the first period. In the aforementioned adaptive filter circuit, the reflected voltage is sampled to generate a feedback signal for the power converter; the reflected voltage is associated with an output voltage of the power converter. In the above adaptive filter circuit, the first switch is turned on during the first period and the second period. In the foregoing adaptive filter circuit, the second switch is turned off during the second period. In the foregoing adaptive filter circuit, the feedback signal is a voltage feedback signal. To achieve the above object, the present invention provides an adaptive filter circuit for a reflected voltage of a transformer for sampling a power converter, comprising: a sample and hold circuit coupled to sample the reflected voltage; and a resistor coupled to the sample a holding circuit; wherein the resistor forms a filter with a capacitor of the sample and hold circuit to sample the reflected voltage; the reflected voltage is not sampled by the filter during a first period; the reflected voltage is at a second The period is sampled by filtering by the filter. In order to achieve the above object, the present invention further provides an adaptive filter circuit for a reflected voltage of a 201244358 voltage converter for sampling a power converter, comprising: a first switch for receiving the reflected voltage; a filter And coupled to the first switch and including a resistor and a capacitor to sample the reflected voltage; and a second switch coupled in parallel to the resistor; wherein during a discharge of the transformer, the reflected voltage is at a first The period is not sampled by the chopper filter; and during the discharge of the transformer, the reflected voltage is sampled by filtering by the filter during a second period. To achieve the above object, the present invention also provides a method for sampling a reflected voltage of a transformer of a power converter, comprising: receiving a reflected voltage after a switching signal is disabled; and disabling a ring during a first period Eliminating the module, and during the first period, the reflected voltage includes a ringing signal; and enabling a ringing cancellation module during a second period, and during the second period, the ringing signal of the reflected voltage is eliminated Wherein the ring cancellation module is coupled to the reflected voltage, and the switching signal is used to switch the transformer. [Embodiment] The embodiments of the present invention and the advantages thereof are best understood by referring to the accompanying drawings. Similar component symbols are used for similar and corresponding components in the various figures. Figure 5 is a block diagram of a controller 100' for controlling the power converter on the primary side in accordance with a preferred embodiment of the present invention. The controller 100' has a function similar to that of the switching controller 100 of Fig. 1 but has the novel features of the present invention. The controller 100' includes a voltage detecting circuit (V-DET) 150, a current detecting circuit (I-DET) 200 - an integrator 250 error amplifier 350 error amplifier 370, and a low 201244358 pass filter (LPF) 400, a low pass filter (LPF) 450 and a pulse width modulation circuit (PWM) 500. The voltage detecting circuit 150 is coupled to the detecting terminal Vs shown in FIG. 1 to receive the signal Vs to generate a voltage feedback signal VV and a discharging time signal SDS. A reference signal VRV is supplied to a positive input of the error amplifier 350, and the voltage feedback signal Vv is received at a negative input of the error amplifier 350. The error amplifier 350 outputs an amplification signal Ev to amplify an error between the voltage feedback signal Vv and the reference signal VRV and provide a voltage loop gain in response to the reference signal VRV. This voltage loop gain is used for output voltage control. The amplified signal Ev is received by the low pass filter 400 to generate a voltage loop signal Vc 〇 MV for frequency compensation of the voltage loop. The current detecting circuit 200 is coupled to the current sensing terminal CS shown in FIG. 1 to receive a current sensing signal Vcs to generate a current waveform signal Vw. The integrator 250 is coupled to the current detecting circuit 200 and the voltage detecting circuit 15A to generate a current feedback signal % based on the current waveform signal Vw and the discharging time signal SDS. The current waveform signal Vw is generated by measuring the primary side switching current Ip shown in Fig. 3. The current feedback signal is generated by integrating the current waveform signal vw and the discharge time signal SDS. The current feedback signal % is further applied to a negative input of the error amplifier 370, and a reference signal VRI is applied to a positive input of the error amplifier 370. The error amplifier 370 generates an amplification signal E1 to amplify an error between the current feedback signal % and the reference signal VRI and provide a current loop gain in response to the reference signal VRI. This current loop gain is used to output current 201244358 control. The low pass filter 450 receives the amplified signal to generate a current loop signal VCOMI for frequency compensation of the current loop. The PWM circuit 500 generates the switching signal Sw and controls the pulse width of the switching signal Sw in response to the voltage loop signal Vc〇MV and the current loop signal VcOMI. Therefore, the controller 100 receives the signal Vs to generate the switching signal. FIG. 6 is a voltage detection circuit 150 including an adaptive furnace circuit for sampling the signal Vs displayed on the detection terminal VS of FIG. 1 according to a preferred embodiment of the present invention. The adaptive filter circuit includes a sample and hold circuit formed by the first switch 171 and the capacitor 172, a second switch 181, a resistor 182, a buffer amplifier 172, a third switch 179, and a capacitor 176. The resistor 182 is structured with the capacitor 172 to form a filter. The signal Vs is associated with the reflected voltage VA of the transformer 10. The resistor 182 is coupled to the first switch 171 and the second switch 181. The capacitor 172 is coupled to the resistor 182 and a positive input of the buffer amplifier 172. A control terminal of the first switch 171 is controlled by a sampling signal SMP. When the sampling signal SMP is enabled and the first switch 171 is turned on, the signal Vs is sampled to the capacitor 172 through the resistor 182. That is, once the sampling signal SMP is enabled and the first switch 171 is turned on, the capacitor 172 is coupled to the first switch 171 to maintain the reflected voltage VA 〇
該第二開關181與該電阻182並聯。該第二開關181的一控制 端由一遮沒訊號(blanking signal)SBu^if控制。當該遮沒訊號SBLK 致能且該第二開關181開啓，將沒有電流通過該電阻182。該緩衝 10 201244358 放大器Π2的負輸入端與正輸入端連接在一起。該第三開關1?9 連接至該緩衝放大器175的輸出端及該電容丨76。該第三開關179 的一控制端由一保持訊號SHD所控制。由一保持訊號Shd所控制的 該第三開關179架構以取樣該電容172內的一 存訊號’且將該 儲存訊號傳至該電容176以產生該電壓回饋訊號乂〃。由該電阻182 與該電容172所形成的該濾波器具有一極點 Λ=—1 .................................⑴ l^rxRmx Cm 其中，忽略電阻51與57的阻値。 該切換訊號Sw、該訊號Vs、該遮沒訊號Sblk '該取樣訊號Smp 以及該保持訊號SHD的波形顯示於圖7。該訊號VS產生於該切換 訊號Sw的截止期間(off-time period)期間。該遮沒訊號Sblk與該取 樣訊號SMP亦產生於該切換訊號Sw的截止期間(off-time period)期 間。該取樣訊號SMP架構以於該遮沒訊號SBLK結束前不被禁能。 如圖ό所示，由該電阻182與該電容172所形成的濾波器接收該 訊號Vs以取樣該反射電壓VA。於該切換訊號SW禁能期間，該 反射電壓VA於第一期間與一第二期間內被取樣至該電容172。該 第一期間與該第二期間藉由開啓與關閉該第一開關與該第二開關 所決定。該第二期間於該第一期間結束後開始。該第一開關171 於該第一期間與該第二期間開啓。該第二開關181於該第二期間 開啓。換言之，該瀘波器於該第二期間被致能而於該第一期間被 禁能。產生取樣訊號SMP的技術描述於以下專利：美國專利 7,349,229，發明名稱 “Causal sampling circuit for measuring 201244358 reflected voltage and demagnetizing time of transformer” ；以及美國 專利 7,486,528，發明名稱 “Linear-predict sampling for measuring demagnetized voltage of transformer”。該保持訊號 SHD 於該切換訊 號Sw起始之前產生，且僅當該切換訊號Sw被禁能時致能。於該 遮沒訊號SBLK致能期間，其對應至該訊號Vs的上升邊緣的期間， 因爲該第二開關181藉由該遮沒訊號SBLK開啓且無電流通過該電 阻182，該訊號Vs未被濾波而取樣。於該遮沒訊號SBLK被禁能之 後，該振鈴訊號VRING藉由該電阻182與該電容172所形成的低通 濾波器被濾除。 藉由該適應性濾波電路，該訊號Vs可更精準地被取樣以獲得 圖7的波形而不是圖4的失真的波形，並且不需要圖3中的該電 容58。因此，可避免該訊號VS的長的上升時間與穩定時間TD的 影響。進一步，當該負載爲輕負載或無載情況，由於該訊號Vs的 較小脈寬所造成的高輸出電壓亦可被避免。 請參見圖8，其說明本發明之取樣一功率轉換器的一變壓器的 一反射電壓的方法。步驟S1說明，禁能一切換訊號後，接收該反 射電壓；步驟S2說明，於一第一期間禁能一振鈴消除模組，且於 該第一期間該反射電壓包含振鈴訊號；步驟S3說明，於一第二期 間致能該振鈴消除模組，且於該第二期間該反射電壓的振鈴訊號 被消除。根據本發明之方法，該振鈴消除模組尙包含：耦合至該 反射訊號的一濾波電路，及耦合至該濾波電路的一取樣保持電 路。該濾波電路包含：一濾波器及耦合至該濾波器的一開關。 12 201244358 上述步驟S2尙包含禁能該濾波電路，以及包含禁能該開關。· 上述步驟S3尙包含致能該濾波電路，以及包含致能該開關。 雖然本發明及其優點已被詳細描述，應可了解在不惊離如以下 申請專利範圍所定義的本發明範疇與精神情況下，可進行不術改 變、置換及更替。亦即，此發明所涵蓋的討論意指作爲一基本描 述。應可了解到特定討論非明確地描述所有可能實施例；眾多選 擇爲隱含的。文中可能未完整說明本發明的通用本質，且可能未 明確解說每一特徵或組件如何確實成爲一較爲槪括的功效或各種 可供選擇或等術組件的代錶。再次，這些隱含於此公開的文件中。 發明說明或術語非意欲限制申請專利範圍的保護範圍。 【圖式簡單說明】 圖1顯示習知的一次側控制功率轉換器的電路圖。 圖2顯示圖1習知的一次側控制功率轉換器的訊號Vs的波形。 圖3顯示習知的一次側控制功率轉換器的另一電路圖。 圖4顯示圖3習知的一次側控制功率轉換器在切換訊號Sw的 截止期間該訊號Vs的失真的波形。 圖5是根據本發明一$交佳實施例用於一次側控制功率轉換器的 一控制器的方塊圖。 圖ό是根據本發明一較佳實施例的電壓偵測電路。 圖7顯示切換訊號Sw、訊號Vs、遮沒訊號SBUC、取樣訊號SMP 以及保持訊號SHD的波形 13 201244358 圖8顯示根據本發明之取樣一功率轉換器的一變壓器的一反射 電壓的方法。 【主要元件符號說明】 10 變壓器 20 功率晶體管 30 電流感測電阻 40 整流器 45 電容 51 電阻 57 電阻 58 電容 60 整流器 65 輸出電容 70 負載 100 切換控制器 150 電壓偵測電路 171 第一開關 172 電容 175 緩衝放大器 176 電容 179 第三開關 181 第二開關 14 201244358 182 電阻 200 電流偵測電路 250 積分器 350 誤差放大器 370 誤差放大器 400 低通濾波器 450 低通濾波器 500 脈寬調變電路The second switch 181 is connected in parallel with the resistor 182. A control terminal of the second switch 181 is controlled by a blanking signal SBu^if. When the blanking signal SBLK is enabled and the second switch 181 is turned on, no current will pass through the resistor 182. The buffer 10 201244358 The negative input of amplifier Π2 is connected to the positive input. The third switch 1-9 is connected to the output of the buffer amplifier 175 and the capacitor 丨76. A control terminal of the third switch 179 is controlled by a hold signal SHD. The third switch 179 controlled by a hold signal Shd is configured to sample a stored signal ' in the capacitor 172 and pass the stored signal to the capacitor 176 to generate the voltage feedback signal 乂〃. The filter formed by the resistor 182 and the capacitor 172 has a pole Λ = -1 ........................ ...(1) l^rxRmx Cm where the resistance of the resistors 51 and 57 is ignored. The switching signal Sw, the signal Vs, the blanking signal Sblk 'the sampling signal Smp and the waveform of the holding signal SHD are shown in FIG. The signal VS is generated during the off-time period of the switching signal Sw. The blanking signal Sblk and the sampling signal SMP are also generated during the off-time period of the switching signal Sw. The sampled signal SMP architecture is not disabled until the end of the blanking signal SBLK. As shown in FIG. ,, the filter formed by the resistor 182 and the capacitor 172 receives the signal Vs to sample the reflected voltage VA. During the disable of the switching signal SW, the reflected voltage VA is sampled to the capacitor 172 during a first period and a second period. The first period and the second period are determined by turning the first switch and the second switch on and off. The second period begins after the end of the first period. The first switch 171 is turned on during the first period and the second period. The second switch 181 is turned on during the second period. In other words, the chopper is enabled during the second period and disabled during the first period. Techniques for generating a sampled signal SMP are described in U.S. Patent No. 7,349,229, entitled "Causal sampling circuit for measuring 201244358 reflected voltage and demagnetizing time of transformer"; and U.S. Patent No. 7,486,528, entitled "Linear-predict sampling for measuring demagnetized voltage of Transformer". The hold signal SHD is generated before the start of the switching signal Sw and is enabled only when the switching signal Sw is disabled. During the period when the blanking signal SBLK is enabled, it corresponds to the rising edge of the signal Vs. Since the second switch 181 is turned on by the blanking signal SBLK and no current flows through the resistor 182, the signal Vs is not filtered. And sampling. After the blanking signal SBLK is disabled, the ringing signal VRING is filtered by the low-pass filter formed by the resistor 182 and the capacitor 172. With the adaptive filter circuit, the signal Vs can be sampled more accurately to obtain the waveform of Fig. 7 instead of the distorted waveform of Fig. 4, and the capacitor 58 of Fig. 3 is not required. Therefore, the influence of the long rise time of the signal VS and the settling time TD can be avoided. Further, when the load is light load or no load, a high output voltage due to a small pulse width of the signal Vs can be avoided. Referring to Figure 8, a method of sampling a reflected voltage of a transformer of a power converter of the present invention is illustrated. Step S1 illustrates that the reflected voltage is received after the switch is disabled, and the step S2 is configured to disable a ringing cancellation module during a first period, and the reflected voltage includes a ringing signal during the first period; The ringing cancellation module is enabled during a second period, and the ringing signal of the reflected voltage is eliminated during the second period. In accordance with the method of the present invention, the ring cancellation module 尙 includes a filter circuit coupled to the reflected signal and a sample and hold circuit coupled to the filter circuit. The filter circuit includes a filter and a switch coupled to the filter. 12 201244358 The above step S2尙 includes disabling the filter circuit and including disabling the switch. The above step S3 includes the enabling of the filter circuit and the enabling of the switch. Although the invention and its advantages have been described in detail, it is understood that modifications, substitutions and substitutions may be made without departing from the scope and spirit of the invention as defined by the following claims. That is, the discussion covered by this invention is intended to be a basic description. It should be understood that the specific discussion does not explicitly describe all possible embodiments; numerous alternatives are implicit. The general nature of the invention may not be fully described herein, and it may not be explicitly stated how each feature or component is indeed a more versatile function or representative of various alternative or equivalent components. Again, these are implicit in the documents disclosed here. The description or terminology of the invention is not intended to limit the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a circuit diagram of a conventional primary side control power converter. FIG. 2 shows the waveform of the signal Vs of the primary side control power converter of the conventional FIG. Figure 3 shows another circuit diagram of a conventional primary side control power converter. Fig. 4 is a view showing the waveform of the distortion of the signal Vs during the off period of the switching signal Sw by the primary side control power converter of Fig. 3. Figure 5 is a block diagram of a controller for a primary side control power converter in accordance with a preferred embodiment of the present invention. Figure 2 is a voltage detection circuit in accordance with a preferred embodiment of the present invention. Figure 7 shows the waveforms of the switching signal Sw, the signal Vs, the blanking signal SBUC, the sampling signal SMP and the holding signal SHD. 13 201244358 Figure 8 shows a method of sampling a reflected voltage of a transformer of a power converter in accordance with the present invention. [Main component symbol description] 10 Transformer 20 Power transistor 30 Current sense resistor 40 Rectifier 45 Capacitor 51 Resistor 57 Resistor 58 Capacitor 60 Rectifier 65 Output capacitor 70 Load 100 Switching controller 150 Voltage detection circuit 171 First switch 172 Capacitor 175 Buffer Amplifier 176 Capacitor 179 Third Switch 181 Second Switch 14 201244358 182 Resistor 200 Current Detecting Circuit 250 Integrator 350 Error Amplifier 370 Error Amplifier 400 Low Pass Filter 450 Low Pass Filter 500 Pulse Width Modulation Circuit