201239858 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種產生液晶顯示器的削角電壓的削角電路及 其方法，尤指一種可在任思時間點產生液晶顯示器的削角電壓的削 角電辂及其方法。 【先前技術】 請參照第1圖’第1圖係為先前技術說明應用在GIP(gate in pand) 面板的削角電路100的示意圖。如第1圖所示，削角電路1〇〇包含 一位準調整器102與一削角單元104，其中削角電路1〇〇可内建在 一電源1C内部。位準調整器1〇2調整一輸入電壓的準位，以 產生一第一電壓LS。削角單元1〇4係耦接於位準調整器1〇2，用以 接收第一電壓LS ’並根據第一電壓LS產生一削角電壓LS 〇，其 中削角電壓LS一Ο即為GIP面板所使用的薄膜電晶體的閘極電壓。 請參照第2圖，第2圖係為說明輸入電壓LS_I、第一電壓LS及削 角電壓LS一Ο的波形的示意圖，其中輸入電壓LS—I的準位係從〇至 尚電壓VDD。如第2圖所示，削角電壓LS—Ο的放電時間是由一外 接電容C決定，且一般說來，削角電壓LS_0係削到電壓VDDA。 而削角電壓LS_〇的放電斜率是由一外接電阻R決定，其中VEEG 係為閘極低電壓以及VGH係為閘極高電壓。因此，先前技術係對 .薄骐電晶體的閘極電壓作削角，減輕GIP面板的閃爍現象及改善面 板均勻度’以提兩晝面品質。但先前技術的缺點是在第一電壓Ls 201239858 >的負緣才會開始做削角的動作，綠在第一電Mls的任意時間點 做削角（例如在第一電塵LS正緣做削角）。 【發明内容】 本私明的-實施例提供一種產生液晶顯示器的削角電壓的削角 電路。該削角電路包含一位準調整器、一相位調整器、一相位比較 器及了削角器。該位準調整器係用以調整一輸入電壓的準位，以產 生第-電壓，該相位調整器係叙接於該位準調整器，用以接收該 第-電壓，並根據-相位調整訊號，調整該第一電壓的相位，以產 生第-電壓，该相位比較器係輕接於該位準調整器與該相位調整 器L用以接收該第-電壓與該第二電壓，其中該相位比較器係用以 比較《亥第電壓㈣第二電壓，以產生—比較結果丨該則器係搞 接於》亥位準s周整器、该相位調整器與該相位比較器，用以根據該第 —電壓、該第二電壓與該比較結果，輸出該削角電壓。 本發明的另一實施例提供一種產生液晶顯示器的削角電壓的方 法。該方法包含調整一輸入電壓的準位，以產生一第一電壓；根據 —相位調整訊號，調整該第一電壓的相位，以產生一第二電壓；比 車又4第一電壓與該第二電壓，以產生一比較結果；根據該第一電壓、 。亥第一電壓與該比較結果，輸出該削角電塵。 本發明提供一種產生液晶顯示器的削角電壓的削角電路及其方 法。S玄削角電路及其方法係利用一位準調整器調整一輸入電壓的準 201239858 -位’以產生一第—電壓’利用一相位調整器調整該輸入電壓的相位， 以產生-第二電壓，再利用—相位味器比較該第—電壓的相位與 該第二電壓的相位，以產生一比較結果。一削角器的第一削角單元 與第二削角單元即可根據該第一電壓、該第二電壓與該比較結果， 輸出-削角電壓。因此，本發明可在料時_上產生的動作， 並可減輕一 GIP面板的閃爍現象及改善該GIP面板均勻度，以提高 晝面品質。 【實施方式】 5月參照第3圖，第3圖係為本發明的一實施例說明一種產生液 晶顯不器賴角電壓賴角電路·的示意圖。則電路3⑽包含 包含一位準調整器3〇2、一相位調整器3〇4、一相位比較器3〇6及— 削角器308。位準調整器302係用以調整一輸入電壓Lsj的準位， 以產生一第一電壓LS ;相位調整器304係耦接於位準調整器3〇2， 用以接收第-電壓LS，並根據-相位調整訊號pRj，調整第—電 壓LS的相位，以產生一第二電壓ps ;相位比較器3〇6軸接於位 準調整器302與相位調整器304,用以接收第一電壓LS與第二電壓 Ps，其中相位比較器306係用以比較第一電壓LS的相位與第二電 壓PS的相位’以產生一比較結果PC ;削角器皿係耦接於位準調 整器302、相位調整器3〇4與相位比較器3〇6，用以根據第一電壓° LS、第一電壓ps與比較結果pc ,輸出—削角電壓〇。 削角器308包含一第一傳輸閘3082、一第一削角單元3〇84、一 201239858 第二削角單元3086、一第二傳輸閘邏及一第三傳輸問_。第 -傳輸閘3082係麵接於相位調整器3〇4與相位比較器3〇6 ;第—削 角單几3084係耦接於位準調整器3〇2與第一傳輸閘3〇82 ;第二削 角單元3086係耦接於位準調整器3〇2與第一傳輸閘3〇82 ;第二傳 輸閘3088係耗接於第一削角單元3〇84、第二削角單元3〇86及相位 比較為306,第二傳輸閘3090係耦接於第一削角單元3〇84、第二削 角單元？086及相位比較器306。 睛參照)第4 ®，第4圖係為說明削角器、3〇8的示意圖。第一削 角單元3084具有一第一端，耦接於位準調整器3〇2，用以接收第一 電壓LS，一第二端，耦接於第—傳輸閘3〇82，一第三端，耦接於 位準調整ϋ 3G2，用以接收第-賴LS，—細端，_於第二傳 輪閘3088，一第五端’用以接收—閘極低電壓v^gG，及一第六端， 麵接於第三傳輸閘3G9G。第-削解元3G84包含—第—N型金氧 半電晶體3_2、-第二N型金氧半電晶體通44、—第一 p型金 氧半電晶體3G846、-第三N型金氧半電晶體3霞及—第二p型 金氧半電晶體30850。第-N型金氧半電晶體遍42具有一第一端， 麵接於第-削角單元3084的第-端，一第二端，搞接於第一 _ 金氧半電晶體3G842的第-端，及—第三端；第二N型金氧半電晶 體30844具有-第-端，搞接於第_N型金氧半電晶體观犯的第 ―立而，一第二端’耦接於第一削角單元3〇84的第二端，及一第三端， 麵接於第-㈣單元3_的第六dP型金氧半電晶體期而你 具有一第一端，耦接於第二N型金氧半電晶體3〇844的第三端，一 8 201239858 第二端，耦接於第二N型金氧半電晶體30844的第二端，及一第三 端；第三N型金氧半電晶體30848具有一第一端，耗接於第一 p型 金氧半電晶體30846的第三端，一第二端，耦接於第—削角單元3〇84 的第一々而，及一第二端，執接於第一削角單元.3084的第四端；第二 P型金氧半電晶體3G850具有-第—端，雛於型金氧半電 晶體30844的第三端，一第二端，轉接於第一削角單元的第三 立而，及一第二端，耗接於第一削角單元3〇84的第五端。 如第4圖所示，第二削角單元駡具有一第一端，搞接於位準 調整器302，用以接收第—電壓LS，―第二端’麵接於第三傳輸問 3090，一第三端，耦接於位準調整器3〇2，用以接收第一電壓， 一第四端，減於第-傳輸閘遞’―第五端，雛於第二傳輸開 3088，及一第六端，用以接收閘極低電壓VEEG。第二削角單元如％ 包含-第四N型金氧半電晶體3觀、—第三？型金氧半電晶體 3〇864、一第四P型金氧半電晶體罵66、-第五N型金氧半電晶體 3_及一第五1>型金氧半電晶體30870。第㈣型金氧半電晶體 30862具有一第一端，柄接於第二削角單元3086的第1，一第二 端，搞接於第二削角單元遍的第一端，及一第三端，她於第二 削角單it 3086的第二端；第三p型金氧半電晶體3_4具有一第— 端’耗接於第四N型金氧半電晶體3〇862的第三端，一第二端，輕 接於第二削角單元3_的第三端，及一第三端；第四p型金氧半電 曰曰體0866 ”有第一端，麵接於第四N型金氧半電晶體駕62的 第二端，一第二端，耦接於第二削角單元3086的第三端，及一第三 201239858 端；第五N型金氧半電晶體30868具有一第一端，耦接於第三？型 金氧半電晶體30864的第三端，一第二端，耦接於第二削角單元3〇86 的第四&，及一第二端，搞接於第二削角單元3086的第五端；第五 p型金氧半電晶體30870具有一第一端，耦接於第四p型金氧半電 晶體3_6的第三端，-第二端，搞接於第二削角單元遍的第四 端，及一第三端，耦接於第二削角單元3〇86的第六端。 如第4圖所示，第一傳輸閘3〇82具有一第一端，爐於相位調 整器304’用以接收第二電壓ps，一第二端，幅於相位比較器遍， 用以接收比較結果PC，一第三端，叙接於第一削角單元麵的第 二端，及一第四端，耦接於第二削角單元3〇86的第四端，其中第一 專輪間3〇82係、用以根據比較結果pc，傳送第二電壓ps至第一削 角單元3084或第二削角單元3_。第—傳輸閘观2包含一第六n201239858 VI. Description of the Invention: [Technical Field] The present invention relates to a chamfering circuit for generating a chamfering voltage of a liquid crystal display and a method thereof, and more particularly to a chamfering voltage for generating a liquid crystal display at any time point. Angled electric cymbal and its method. [Prior Art] Referring to Fig. 1 'Fig. 1 is a schematic view showing a chamfering circuit 100 applied to a GIP (gate in pand) panel in the prior art. As shown in Fig. 1, the chamfering circuit 1A includes a quasi-regulator 102 and a chamfering unit 104, wherein the chamfering circuit 1A can be built in a power supply 1C. The level adjuster 1〇2 adjusts the level of an input voltage to generate a first voltage LS. The chamfering unit 1〇4 is coupled to the level adjuster 1〇2 for receiving the first voltage LS′ and generating a chamfering voltage LS 根据 according to the first voltage LS, wherein the chamfering voltage LS is GIP The gate voltage of the thin film transistor used in the panel. Referring to Fig. 2, the second figure is a schematic diagram illustrating the waveforms of the input voltage LS_I, the first voltage LS, and the chamfer voltage LS, wherein the level of the input voltage LS_I is from 〇 to the voltage VDD. As shown in Fig. 2, the discharge time of the chamfering voltage LS_Ο is determined by an external capacitor C, and in general, the chamfering voltage LS_0 is cut to the voltage VDDA. The discharge slope of the chamfering voltage LS_〇 is determined by an external resistor R, where VEEG is the gate low voltage and VGH is the gate high voltage. Therefore, the prior art has performed a chamfering of the gate voltage of the thin germanium transistor, reducing the flickering phenomenon of the GIP panel and improving the uniformity of the panel to improve the quality of the two sides. However, the disadvantage of the prior art is that the negative edge of the first voltage Ls 201239858 > will start the chamfering action, and the green is chamfered at any time point of the first electric Mls (for example, in the first electric dust LS positive edge) Chamfering). SUMMARY OF THE INVENTION The present invention provides a chamfering circuit for generating a chamfer voltage of a liquid crystal display. The chamfering circuit includes a quasi-regulator, a phase adjuster, a phase comparator and a chamfer. The level adjuster is configured to adjust a level of an input voltage to generate a first voltage, the phase adjuster is connected to the level adjuster for receiving the first voltage, and adjusting the signal according to the phase Adjusting a phase of the first voltage to generate a first voltage, the phase comparator is lightly connected to the level adjuster and the phase adjuster L for receiving the first voltage and the second voltage, wherein the phase The comparator is configured to compare the second voltage of the (Hi) voltage (four) to generate a comparison result, and the device is connected to the squaring device, the phase adjuster and the phase comparator for The first voltage, the second voltage, and the comparison result output the chamfer voltage. Another embodiment of the present invention provides a method of producing a chamfer voltage of a liquid crystal display. The method includes adjusting a level of an input voltage to generate a first voltage; adjusting a phase of the first voltage according to a phase adjustment signal to generate a second voltage; and comparing the first voltage to the second Voltage to produce a comparison result; according to the first voltage, . The first voltage of the sea and the comparison result output the chamfered electric dust. The present invention provides a chamfering circuit for generating a chamfer voltage of a liquid crystal display and a method therefor. The S-sharp angle circuit and the method thereof use a quasi-regulator to adjust the quasi-201239858-bit ' of an input voltage to generate a first-voltage'. The phase adjuster adjusts the phase of the input voltage to generate a second voltage. And recycling the phase odorizer to compare the phase of the first voltage with the phase of the second voltage to produce a comparison result. The first chamfering unit and the second chamfering unit of a chamfer may output a chamfering voltage according to the first voltage, the second voltage, and the comparison result. Therefore, the present invention can perform the action on the material time, and can reduce the flicker phenomenon of a GIP panel and improve the uniformity of the GIP panel to improve the quality of the kneading surface. [Embodiment] Fig. 3 is referred to in Fig. 3, and Fig. 3 is a schematic view showing a circuit for generating a liquid crystal display. Circuit 3 (10) includes a quasi-regulator 3 〇 2, a phase adjuster 3 〇 4, a phase comparator 3 〇 6 and a chamfer 308. The level adjuster 302 is configured to adjust the level of an input voltage Lsj to generate a first voltage LS; the phase adjuster 304 is coupled to the level adjuster 3〇2 for receiving the first voltage LS, and Adjusting the phase of the first voltage LS according to the phase adjustment signal pRj to generate a second voltage ps; the phase comparator 3〇6 is coupled to the level adjuster 302 and the phase adjuster 304 for receiving the first voltage LS And a second voltage Ps, wherein the phase comparator 306 is configured to compare the phase of the first voltage LS with the phase of the second voltage PS to generate a comparison result PC; the chamfering vessel is coupled to the level adjuster 302, the phase The regulator 3〇4 and the phase comparator 3〇6 are configured to output a-cut angle voltage 根据 according to the first voltage LS, the first voltage ps and the comparison result pc. The chamfer 308 includes a first transmission gate 3082, a first chamfering unit 3〇84, a 201239858 second chamfering unit 3086, a second transmission gate logic and a third transmission. The first transmission gate 3082 is connected to the phase adjuster 3〇4 and the phase comparator 3〇6; the first chamfering unit 3084 is coupled to the level adjuster 3〇2 and the first transmission gate 3〇82; The second chamfering unit 3086 is coupled to the level adjusting unit 3〇2 and the first transmission gate 3〇82; the second transmission gate 3088 is coupled to the first chamfering unit 3〇84 and the second chamfering unit 3 〇86 and the phase comparison is 306, and the second transmission gate 3090 is coupled to the first chamfering unit 3〇84 and the second chamfering unit. 086 and phase comparator 306. Eye reference) 4th, 4th is a schematic diagram illustrating the chamfering device, 3〇8. The first chamfering unit 3084 has a first end coupled to the level adjuster 3〇2 for receiving the first voltage LS, and a second end coupled to the first transmission gate 3〇82, a third The end is coupled to the level adjustment ϋ 3G2 for receiving the first LS, the thin end, the _ to the second transfer gate 3088, and the fifth end 'for receiving the gate low voltage v^gG, and A sixth end is connected to the third transmission gate 3G9G. The first-cutting element 3G84 comprises a -N-type oxynitride transistor 3_2, a second N-type MOS transistor 70, a first p-type MOS transistor 3G846, a third N-type gold Oxygen semi-transistor 3 Xia and - second p-type gold oxide semi-transistor 30850. The first-N-type MOS transistor 42 has a first end, which is connected to the first end of the first-corner unit 3084, and a second end is connected to the first _ gold-oxygen semiconductor 3G842. - the end, and - the third end; the second N-type oxy-halide transistor 30844 has a - first end, which is connected to the first _N-type oxy-halide transistor, and a second end The second end of the first chamfering unit 3〇84 and the third end are connected to the sixth dP type MOS transistor of the fourth (4) unit 3_ and have a first end. The second end of the second N-type MOS transistor 3844 is coupled to the second end of the second N-type MOS transistor 3844, and the third end is coupled to the second end of the second N-type MOS transistor 30844. The third N-type MOS transistor 30848 has a first end, which is connected to the third end of the first p-type MOS transistor 30846, and a second end coupled to the first-corner unit 3〇 The first end of 84, and a second end, is connected to the fourth end of the first chamfering unit .3084; the second P-type MOS micro-transistor 3G850 has a --end end, which is shaped by the type of gold oxide half. The third end of the transistor 30844, a second end, is switched to the The third vertical cutting unit and angle, and a second terminal, the consumption of the fifth to the first end of the cutting angle of the unit 3〇84. As shown in FIG. 4, the second chamfering unit 骂 has a first end, which is connected to the level adjuster 302 for receiving the first voltage LS, and the second end is connected to the third transmission 3090. a third end, coupled to the level adjuster 3〇2, for receiving the first voltage, a fourth end, minus the first-transmission gate 'the fifth end, the second transmission opening 3088, and a sixth end for receiving the gate low voltage VEEG. The second chamfering unit such as % contains - the fourth N-type MOS transistor 3, - the third? A type of gold oxide semi-transistor 3 〇 864, a fourth P-type MOS transistor 骂 66, a fifth N-type MOS transistor 3_ and a fifth 1> type MOS transistor 30870. The fourth type MOS transistor 30862 has a first end, the handle is connected to the first and second ends of the second chamfering unit 3086, and is connected to the first end of the second chamfering unit, and a first end At the three ends, she is at the second end of the second chamfered single it 3086; the third p-type MOS semi-transistor 3_4 has a first end consuming the fourth N-type MOS transistor 3〇862 a third end, a second end, lightly connected to the third end of the second chamfering unit 3_, and a third end; the fourth p-type gold-oxygen semi-electric body 0866" has a first end, the surface is connected to a second end of the fourth N-type MOS transistor 27, a second end coupled to the third end of the second chamfering unit 3086, and a third 201239858 end; the fifth N-type oxy-oxygen semi-electric The crystal 30868 has a first end coupled to the third end of the third type MOS transistor 30864, a second end coupled to the fourth & amp of the second chamfering unit 3 〇 86, and a The second end is connected to the fifth end of the second chamfering unit 3086. The fifth p-type MOS transistor 30870 has a first end coupled to the third of the fourth p-type MOS transistor 3_6. End, - second end, engage in the second chamfer The fourth end of the unit and the third end are coupled to the sixth end of the second chamfering unit 3〇86. As shown in Fig. 4, the first transmission gate 3〇82 has a first end, the furnace The phase adjuster 304' is configured to receive the second voltage ps, a second end, the phase comparator is used to receive the comparison result PC, and the third end is connected to the second surface of the first chamfering unit surface. And a fourth end coupled to the fourth end of the second chamfering unit 3〇86, wherein the first inter-wheel is 3〇82, for transmitting the second voltage ps to the first according to the comparison result pc The chamfering unit 3084 or the second chamfering unit 3_. The first transmission gate 2 includes a sixth n
型金氧半電晶體3G822及一第六p型金氧半電晶體3，。第六N 型金氧半電晶體3G822具有-第-端，祕於第—傳輸閘3〇82的第 一端，一第二端，耦接於第一傳輸閘3082的第二端，及一第三端， 搞接於第-傳輪閘麗的第三端；第六p型金氧半電晶體3〇824 具有-第-端’接於第—傳輸閘3Q82的第—端，—第二端，減 於第—傳輸閘3082的第二端，及-第三端，麵接於第一傳輸閘3〇82 的第四端。 口。如第4圖所示’第二傳輸閘纖具有一第一端，墟於第一削 角單元3084的第四端，一第二端，耦接於一外接電阻r，一第三端， 10 201239858 轉接於相位比較器306 ’用以接收比較結果pc，及一第四端’辆接 於该第二削角單兀的第五端’其中第二傳輸閘3〇88係用以根據比較 結果PC’將第-削角單元聰的第六端的電位或第二削角單元 3086的第二端的電位透過外接電阻R放電至—電壓vdda。第二傳 輪間3Q88包含-第七N型金氧半電晶體3()882及—第七p型金氧 半電晶體30884。第七N型金氧半電晶體3〇882具有一第—端，搞 接於第二傳輸閘3088的第一端，一第二端，雛於第二傳輪問薦 的第三端，及一第三端，耦接於第二傳輸閘3088的第二端；第七p 型金氧半電晶體3圓具有—第—端姻於第二傳輸閘雇的第 四端’-第二端，祕於第二傳輸閘·8的第三端，及—第三端， 耗接於第二傳輸閘3088的第二端。 '如第4圖所示’第三傳輸閘3090具有-第一端，雛於第二削 角單το 3086的第一端’一第二端，麵接於相位比較器，用以接 枚比較結果PC，-第三端，轉接於第一削角單元雇的第六端， 及一第四端’肋輸出肖削壓LS—〇，其#三傳輸閘編係用 从根據比較結果PC，決定第一削角單元3_的第六端或第二削角 早元遍的第二端輸出削角電壓LSJ)。第三傳輸問謂包含一 第八P型金氧半電晶體3_2及—第型金氧半電晶體删4。 第八P型金氧半電晶體30902具有一第一端，耗接於第三傳輸閘 〇9〇的第-ir而’一第二端，搞接於第三傳輸閘侧的第二端，及 第二端’麵接於第二傳輸閘3Q9Q的第四端；第八^型金氧半電 晶體30904具有-第-端，耦接於第三傳輸問細的第三端，一第 201239858 二端，耦接於3090第三傳輸閘的第二端，及一第三端，耦接於第三 傳輸閘3090的第四端。 請參照第5A圖、第5B圖及第5c圖，第5A圖係為說明當第 一電壓LS的相位落後第二電壓PS時，削角電路300產生的削角電 壓LS一〇的示意圖，第5B圖及第5c圖係為分段說明當第一電壓 LS的相位落後第二電壓ps時，第—削角單元3〇84的動作的示意 圖。如第5A圖所示，當第一電壓ls落後第二電壓ps時間耵時， 比較結果pc係為-邏輯高電位，且削角電壓LS_〇根據第二電壓 ps的負緣開始放電，並於.第一電壓Ls的負緣結束放電，亦即可藉 由時間T1控制削角電壓LS—〇的放電時間(削角的時間）。因為比較 結果pc係為邏輯高電位，所以第六N型金氧半電晶體麗2、第 七N型金氧半電晶體邏2及第人N裂金氧半電日日日體删4開啟， 因此第肖ij角單元細4的第二端透過第一傳輸間細2接收第二電 堅ps第削角單元3〇84的第四端透過第二傳輪閘通8耗接於外 接電阻R及第-削角單元3〇84的第六端透過第三傳輸問_輸出 削角電壓LS—Ο。另外，削角親Ls_⑽放電斜率係由第—削角單 兀3084的寄生電谷與外接電阻尺所決定。但因為第一削角單元爾 的寄生電祕小，所以可n由外接電阻⑽糊肖電壓〇的放 電斜率。另外，在第冗圖中，閘極高電壓VGH以丫表示以及 問極低電壓vEEGr‘0”表示。如第4圖、第犯圖及第冗圖所 不’“在第5B圖的1區，第—電壓LS係為以及第二電壓㈣ 為1 ’所以第-N型金氧半電晶體3〇842關閉、第二N型金氧 12 201239858Type MOS semi-transistor 3G822 and a sixth p-type MOS semi-transistor 3,. The sixth N-type MOS transistor 3G822 has a first end, a first end of the first transmission gate 3〇82, a second end coupled to the second end of the first transmission gate 3082, and a first end The third end is connected to the third end of the first-passing wheel gate; the sixth p-type gold-oxygen semi-transistor 3〇824 has a -first end connected to the first end of the first transmission gate 3Q82, - The second end is reduced from the second end of the first transmission gate 3082, and the third end is connected to the fourth end of the first transmission gate 3〇82. mouth. As shown in FIG. 4, the second transmission brake fiber has a first end, which is connected to the fourth end of the first chamfering unit 3084, and a second end coupled to an external resistor r, a third end, 10 201239858 is transferred to the phase comparator 306' for receiving the comparison result pc, and a fourth end 'carriage is connected to the fifth end of the second chamfered unit', wherein the second transmission gate 3〇88 is used for comparison As a result, PC' discharges the potential of the sixth end of the first-corner unit Cong or the potential of the second end of the second chamfering unit 3086 to the voltage vdda through the external resistor R. The second inter-wheel 3Q88 includes a seventh N-type MOS transistor 3 () 882 and a seventh p-type MOS semi-transistor 30884. The seventh N-type MOS transistor 3 882 has a first end, which is connected to the first end of the second transmission gate 3088, and a second end, which is nested at the third end of the second transmission, and a third end coupled to the second end of the second transfer gate 3088; the seventh p-type MOS transistor 3 circle has a first end - the fourth end of the second transfer gate employed - the second end The third end of the second transmission gate 8 and the third end are connected to the second end of the second transmission gate 3088. 'As shown in Fig. 4', the third transmission gate 3090 has a first end, which is a second end of the second chamfered single το 3086, and is connected to the phase comparator for comparison. The result PC, the third end, is transferred to the sixth end of the first chamfering unit, and the fourth end of the 'rib output shawl pressure LS-〇, the #三 transmission gate is used according to the comparison result PC Determining the sixth end of the first chamfering unit 3_ or the second chamfering output of the second end of the first chamfering unit 3_. The third transmission question includes an eighth P-type MOS transistor 3_2 and a -type MOS transistor. The eighth P-type MOS transistor 30902 has a first end, which is connected to the first-ir and the second end of the third transmission gate 9〇, and is connected to the second end of the third transmission gate side. And the second end is connected to the fourth end of the second transmission gate 3Q9Q; the eighth type of gold oxide semi-transistor 30904 has a -th-end, coupled to the third end of the third transmission, a 201239858 The second end is coupled to the second end of the third transmission gate of the 3090, and the third end is coupled to the fourth end of the third transmission gate 3090. Please refer to FIG. 5A, FIG. 5B and FIG. 5c. FIG. 5A is a schematic diagram illustrating the chamfering voltage LS generated by the chamfering circuit 300 when the phase of the first voltage LS is behind the second voltage PS. 5B and 5c are diagrams illustrating the operation of the first chamfering unit 3〇84 when the phase of the first voltage LS is behind the second voltage ps. As shown in FIG. 5A, when the first voltage ls falls behind the second voltage ps time ,, the comparison result pc is a logic high potential, and the chamfer voltage LS_〇 starts to discharge according to the negative edge of the second voltage ps, and The discharge is terminated at the negative edge of the first voltage Ls, and the discharge time (the time of the chamfering) of the chamfering voltage LS_〇 can be controlled by the time T1. Because the comparison result pc is a logic high potential, the sixth N-type MOS transistor 2, the seventh N-type MOS transistor 2 and the first N-cracked gold-oxygen semi-electric day and day are deleted. Therefore, the second end of the fourth XI corner unit thin 4 receives the second electric pole through the first transmission room 2; the fourth end of the chamfering unit 3 〇 84 is circulated to the external resistor through the second transmission gate 8 The sixth end of the R and the first chamfering unit 3〇84 is transmitted through the third transmission _ output chamfering voltage LS_Ο. In addition, the slope of the chamfering pro-Ls_(10) is determined by the parasitic electric valley of the first chamfering unit 3084 and the external resistance. However, since the parasitic capacitance of the first chamfering unit is small, the discharge slope of the external resistor (10) can be used. In addition, in the redundancy diagram, the gate high voltage VGH is represented by 以及 and the extremely low voltage vEEGr '0" is represented. As shown in Fig. 4, the first map, and the second redundant graph, the region 1 in Fig. 5B , the first voltage LS is and the second voltage (four) is 1 ', so the first-N type MOS transistor 3 842 is closed, and the second N-type gold oxide 12 201239858
•半電晶體30844開啟、第一 P型金氧半電晶體30840關閉、第三N 型金氧半電晶體30848關閉及第二p型金氧半電晶體3〇85〇開啟。 因為，第一 P型金氧半電晶體30850開啟，所以削角電壓lS_〇經 由第一削角單元3〇84的第五端被下拉至“〇”。在第5B圖的n區， 第一電壓LS係為“Γ以及第二電壓PS係為“丨”，所以第 金氧半電晶體30842開啟、第二N型金氧半電晶體3〇844開啟、第 P型金氧半電晶體30846關閉、第三N型金氧半電晶體30848開 啟及第二P型金氧半電晶體30850關閉。因為，第一 N型金氧半電 晶體30842開啟和第二N型金氧半電晶體3〇844開啟，所以削角電• The half transistor 30844 is turned on, the first P-type MOS transistor 30840 is turned off, the third N-type MOS transistor 30848 is turned off, and the second p-type MOS transistor is turned on. Since the first P-type MOS transistor 30850 is turned on, the chamfering voltage lS_〇 is pulled down to "〇" by the fifth end of the first chamfering unit 3 〇 84. In the n region of FIG. 5B, the first voltage LS is “Γ and the second voltage PS is “丨”, so the first oxygen half transistor 30842 is turned on, and the second N-type metal oxide semiconductor transistor 3〇844 is turned on. The P-type MOS transistor 30846 is turned off, the third N-type MOS transistor 30848 is turned on, and the second P-type MOS transistor 30850 is turned off because the first N-type MOS transistor 30842 is turned on and The second N-type MOS transistor 3〇844 is turned on, so the angle is reduced.
壓LS—Ο經由第一削角單元3〇84的第一端被上拉至“丨”。在第5B 圖的III區，第一電壓LS係為“1”以及第二電壓ps係為‘‘〇，’ ， 所以第N型金氧半電晶體30842開啟、第二n型金氧半電晶體 30844關閉、第一P型金氧半電晶體3〇846開啟、第三n型金氧半 電晶體30848開啟及第二p型金氧半電晶體3〇85〇關閉。因為，第 - P.型金氧半電晶體3祕開啟及第三N型金氧半電晶體3麵開 啟’所以削角電壓LS_〇經由第一削角單元3〇84的第四端透過第二 傳輸閘3〇88被外接電阻R放電至電麗VDDA。在第也圖的ιν區， 第-電壓LS係為“〇”以及第二電壓ps係為“〇，，，所以第一 N型 金氧半電晶體30842關閉、第二N型金氧半電晶體娜斗關閉、第 3L金氧半電曰曰體30846開啟、第三n型金氧半電晶體3〇848關 閉及第二1>型金氧半電晶體鄕5〇開啟。因為，第二？型金氧半電 晶體30850開啟，所以削角電壓LS_〇經由第-削角單元3084的第 五端被下拉至“〇，，。 13 201239858 一雪=ΓΑ圖、第6B圖及第6C圖，第6a圖係為說明當第 電壓LS的相位領先第二電壓ps時 壓LS Ο的干立Η⑯ ㈣電路3⑻產生的削角電 — ㈣，第6Β 第6C圖係為分段說明當第一電懕 LS的相位領先第二電壓PS時，第二削角單元娜的動作的示旁 圖。如第6A圖所不，當第一電壓LS領先第二電壓ps時間 比較結果PC係為—邏輯低電位，且削_ls—〇根據第一電壓 LS的負'賴始放電，並於第二糕ps的負緣結束放電，亦即 由時間T2控制削角電壓LS_〇的放電時_角的時間）。因為比車: 結果PC係為糖低電位，所以第六p型金氧半電晶體應、第七 P·氧半電晶體纖4及第/vp型金氧半電晶體麵開啟，因 此第=削角單元雇的第四端透過第—傳輸閘搬接收第二· PS、第二削角單元3_的第五端透過第二傳輸閘遞減於外接 電阻R及第二削角單元3086的第二端透過第三傳輸閘細輸出削 角電壓LS—0。另外，削角電壓LS—〇的放電斜率係由第二削角單元 3086的寄生電容與外接所決定。但_第二削鮮元雇 的寄生電容彳M、’所以可藉由外接控細肖^LS—〇的放 電斜率。另外，在第6C圖中，間極高電壓VGH以“Γ，表示以及 閘極低電壓VEEG以“〇’，表示。如第4圖、第6B圖及第6C圖所 不’在第6B圖的I’區，第一電壓Ls係為“j”以及第二電壓四係 為〇 ，所以第四N型金氧半電晶體3〇862開啟、第三p型金氧 半電晶體30864關閉、第四p型金氧半電晶體3〇866關閉、第五N 型金氧半電晶體30868關閉及第五p型金氧半電晶體3〇87〇開啟。 14 201239858 因為，第四N型金氧半電晶體30862開啟，所以削角電壓LS Ο經 由第二削角單元3086的第一端被上拉至“1”。在第6Β圖的π，區， 第一電壓LS係為“Γ以及第二電壓ps係為“Γ，所以第四ν型 金氧半電晶體30862開啟、第三ρ型金氧半電晶體30864關閉、第 四Ρ型金氧半電晶體30866關閉、第五Ν型金氧半電晶體30868開 啟及第五Ρ型金氧半電晶體30870關閉。因為，第四ν型金氧半電 晶體30862開啟，所以削角電壓LS一〇經由第二削角單元3086的第 一立而被上拉至1” 。在第6Β圖的III’區，第一電壓LS係為 以及第二電壓PS係為“1”，所以第金氧半電晶體3〇862關 閉、第二P型金氧半電晶體30864開啟、第四P型金氧半電晶體30866 開啟、第五N型金氧半電晶體30868開啟及第五p型金氧半電晶體 3087〇關閉。因為，第三p型金氧半電晶體咒％4開啟及第五 金氧半電晶體30868開啟，所以削角電壓LS_0經由第二削角單元 3086的第五端透過第二傳輸閘3〇88被外接電阻R放電至電壓 VDDA。在第6B圖的IV，區，第一電壓LS係為“〇”以及第二電壓 PS係為“〇” ，所以第四N型金氧半電晶體30862關閉、第三p型 金氧半電晶體30864開啟、第四p型金氧半電晶體3〇866開啟、第 iN型金氧半電晶體遍8關閉及第五p型金氧半電晶體開 啟。因為，第四P型金氧半電晶體30860開啟及第五P型金氧半電 晶體30870開啟’所以削角電壓LS—〇經由第二削角單元遍的第 六端被下拉至“〇，，。 凊參照第7圖’第7圖係為本發明的另一實施例說明一種產生 15 201239858 液晶顯示器的削角電壓的方法之流程圖。第7圖之方法係利用第3 圖的削角電路300說明，詳細步驟如下： 步驟700 : 開始； 步驟702 : s周整輪入電壓LS一I的準位，以產生第一電麼ls · 步驟704 : 根據相位調整訊號PR_I，調整第一電壓Ls的相位， 以產生第二電壓PS ; 步驟706 : 比較第一電壓LS的相位是否領先第二電壓ps的相 位’並產生比較結果PC ;如果是，進行步驟;如 果否，跳至步驟710 ; 步驟708 : 第二削角單元3086根據第一電壓LS、第二電壓1^與 比較結果PC，輸出削角電壓LS_0 ; 步驟710 : 第一削角單元3084根據第一電壓LS、第二電壓1>3與 比較結果PC，輸出削角電壓LS_0。 在步驟702中，位準調整器302調整輸入電壓LSJ的準位，以 產生第一電壓LS。在步驟704中，相位調整器3〇4根據相位調整訊 號PR—I，調整第—電壓LS的相位，以產生第三電壓ps。在步驟 7〇6中，相位比較為306比較第一電壓LS的相位與第二電壓ps的 相位’以產生比較結果PC。在步驟7〇8巾，當第一電愿LS的相位 領先第二電壓ps的相位時，第二削角單元3〇86根據比較結果pc 透過第一傳輸閘3082接收第二電壓PS。然後第二削角單元3〇86根 據第二電M PS、第-麵LS與比較結果pc，輸出㈣錢LS—〇。 16 201239858 在步驟7K)中’當第iaLS的相位落後第二雜ps的相位時， 第-削角單元3G84根據比較結果pc透過第—傳輸閘3Q82接收第 二電壓PS。然後第一削角單元3084根據第二電壓ps、第—電壓 LS與比較結果PC，輸出削角電壓ls 〇。 綜上所述’本發明所提供的產生液晶顯示器的削角電壓的削角 電路及其方法’係湘位準輕H調整輸人電壓的準位，以產生第 一電壓，利用相位調整器調整輸入電壓的相位，以產生第二電壓， 再利用相位比較器比較第一電壓的相位與第二電壓的相位，以產生 比較結果。削角器的第一削角單元與第二削角單元即可根據第一電 壓、第二電壓與比較結果，輸出削角電壓。因此，本發明可在任意 時間點上產生削角的動作，並可減輕GIP面板的閃爍現象及改善 GIP面板均勻度，以提高晝面品質。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 ，第1圖係為先前技術說明應用在GIP面板的削角電路系統的示意 圖。 第2圖係為說明輪入電壓、第一電壓及削角電壓的波形的示意圖。 第3圖係為本發明的一實施例說明一種產生液晶顯示器的削角電壓 的削角電路的示意圖。 17 201239858 第4圖係為說明削角器的示意圖。 第5A圖係為說明當第一電壓的相位落後第二電壓時，削角電路產 生的削角電壓的示意圖。 第5B圖及第5C圖係為分段說明當第一電壓的相位落後第二電壓 時，第一削角單元的動作的示意圖。 第6A圖係為說明當第一電壓的相位領先第二電壓時，削角電路產 生的削角電壓的示意圖。 第6B圖及第6C圖係為分段說明當第一電壓的相位領先第二電壓 時，第二削角單元的動作的示意圖。 第7圖係為本發明的另 壓的方法之流程圖 一實施例說明-種產生液晶顯示器的削角電 【主要元件符號說明】 l〇d' 300 削角電路 位準調整器 削角單元 相位調整器 相位比較器 削角器 第一傳輸閘 第一削角單元 第二削角單元 第二傳輸閘 102 > 302 104 304 306 308 3082 3084 3086 3088 18 201239858 3090 第三傳輸閘 30822 第六N型金氧半電晶體 30824 第六P型金氧半電晶體 30842 第一N型金氧半電晶體 30844 第二N型金氧半電晶體 30846 第一 P型金氧半電晶體 30848 第三N型金氧半電晶體 30850 第二P型金氧半電晶體 30862 第四N型金氧半電晶體 30864 第三P型金氧半電晶體 30866 第四P型金氧半電晶體 30868 第五N型金氧半電晶體 30870 第五P型金氧半電晶體 30882 第七N型金氧半電晶體 30884 第七P型金氧半電晶體 30902 第八P型金氧半電晶體 30904 第八N型金氧半電晶體 C 外接電容 LS 第一電壓 LSI 輸入電壓 LS_0 削角電壓 PC 比較結果 PR I 相位調整訊號 19 201239858 PS 第二電壓 R 外接電阻 ΤΙ ' T2 時間 VDD 高電壓 VEEG 閘極低電壓 VGH 閘極高電壓 VDDA 電壓 700 至 710 步驟 20The pressure LS-Ο is pulled up to "丨" via the first end of the first chamfering unit 3〇84. In the III region of FIG. 5B, the first voltage LS is "1" and the second voltage ps is "'〇,", so the N-type MOS transistor 30842 is turned on, and the second n-type MOS is half-electric. The crystal 30844 is turned off, the first P-type MOS transistor 3 〇 846 is turned on, the third n-type MOS transistor 30848 is turned on, and the second p-type MOS transistor 3 〇 85 〇 is turned off. Because the first P-type MOS transistor 3 is turned on and the third N-type MOS transistor is turned on, the chamfering voltage LS_〇 is transmitted through the fourth end of the first chamfering unit 3〇84. The second transfer gate 3〇88 is discharged to the battery VDDA by the external resistor R. In the ιν region of the figure, the first voltage LS is "〇" and the second voltage ps is "〇,", so the first N-type MOS transistor 30842 is turned off, and the second N-type MOS is half-electric. The crystal hopper is closed, the 3L MOS semi-electric body 30846 is turned on, the third n-type MOS transistor 3 〇 848 is turned off, and the second 1 gt type MOS transistor 鄕 5 〇 is turned on. Because, the second The type MOS transistor 30850 is turned on, so the chamfering voltage LS_〇 is pulled down to the fifth end of the first-corner unit 3084 to "〇,. 13 201239858 A snow = map, 6B and 6C, Fig. 6a is a diagram illustrating the angle of cut generated by the dry Η 16 (four) circuit 3 (8) of the voltage LS 当 when the phase of the voltage LS leads the second voltage ps - (4), Fig. 6C Fig. 6C is a side view showing the action of the second chamfering unit Na when the phase of the first electric pole LS leads the second voltage PS. As shown in FIG. 6A, when the first voltage LS leads the second voltage ps, the comparison result PC is - logic low, and the cut_ls_〇 is discharged according to the negative '' of the first voltage LS, and is second. The negative edge of the cake ps ends the discharge, that is, the time at which the cornering voltage LS_〇 is discharged by the time T2. Because the car: The result is that the PC is low in sugar, so the sixth p-type MOS transistor, the seventh P-oxygen semi-crystalline fiber 4 and the /vp-type MOS semi-transistor face open, so the first = The fourth end of the chamfering unit is configured to receive the second PS through the first transmission gate, and the fifth end of the second chamfering unit 3_ is decremented by the second transmission gate to the external resistor R and the second chamfering unit 3086. The two ends output the chamfering voltage LS-0 through the third transmission gate. In addition, the discharge slope of the chamfering voltage LS_〇 is determined by the parasitic capacitance of the second chamfering unit 3086 and the external connection. However, the parasitic capacitance 彳M,' employed by the second sharp-cut element can be controlled by externally controlling the discharge slope of the LS-〇. Further, in Fig. 6C, the inter-pole high voltage VGH is expressed by "Γ" and the gate low voltage VEEG by "〇". As shown in Fig. 4, Fig. 6B, and Fig. 6C, in the I' region of Fig. 6B, the first voltage Ls is "j" and the second voltage is 〇, so the fourth N-type oxy-half The transistor 3〇862 is turned on, the third p-type MOS transistor 30864 is turned off, the fourth p-type MOS transistor 3〇866 is turned off, the fifth N-type MOS transistor 30868 is turned off, and the fifth p-type gold is turned off. The oxygen semi-transistor 3〇87〇 is turned on. 14 201239858 Because the fourth N-type MOS transistor 30862 is turned on, the chamfering voltage LS 上 is pulled up to "1" by the first end of the second chamfering unit 3086. In the π, region of the sixth diagram, the first voltage LS is "Γ and the second voltage ps is "Γ, so the fourth ν-type MOS transistor 30862 is turned on, and the third ρ-type MOS transistor 30864 is turned on. The turn-off, fourth-type MOS transistor 30866 is turned off, the fifth-type MOS transistor 30868 is turned on, and the fifth-type MOS transistor 30870 is turned off. Because the fourth ν-type MOS transistor 30862 is turned on, the chamfering voltage LS is pulled up to 1" via the first standing of the second chamfering unit 3086. In the III' area of the sixth drawing, A voltage LS is and the second voltage PS is "1", so the gold oxide half transistor 3 862 is closed, the second P-type MOS transistor 30864 is turned on, and the fourth P-type MOS transistor is 30866. Open, the fifth N-type MOS transistor 30868 is turned on and the fifth p-type MOS transistor 3087 〇 is turned off. Because, the third p-type MOS transistor is opened and the metal oxide half transistor 30868 Turning on, the chamfering voltage LS_0 is discharged to the voltage VDDA through the second transmission gate 3〇88 through the second transmission gate 3〇88 via the fifth terminal of the second chamfering unit 3086. In the IV, region of FIG. 6B, the first voltage LS is "〇" and the second voltage PS are "〇", so the fourth N-type MOS transistor 30862 is turned off, the third p-type MOS transistor 30864 is turned on, and the fourth p-type MOS transistor is turned on. 866 is turned on, the i-th type MOS transistor is turned off 8 and the fifth p-type MOS transistor is turned on. Because the fourth P-type oxy-half is half 30860 Crystal opening and fifth P-type metal-oxide-semiconductor transistor 30870 is turned on 'so chamfered square sixth LS-voltage terminal of the second pass unit is chamfered down to the "square ,, via. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 7 is a flow chart showing a method of generating a chamfering voltage of a liquid crystal display of 201239858 according to another embodiment of the present invention. The method of FIG. 7 is illustrated by the chamfering circuit 300 of FIG. 3, and the detailed steps are as follows: Step 700: Start; Step 702: s Weekly rounding voltage LS-I level to generate the first electric ls Step 704: Adjust the phase of the first voltage Ls according to the phase adjustment signal PR_I to generate the second voltage PS. Step 706: Compare whether the phase of the first voltage LS leads the phase of the second voltage ps and generate a comparison result PC; If yes, go to step 710; Step 708: The second chamfering unit 3086 outputs the chamfering voltage LS_0 according to the first voltage LS, the second voltage 1^ and the comparison result PC; Step 710: First shaving The corner unit 3084 outputs the chamfer voltage LS_0 based on the first voltage LS, the second voltage 1 > 3, and the comparison result PC. In step 702, the level adjuster 302 adjusts the level of the input voltage LSJ to generate a first voltage LS. In step 704, the phase adjuster 3〇4 adjusts the phase of the first voltage LS according to the phase adjustment signal PR_I to generate a third voltage ps. In step 7〇6, the phase comparison 306 compares the phase of the first voltage LS with the phase ' of the second voltage ps to produce a comparison result PC. In step 7〇8, when the phase of the first power LS leads the phase of the second voltage ps, the second chamfering unit 3〇86 receives the second voltage PS through the first transmission gate 3082 according to the comparison result pc. Then, the second chamfering unit 3〇86 outputs (4) money LS_〇 according to the second electric M PS , the first-plane LS and the comparison result pc. 16 201239858 In step 7K), when the phase of the iaLS is behind the phase of the second ps, the first-corner unit 3G84 receives the second voltage PS through the first-transmission gate 3Q82 according to the comparison result pc. Then, the first chamfering unit 3084 outputs the chamfering voltage ls 〇 according to the second voltage ps, the first voltage LS, and the comparison result PC. In summary, the present invention provides a chamfering circuit for generating a chamfering voltage of a liquid crystal display and a method thereof, and adjusts the level of the input voltage to generate a first voltage, which is adjusted by a phase adjuster. The phase of the voltage is input to generate a second voltage, and the phase comparator is used to compare the phase of the first voltage with the phase of the second voltage to produce a comparison result. The first chamfering unit and the second chamfering unit of the chamfering device can output the chamfering voltage according to the first voltage, the second voltage and the comparison result. Therefore, the present invention can produce chamfering action at any time point, and can reduce the flickering phenomenon of the GIP panel and improve the uniformity of the GIP panel to improve the kneading quality. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a chamfering circuit system applied to a GIP panel in the prior art. Fig. 2 is a schematic view showing the waveforms of the wheeling voltage, the first voltage, and the chamfering voltage. Fig. 3 is a schematic view showing a chamfering circuit for generating a chamfering voltage of a liquid crystal display according to an embodiment of the present invention. 17 201239858 Figure 4 is a schematic diagram illustrating the chamfer. Fig. 5A is a view showing the chamfering voltage generated by the chamfering circuit when the phase of the first voltage is behind the second voltage. 5B and 5C are diagrams illustrating the operation of the first chamfering unit when the phase of the first voltage is behind the second voltage. Fig. 6A is a diagram showing the chamfering voltage generated by the chamfering circuit when the phase of the first voltage leads the second voltage. 6B and 6C are diagrams illustrating the operation of the second chamfering unit when the phase of the first voltage is ahead of the second voltage. Figure 7 is a flow chart of a method for pressing another embodiment of the present invention. - Description of the method for producing a liquid crystal display. [Main component symbol description] l〇d' 300 chamfering circuit level adjuster chamfering unit phase Regulator phase comparator chamfer first transmission gate first chamfering unit second chamfering unit second transmission gate 102 > 302 104 304 306 308 3082 3084 3086 3088 18 201239858 3090 third transmission gate 30822 sixth type N Gold Oxygen Half Crystal 30824 Sixth P Type Gold Oxygen Half Crystal 30842 First N Type Gold Oxygen Half Crystal 30844 Second N Type Gold Oxygen Half Crystal 30846 First P Type Gold Oxygen Half Crystal 30848 Third N Type Gold Oxygen Half Crystal 30850 Second P Type Gold Oxygen Half Crystal 30862 Fourth N Type Gold Oxygen Half Crystal 30864 Third P Type Gold Oxygen Half Crystal 30866 Fourth P Type Gold Oxygen Half Crystal 30868 Fifth N Type Gold Oxygen Half Crystal 30870 Fifth P Type Gold Oxygen Half Crystal 30882 Seventh N Type Gold Oxygen Half Crystal 30884 Seventh P Type Gold Oxygen Half Crystal 30902 Eighth P Type Gold Oxygen Half Crystal 30904 Eighth Type N Gold oxide semi-transistor C external capacitor LS first voltage LSI input voltage LS_0 chamfer voltage PC comparison result PR I phase adjustment signal 19 201239858 PS second voltage R external resistor ΤΙ ' T2 time VDD high voltage VEEG gate low voltage VGH gate high voltage VDDA voltage 700 to 710 Step 20