201239373 六、發明說明： 【發明所屬之技術領域】 剛本發明涉及-種二極體測試^及在财法巾使用的型 材’㈣是指-種發光二極_試方法及在該方法中使 用的型材。 【先前技術】 國發光二極體作為-觀興料源，目前已廣泛應用於多 種場合之中’並大有取代傳統光源的趨勢。 〇 剛f知的發光二極體的料方_常是先在—塊基板上固 疋多個發光晶片’然後通過封裝想同時封裝所有的發光 晶片’最後再經由切割形成多個獨立的發光二極體。 [_為確定發光二極體鮮正常卫作歧㈣二極體的各種 光學特性，通常會對切割之後的各個發光二極體進行電 氣性能測試《然而，由於發光二極體的數量較多，逐個 對各發光二極體測試需要較長的時間，造成生產週期的 拉長。並且，逐個進行測試還需要耗費較多的人力，造 成生產成本的增加.。 , , 【發明内容】 [0005] 因此’有必要提供一種能同時對多個發光二極體進行測 試的方法及在該方法中使用的發光二極體型材。 [0006] —種發光二極體測試方法，包括步驟： [00〇7]提供引線框，該引線框包括外框及位於外框内的複數接 線區，外框包括二相對的第一側壁及二相對的第二側壁 ，接線區在外框内排列為複數行及複數列，每一接線區 100111208 表單編號A0101 第3頁/共32頁 201239373 包括第一引腳及與第一引腳間隔斷開的第二引腳，每一 接線區的第一引腳及第二引腳均通過各自的連接段與相 鄰的接線區或外框連接； [0008] 在引線框上形成絕緣的支架，支架覆蓋各接線區並開設 暴露各接線區第一引腳及第二引腳的凹槽； [0009] 去除引線框的部分區域，使二第一侧壁與相鄰的連接段 及第二側壁斷開； [0010] 在各凹槽内固定發光晶片並將發光晶片電連接至相應的 第一引腳及第二引腳； [0011] 在各凹槽内形成覆蓋發光晶片的封裝層； [0012] 將靠近一第一侧壁的任一第一引腳與該第一側壁斷開的 連接段電連接至第一電極，並將靠近任一第一側壁的任 一第二引腳與該任一第一側壁斷開的連接段電連接至第 二電極，從而將電流通入位於該任一第一引腳及任一第 二引腳之間的至少一列發光晶片，第一電極與第二電極 的極性相反；及 [0013] 根據發光晶片的出光判斷各發光晶片的工作情況或光學 特性。 [0014] 一種發光二極體型材，包括引線框、形成於引線框上的 支架、固定於引線框上的多個發光晶片及覆蓋各發光晶 片的封裝層，引線框包括一外框及在外框内以複數行及 複數列排列的接線區，該外框包括二相對的第一側壁及 二相對的第二側壁，每一接線區包括第一引腳及與第二 100111208 表單編號A0101 第4頁/共32頁 1002018757-0 201239373 引腳間隔斷開的第二引腳，各發光晶片固定在相應的接 線區上並與第一引腳及第二引腳電連接，每一接線區的 第一引腳及第二引腳朝向相鄰的接線區或外框延伸出連 接段，其中每一接線區的第一引腳及第二引腳的連接段 與相鄰的接線區的連接段連接，靠近第一側壁的接線區 的第一引腳及第二引腳的連接段與第一侧壁斷開，每一 第一側壁開設有開槽而與二第二側壁斷開。 [0015] 該發光二極體的測試方法由於可通過對相應的第一引腳 及第二引腳通入電流，同時對至少一列上的多個發光晶 片進行測試，因此可減少整體的測試時間，並減少工作 的強度，從而縮短生產週期並降低生產成本。 【實施方式】 [0016] 請參閱圖卜16，示出了本發明測試發光二極體的方法， 其主要包括如下步驟： [0017] 首先，如圖1-2所示提供一引線框10。該引線框10由一金 屬片材一體沖裁而成。該引線框10包括一框架12及位於 該框架12中的多個接線區14。該框架12為一中空的矩形 Ο 〇 結構，其由二相對的第一側壁120及二相對的第二側壁 122構成。每一第一側壁120垂直連接二第二側壁122。 這些接線區14以矩陣的方式排布於框架12内，其包括複 數平行於第一側壁120的行及複數平行第二侧壁122的列 。每一接線區14包括一第一引腳140及通過一間隙144與 第一引腳140隔開的一第二引腳142。該第一引腳140呈 矩形，其在除與第二引腳142相對的一邊的另外相鄰的三 邊分別延伸出三連接段16。該第二引腳142也呈矩形，其 100111208 表單編號A0101 第5頁/共32頁 1002018757-0 201239373 長度與第一引腳140的長度相同，寬度小於第一引腳140 的寬度。該第二引腳142也在除與第一引腳140相對的一 邊的另外相鄰的三邊分別延伸出三連接段16。每一接線 區14的連接段16均與相鄰的接線區14或者外框12相連接 ，其中靠近外框12的接線區14的第一引腳140及第二引腳 142的連接段16與外框12的相應側壁120、122連接，遠 離外框12的接線區14的第一引腳140及第二引腳142的連 接段16與相鄰的接線區14的相應連接段16連接。 [0018] 然後，如圖3 -4所示在引線框10上成型一支架20。該支架 20可由環氧樹脂、破璃環氧化物、BT樹脂 (Bismaleimide Triazine. Resin)、梦膠等易於成型 的材料製成。該支架20覆蓋住引線框1〇ι的大部分區域， 其中支架20的相對兩側與引線框1〇的二第二侧壁！22連接 ’支架20的另外相對兩侧與引線框1 〇的二第一側壁12〇隔 開而留出部分連接段16暴露在外。支架20的底部與引線 ；i；； .... 框10的底部齊平並填充每一接線區14苐一引腳140及第二 引腳142之間的間隙144而形成一間隔4200，支架20的 頂部高於引線框10的頂部。支架20在對應每一接線區14 的位置處開設一凹槽22，以暴露出第一引腳14〇、第二引 腳142及填充於間隙144内的間隔塊200。該凹槽22的面 積小於相應的接線區14的面積而使第一引腳140、第二引 腳142及間隔塊200僅有部分暴露在凹槽22中，其他部分 則被支架20所覆蓋。該凹槽22具有四豎直的内壁面，以 用於對光線進行反射。當然，為提升凹槽22内光線的反 射效率，凹槽22的内壁面還可以如圖5所示呈傾斜狀，以 100111208 表單編號A0101 第6頁/共32頁 1002018757-0 201239373 使更多的光線能朝向凹槽2 2的頂部反射。 [0019] 之後，如圖6-7所示移除引線框1〇的部分區域，使二第一 側壁120與二第二側壁122以及相鄰的連接段16斷開。具 體地’未被支架20所覆蓋而暴露在外的連接段16與相應 的第一側壁120所連接的部分被切除而與第一側壁120斷 開，第一側壁120在對應於每一列的接線區14與該第一側 壁120連接的二連接段16之間的位置處也斷開而形成複數 槽道124。移除引線框1〇部分區域的方法可以為切割、衝 〇 壓或其他相關的工藝制程。： .' . . : [0020] 隨後，如圖8-9所示在各凹槽22底部固定一發光晶片30並 對發光晶片30進行打線。該發光晶片30可以為氮化鎵、 氮化銦鎵、氮化鋁銦鎵、砷化鎵、砷化鉛鎵等半導體發 光材料所製成，具體取決於實際的顏色需求。優選地， 本實施例採用可發出藍光的氮化鎵作為發光晶片30的材 料。每一發光晶片30通過導熱膠或其他方式固定在相應 接線區14的第一引腳140上，並通過二金線40分別與第一 ...!« ：：:. ：Λ · 〇 引腳140及第二·引腳U2的頂面連接。由於間隔塊200的 絕緣，第一引腳140及第二引腳142只能通過發光晶片30 及金線40導通。由於相鄰列的第一引腳140及第二引腳 , 142也相互連接，因此每一列的接線區14均與相鄰列的接 線區14導通。同時，由於二第二側壁122還通過連接段16 與相鄰的兩列接線區14連接，因此每列的接線區μ也同 時與二第二侧壁122導通。彼此導通的接線區14以及二第 二侧壁122與斷開的二第一側壁120保持絕緣。每列接線 區14的發光晶片30相互並聯，每行接線區14的發光晶片 100111208 表單編號Α0101 第7頁/共32頁 1002018757-0 201239373 3 0相互串聯。 [0021] 然後，如圖10所示在每一凹槽22内填充一透明的封裝層 50。該封裝層50可由透光性良好的材料製成，如玻璃、 聚碳酸酯、聚曱基丙烯酸曱酯等。該封裝層50覆蓋發光 晶片30及金線40以將二者與外界隔絕。該封裝層50内還 可進一步填充螢光粉60，以改變發光晶片30的出光顏色 。該螢光粉60的材料可選自矽酸鹽、石榴石、氮化物、 氮氧化物等螢光材料，具體取決於實際需求。優選地， 本實施例採用可發出黃光的石榴石作為螢光粉60的材料 ，其在受到發光晶片30發出的藍光之後激發出黃光，從 而與剩餘的藍光共同混合為白光。 [0022] 之後，對所需的發光晶片30進行測試。設定測試目標為 如圖11-1 2所示的區域I内的發光晶片30，由於該區域僅 包括一列發光晶片30，因此可將該列接線區14中靠近其 中一第一侧壁120的第一引腳140的斷開的連接段16作為 一第一接觸端，並將該列接線區14中靠近該第一側壁120 的第二引腳142的斷開的連接段16作為一第二接觸端。將 該第一接觸端與一外部的第一電極70連接，將該第二接 觸端與一外部的第二電極72連接。該第一電極70及第二 電極72的極性需保持相反，並與發光晶片30的極性相對 應，以避免造成反接而損壞發光晶片30。本實施例中該 第一電極70為正極，第二電極72為負極，發光晶片30的 正極與第一電極70連接，發光晶片30的負極與第二電極 72連接。由於每列的發光晶片30均是並聯，因此在第一 電極70及第二電極72通入電流之後，區域I内的發光晶片 100111208 表單編號Α0101 第8頁/共32頁 1002018757-0 201239373 3〇均有電流流過而發光。如若有發光晶片30損壞或金線 60接觸不良，則該發光晶片30不會發光而—直熄滅。由 於是相互並聯，損壞或接觸不良的發光晶片3〇將不會對 其他的發光晶片3 0邊成衫響，從而得到正確的測試結果 。經由此種測試，句同時得知該區域I内所有的發光晶片 30的工作狀態，判斷出是否有發光晶片3〇不能正常工作 。另外，除工作狀態外，還可通過肉眼或儀器對發光的201239373 VI. Description of the invention: [Technical field to which the invention pertains] The invention has been described in the context of a diode test and the profile used in the method of ''fourth' refers to a type of light-emitting diode-test method and used in the method Profiles. [Prior Art] National Light Emitting Diodes, as the source of Guanxing, have been widely used in many occasions and have a tendency to replace traditional light sources. The material of the light-emitting diode of 〇 f _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Polar body. [_In order to determine the various optical characteristics of the LEDs of the LEDs, the LEDs are usually tested for electrical properties after cutting. However, due to the large number of LEDs, It takes a long time to test each of the light-emitting diodes one by one, resulting in an elongated production cycle. Moreover, testing one by one requires more manpower, resulting in an increase in production costs. SUMMARY OF THE INVENTION [0005] Therefore, it is necessary to provide a method capable of simultaneously testing a plurality of light-emitting diodes and a light-emitting diode profile used in the method. [0006] A method for testing a light-emitting diode, comprising the steps of: [00〇7] providing a lead frame, the lead frame comprising an outer frame and a plurality of wiring areas located in the outer frame, the outer frame comprising two opposite first side walls and Two opposite second side walls, the wiring area is arranged in a plurality of rows and a plurality of columns in the outer frame, each wiring area 100111208 Form No. A0101 Page 3 / Total 32 pages 201239373 includes the first pin and is disconnected from the first pin The second pin, the first pin and the second pin of each of the wiring areas are connected to the adjacent wiring area or the outer frame through the respective connecting sections; [0008] an insulating bracket is formed on the lead frame, the bracket Covering each wiring area and opening a groove exposing the first pin and the second pin of each wiring area; [0009] removing a part of the lead frame, so that the two first side walls are disconnected from the adjacent connecting section and the second side wall [0010] fixing the light-emitting chip in each groove and electrically connecting the light-emitting chip to the corresponding first pin and the second pin; [0011] forming an encapsulation layer covering the light-emitting chip in each groove; [0012] Any first pin that is adjacent to a first sidewall and the first The connecting portion of the sidewall is electrically connected to the first electrode, and the connecting portion of any second pin adjacent to any of the first sidewalls is disconnected from the connecting portion of the first sidewall to the second electrode, thereby discharging current Passing at least one column of illuminating wafers between any one of the first pins and any of the second pins, the polarities of the first electrodes and the second electrodes are opposite; and [0013] determining the illuminating wafers according to the light emitted from the illuminating wafer Working condition or optical characteristics. [0014] A light emitting diode profile, comprising a lead frame, a bracket formed on the lead frame, a plurality of light emitting chips fixed on the lead frame, and an encapsulation layer covering each of the light emitting chips, the lead frame including an outer frame and the outer frame a wiring area arranged in a plurality of rows and a plurality of columns, the outer frame comprising two opposite first side walls and two opposite second side walls, each of the wiring areas including the first pin and the second 100111208 Form No. A0101, page 4 / Total 32 pages 1002018757-0 201239373 The second pin with the pin spacing is disconnected, each illuminating chip is fixed on the corresponding wiring area and electrically connected with the first pin and the second pin, the first of each wiring area The pin and the second pin extend toward the adjacent wiring area or the outer frame, and the connecting portion of the first pin and the second pin of each of the connecting portions is connected to the connecting portion of the adjacent connecting area. The first pin and the connecting portion of the second pin of the wiring area adjacent to the first sidewall are disconnected from the first sidewall, and each of the first sidewalls is slotted to be disconnected from the second sidewall. [0015] The test method of the light-emitting diode can reduce the overall test time by inputting current to the corresponding first pin and the second pin while testing a plurality of light-emitting wafers in at least one column And reduce the intensity of work, thereby shortening the production cycle and reducing production costs. [Embodiment] [0016] Referring to FIG. 16, a method for testing a light-emitting diode of the present invention is shown, which mainly includes the following steps: [0017] First, a lead frame 10 is provided as shown in FIGS. 1-2. The lead frame 10 is integrally formed from a metal sheet. The lead frame 10 includes a frame 12 and a plurality of wiring areas 14 in the frame 12. The frame 12 is a hollow rectangular Ο structure composed of two opposing first side walls 120 and two opposite second side walls 122. Each of the first sidewalls 120 vertically connects the second sidewalls 122. These wiring areas 14 are arranged in a matrix in the frame 12 and include a plurality of rows parallel to the first side wall 120 and a plurality of parallel second side walls 122. Each of the wiring regions 14 includes a first pin 140 and a second pin 142 spaced apart from the first pin 140 by a gap 144. The first pin 140 has a rectangular shape, and the three adjacent connecting segments 16 extend respectively on the other adjacent three sides of the side opposite to the second pin 142. The second pin 142 is also rectangular, and its 100111208 form number A0101 page 5/32 page 1002018757-0 201239373 has the same length as the first pin 140 and a width smaller than the width of the first pin 140. The second pin 142 also extends out of the three connecting segments 16 on the other adjacent three sides of the side opposite the first pin 140, respectively. The connecting section 16 of each of the wiring areas 14 is connected to the adjacent wiring area 14 or the outer frame 12, wherein the first pin 140 of the wiring area 14 of the outer frame 12 and the connecting section 16 of the second pin 142 are The respective side walls 120, 122 of the outer frame 12 are connected, and the first pin 140 away from the wiring area 14 of the outer frame 12 and the connecting portion 16 of the second pin 142 are connected to the corresponding connecting portion 16 of the adjacent wiring area 14. [0018] Then, a bracket 20 is formed on the lead frame 10 as shown in FIG. The holder 20 may be made of an easily formed material such as an epoxy resin, a glass epoxide, a BT resin (Bismaleimide Triazine. Resin), or a dream gel. The bracket 20 covers most of the area of the lead frame 1〇, wherein the opposite sides of the bracket 20 and the second side wall of the lead frame 1〇! The other opposite sides of the 22-joint' bracket 20 are spaced apart from the first side walls 12 of the lead frame 1 而 leaving the portion of the connecting section 16 exposed. The bottom of the bracket 20 is flush with the bottom of the frame; i;;.. The bottom of the frame 10 is filled and fills the gap 144 between each of the wiring areas 14, a pin 140 and the second pin 142 to form a space 4200, the bracket The top of 20 is higher than the top of leadframe 10. The bracket 20 defines a recess 22 at a position corresponding to each of the wiring areas 14 to expose the first pin 14A, the second pin 142, and the spacer block 200 filled in the gap 144. The area of the recess 22 is smaller than the area of the corresponding wiring area 14 such that the first lead 140, the second lead 142, and the spacer block 200 are only partially exposed in the recess 22, and the other portions are covered by the bracket 20. The recess 22 has four vertical inner wall faces for reflecting light. Of course, in order to improve the reflection efficiency of the light in the groove 22, the inner wall surface of the groove 22 can also be inclined as shown in FIG. 5, with 100111208 Form No. A0101 Page 6 / Total 32 Page 1002018757-0 201239373 Light can be reflected towards the top of the groove 22. [0019] Thereafter, a portion of the lead frame 1A is removed as shown in FIGS. 6-7, and the two first sidewalls 120 are disconnected from the second sidewalls 122 and the adjacent connecting segments 16. Specifically, the portion of the connecting portion 16 that is not covered by the bracket 20 and exposed and connected to the corresponding first side wall 120 is cut away from the first side wall 120, and the first side wall 120 is in the wiring area corresponding to each column. The position between the two connecting sections 16 connected to the first side wall 120 is also broken to form a plurality of channels 124. The method of removing a portion of the lead frame 1 may be a cutting, punching, or other related process. [0020] Subsequently, an illuminating wafer 30 is attached to the bottom of each of the grooves 22 as shown in Figs. 8-9 and the luminescent wafer 30 is wired. The luminescent wafer 30 can be made of a semiconductor luminescent material such as gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide or lead arsenide, depending on actual color requirements. Preferably, this embodiment employs gallium nitride which emits blue light as a material of the light-emitting wafer 30. Each of the illuminating wafers 30 is fixed on the first pin 140 of the corresponding wiring area 14 by a thermal conductive adhesive or the like, and is respectively connected to the first...!« :::. The top surface of the 140 and the second pin U2 are connected. Due to the insulation of the spacer block 200, the first pin 140 and the second pin 142 can only be turned on through the light emitting chip 30 and the gold wire 40. Since the first pin 140 and the second pin 142 of the adjacent columns are also connected to each other, the wiring area 14 of each column is electrically connected to the wiring area 14 of the adjacent column. At the same time, since the two second side walls 122 are also connected to the adjacent two rows of wiring areas 14 through the connecting portion 16, the wiring area μ of each column is also electrically connected to the second second side walls 122 at the same time. The wiring area 14 and the second and second side walls 122 which are electrically connected to each other are insulated from the two first side walls 120 which are disconnected. The light-emitting wafers 30 of each of the wiring areas 14 are connected in parallel with each other, and the light-emitting wafers of each of the wiring areas 14 are patterned. 表单0101 Page 7 of 32 1002018757-0 201239373 3 0 are connected in series. [0021] Then, a transparent encapsulation layer 50 is filled in each of the grooves 22 as shown in FIG. The encapsulating layer 50 may be made of a material having good light transmittance such as glass, polycarbonate, decyl acrylate or the like. The encapsulation layer 50 covers the luminescent wafer 30 and the gold wire 40 to isolate the two from the outside. The encapsulating layer 50 may further be filled with the phosphor powder 60 to change the color of the light emitted from the light emitting wafer 30. The material of the phosphor powder 60 may be selected from fluorescent materials such as citrate, garnet, nitride, and oxynitride, depending on actual needs. Preferably, this embodiment employs garnet which emits yellow light as a material of the phosphor powder 60 which excites yellow light after being subjected to blue light emitted from the light-emitting chip 30, thereby being mixed with the remaining blue light to be white light. [0022] Thereafter, the desired luminescent wafer 30 is tested. The test target is set to the illuminating wafer 30 in the area I as shown in FIG. 11-1. Since the area includes only one column of the illuminating wafer 30, the first wiring section 14 can be adjacent to one of the first side walls 120. The disconnected connecting portion 16 of a pin 140 serves as a first contact end, and the disconnected connecting portion 16 of the column of the second terminal 142 of the first side wall 120 is used as a second contact. end. The first contact end is connected to an external first electrode 70, and the second contact end is connected to an external second electrode 72. The polarities of the first electrode 70 and the second electrode 72 need to be reversed and correspond to the polarity of the luminescent wafer 30 to avoid causing the reverse connection to damage the luminescent wafer 30. In this embodiment, the first electrode 70 is a positive electrode, the second electrode 72 is a negative electrode, the positive electrode of the luminescent wafer 30 is connected to the first electrode 70, and the negative electrode of the luminescent wafer 30 is connected to the second electrode 72. Since the illuminating wafers 30 of each column are connected in parallel, after the first electrodes 70 and the second electrodes 72 are supplied with current, the illuminating wafer 100111208 in the area I is Α0101, page 8 / total 32 pages 1002018757-0 201239373 3〇 Both currents flow through and illuminate. If the luminescent wafer 30 is damaged or the gold wire 60 is poorly contacted, the luminescent wafer 30 does not emit light and is extinguished. Thus, the light-emitting wafers 3, which are connected in parallel with each other, which are damaged or have poor contact, will not be twisted on the sides of the other light-emitting wafers, thereby obtaining correct test results. Through this test, the sentence simultaneously knows the operating states of all the light-emitting wafers 30 in the area I, and judges whether or not the light-emitting chip 3 is not working properly. In addition, in addition to the working state, it can also be illuminated by the naked eye or instrument.
DD
發光晶片30的光學特性進行簡單或精確的測定，利於後 續的篩選。當然，可以理解地，測試過程中還可將該列 接線區14中靠近另一爭一側堂12 〇的第二引腳丨4 2的斷開 的連接段16作為第二接觸端，再將其與第二電極72連接 ，同樣可起到相同的測試效果。如若需同時對多列發光 晶片30進行測試，比如圖13-14所示的區域I及區域 的兩列發光晶片30 ’則可將區域I中的靠近任一第一側壁 120的第一引腳140的斷開的連接段16與第一電極7〇連接 ，將區域π中的靠近任一第一側壁120的第二引腳142的 斷開的連接段16與第今電極72連接，從而組成多行發光 晶片電路。每一行g备光晶片3〇形成串聯，並與其他行 的發光晶片30形成並聯。此種連接方式可同時對區域1及 區域11内的所有發光晶片3〇進行測試，以判斷其工作狀 態或光學特性。更進一步地，如果需要同時對所有的發 光晶片30進行測試，可如圖15_16所示將第—列接線區 14的靠近任一第一側壁丨2〇的第一引腳〗4〇的斷開的連接 段16與第一電極70連接，並將最後—列接線區14的靠近 任一第一側壁120的第二引腳丨42的斷開的連接段丨6與第 二電極72連接《由此，外框12内的所有發光晶片3〇均被 100111208 表单編號A0101 第§頁//共π頁 1002018757-0 201239373 、接起來從而同時破測試。當然’如果要對任意多列相 :的發光晶片3G進行職，也可採用相同的方法，僅需 變更第#觸端及第二接觸端的位置。 [0023] [0024] [0025] 可以理解地，由於左側的第二側壁122是直接與第-列接 線區⑽第—引腳U0連通，因此當第—列接線區14位於 1 Μ區域中時還可直接將該第二側壁⑵作為第一接觸 端與第電極70接觸，此時第-列接線區14中靠近任-第一側壁12G的第-弓丨腳14()的斷開的連接段咐斑第一 電極電連接。同理，右侧的第二側壁122是直接與 最後-列的接線區14的第二引腳142連通，因此當最後一 列接線區14位於被測試區域中時可將該第二侧壁⑵作為 第：接觸端與第二電極72接:觸，此時最後一列接線區14 中靠近任-第-側壁m的第二引腳142的斷開的連接段 16與第二電極72亦保持電連接。 最後，沿各接線區14的邊緣,行切割ί，形成多個獨立的 發光二極體。由於之前已經經過測試，因此可直接根據 各發光二極體的狀態對其進行f，即淘汰掉損壞的發 光二極體，並依據不同的光學特性將正常工作的發光二 極體分類。 通過使用此種方法，可同時對多個發光二極體進行測試 ，從而節省測試時間，降低工作強度，有利於實現成本 的卽約。此外，由於測試過裎是集成在發光二極體的製 la過程中的，因此可進一步減少額外的工作縮短整個 製造週期。 1001Π208 表單編號Α〇ΐ〇ι 第頁/共32頁 1002018757-0 201239373 [0026] 综上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0027] 圖1為本發明發光二極體測試方法的第一個步驟。 [0028] 圖2為發光二極體在圖1的第一個測試步驟當中的截面圖The optical characteristics of the luminescent wafer 30 are simply or accurately determined for subsequent screening. Of course, it can be understood that, during the test, the disconnected connecting section 16 of the second pin 丨 4 2 of the column wiring area 14 adjacent to the other side of the body 12 can be used as the second contact end, and then It is connected to the second electrode 72 and can also perform the same test effect. If multiple rows of illuminating wafers 30 are to be tested at the same time, such as the regions I and regions of the two rows of illuminating wafers 30' shown in FIGS. 13-14, the first pin of the region I near any of the first sidewalls 120 can be used. The disconnected connecting portion 16 of the 140 is connected to the first electrode 7A, and the disconnected connecting portion 16 of the second pin 142 of the first side wall 120 in the region π is connected to the first electrode 72, thereby forming Multi-row light emitting chip circuit. Each row of the matte wafers 3 is formed in series and is formed in parallel with the other rows of the light-emitting wafers 30. This type of connection allows simultaneous testing of all of the light-emitting wafers 3 in Zone 1 and Zone 11 to determine their operational or optical characteristics. Further, if it is necessary to test all of the light-emitting wafers 30 at the same time, the first pin of the first-row wiring area 14 close to any of the first side walls 丨2〇 can be disconnected as shown in FIG. 15-16. The connecting portion 16 is connected to the first electrode 70, and connects the disconnected connecting portion 丨6 of the second pin 丨42 of the last-stage wiring region 14 adjacent to any of the first sidewalls 120 to the second electrode 72. Therefore, all the light-emitting wafers 3 in the outer frame 12 are connected by the 100111208 form number A0101 page § / / π page 1002018757-0 201239373 to simultaneously break the test. Of course, if the illuminating wafer 3G of any multi-column phase is to be used, the same method can be used, and it is only necessary to change the positions of the ##-contact and the second-contact end. [0025] [0025] It can be understood that since the second sidewall 122 on the left side is directly connected to the first pin U0 of the first column connection region (10), when the first column wiring region 14 is located in the 1 Μ region The second side wall (2) can also be directly contacted as the first contact end with the first electrode 70, at which time the disconnected connection of the first-to-column 14 () of the first-side side wall 12G in the first-row wiring area 14 The first electrode of the segment freck is electrically connected. Similarly, the second side wall 122 on the right side is in direct communication with the second pin 142 of the last-column wiring area 14, so that the second side wall (2) can be used when the last column of wiring areas 14 is located in the tested area. The contact end is connected to the second electrode 72: the disconnected connection section 16 of the second pin 142 of the last column of the wiring area 14 adjacent to the any-the-side wall m is also electrically connected to the second electrode 72. . Finally, along the edges of the wiring areas 14, the lines are cut to form a plurality of individual light-emitting diodes. Since it has been tested before, it can be directly f according to the state of each light-emitting diode, that is, the damaged light-emitting diodes are eliminated, and the normal working light-emitting diodes are classified according to different optical characteristics. By using this method, multiple light-emitting diodes can be tested at the same time, thereby saving test time, reducing work intensity, and facilitating cost reduction. In addition, since the test is integrated in the process of forming the LED, further work can be further reduced to shorten the entire manufacturing cycle. 1001Π208 Form number Α〇ΐ〇ι page/total 32 pages 1002018757-0 201239373 [0026] In summary, the present invention complies with the invention patent requirements, and patents are filed according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0027] FIG. 1 is a first step of the method for testing a light-emitting diode of the present invention. 2 is a cross-sectional view of the light emitting diode in the first test step of FIG. 1.
[0029] 圖3為本發明發光二極體測試方法的第二個步驟。 [0030] 圖4為發光二極體在圖3的第二個測試步驟當中的部分截 面圖。 [0031] 圖5為圖4中發光二極體的一種變型。^ [0032] 圖6為本發明發光二極體測試方法的第三個步驟。 [0033] 圖7為圖6的透視圖》 [0034] 圖8為本發明發光二極體測試方法的第四個步驟。 [0035] 圖9為發光二極體在圖8的第四個測試步驟當中的部分截 面圖。 [0036] 圖1 0為本發明發光二極體測試方法的第五個步驟。 [0037] 圖11為本發明發光二極體測試方法的第六個步驟，其中 區域I被作為測試目標。 [0038] 圖12為圖11中區域I的電路結構。 [0039] 圖13與圖11類似，其中測試區域I及II被作為測試目標。 100111208 表單編號 A0101 第 11 頁/共 32 頁 1002018757-0 201239373 [0040] 圖1 4為圖1 3中區域I及II的電路結構。 [0041] 圖15與圖11類似，其中測試區域被擴大至整個引線框。 [0042] 圖16為圖15中整個引線框的電路結構。 【主要元件符號說明】 [0043] 10 :引線框 [0044] 12 :外框 [0045] 120:第一侧壁 [0046] 122:第二側壁 [0047] 124 :開槽 [0048] 14 :接線區 [0049] 140 :第一引腳 [0050] 142 :第二引腳 [0051] 144 :間隙 [0052] 16 :連接段 [0053] 20 :支架 [0054] 2 0 0 :間隔塊 [0055] 22 :凹槽 [0056] 3 0 :發光晶片 [0057] 40 :金線 [0058 ] 50 :封裝層 100111208 表單編號Α0101 第12頁/共32頁 1002018757-0 201239373 [0059] 60 ： 螢光粉 [0060] 70 ·· 第一電極 [0061] 72 : 第二電極 ❹ Ο 100111208 表單編號Α0101 第13頁/共32頁 1002018757-03 is a second step of the method for testing a light-emitting diode according to the present invention. 4 is a partial cross-sectional view of the light emitting diode in the second test step of FIG. 3. [0031] FIG. 5 is a modification of the light emitting diode of FIG. 4. [0032] FIG. 6 is a third step of the method for testing a light-emitting diode of the present invention. 7 is a perspective view of FIG. 6. [0034] FIG. 8 is a fourth step of the method for testing a light-emitting diode of the present invention. 9 is a partial cross-sectional view of the light emitting diode in the fourth test step of FIG. 8. 10 is a fifth step of the method for testing a light-emitting diode according to the present invention. 11 is a sixth step of the method for testing a light-emitting diode of the present invention, in which the region I is used as a test target. 12 is a circuit configuration of a region I in FIG. 11. [0039] FIG. 13 is similar to FIG. 11 in which test areas I and II are used as test targets. 100111208 Form No. A0101 Page 11 of 32 1002018757-0 201239373 [0040] FIG. 14 is a circuit configuration of the regions I and II in FIG. [0041] FIG. 15 is similar to FIG. 11 in which the test area is enlarged to the entire lead frame. 16 is a circuit configuration of the entire lead frame of FIG. 15. [Main component symbol description] [0043] 10: lead frame [0044] 12: outer frame [0045] 120: first side wall [0046] 122: second side wall [0047] 124: slotted [0048] 14: wiring Area [0049] 140: first pin [0050] 142: second pin [0051] 144: gap [0052] 16: connection section [0053] 20: bracket [0054] 2 0 0 : spacer block [0055] 22: Groove [0056] 3 0 : Light-emitting wafer [0057] 40: Gold wire [0058] 50: Package layer 100111208 Form number Α 0101 Page 12 / Total 32 page 1002018757-0 201239373 [0059] 60 : Fluorescent powder [ 0060] 70 ·· First electrode [0061] 72 : Second electrode ❹ Ο 100111208 Form number Α 0101 Page 13 / Total 32 pages 1002018757-0