TW201237615A - Method, apparatus and system to save processor state for efficient transition between processor power states - Google Patents

Method, apparatus and system to save processor state for efficient transition between processor power states Download PDF

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TW201237615A
TW201237615A TW100145341A TW100145341A TW201237615A TW 201237615 A TW201237615 A TW 201237615A TW 100145341 A TW100145341 A TW 100145341A TW 100145341 A TW100145341 A TW 100145341A TW 201237615 A TW201237615 A TW 201237615A
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processor
task
state
switching
transition
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TW100145341A
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Chinese (zh)
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TWI464572B (en
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Rajeev Muralidhar
Harinarayanan Seshadri
Bruce L Fleming
Vishwesh Rudramuni
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Intel Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/463—Program control block organisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
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Abstract

Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.

Description

201237615 六、發明說明： 【發明所屬之技術領域】 實施例主要有關於電腦平台中之電力管理的技術。詳 言之，某些實施例提供保存或擷取處理器之狀態以支援在 處理器電力狀態之間變遷電腦平台的方法。 【先前技術】 積體電路（1C)生產及電腦裝置製造的其他態樣中的 改良允許更小及/或更密集的積體平台架構。在這種平台 中的電路一般對無效率的電力使用及/或無效率的晶粒空 間使用有越來越敏感的趨勢。因此，電力效率、晶粒大小 、及/或晶粒利用率的漸進改良在這種平台中提供越來越 大的性能增益。這在小形式因子平台（比如手持裝置-例 如，智慧型電話、平板電腦、及類似者）的情況中尤其如 此。 現有的電腦平台不同程度地包括用於管理至這種平台 之處理器的電力分配或電力使用之一或更多特徵》例如， 這種特徵可例如回應於使用者啓動的平台中止或休眠請求 ，不同程度地實現處理器閒置狀態。欲支援比如C6電力 狀態之處理器閒置電力狀態，平台必須確保當處理器係在 處理器閒置電力狀態時的時期中不會喪失處理器的狀態資 訊。在現有技術中，處理器不同程度地包括專用硬體，其 將處理器狀態卸載到晶片上的被不同供電之區域，或將處 理器狀態持續維持在和處理器的另一普通電力域分別之專 -5- 201237615 門電力域中。 對用於實現處理器閒置電力狀態之這種技術的依賴已 強加了在處理器的1C晶片上得包括各種實作電路（例如 ，暫存器、電力分配跡線、控制邏輯等等之一或更多）的 要求。這種要求迄今對減少及/或改善處理器之晶粒空間 的利用率之努力已加諸了某些限制。 【發明內容及實施方式】 實施例不同程度地提供對處理器狀態的存取以供在處 理器電力狀態之間變遷處理器。可在組態成（例如，以平 台之處理器和記憶體）執行操作系統（OS )之電腦平台上 實現各種實施例。平台的處理器可能缺少專用電路，其能 夠獨立維持一些或所有處理器狀態以供後續擷取及/或使 用，例如以供當處理器從處理器閒置返回到較高電路操作 處理器狀態時所用。 「處理器狀態資訊」或簡稱「處理器狀態」係指敘述 在特定時間由一或更多處理器之處理的狀態之資訊，例如 由處理器快取或儲存之資料、被執行之當前（或下一個） 指令、堆疊之條件、判定異常處置、錯誤處置等等之參數 、或否則判定在特定點處理器正如何履行及/或將如何履 行處理之資訊。提供對處理器狀態之存取可包括例如提供 處理器狀態以供處理器外部的儲存，例如，以爲處理器變 遷到處理器閒置狀態做準備。替代或額外地，提供對處理 器狀態之存取可包括使處理器狀態可供載入到處理器中，201237615 VI. Description of the invention: [Technical field to which the invention pertains] Embodiments mainly relate to techniques for power management in a computer platform. In particular, some embodiments provide a method of saving or capturing the state of a processor to support transitioning the computer platform between processor power states. [Prior Art] Improvements in integrated circuit (1C) production and other aspects of computer device manufacturing allow for smaller and/or more dense integrated platform architectures. Circuitry in such platforms is generally increasingly sensitive to inefficient power usage and/or inefficient use of die space. Thus, progressive improvements in power efficiency, grain size, and/or die utilization provide increased performance gains in such platforms. This is especially true in the case of small form factor platforms such as handheld devices - for example, smart phones, tablets, and the like. Existing computer platforms include, to varying degrees, one or more features for managing power distribution or power usage to a processor of such a platform. For example, such features may, for example, be responsive to a user initiated platform abort or hibernation request. The processor idle state is implemented to varying degrees. To support a processor idle state such as the C6 power state, the platform must ensure that the processor's state information is not lost while the processor is in the idle power state of the processor. In the prior art, the processor includes, to varying degrees, dedicated hardware that offloads the processor state to a differently powered area on the wafer, or maintains the processor state continuously in another common power domain of the processor. Special-5- 201237615 Door power domain. The reliance on this technique for implementing the processor's idle power state has imposed on the processor's 1C die to include various implementation circuits (eg, scratchpads, power distribution traces, control logic, etc.) More) requirements. This requirement has so far imposed certain limitations on efforts to reduce and/or improve the utilization of the die space of the processor. SUMMARY OF THE INVENTION Embodiments provide access to processor states to varying degrees for varying processors between processor power states. Various embodiments may be implemented on a computer platform configured to execute an operating system (OS) (e.g., on a processor and memory of a platform). The processor of the platform may lack dedicated circuitry that is capable of independently maintaining some or all of the processor state for subsequent retrieval and/or use, such as for use when the processor is idle from processor back to higher circuit operation processor state. . "Processor Status Information" or "Processor Status" means information describing the status of processing by one or more processors at a particular time, such as data cached or stored by the processor, current (or executed) Next) Parameters of instructions, stacking conditions, determination of abnormal handling, error handling, etc., or information that otherwise determines how the processor is performing at a particular point and/or how it will be processed. Providing access to the state of the processor can include, for example, providing processor state for storage external to the processor, for example, in preparation for the processor transitioning to the processor idle state. Alternatively or additionally, providing access to the processor state can include making the processor state available for loading into the processor,

S -6- 201237615 例如，以爲從處理器閒置狀態變遷到較高電力操 狀態做準備。 在某些實施例中，〇s可啓動至（或從）處 電力狀態之變遷。舉例而非限制性而言，回應於 處理器電力狀態之間變遷處理器的機會，在那個 執行之OS可觸發處理器來履行任務切換。在某 中，任務切換可將一些或全部處理器狀態保存到 儲存庫，例如在記憶體中之資料結構，其係另在 常運行時間執行期間可供〇 S用於通用任務切換 些實施例不限於此方面，記憶體中之任務切換儲 置、任務切換儲存庫中資料的配置、及/或尤其 料對任務切換儲存庫的參照可與美國加州聖塔克 英特爾公司（Intel Corporation)之X86架構的 〇 例如，任務切換儲存庫可包括任務狀態段（ 舉例而非限制性而言，任務切換可將段暫存器狀 暫存器狀態、EFLAG暫存器狀態、EIP暫存器狀 選擇器狀態的一或更多者保存到TSS中。雖在本 取TSS來敘述某些實施例之特徵，可了解的是， 可延伸至應用於其他實施例來存取任何各種額外 任務切換儲存庫。 在一實施例中，任務切換可包括將處理器從 OS上運作的應用之任務切離。在這種情況中， 該應用沒有接收到爲了電力狀態變遷而需凍結操 作處理器 理器閒置 檢測到在 處理器上 些實施例 任務切換 OS之正 。雖然某 存庫的位 他平台資 拉拉市的 使用相容 TSS )。 態、控制 態、及段 文中以存 這種特徵 或替代的 執行正在 可例如在 作的任何 201237615 指示下履行任務切換。 替代或額外地，啓動處理器電力狀態變遷之任務切換 的OS可例如包括將所涉的處理器從在OS情境中執行任 務切換到在另一情境中執行電力管理任務。例如，處理器 可切換到非OS情境的情境之任務。舉例而非限制性而言 ，任務切換可包括切換處理器到執行單線程情境或其他情 境，以執行並非OS的任何任務之電力管理任務。這種電 力管理任務可例如包括基本輸入/輸出系統（BIOS)或其 他韌體任務。 第1圖繪示根據某些示範實施例之系統100的選擇元 件。系統1 00可包括平台1 05，其具有不同程度地提供電 力到平台1 0 5的其他組件之電源1 5 0。雖各種實施例的範 圍不限於此方面，平台105可包括個人電腦（PC)、個人 數位助理（PDA )、網際網路器具、手機、膝上型電腦、 平板式裝置、行動單元、無線通訊裝置、及/或任何其他 運算裝置的一或更多者。 根據某些實施例，平台105可包括直接或間接耦合到 一或更多其他組件（例如記憶體1 2 5及系統互連1 3 5 )之 處理單元110。替代或額外地，處理單元110可存取例如 儲存在記憶體1 25中或分別的儲存裝置（1 20 )中之基本 輸入/輸出系統（BIΟ S )指令。例如，處理單元1 1 〇可經 由一或更多位址及/或資料匯流排不同程度地耦合到平台 1 05之組件。應了解’這種匯流排以外或額外的互連可用 來連接處理單元1 1 〇。例如，一或更多專用線、交叉開關S -6- 201237615 For example, consider preparing for a transition from a processor idle state to a higher power operation state. In some embodiments, 〇s can initiate to (or from) a change in power state. By way of example and not limitation, in response to an opportunity to transition the processor between power states of the processor, the executing OS can trigger the processor to perform the task switch. In some cases, task switching may save some or all of the processor state to a repository, such as a data structure in memory, which may be used for general task switching during normal runtime execution. In this respect, the task switching storage in the memory, the configuration of the data in the task switching repository, and/or the reference to the task switching repository, in particular, may be related to the X86 architecture of Intel Corporation of California, USA. For example, the task switching repository may include a task status segment (for example and not by way of limitation, the task switch may have a segment scratchpad state, an EFLAG register state, an EIP scratchpad selector state) One or more of the ones are saved in the TSS. While the TSS is taken to describe the features of certain embodiments, it will be appreciated that it can be extended to other embodiments to access any of the various additional task switching repositories. In an embodiment, the task switching may include disconnecting the processor from the task of the application running on the OS. In this case, the application does not receive a change in power state. However, it is necessary to freeze the operating processor idle. It is detected that some of the tasks on the processor are switched to the OS. Although the location of a certain library is compatible with the use of TSA. The execution of this feature or alternative in the state, control state, and section is being able to perform task switching, for example, under any of the instructions of 201237615. Alternatively or additionally, the OS that initiates the task switch of the processor power state transition may, for example, include switching the processor in question from performing the task in the OS context to performing the power management task in another context. For example, the processor can switch to a task in a non-OS context. By way of example and not limitation, task switching may include switching the processor to executing a single-threaded context or other context to perform power management tasks that are not tasks of the OS. Such power management tasks may include, for example, a basic input/output system (BIOS) or other firmware task. FIG. 1 illustrates selected elements of system 100 in accordance with certain exemplary embodiments. System 100 can include a platform 105 having power supplies 150 that provide power to other components of platform 105 to varying degrees. Although the scope of various embodiments is not limited in this respect, the platform 105 may include a personal computer (PC), a personal digital assistant (PDA), an internet appliance, a mobile phone, a laptop, a tablet device, a mobile unit, and a wireless communication device. And/or one or more of any other computing device. According to some embodiments, platform 105 may include processing unit 110 coupled directly or indirectly to one or more other components, such as memory 1 255 and system interconnect 135. Alternatively or additionally, processing unit 110 may access, for example, a basic input/output system (BIΟS) instruction stored in memory 256 or in separate storage devices (1 20). For example, the processing unit 1 1 can be coupled to components of the platform 105 to varying degrees via one or more address locations and/or data busses. It should be understood that such a bus or other additional interconnects may be used to connect the processing unit 1 1 . For example, one or more dedicated lines, crossbars

S -8- 201237615 等等可用來連接處理單元1 10到記憶體125。 如上所討論，處理單元110可包括一或更多核心115 來執行操作系統（0 S )，未圖示。在各種實施例，執行 OS可實現一或更多特徵，例如先進組態及電力界面（ ACPI )及/或操作系統電力管理（OSPM )碼，以提供在平 台105上之電力分配及/或消耗的管理。 另外，處理單元1 1 0可包括快取記憶體（未圖示）， 例如像是，靜態隨機存取記憶體（SRAM )及類似者，或 任何各種類型的內部積體記憶體。記憶體1 2 5可包括動態 隨機存取記憶（DRAM )、非依電性記憶體、或類似者。 在一範例中，記憶體1 2 5可儲存可被處理單元1 1 0執行之 軟體程式。 互連135可互連平台105的各種組件以不同程度地交 換資料及/或控制訊息。舉例而非限制性而言，互連135 可包括乙太網路介面、通用序列匯流排（USB )介面、周 邊組件互連介面、及類似者的一或更多者。額外或替代地 ，互連1 3 5可包括控制藉此互連之各種組件的電路。例如 ，互連1 3 5可包括一或更多控制器集線器，比如I/O控制 器集線器、平台控制器集線器、記憶體控制器集線器及/ 或類似者。 爲了繪示某些實施例的各種特徵，將互連135顯示成 耦合處理單元110到用於在平台105接收通訊輸入裝置 130、用於從平台105發送通訊之輸出裝置140、及用於在 平台1 05中儲存資料的貯存裝置1 45。舉例而非限制性而 -9- 201237615 言’輸入裝置130及輸出裝置14〇之一或兩者可包括鍵盤 、小鍵盤、滑鼠、觸碰螢幕、顯示器、生物識別裝置及類 似者的一或更多者》貯存裝置145可包括硬碟驅動機（ HDD)、固態驅動機（SSD)、光碟（CD)驅動機、數位 多功能碟驅動機（DVD )、及/或其他電腦媒體輸入/輸出 (I/O)裝置的一或更多者。在一實施例中，輸入裝置130 、輸出裝置140、及貯存裝置丨45的一或更多者可爲在平 台105外部’並耦合到平台1〇5，例如作爲平台1〇5周邊 的各種裝置。 可了解的是’根據各種實施例，平台105之任何各種 額外或替代裝置、電路區塊等等可耦合到處理單元11〇。 也了解到平台105之特定架構，例如相關於處理單元110 之平台105的裝置、電路區塊等等之相對組態，不限於某 些實施例。 根據某些實施例，系統1 00可經由至網路1 5 5的連結 ，例如使用平台105之網路介面卡、無線網路介面、或天 線（未圖示），與其他裝置交換資料。網路連結可包括任 何種類的網路連結，比如乙太網路連結、數位用戶線（ DSL) '電話線、同軸電纜等等。網路155可爲任何種類 的網路’比如網際網路、電話網路、電纜網路、無線網路 (比如，例如符合IEEE標準802.1 1 ( 1 999 )、一或更多 IEEE 802.1 1相關標準、無線都會網路之IEEE 802.1 6標 準）及/或類似者。 根據一實施例，處理單元1 1 〇，例如一或更多核心S-8-201237615 and the like can be used to connect the processing unit 1 10 to the memory 125. As discussed above, processing unit 110 may include one or more cores 115 to execute an operating system (OS), not shown. In various embodiments, the execution OS may implement one or more features, such as Advanced Configuration and Power Interface (ACPI) and/or Operating System Power Management (OSPM) codes, to provide power distribution and/or consumption on the platform 105. Management. Alternatively, processing unit 110 may include cache memory (not shown) such as, for example, static random access memory (SRAM) and the like, or any of various types of internal integrated memory. The memory 1 2 5 may include dynamic random access memory (DRAM), non-electrical memory, or the like. In one example, memory 1 2 5 can store software programs that can be executed by processing unit 110. Interconnect 135 can interconnect various components of platform 105 to exchange data and/or control information to varying degrees. By way of example and not limitation, the interconnect 135 can include one or more of an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect interface, and the like. Additionally or alternatively, the interconnects 135 may include circuitry to control the various components that are interconnected thereby. For example, interconnect 135 may include one or more controller hubs, such as an I/O controller hub, a platform controller hub, a memory controller hub, and/or the like. To illustrate various features of certain embodiments, interconnect 135 is shown as coupling processing unit 110 to an output device 140 for receiving communication input device 130 at platform 105, for transmitting communications from platform 105, and for use in a platform Storage device for storing data in 1 05 1 45. By way of example and not limitation, -9-201237615, 'either one of the input device 130 and the output device 14 or both may include a keyboard, a keypad, a mouse, a touch screen, a display, a biometric device, and the like. The more " storage device 145" may include a hard disk drive (HDD), a solid state drive (SSD), a compact disc (CD) drive, a digital versatile disc drive (DVD), and/or other computer media input/output. One or more of the (I/O) devices. In an embodiment, one or more of the input device 130, the output device 140, and the storage device 45 may be external to the platform 105 and coupled to the platform 1〇5, for example, as various devices around the platform 1〇5. . It will be appreciated that any of a variety of additional or alternative devices, circuit blocks, and the like of platform 105 may be coupled to processing unit 11 in accordance with various embodiments. It is also understood that the particular architecture of platform 105, such as the relative configuration of devices, circuit blocks, etc., associated with platform 105 of processing unit 110, is not limited to certain embodiments. According to some embodiments, system 100 can exchange data with other devices via a connection to network 155, such as a network interface card using platform 105, a wireless network interface, or an antenna (not shown). Network connections can include any type of network connection, such as an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, and the like. The network 155 can be any kind of network 'such as the Internet, a telephone network, a cable network, a wireless network (for example, conforming to IEEE standard 802.1 1 (1 999), one or more IEEE 802.1 1 related standards) , IEEE 802.1 6 standard for wireless metro networks) and/or the like. According to an embodiment, the processing unit 1 1 , for example one or more cores

S -10- 201237615 115之一特定處理核心，可不同程度地在兩或更多個處理 器電力狀態中操作。如本文所使用，電力狀態係指一或更 多特性’例如被遞送至在那個電力狀態中的裝置或多裝置 的結合及/或被該裝置或裝置的結合所使用的電力之電壓 位準、電流位準、時脈頻率等等。平台1〇5可提供硬體及 /或執行軟體來支援、啓動、或否則實現在這種處理器電 力狀態之間的處理器核心之變遷。 第2圖繪示根據一實施例之用於提供對處理器狀態資 訊的存取之平台200的選擇元件。平台200可包括例如平 台105之一些或全部的特徵。 舉例而非限制性而言，平台2 0 0可包括處理器核心 210以執行操作系統（OS) 25 0。爲了繪示一實施例之某 些特徵’將處理器核心2 1 0顯示成位在平台200的系統晶 片（SoC) 205上。可了解到處理器核心210可在一替代 實施例中位在平台的一或任何S 〇 C之外部，例如在一隔離 的單核心或多核心CPU 1C晶片中。 處理器核心210可不同程度地耦合到平台200之一或 更多其他的組件，例如包括位在S 〇 C 2 0 5上或以外的組件 。舉例而非限制性而言，SoC 205可包括具有履行圖形資 料之計算或其他處理的呈現之電路或其他邏輯的圖形模組 215。替代或額外地，SoC 205可包括具有用於提供視頻資 訊到顯示器之介面、驅動器、或其他電路/邏輯之顯示模 組220。替代或額外地，SoC 205可包括記憶體控制器225 ，其包括電路或其他邏輯以管理對平台200之資料儲存組 -11 - 201237615 件的存取。替代或額外地，SoC 205可包括電力管 (PMU ) 2 3 0以不同程度地檢測、判定、或提供 200之一或更多組件的電力管理關聯之資料及/或控 〇 在各種實施例中，耦合到處理器核心2 1 0的平 之一些或全部的組件在各種替代實施例中可與平台 一或任何SoC分開設置。並且，可了解到平台200 其他耦合的組件之組合及/或組態僅爲例示性，且平 根據不同實施例可包括任何耦合到處理器核心2 1 0 更多額外或替代組件的任何各種之組合。 0S 250可在處理器核心210之一或更多操作， 閒置，處理器電力狀態期間呈現基線運行時間執行 種正常運行時間執行期間，0S 25 0可履行各種任務 理器核心2 1 0正執行0 S 2 5 0的指令時，例如，代 250來履行任務，處理器核心210可稱爲在0S 250 中操作。在0S 2 5 0的情境中所履行之任務可包括 限於，履行在0S 250上運行的應用之操作的任務、 25 0實現中斷處置的任務、使0S 25 0實現異常處置 及類似者。 在這種運行時間執行期間，〇 S 2 5 0可不同程度 於這種任務之間，同時維持在操作處理器電力狀態 ，0S 2 5 0可引動任務切換呼叫以將資訊保存於處理 2 1 0中，該資訊描述當前執行之任務的執行之狀態 入描述即將被切換至的下一個任務之執行的狀態（ 理單元 與平台 制訊息 台200 200之 之這種 台200 之一或 亦即非 。在這 。當處 :表0S 的情境 ，但不 使0S 的任務 地切換 。例如 器核心 ，並載 例如開One of the specific processing cores of S-10-201237615 115 can operate in two or more processor power states to varying degrees. As used herein, a power state refers to one or more characteristics 'eg, a device that is delivered to that power state or a combination of multiple devices and/or a voltage level of power used by the device or device combination, Current level, clock frequency, etc. Platforms 1〇5 can provide hardware and/or execution software to support, initiate, or otherwise implement changes in the processor core between such processor power states. Figure 2 illustrates selected elements of platform 200 for providing access to processor state information in accordance with an embodiment. Platform 200 can include features such as some or all of platform 105. By way of example and not limitation, platform 200 may include processor core 210 to perform an operating system (OS) 25 0 . The processor core 210 is shown as being located on the system chip (SoC) 205 of the platform 200 in order to illustrate some of the features of an embodiment. It can be appreciated that processor core 210 can be external to one or any of the S 〇 C of the platform in an alternate embodiment, such as in an isolated single core or multi-core CPU 1C chip. The processor core 210 can be coupled to one or more other components of the platform 200 to varying degrees, including, for example, components located on or in the S 〇 C 205. By way of example and not limitation, the SoC 205 may include a graphics module 215 having circuitry or other logic for performing the rendering of graphics data or other processing. Alternatively or additionally, the SoC 205 can include a display module 220 having an interface, driver, or other circuitry/logic for providing video information to the display. Alternatively or additionally, the SoC 205 can include a memory controller 225 that includes circuitry or other logic to manage access to the data storage group -11 - 201237615 of the platform 200. Alternatively or additionally, the SoC 205 may include power management (PMU) 230 to detect, determine, or provide power management associated data and/or control of one or more components of 200 in varying degrees in various embodiments. Some or all of the components coupled to the processor core 210 may be arranged separately from the platform one or any SoC in various alternative embodiments. Also, it can be appreciated that the combinations and/or configurations of other coupled components of platform 200 are merely exemplary, and that any of the various additional or alternative components coupled to processor core 2 1 0 may be included in accordance with various embodiments. combination. The 0S 250 may be present during one or more operations of the processor core 210, idle, during the power state of the processor, and during the execution of the normal running time, the OSS 25 0 may perform various tasks, the processor core 2 1 0 is executing 0 When the S 2 50 instruction is executed, for example, on behalf of 250 to perform the task, the processor core 210 may be referred to as operating in the OS 250. Tasks performed in the context of OS 2 250 may include, limited to, fulfilling the tasks of the operations of the application running on OS 250, tasks implementing interrupt handling, implementing exception handling and the like. During this runtime execution, 〇S 2 5 0 may be different between such tasks while maintaining the operating processor power state, and 0S 250 may steer the task switching call to save the information in processing 2 1 0 The information describes the status of the execution of the currently executed task into a state describing the execution of the next task to be switched to (one of the stations 200 of the unit and platform information station 200 200 or not. Here. At the moment: the situation of Table 0S, but does not make the task of 0S switch. For example, the core of the machine, and for example

S -12- 201237615 始或恢復執行之任務）之其他資訊到處理器核心2 1 0中。 舉例而非限制性而言，〇 S 2 5 0可發信一或更多任務切換， 其導致處理器核心210藉由分別存取記憶體23 5的任務狀 態段（TSS ) 240a、…、240η的相應者來不同程度地保存 及/或載入個別任務的任務狀態。 在一實施例中，0S 250可包括處理器管理器255，例 如來自一組執行指令的功能，其操作以評估或否則檢測處 理器核心2 1 0的一或更多處理器閒置情況。在一實施例中 ，處理器管理器255可包括Linux OS之CPUIDLE管理器 常式。替代或另外地，處理器管理器25 5可包括使用OS 電力管理（OSPM )代理者可得之一或更多處理器閒置/載 入檢測功能，該代理者比如爲在先進組態及電力介面（ ACPI )開放標準（比如2 010年4月5日發布之A C PI修 正4.0 )中可得者。雖本文以處理器管理器25 5做描述， 可了解到根據各種實施例OS 25 0可包括或提供任何各種 額外或替代的檢測邏輯來檢測處理器閒置情況。 舉例而非限制性而言，處理器管理器2 5 5可執行以判 定、接收指示關於、或檢測當前處理器閒置之程度或類型 、目前處理閒置的改變率、預期未來的處理器閒置、預期 未來的處理器閒置的改變率及/或類似者。了解到檢測處 理器核心2 1 0之閒置狀態可包括檢測處理器核心2 1 0之相 應載入狀態。 例如，0S 250可包括或可存取排程器（未圖示），其 意圖替0S 2 5 0排程下一個操作、線程等等。處理器管理 -13- 201237615 器25 5可檢測OS 250的排程器已判定沒有或預期將沒有 準備好排程以供0 S 2 5 0執行之操作或線程。 基於當前或預期未來的處理器閒置情況之檢測，處理 器管理器2 5 5可判定閒置情況代表變遷處理器核心2 1 0到 處理器閒置狀態（例如C 6 (或更低）電力狀態）的機會 。回應於識別這種機會，處理器管理器255可發動這種電 力狀態變遷。在一實施例中，啓動電力狀態變遷可包括處 理器管理器255履行對0S 250的任務切換邏輯260之呼 叫。轉而，任務切換邏輯2 6 0可提供低位準信號給處理器 核心210之硬體來履行任務切換。在一實施例中，任務切 換將處理器核心2 1 0的狀態保存到TSS，例如記憶體235 的任務狀態段（TSS) 240a、…、240η之一，其在OS 250 留在操作電力狀態或諸狀態中時可供任務切換用》 例如，處理器核心210可切換到非0S 250之情境的 情境之任務。舉例而非例示性而言，任務切換可包括切換 處理器至執行單線程情境或其他情境，以供執行並非0S 2 5 0的任何任務之電力管理任務。這種電力管理任務可例 如包括電力管理韌體24 5的任務，例如基本輸入/輸出系 統（BIOS)任務。 第3圖繪示處理器狀態3 00之選擇元件，該處理器狀 態根據一實施例係提供至TSS 305 (或從TSS 3 05提供） ，其中提供爲針對支援處理器電力狀態變遷的任務切換。 TSS 305可包括例如TSS 240a的一些或全部的特徵。 在一實施例中，TSS 3 05可進一步用於處理器狀態之S -12- 201237615 Other tasks of starting or restoring the execution of the task to the processor core 2 1 0. By way of example and not limitation, 〇S 2 50 may signal one or more task switches, which cause processor core 210 to access task state segments (TSS) 240a, ..., 240n of memory 23, respectively. The corresponding person saves and/or loads the task status of the individual tasks to varying degrees. In an embodiment, OS 250 may include a processor manager 255, such as from a set of execution instructions that operate to evaluate or otherwise detect one or more processor idle conditions of processor core 210. In an embodiment, processor manager 255 may include the CPUIDLE manager of the Linux OS. Alternatively or additionally, the processor manager 25 5 may include one or more processor idle/load detection functions available to the OS Power Management (OSPM) agent, such as in advanced configuration and power interface (ACPI) Open standards (such as the AC PI Revision 4.0 released on April 5, 2010). Although described herein with processor manager 25 5, it can be appreciated that OS 25 0 can include or provide any of a variety of additional or alternative detection logic to detect processor idle conditions in accordance with various embodiments. By way of example and not limitation, the processor manager 255 can be executed to determine, receive an indication of, or detect the extent or type of current processor idle, current rate of change of idle processing, expected future processor idle, expected Future processor idle rate of change and/or the like. It is understood that detecting the idle state of the processor core 210 may include detecting the corresponding loading state of the processor core 210. For example, OS 120 may include or have access to a scheduler (not shown) that is intended to schedule the next operation, thread, etc. for OS 250. Processor Management -13- 201237615 25 5 Detects that the OS 250 scheduler has determined that there are no or expected operations or threads that are not scheduled for execution by 0 S 250. Based on the detection of current or expected future processor idle conditions, the processor manager 255 may determine that the idle condition represents the transition processor core 210 to the processor idle state (eg, C6 (or lower) power state) opportunity. In response to identifying such an opportunity, the processor manager 255 can initiate this power state transition. In an embodiment, initiating a power state transition may include the processor manager 255 fulfilling a call to the task switching logic 260 of the OS 250. In turn, task switching logic 260 can provide a low level signal to the hardware of processor core 210 to perform task switching. In an embodiment, the task switch saves the state of the processor core 210 to the TSS, such as one of the task state segments (TSS) 240a, ..., 240n of the memory 235, which remains in the operating power state at the OS 250 or For example, the state of the processor can be switched to a task of a situation other than the context of the OS 250. By way of example and not by way of example, task switching may include switching the processor to executing a single-threaded context or other context for performing power management tasks for any task other than OS 250. Such power management tasks may include, for example, tasks for power management firmware 24, such as basic input/output system (BIOS) tasks. Figure 3 illustrates the selection of processor state 300, which is provided to TSS 305 (or provided from TSS 305) in accordance with an embodiment, where is provided for task switching for supporting processor power state transitions. TSS 305 may include features such as some or all of TSS 240a. In an embodiment, TSS 305 can be further used in processor state

S -14- 201237615 另一提供，例如儲存或卸載，其中該另一提供爲針對一任 務切換’其中在整個該任務切換中，所涉之處理器維持在 相同操作處理器電力狀態中。 針對這一種或兩種任務切換（亦即，針對處理器電力 狀態變遷或針對無改變操作處理器電力狀態）之TSS 305 的可得性可例如源於記憶體中之TSS 3 05的位置及/或在 TSS 305內之處理器狀態資訊的配置。替代或額外地，針 對這兩種任務切換之TSS 3 05的可能性皆可源自在TSS 305之外並參照其的暫存器、表、指標、或其他平台資料 元件（未圖示），例如指出TSS 305爲可供存取以在OS 的正常運行時間執行期間實現同屬任務切換之一種處理器 狀態儲存庫。 舉例而非例示性而言，在平台中T S S 3 0 5之位置、配 置、及/或對其之參照可與以美國加州聖塔克拉拉市的英 特爾公司（Intel Corporation)之x86架構的TSS 3 0 5之 使用相容。尤其，TSS 3 05可包括儲存碼段3 15之選擇器 的CS暫存器310、儲存資料段325之選擇器的DS暫存器 320、及儲存堆疊段335之選擇器的SS暫存器330的一或 更多者。 可以任務切換輕易載入CS暫存器310、DS暫存器 3 20、及SS暫存器3 3 0之選擇器到處理器，或從其卸載， 以例如分別恢復或保留在實現任務切換時任務執行的當前 狀態。 TSS 3 05可包括各種替代或額外的結構，其例如可與 -15- 201237615 由x86架構處理器之任務切換的實現相容。舉例而非例示 性而言，TSS 3 05可包括一或更多額外資料段暫存器，例 示性由可儲存額外資料段3 45、3 5 5、及3 6 5的個別選擇器 之ES暫存器340、FS暫存器350、及GS暫存器360所代 表。替代或額外地，TSS 305可儲存EFLAG暫存器370來 儲存指示用於履行與TSS 3 05關聯的任務之處理器操作的 模式（例如單步驟模式、中斷處置模式、任務鏈接模式等 等）之各種旗標。替代或額外地，TSS 305可儲存ΕΙΡ暫 存器3 75來儲存指向執行任務的當前指令之指標。藉由以 x86架構處理器存取TSS來儲存及/或擷取處理器狀態的技 術已有詳細文獻記載，且不限於各種實施例，其延伸這些 與其他這種技術以供支援處理器電力狀態變遷之任務切換 應用。S-14-201237615 Another provision, such as storage or offloading, wherein the other is provided for a task switch' wherein the processor involved is maintained in the same operational processor power state throughout the task switch. The availability of TSS 305 for one or both of the task switching (i.e., for processor power state transitions or for no change operating processor power states) may be derived, for example, from the location of TSS 305 in memory and/or Or configuration of processor status information within the TSS 305. Alternatively or additionally, the possibility of switching TSS 305 for both tasks may be derived from a register, table, indicator, or other platform data element (not shown) that is external to and referenced by TSS 305, For example, it is pointed out that TSS 305 is a processor state repository that is accessible for implementing peer-to-peer task switching during OS uptime execution. By way of example and not by way of example, the location, configuration, and/or reference to TSS 305 in the platform may be related to TSS 3 of the x86 architecture of Intel Corporation of Santa Clara, California, USA. 0 5 is compatible. In particular, the TSS 305 may include a CS register 310 that stores the selector of the code segment 3 15 , a DS register 320 that stores the selector of the data segment 325 , and an SS register 330 that stores the selector of the stacked segment 335 . One or more. The task switch can be easily loaded into or unloaded from the CS register 310, the DS register 3 20, and the SS register 3 30 selector to the processor, for example, respectively, to restore or remain in the task switching. The current state of the task execution. The TSS 3 05 may include various alternatives or additional structures that are compatible, for example, with the implementation of the task switching of the x86 architecture processor from -15 to 201237615. For example and not by way of example, the TSS 305 may include one or more additional data segment registers, illustratively by an ES of an individual selector that can store additional data segments 3 45, 3 5 5, and 3 6 5 The register 340, the FS register 350, and the GS register 360 are represented. Alternatively or additionally, TSS 305 may store EFLAG register 370 to store patterns indicating processor operations for fulfilling tasks associated with TSS 305 (eg, single-step mode, interrupt handling mode, task linking mode, etc.) Various flags. Alternatively or additionally, the TSS 305 can store the ΕΙΡ register 3 75 to store metrics directed to the current instructions that perform the task. Techniques for storing and/or capturing processor state by accessing TSS with an x86 architecture processor are well documented and are not limited to the various embodiments, extending these and other such techniques to support processor power states Transition task switching application.

了解到TSS 3 05中所示之結構僅爲例示性，且TSS 305可包括任何各種額外或替代的結構及/或資訊來儲存處 理器狀態。此外，這種結構及/或資訊可向處理器指示TSS 3 〇 5是否可供存取以實現與處理器的電力狀態變遷（例如 至或自閒置處理器電力狀態）關聯之任務切換及當處理器 保持在單一操作電力狀態中時之任務切換的任一者。 第4圖繪示根據一實施例的提供處理器狀態之方法 400的選擇元件。可藉由例如執行〇S的平台105之硬體 來履行方法400。在一實施例中，方法400可包括，在 4 1 〇，OS檢測執行OS之處理器變遷到第一電力狀態的機 會。例如，Ο S可判定處理器閒置情況指出藉由將處理器It is understood that the structure shown in TSS 3 05 is merely exemplary, and TSS 305 can include any of a variety of additional or alternative structures and/or information to store processor status. Moreover, such structure and/or information can indicate to the processor whether TSS 3 〇 5 is available for access to enable task switching associated with a power state transition of the processor (eg, to or from an idle processor power state) and when processing Any of the task switches that remain in a single operational power state. FIG. 4 illustrates selected elements of a method 400 of providing processor status, in accordance with an embodiment. Method 400 can be performed by, for example, hardware that executes platform 105 of 〇S. In an embodiment, method 400 can include, at 4 1 〇, the OS detecting an opportunity for the processor executing the OS to transition to the first power state. For example, Ο S can determine that the processor is idle, indicating that the processor is

S -16- 201237615 置於閒置處理器電力狀態可有電力節省。 回應於檢測該機會，在420，OS可啓動電力狀態變遷 。在一實施例中，OS啓動變遷可包括OS觸發處理器之任 務切換。被觸發的任務切換可將處理器的處理器狀態之至 少一部分保存到平台的任務切換儲存庫之至少一部分。在 一實施例中，平台中之資料的一或更多特徵，例如在任務 切換儲存庫中之資料的配置、在平台中之任務切換儲存庫 的位置、在任務切換儲存庫外部並參照其之資料，可指示 任務切換儲存庫是否可供存取以實現與處理器的電力狀態 變遷（例如至或自閒置處理器電力狀態）關聯之任務切換 及當處理器保持在單^操作電力狀態中時之任務切換的任 一者。 在本文中描述提供對處理器狀態之存取的技術和架構 。在本文的說明中，爲了便於解釋，提出各種特定細節以 提供某些實施例的詳盡理解。然而，對熟悉此技藝人士很 明顯地可在無這些特定細節下實行某些實施例。在其他實 例中，以區塊圖形式顯示結構和裝置以避免混淆說明。 在本說明書中對於「一實施例（one embodiment)」 或「實施例（an embodiment )」之參照意指連同該實施 例所述的特徵、結構、或特性係包括在本發明的至少一實 施例中。在說明書各處中片語「在一實施例中」的出現不 一定都參照至相同的實施例。 以對電腦記憶體內之資料位元做運算之演算法及符號 表示來呈現本文中之詳細說明的一些部分。由這些演算法 -17- 201237615 描述及表示爲熟悉運算技藝之人士用來最有效傳達其成果 的本質給熟悉此技藝之他人的手段。演算法在此，且一般 地，被詮釋爲導致希望結果的自我一致的步驟序列。這些 步驟爲需要物理量之物理操縱者。通常，雖非必要，這些 量具有電或磁信號的形式，能夠被儲存、轉移、結合、比 較、及其他之操縱。已證明有時爲了方便，主要係因慣用 語的緣故，將這些信號稱爲位元、値、元件、符號、字符 、項、數字或類似者。 然而，應注意到所有這些及類似的術語應與適當物理 量關聯，且僅爲適用於這些量的方便標記。除非從本文討 論中顯然另有所指，應認知到在整份說明書中，利用比如 「處理」或「運算」或「計算」或「判定」或「顯示」或 類似者。的詞之討論可指電腦系統或類似的電子運算裝置 之動作及程序，其將電腦系統內的暫存器及記憶體內以物 理（電子）量表示之資料操縱並變換成在電腦系統記憶體 或暫存器或其他這種資訊儲存、傳輸、或顯示裝置內類似 地以物理量表示的其他資料。 某些實施例亦有關於履行本文之操作的設備。此設備 可針對所需目的而特別加以建構，或其可包含通用電腦， 由儲存在電腦中之電腦程式加以選擇性啓動或重新組態。 可將這種電腦程式儲存在電腦可讀取儲存媒體中，比如， 但不限於，包括軟碟、光碟、CD-ROM、及光磁碟之任何 種類的碟片、唯讀記憶體（ROM )、比如動態RAM ( DRAM )之隨機存取記憶體（RAM )、可抹除可編程唯讀S -16- 201237615 Power saving can be achieved by placing the idle processor power state. In response to detecting the opportunity, at 420, the OS can initiate a power state transition. In an embodiment, the OS boot transition may include a task switch of the OS trigger processor. The triggered task switch can save at least a portion of the processor state of the processor to at least a portion of the platform's task switching repository. In one embodiment, one or more features of the material in the platform, such as configuration of data in the task switching repository, location of the task switching repository in the platform, outside of the task switching repository, and reference thereto Data indicating whether the task switching repository is accessible for task switching associated with a power state transition of the processor (eg, to or from an idle processor power state) and when the processor remains in the single operating power state Any of the task switches. Techniques and architectures that provide access to processor states are described herein. In the description herein, for the purposes of illustration However, it will be apparent to those skilled in the art that certain embodiments may be practiced without these specific details. In other examples, structures and devices are shown in block diagram form to avoid obscuring the description. References to "one embodiment" or "an embodiment" in this specification means that a feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. in. The appearances of the phrase "in an embodiment" are not necessarily referring to the same embodiment. Some of the detailed descriptions herein are presented in terms of algorithms and symbolic representations of operations on the data bits in the computer memory. These algorithms -17-201237615 describe and represent the means by which those skilled in the art can best communicate the essence of their results to others who are familiar with the art. The algorithm is here, and generally, interpreted as a self-consistent sequence of steps leading to a desired result. These steps are physical operators who require physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals and can be stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for convenience, to refer to these signals as bits, symbols, elements, symbols, characters, terms, numbers or the like. However, it should be noted that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels that apply to these quantities. Unless expressly stated otherwise in this discussion, it should be recognized that throughout the specification, such as "processing" or "operation" or "calculation" or "decision" or "display" or the like. The term discussion may refer to the actions and procedures of a computer system or similar electronic computing device that manipulates and converts data represented by physical (electronic) quantities in a scratchpad and memory within a computer system into memory in a computer system or A temporary storage or other such information is stored, transmitted, or otherwise displayed in the device in a physical quantity. Certain embodiments are also directed to devices that perform the operations herein. This device may be specially constructed for the required purpose, or it may comprise a general purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. The computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disc including a floppy disk, a compact disc, a CD-ROM, and an optical disk, and a read-only memory (ROM). Such as dynamic RAM (DRAM) random access memory (RAM), erasable programmable read only

S -18- 201237615 記憶體（EPROM)、電性EPROM(EEPROM)、磁或光卡 、或適合儲存電子指令之任何種類的媒體，並且各耦合至 電腦系統匯流排。 本文所呈現之演算法及顯示並非本質上關於任何特定 電腦或其他設備。可根據本文之教示與程式一起使用各種 通用系統，或已證明建構更專門的設備來履行所需方法步 驟較方便。各種這些系統的所需結構將出現在本文說明中 。另外，並未參照任何特定程式語言來描述某些實施例。 將可認知到各種程式語言可用來實現如本文所述之這種實 施例的教示。 除了在本文中所述者外，可對所揭露之實施例及實作 進行各種修改而不悖離其之範疇。因此，應以例示性，而 非限制性意義，詮釋本文之圖解及範例。應完全由對下列 申請專利範圍之參照來衡量本發明之範疇。 【圖式簡單說明】 在附圖的圖式中經由.例示性且非限制性繪示本發明之 各種實施例，且圖中： 第1圖爲繪示根據一實施例的提供對處理器狀態資訊 之存取的系統之選擇元件的區塊圖。 第2圖爲繪示根據一實施例的提供對處理器狀態資訊 之存取的系統之執行操作系統及硬體的選擇元件之區塊圖 〇 第3圖爲繪示根據一實施例的儲存處理器狀態資訊之 -19- 201237615 任務狀態段的選擇元件之區塊圖。 第4圖爲繪示根據一實施例的提供對處理器狀態資訊 之演算法的選擇元件之流程圖。 【主要元件符號說明】 1 0 0 :系統 1 05 :平台 1 10 :處理單元 1 1 5 :核心 120 :儲存裝置 1 2 5 :記憶體 1 3 0 :輸入裝置 1 3 5 :系統互連 1 4 0 :輸出裝置 1 4 5 :貯存裝置 1 5 0 :電源 155 :網路 200 :平台 2 0 5 :系統晶片 2 1 0 :處理器核心 2 1 5 :圖形模組 220 :顯示模組 22 5 :記憶體控制器 230 :電力管理單元 201237615 23 5 :記憶體 240a〜240η :任務狀態段 245 :電力管理韌體 25 5 :處理器管理器 260 :任務切換邏輯 3 00 :處理器狀態 3 05 :任務狀態段 310 :暫存器 3 1 5 :碼段 3 20 :暫存器 3 2 5 :資料段 3 3 0 :暫存器 3 3 5 :堆疊段 3 40 :暫存器 3 4 5 :資料段 3 50 :暫存器 3 5 5 :資料段 3 60 :暫存器 3 65 :資料段 3 70 :暫存器 3 7 5 :暫存器 -21 -S -18- 201237615 Memory (EPROM), electrical EPROM (EEPROM), magnetic or optical card, or any type of media suitable for storing electronic commands, and each coupled to a computer system bus. The algorithms and displays presented herein are not intrinsically related to any particular computer or other device. Various general-purpose systems may be used in conjunction with the programs in accordance with the teachings herein, or it may be convenient to construct a more specialized apparatus to perform the required method steps. The required structure for each of these systems will appear in the description of this article. In addition, some embodiments are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments as described herein. Various modifications may be made to the disclosed embodiments and implementations without departing from the scope of the invention. Therefore, the illustrations and examples herein should be construed in an illustrative and non-limiting sense. The scope of the invention should be measured by reference to the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0009] Various embodiments of the present invention are illustrated by way of example and not limitation in the drawings of the drawings, and FIG. A block diagram of the selected components of the system for accessing information. 2 is a block diagram showing an execution operating system and hardware selection elements of a system for providing access to processor state information according to an embodiment. FIG. 3 is a diagram showing storage processing according to an embodiment. -19-201237615 Block diagram of the selected component of the task status segment. 4 is a flow chart showing selection elements of an algorithm for providing processor status information, in accordance with an embodiment. [Main component symbol description] 1 0 0 : System 1 05 : Platform 1 10 : Processing unit 1 1 5 : Core 120 : Storage device 1 2 5 : Memory 1 3 0 : Input device 1 3 5 : System interconnection 1 4 0: Output device 1 4 5: Storage device 1 50: Power supply 155: Network 200: Platform 2 0 5: System chip 2 1 0: Processor core 2 1 5: Graphics module 220: Display module 22 5 : Memory controller 230: power management unit 201237615 23 5: memory 240a~240n: task status segment 245: power management firmware 25 5: processor manager 260: task switching logic 3 00: processor state 3 05: task Status segment 310: register 3 1 5 : code segment 3 20 : register 3 2 5 : data segment 3 3 0 : register 3 3 5 : stack segment 3 40 : register 3 4 5 : data segment 3 50 : register 3 5 5 : data segment 3 60 : register 3 65 : data segment 3 70 : register 3 7 5 : register 21 -

Claims (1)

201237615 七、申請專利範圍： 1. 一種方法，包含： 以操作系統（OS )，檢測執行該OS的處理器變遷到 第一電力狀態的機會；及 回應於檢測到該機會，該OS開始該變遷，包括該OS 藉由該處理器觸發任務切換，該任務切換將該處理器的處 理器狀態的至少一部分保存到任務切換儲存庫的至少一部 分，其中該任務切換儲存庫可供並不支援藉由該處理器的 電力狀態變遷的另一任務切換存取。 2. 如申請專利範圍第1項所述之方法，其中該第一電 力狀態包括處理器閒置狀態。 3 ·如申請專利範圍第1項所述之方法，其中該任務切 換包括切換該處理器從在0 S情境中執行任務到在另一情 境中執行電力管理任務。 4.如申請專利範圍第3項所述之方法，其中該另一情 境爲單線程情境。 5 ·如申請專利範圍第3項所述之方法，其中執行該電 力管理任務包括執行韌體。 6.如申請專利範圍第5項所述之方法，其中執行該電 力管理任務包括執行基本輸入/輸出系統（BIOS)碼。 7 .如申請專利範圍第1項所述之方法，其中該任務切 換包括從執行在該0S上運行的應用之任務切換該處理器 ，其中履行該任務切換而不向該應用指示爲了該變遷而凍 結操作的任何需要。 S -22- 201237615 8 .如申請專利範圍第1項所述之方法，其中該任務切 換保存該處理器的處理器狀態的該至少一部分包括該任務 切換將段暫存器狀態、控制暫存器狀態、E F L A G暫存器狀 態、EIP暫存器狀態、及段選擇器狀態的一或更多者保存 到該任務切換儲存庫。 9.—種設備，包含： 記憶體； 耦合到該記憶體的處理器，該處理器執行操作系統（ 〇 S )以檢測執行該處理器變遷到第一電力狀態的機會，且 回應於檢測到該機會，開始該變遷，包括該OS藉由該處 理器觸發任務切換，該任務切換將該處理器的處理器狀態 之至少一部分保存到任務切換儲存庫的至少一部分，其中 該任務切換儲存庫可供並不支援藉由該處理器的電力狀態 變遷的另一任務切換存取。 10·如申請專利範圍第9項所述之設備，其中該OS的 處理器管理器檢測該變遷的該機會。 1 1 ·如申請專利範圍第9項所述之設備，其中該第一 電力狀態包括處理器閒置狀態。 1 2 .如申請專利範圍第9項所述之設備，其中該任務 切換包括該OS切換該處理器從在OS情境中的任務之執 行到在另~情境中的電力管理任務之執行。 1 3 .如申請專利範圍第1 2項所述之設備，其中該另一 情境爲單線程情境。 如申請專利範圍第12項所述之設備’其中該電力 -23- 201237615 管理任務之執行包括韌體之執行。 15.如申請專利範圍第9項所述之設備，其中該 切換包括該OS從在該OS上運行的應用之任務的執 換該處理器，其中履行該任務切換而不向該應用指示 該變遷而凍結操作的任何需要。 1 6 .如申請專利範圍第9項所述之設備，其中該 切換保存該處理器的處理器狀態的該至少一部分包括 務切換將段暫存器狀態、控制暫存器狀態、EFLAG暫 狀態、EIP暫存器狀態、及段選擇器狀態的一或更多 存到該任務切換儲存庫。 · 1 7 . —種電腦可讀取儲存媒體，包含指令儲存於 ，當由一或更多處理器執行該些指令時，履行： 以操作系統（OS )，檢測執行該OS的處理器變 第一電力狀態的機會；及 回應於檢測到該機會，該os開始該變遷，包括f 藉由該處理器觸發任務切換，該任務切換將該處理器 理器狀態的至少一部分保存到任務切換儲存庫的至少 分’其中該任務切換儲存庫可供並不支援藉由該處理 電力狀態變遷的另一任務切換存取。 1 8.如申請專利範圍第1 7項所述之電腦可讀取儲 體，其中該第一電力狀態包括處理器閒置狀態， 1 9 ·如申請專利範圍第1 7項所述之電腦可讀取儲 體’其中該任務切換包括切換該處理器從在OS情境 行任務到在另一情境中執行電力管理任務。 任務 行切 爲了 任務 該任 存器 者保 其上 遷到 % OS 的處 一部 器的 存媒 存媒 中執 S -24- 201237615 20.如申請專利範圍第19項所述之電腦可讀 體，其中該另一情境爲單線程情境。 2 1 .如申請專利範圍第1 9項所述之電腦可讀 體，其中執行該電力管理任務包括執行韌體。 22.如申請專利範圍第21項所述之電腦可讀 體，其中執行該電力管理任務包括執行基本輸^ 統（BIOS)碼。 2 3 .如申請專利範圍第1 7項所述之電腦可讀 體，其中該任務切換包括從執行在該0S上運行 任務切換該處理器，其中履行該任務切換而不向 示爲了該變遷而凍結操作的任何需要。 2 4 .如申請專利範圍第1 7項所述之電腦可讀 體，其中該任務切換保存該處理器的處理器狀態 一部分包括該任務切換將段暫存器狀態、控制暫 、EFLAG暫存器狀態、EIP暫存器狀態、及段選 的一或更多者保存到該任務切換儲存庫。 25.—種系統，包含： 記憶體； 耦合到該記憶體的處理器，該處理器執行操 0S )以檢測執行該處理器變遷到第一電力狀態的 回應於檢測到該機會，開始該變遷，包括該 理器觸發任務切換，該任務切換將該處理器的處 之至少一部分保存到任務切換儲存庫的至少一部 該任務切換儲存庫可供並不支援藉由該處理器的 取儲存媒 取儲存媒 取儲存媒 t /輸出系 取儲存媒 的應用之 該應用指 取儲存媒 的該至少 存器狀態 擇器狀態 作系統（ 機會，且 藉由該處 理器狀態 分，其中 電力狀態 -25- £ 201237615 變遷的另一任務切換存取；及 耦合到該處理器的天線，該天線耦合該系統到無線網 路》 26. 如申請專利範圍第25項所述之系統，其中該OS 的處理器管理器檢測該變遷的該機會。 27. 如申請專利範圍第25項所述之系統，其中該第一 電力狀態包括處理器閒置狀態。 28. 如申請專利範圍第25項所述之系統，其中該任務 切換切換該處理器從在OS情境中的任務之執行到在另一 情境中的電力管理任務之執行。 2 9.如申請專利範圍第28項所述之系統，其中該電力 管理任務之執行包括韌體之執行。 30.如申請專利範圍第25項所述之系統，其中該任務 切換保存該處理器的處理器狀態的該至少一部分包括該任 務切換將段暫存器狀態、控制暫存器狀態、EFLAG暫存器 狀態、EIP暫存器狀態、及段選擇器狀態的一或更多者保 存到該任務切換儲存庫。 S -26-201237615 VII. Patent application scope: 1. A method comprising: detecting, by an operating system (OS), an opportunity for a processor executing the OS to transition to a first power state; and in response to detecting the opportunity, the OS starts the transition Including the OS triggering task switching by the processor, the task switching saves at least a portion of the processor state of the processor to at least a portion of the task switching repository, wherein the task switching repository is not supported by Another task switching access of the processor's power state transition. 2. The method of claim 1, wherein the first power state comprises a processor idle state. 3. The method of claim 1, wherein the switching comprises switching the processor from performing a task in a scenario to performing a power management task in another context. 4. The method of claim 3, wherein the other context is a single threaded context. 5. The method of claim 3, wherein performing the power management task comprises performing firmware. 6. The method of claim 5, wherein performing the power management task comprises performing a basic input/output system (BIOS) code. 7. The method of claim 1, wherein the task switching comprises switching the processor from a task executing an application running on the OS, wherein the task switching is performed without indicating to the application that the transition is for the application Freeze any need for operation. The method of claim 1, wherein the task switching saves at least a portion of a processor state of the processor comprises the task switching a segment register state, a control register One or more of the status, EFLAG register status, EIP register status, and segment selector status are saved to the task switching repository. 9. A device comprising: a memory; a processor coupled to the memory, the processor executing an operating system (〇S) to detect an opportunity to perform the processor transition to a first power state, and in response to detecting The opportunity to initiate the transition, including the OS triggering a task switch by the processor, the task switch saving at least a portion of the processor state of the processor to at least a portion of the task switch repository, wherein the task switch repository is Another task switching access that does not support power state transitions of the processor. 10. The device of claim 9, wherein the processor manager of the OS detects the opportunity for the transition. The device of claim 9, wherein the first power state comprises a processor idle state. The device of claim 9, wherein the task switching comprises the OS switching the execution of the processor from a task in an OS context to a power management task in another context. The device of claim 12, wherein the other scenario is a single-threaded scenario. For example, the device described in claim 12 of the invention is in which the execution of the power -23-201237615 management task includes the execution of the firmware. 15. The device of claim 9, wherein the switching comprises exchanging, by the OS, a task from an application running on the OS, wherein the task is switched without indicating the transition to the application And any need for freezing operations. The device of claim 9, wherein the switching saves at least a portion of a processor state of the processor comprises: switching a segment register state, controlling a scratchpad state, an EFLAG temporary state, One or more of the EIP register status and the segment selector status are stored in the task switching repository. · 7 7 . A computer readable storage medium containing instructions stored when executed by one or more processors, fulfilling: using an operating system (OS) to detect a processor executing the OS An opportunity for a power state; and in response to detecting the opportunity, the os begins the transition, including f triggering a task switch by the processor, the task switch saving at least a portion of the processor state to the task switch repository At least the 'the task switching repository is available to not support another task switching access by the processing power state transition. The computer readable storage device of claim 17, wherein the first power state comprises a processor idle state, and the computer is readable as described in claim 17 The storage bank 'where the task switching includes switching the processor from the OS context task to performing the power management task in another context. The task line is cut for the purpose of the task, and the server is moved to the storage medium of the device of the % OS. S-24-201237615 20. The computer readable body described in claim 19, The other scenario is a single-threaded scenario. The computer readable body of claim 19, wherein performing the power management task comprises performing firmware. 22. The computer readable body of claim 21, wherein performing the power management task comprises executing a BIOS code. 2. The computer readable body of claim 17, wherein the task switching comprises switching the processor from execution of a task running on the OS, wherein the task switching is performed without indicating to the transition. Freeze any need for operation. 2 . The computer readable body of claim 17, wherein the task switching saves a processor state of the processor, the part of the task switching includes a segment register state, a control temporary, and an EFLAG register. One or more of the status, EIP register status, and segment selection are saved to the task switching repository. 25. A system comprising: a memory; a processor coupled to the memory, the processor executing an operation to detect a change in execution of the processor to a first power state in response to detecting the opportunity to initiate the transition Including the processor triggering task switching, the task switching saves at least a portion of the processor to at least one of the task switching repository, the task switching repository is available, and does not support the storage medium by the processor The application that takes the storage medium to take the storage medium t/output to the storage medium refers to the at least the state of the storage medium of the storage medium as a system (opportunity, and by the processor status, wherein the power status is -25 - £ 201237615 Another task switching access of the transition; and an antenna coupled to the processor, the antenna coupling the system to the wireless network. 26. The system of claim 25, wherein the processing of the OS 27. The system of claim 25, wherein the first power state comprises a processor idle state. 28. The system of claim 25, wherein the task switching switches execution of the processor from execution of a task in an OS context to execution of a power management task in another context. The system of claim 28, wherein the execution of the power management task comprises the execution of a firmware. The system of claim 25, wherein the task switching saves the processor state of the processor At least a portion including the task switch saves one or more of a segment register state, a control register state, an EFLAG register state, an EIP register state, and a segment selector state to the task switching repository. S -26-
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