TW201232261A - Memory control method, memory device and memory system - Google Patents
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201232261 六、發明說明: 【發明所屬之技術領域】 本發明是有關於一種半導體記憶體,且特別是一種快 閃記憶體裝置。 【先前技術】 快閃έ己憶體裝置為一種電子可抹拭唯讀記憶體 (Electrically-Erasable Programmable Read-Only Memory , EEPROM),其多個記憶區域可透過程式操作以被抹除或 程式化。傳統的EEPROM —次只會使一個記憶區域被抹除 或程式化。如果不同的記憶體區域可以同時被寫入,則快 閃記憶體裝置可以被更快速的操作。在預定的抹除操作次 數之後’所有種類的快閃記憶體以及EEpR〇M可能合因 絕緣層周邊_謂存資料_存電荷的損耗或退;而耗 損0 次快閃記㈣裝置藉由不需要電力保存儲存树芯 的貝枓的方式來㈣儲存於料4上的料。 =體因提供組㈣物理料,而相對地加快存^ 種特性,快閃記憶體裝置通常被用於電池供電二諸 【發明内容】 偏移位址所產生 函數的方法與展 本發明的-實施例為針對可_ 的初始種子以執行隨機資料的可提供隨機 4 201232261 本發明提出一種記憶體的控制方法,此記憶體的控制 方法包括判斷資料存取是否為隨機的。如果資料存取不是 隨機的’依據第一種子產生第一隨機序列資料。混合第: 隨機序列資料與從記憶體讀取的資料或被寫入至記憶體的 資料。如果資料存取為隨機的,從第一種子產生第二種子。 依據弟一種子產生第二隨機序列資料。以及,混合第二隨 機序列資料與從記憶體讀取的資料或被寫入至記憶體的資 料 、 在本發明之一實施例中’所述第一種子是依據列位 址、頁位址、區塊單元或扇區單元的其中一者。當行位址 不為零時,資料存取為隨機的存取。 在本發明之一實施例中,所述之第二隨機序列資料包 括滿足l+X^+xk多項式的隨機序列資料。在本發明之一實 施例中,所述之K=ll。 在本發明之一實施例中,所述記憶體的控制方法更包 括使用第一種子作為第一區段’依據第一種子產生的第二 種子作為中間區段’以及依據第一或第二種子產生的第三 種子作為產生隨機序列的第三區段。 在本發明之一實施例中,被寫入的資料被從輸入/輸出 接腳接收以及被混合的資料被輸出至頁緩衝器。 本發明提出一種記憶體的控制方法,包括接收偏移位 址值Ν,且Ν為存取位址的行部分。在依據存取位址解隨 機化第一讀取資料之前產生Μ隨機序列資料,其中ν為 201232261 Μ的最大值。以及藉由混合第n個隨機序列資料與第一讀 取資料以解隨機化第一讀取資料。 在本發明之一實施例中’所述之M=N。 在本發明之一實施例中,記憶體的控制方法包括藉由 選擇包含預移輸出的隨機序列資料串路徑以加速產生Μ 隨機序列資料。 本發明提出-種記憶體的控制方法,包括接收偏移植 Ν,Ν為存取位址的行部分。在依據存取位址解隨機化第 -讀取資料之前產生Μ隨機序列資料,其中Μ為從i到 小於存取位址的行部分的結尾的範圍。以及使料N個隨 機序列資料以解隨機化第一讀取資料。 本發明提出-種記憶體裝置,包括快閃記憶胞陣列、 P迎機序列胃料產生器、隨機電路、解隨機電路以及控制電 路。隨機序列資料產生器用以依據第—種子產生至少一隨 機,列貝料串。隨機電路㈣混合隨機序列資料與寫入快 閃.己隐料列的賴。解隨機電路㈣解隨機化從快閃記 憶=列讀取的資料。控制電路用以控制對快閃記憶胞陣 及依據記憶體存取模式啟動隨機序列資料產生 二山:機電路及解隨機電路被設置於頁缓衝器與輸入/ 輸出接腳之間。 够ίΐ發明之—實施例中,在—模式中記憶體位址的一 :二丨-為第一種子以及在第二模式中第二種子被隨 產生°且隨機序列資料產生器用來產生 滿足1+x +x多項式的隨機序列資料。 6 201232261 在本發明之一實施例中,隨機序列資料產生器用以依 據加速信號的回覆以輸出至少一預設隨機序列資料。 本發明提出一種記憶體系統,包括記憶體裝置與記憶 體控制器。記憶體裝置包括快閃記憶胞陣列、隨機序列電 路以及混合器。隨機序列電路用以產生隨機序列資料。混 合器用以混合隨機序列資料與寫入至快閃記憶胞陣列的資 料以及解隨機化從快閃記憶胞陣列讀取的資料。記憶體控 制器包括控制電路’用以控制寫入以及從快閃記憶體胞陣 列透過混合器讀取資料。 在本發明之一實施例中’記憶體系統更包括至少一其 餘記憶體裝置以及隨機序列電路。此至少一其餘記憶體裝 置包括快閃記憶胞陣列。隨機序列電路用以混合隨機序列 資料與將被寫入至快閃記憶胞陣列的資料以及解隨機化從 快閃記憶胞陣列讀取的資料。 本發明之一實施例中,記憶體控制器更包括錯誤控制 電路,用以在從快閃記憶胞陣列讀取資料時執行錯誤更正 功能。 在本發明之一實施例中,快閃記憶胞陣列為多階層胞 型態。 θ 在本發明之一實施例中,記憶體裝置内嵌於固態硬碟 卡。 ^ 在本發明之一實施例中,記憶體裝置以及記憶體控制 器均内嵌於固態硬碟卡。 201232261 更磲卡以及至少一其餘固態硬碟卡。 * 纟月之貫施例中’記憶體系統更包括词服号猶 ==冗餘陣列控制器。伺服器用以控制固態硬碟卡 =碟冗餘陣列控制器用以控制其他固態硬碟卡,14 對應的管理功能。 I具有 在t發明之-實施财,記憶體线更包括 裝置,用以與多個固態硬碟卡通訊。 里 通訊。 在本發明之-實施例中,記憶體系統更包括 盗,用以提供线處理裝置與多_態硬碟卡之間的= 在本發明之-實施例中,記憶體系統更包括網路 接多個處理裝置以及多個固態硬碟卡。 在本發明之一實施例中’記憶體系統更包括蜂巢式 輸器,用以與一蜂巢式網路通訊。 在本發明之一實施例中 器,用以擷取影像。 記憶體系統更包括影像感應 本發明提出一種記憶體裝置,包括快閃記憶胞陣列、 隨機序列資料產生器、混合器以及控制電路。隨機序列資 料產生器用以依據第一種子產生至少一隨機序列資料串。 混合器用以解隨機化從快閃記憶胞陣列讀取的資料。控制 電路用以控制對快閃記憶胞陣列的存取以及依據記憶體存 取模式啟動隨機序列資料產生器,其中在一模式中記憶體 8 201232261 -----Γ -1 位址的一部份被用以作為第一種子以及在第二模式中第二 種子被隨機序列資料產生器產生。 在本發明之一實施例中,混合器更用以以隨機序列資 料隨機化將被寫入至快閃記憶胞陣列的資料。 在本發明之一實施例中,混合器用以透過頁緩衝器接 收從快閃記憶胞陣列讀取的資料,以及隨機化資料被透過 輸入/輸出接腳輸出。 在本發明之一實施例中,控制電路用以依據第一種子 產生中間種子’以及依據中間種子產生隨機序列資料。 在本發明之一實施例中,所述之快閃記憶胞陣列包括 多層胞型態的快閃,以及混合器用以透過按位元的異或操 作以混合多值資料。 【實施方式】 以下將以本發明之實施例以及所附圖示對本發明做更 詳細的說明。然而’本發明可能會以不同的形式體現,且 本發明並不限於這些實施例。而這些實施例用以對本發明 以及本發明所屬領域的先前技術提供徹底且完整的揭露。 在34些圖示中,各階層與各區域的大小以及相對大小可能 會因為說明方便而被誇大。同樣的編號始終對應至同樣的 元件。 /必須了解的是,雖然第一、第二或第三等用語會被用 以描述不同的元件、組件、區域、階層或部分,但這些元 件、組件、區域、階層或部分並不以此為限。這些用語只 被用以區別一元件、組件、區域、階層或部分與另一元件、 201232261 ,u ,、且件區域、階層或部分。因此,以下討論的第一元件、 、、且,區域H或部分可關以表示不超出本發明範圍 的第二元件、組件、區域、階層或部分。 圖1為根據本發明之一實施例所繪示的快閃記憶體裝 置的功能方塊圖。 请參照®1 1,快Μ記憶體裝i包括記憶胞陣列100,記 憶胞陣列1GG具有列(_,其對應字線為:WL)以及行 (column,其對應位元線為:BL)排列的記憶胞。每個記 憶胞儲存1個位元的資料或訄個位元(multi bi〇的資料 (M為大於2的正整數)。每個記憶胞的形式可以是具有 電荷儲存層的記憶胞,例如浮柵(fl〇atinggate)、電荷陷 味層(charge trap layer) ’或具有可變電阻元件的記憶胞。 S己憶胞陣列100的形式可以是單層(2維)陣列結構或多 層陣列結構,也可以是垂直類型或堆疊類型的3維陣列結 構。記憶體裝置可以是反及(N AND )類型的快閃記憶體。 列選擇電路200被控制電路300所控制,並被用以執 列選擇以及於記憶胞陣列100的列上的驅動操作。控制電 路300用以控制快閃記憶體裝置的整體操作。頁緩衝電路 400被控制電路300所控制,並如同感測放大器(sense amplifier)或寫入驅動器(write driver)根據操作的模式操 作。舉例來說’在讀取操作期間,頁緩衝電路4〇〇如同^ 測放大器,感測從連接至記憶胞的被選擇的列的記憶胞的 資料。在程式化期間,頁緩衝電路400可作為寫入驅動器, 以驅動資料進入連接至被選擇的列的記憶胞。頁緩衝哭 201232261 111 對應缝元線或位元雜❹缓衝器。 記憶胞儲存多位元資料,頁緩衝電路400的各個 頁,可以有2個以上的閂鎖器(latch)。 ㈣。^續*參照圖1 ’行選擇電路500被控制邏輯300所 L ’百式化模^巾透過預鮮元依序選擇行 二。隨機產生器電路_ (以T簡稱隨機 ;隧機化透過輪入/輸出介面7〇〇傳輸的(例 ^ ’,至輸人/輸出接腳的或從輸人/輸出接腳接收的 ==料。Ϊ機產生器電路_也用來依據控制邏 -、工,以解隧機化從頁緩衝電路400接收並透過行 傳輪㈣料。根據本實施例,被解J二 貝+被包括輸人/輸出接腳的輸人/輸出介面輸出 ^夕相及至㈣記憶職置。在本發明之-實施例中, k機產生器電路_不只用來對整頁(fuiipage)的 „化操作也用來對少於整頁的#料(例如 = 域的資料、扇區資料、多於扇區資料 以及少於扇區資料的資料等)執伊料^機^;貝料 對此做更為詳細的解說。—化。以下將 電瓣裝置的電荷量轉電壓二、== 佈因為相鄰記《的電荷損耗細合(稱為字m電^ 正確地存取記⑽會受騎_軌所料。^ 1)時’ 11 201232261^ 差。資料的隨機化(例如’將資料與隨機序列混合)會減 少a己憶胞目為?線㉝合造成軸界電壓差的魏。換句話 說’虽心隐胞的狀態更均勻的分佈日夺,相對於資料(1 遺機化 之刖’其字線耦合的發生會被減少。 在本發明之實施例中,隨機產生器的操作可以被選擇 地執行。舉例來說,當被請求存取狀的㈣或特定區域 時’隨機產生器電路_被絲執行其隨機產生器的操作。 圖2為圖1中由所有位元線(all bit line,ABL)記憶 體架構或奇偶(odd-even)記憶體架構的記㈣區塊所組 成的記憶胞陣列的範例的示意圖。記憶胞陣列刚的架構 範例在以下做綱H施例巾,NAND㈣記憶體裝 置包括被切割為1024個區塊的記憶胞陣列1〇〇將在以下做 說明。儲存於各個區塊的資料可叫㈣地抹除或透過纪 憶體子區塊單元抹除。在-實糊+,織體區塊或記憶 體子區塊為儲存元件巾最小料元,且記憶體區塊或記憶 體子區塊同時被抹除。各個記憶體區塊,舉例來說,有對 應至位元線(例如,1KB的位元線)的列。在參照所有位 元線架構的實施例中,記憶體區塊的所有位元線在讀取或 程式化操作時可以被同時地選擇4字線中被列選擇電路 細所選擇的且連接至所有位元線的儲存元件可以同時被 程式化。 在-實施例中,在相同的行的多數個儲存元件被串聯 以形成NAND字串。NAND字串的其中一端透過被字事遽 擇線SSL控制的選擇電晶體以被連接至對應的位元線,而 12 201232261 • X -* 控制的選擇電晶體以被連 另-·端透過被接地選擇線GSL 接至通用來源線CSL。 -Λ另一參的實施例中,位元線被分為偶位 几、uBLe以及奇位元線BLg。在奇偶位元線架射,在通 第 立元線的儲存元件在第-時間被程式 化’而在賴子線巾且連接至偶位元線的儲存 時間被程式化。 圖3為根據本發明之一範例實施例所緣示的圖i中的 隨機產生器電路的功能方塊圖。 ,參照圖3,根據本發明之—範例實施例 =_包括時序產生器⑽、選擇器62〇、虛擬隨機序 f f㈣、自由運行烟器_以及混合器㈣。而資 庠ίΐί Γ°包括時序產生器610、選擇器62°、虛擬隨機 序列產生器630以及自由谨;、日,丨„„ 汉目由運仃偵測裔640,這些裝置耦接 運作並依序地赵隨機相資料㈣。—崎機序列資料 隨ί序列RS。混合11㈣也用以提取與_序列 貝;口的資料’例如被從記憶胞陣列⑽讀取用以產生 解隨機化資料的資料。混合器㈣用以透過適用於單階層 ㈣態的㈣記憶體的二進制單元混合,也可以用以透過 位(blMV1Se)操作以混合多位元值,例如透過逐位的異 或(XOR)操作。 、理娜▲生益610用以產生時序信號CLK。選擇器620 G〜入L號CLK以及讀取/寫入致能訊號RE/WE其中之 -以回應從自由運行伯測器64〇接收的選擇信號(自由運 13 201232261 行信號)FRS。舉例來說,當自由運行信號FRS被啟動時, 選擇斋620會從時序產生器610選擇時序信號clk作為其 輸出L 5虎。當自由運行信號FRS被阻止啟動時,選^ 620選擇讀取/寫入致能訊號RE/WE。被選擇器62〇選擇的 信號CLK或RE/WE會被提供給虛擬隨機序列產生器63〇 作為隨機序列時序信號CLK_RS以依據預定的種子依序產 生隨機序列資料RSD。 在一範例實施例中,預定的種子可以由列位址、頁位 址、區塊單元、位址或扇區單元的其中一者所組成。但是, 需了解的是,種子的預定方式不以上述方式為限。根據本 發明之一貫施例,當被請求對任一頁存取時,頁位址位會 被k供給虛擬隨機序列產生器630以作為種子。此種子會 被作為一常數值而提供給虛擬隨機序列產生器630。用來 隨機化提供給混合器650的第一資料或產生初始隨機序列 資料的種子稱為第一種子。根據本發明之一實施例,參考 頁的扇區單元的列位址與行位址也可以作為初始種子。 在一範例實施例中,虛擬隨機序列產生器63()可以搭 配由移位暫存器以及—個或多個x〇R邏輯閘組成的線^ 回饋移位暫存器.(linear feedback shift register)來實作。 ^是,需了解的是,虛擬隨機序列產生器63〇可以由虛擬 隨機數字(或,亂數)序列產生器、循環冗餘碼(cycUc fedundancy c〇de,CRC )產生器或類似裝置組成。 繼續參照圖3,自由運行偵測器640依據行偏移值產 生自由運行信號!?!^。在一範例實施例中,行偏移值可以 201232261 x i 疋存取响求中提供的行位址的值。根據一實施例,當被請 求於整頁資料的讀取或寫人操作時,行偏移值可以是零。 當被睛求7遺機’’存轉作時,行位址或偏移值不為零。舉 例來說’頁資料的第—存取點由具有位址的值為零的行位 關決定’而其㈣的棘點由具有大於零的值的 灯位址所分別決定。在此,資料讀出位置可以包括頁緩衝 電路400的行位置或—頁的行位置。同樣地,根據存取請 求(或’存取點)儲存資料的位置可以透過行位址而被決 疋為不同的。在此,行偏移值或偏移位址可以互換使用。 自由運行偵測器640包括計數器641以及比較器 642。計數器641可以同步操作由時序產生器61〇產生的時 序指號CKL。比較器642比較計數器641的計數值以及行 偏移值並根據比較結果以產生自由運行錢FRS。舉例來 說,當计數器641的初始值與行偏移值相同時,自由運行 信號FRS會被阻止啟動。當計數器⑷的初始值與行偏移 值不同時,自由運行信號FRS會被啟動。在上述的後一種 情況下’當計數器641的計數值達到行偏移值時,比較器 642會阻止啟動自由運行信號FRS。 當於讀取或寫入操作且行偏移值為零時,計數器641 不會動作,且自由運行信號FRS被阻止啟動。自由運行信 號FRS雜止啟練示—存取請求與整頁資财關。在此 種清況下讀取/寫入致能信號RE/WE會被選擇以及於資 料輸入/輸出尹被切換的RE/WE會透過選擇器62〇提供給 15 201232261 r Γ 虛擬,機序列產生器63〇。於讀取/寫入請求下,讀取/寫入 致能^號RE/WE會被娜以提供㈣至混合器65〇。 畐於讀取/寫入操作且行偏移值不為零時,計數器641 執行《十數作。也就是說,當行偏移值與計數^ 641的初 二值不同時,自由運行偵測器64〇同步利用時序信號clk 執行計數操作以及啟動自由運行信號聊。啟動自由運行 b虎FRS表示-存取請求與隨機資料有關。在此種情況 下,時序產生器όΐο產生的時序信號CKL被選擇器62〇 選擇且此時序信號CKL被提供給虛擬隨機序列產生哭 ㈣’以及虛擬隨機序列產生器㈣會同步利用時序作^ 序產生隨機序職料。產生用來大幅度的隨機化 第一貝料的初始隨機序列資料的操作稱為自由運行操作。 當計數值達到體積偏移值時,自由運行偵測器_阻止啟 ’自由運行信號FRS。當自由運行信號FRS的狀態從啟動 狀癌過渡至阻止啟動狀態時,於#料的輸人/輸㈣讀取/ 寫入致能錢RE/WE會㈣換,且讀取㉟ =E會透過選擇器63。被提供給虛擬隨機序列產j 混合器650執行隨機化與解隨機化功能。舉例 在讀取操作時,混合ϋ 65〇邏輯地結合_相資料咖 與從記憶胞陣列透過頁緩衝器_以及行選擇電路500读 取的隨機化的資料,以輸出解隨機化的資料至輸入/輸出二 面期。在寫入操作時,混合器650邏輯地結合隨機序列 資料RSD與透過輸入/輸出介面提供的資料,以輪= 201232261^ 合的資料作為隨機化的資料至行選擇電路5〇〇,以及使此 結合的資料被寫入至記憶胞陣列100。混合器650可以包 括邏輯電路,例如XOR閘,以實現邏輯性的附加功能。 在位元組單元(byte-unit)資料被提供至混合器65〇的情 況下’隨機序列資料位元可以被邏輯地與各個被讀取或程 式化的資料位元結合。 自由運行#號FRS可以依據被請求的存取是否為隨 機資料存取而具有主動高水平(active_high level)以及主 動低水平(active-low level)其中之一。 圖4為根據本發明之一範例實施例所綠示之用以說明 快閃記憶體裝置的讀取操作的時序示意圖。 讀取操作可以依據輸入的指令以及位址的組合來進 行。舉例來說,如圖4所示,第一指令〇〇h、位址 C1C2R1R2R3以及第二指令3〇h可以被依序提供給快閃記 憶體裝置。被提供的位址C1C2R1R2R3可以包括行位址 C1C2以及列位址R1R2R3。因為行偏移值為行位址C1C2 且行位址C1C2不為零’所以資料存取為隨機的,並以列 位址R1R2R3作為種子來產生初始隨機序列資料。此外, 當被隨機化的單位小於一頁時,行位址或扇區位址可以被 作為開始種子以產生中間種子,此中間種子用以反過來產 生隨機序列資料以解隨機化從快閃記憶胞陣列讀取的資 料。 在第二指令3〇11被提供至快閃記憶體裝置之後,在時 間區間tR中’頁緩衝電路400將資料從記憶胞陣列100 17 201232261 讀出作為對控制邏輯300的控制的回應。如圖4所示,在 時間區間tR中,就緒/忙碌信號可以被維持於低水平。 因為行偏移值不為零且與計數器641的初始值不同,故自 由運行偵測器640啟動自由運行信號FRS。也就是說,時 序彳5號CLK被透過選擇器620選擇並被提供至虛擬隨機序 列產生器630。虛擬隨機序列產生器63〇利用列位址 R1R2R3作為種子產生初始隨機序列資料。計數器641在 第二指令30h輸入後依據時序信號CLK開始計數。 行位址以及行偏移值被讀取進入比較器642。當計數 器641的計數值達到行偏移值時,比較器642阻止啟動自 由運行信號FRS。當自由運行信號FRS被阻止啟動時,時 序信號CLK不會被選擇器620選擇且自由運作操作被停 止。此時’虛擬隨機序列產生器630被提供初始隨機序列 資料作為隨機化第一資料的種子。在時間區間tR之後,頁 緩衝電路400的資料(也就是,已隨機化的資料)可以根 據讀取/寫入致能信號RE/WE的切換並透過行選擇電路 500被提供至隨機產生器電路600。此時,虛擬隨機序列產 生器630會與讀取/寫入致能信號RE/WE的切換同步並依 序產生隨機序列資料RSD。混合器650邏輯地結合隨機序 列資料RSD與從行位址C1C2選擇的資料,以及此結合後 的資料會被作為解隨機化的資料並透過輸入/輸出介面700 被提供至外部裝置。解隨機化的操作可以被重複執行直到 被要求存取的資料全部被輸出。 201232261201232261 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor memory, and more particularly to a flash memory device. [Prior Art] A flash memory device is an Electrically-Erasable Programmable Read-Only Memory (EEPROM), and multiple memory areas can be erased or programmed by a program operation. . Traditional EEPROM - only erases or stylizes a memory area. If different memory areas can be written at the same time, the flash memory device can be operated more quickly. After the predetermined number of erasing operations, 'all kinds of flash memory and EEpR〇M may be due to the loss or retreat of the storage _ stored data _ stored data charge; and the loss of 0 flash memory (four) device by not needing The electricity is stored in a manner that stores the shell of the tree core (4) the material stored on the material 4. = The physical factor provides the group (4) physical material, and relatively accelerates the storage characteristics. The flash memory device is usually used for battery power supply. [Inventive content] The method for generating the function of the offset address and the invention - The embodiment is a randomizable method for performing initial data for the initial seed. The present invention proposes a memory control method, and the method for controlling the memory includes determining whether the data access is random. If the data access is not random, the first random sequence data is generated based on the first seed. Hybrid: Random sequence data and data read from memory or data written to memory. If the data access is random, a second seed is generated from the first seed. The second random sequence data is generated according to a child. And mixing the second random sequence data with the data read from the memory or the data written to the memory, in an embodiment of the invention, the first seed is based on a column address, a page address, One of a block unit or a sector unit. When the row address is not zero, the data access is random access. In an embodiment of the invention, the second random sequence data includes random sequence data satisfying a l+X^+xk polynomial. In one embodiment of the invention, said K = ll. In an embodiment of the present invention, the method for controlling the memory further includes using the first seed as the first segment 'the second seed generated according to the first seed as the intermediate segment' and according to the first or second seed The resulting third seed acts as a third segment that produces a random sequence. In one embodiment of the invention, the data being written is received from the input/output pins and the mixed material is output to the page buffer. The present invention proposes a method of controlling a memory, comprising receiving an offset address value Ν and Ν being a line portion of an access address. The random sequence data is generated before the first read data is randomly decoded according to the access address, where ν is the maximum value of 201232261 Μ. And decomposing the first read data by mixing the nth random sequence data with the first read data. In one embodiment of the invention, the stated M = N. In one embodiment of the invention, the memory control method includes accelerating the generation of the 随机 random sequence data by selecting a random sequence data string path including the pre-shifted output. The present invention proposes a method of controlling a memory, comprising receiving a partial migration, and Ν is a line portion of an access address. The random sequence data is generated prior to randomizing the first-read data according to the access address, where Μ is the range from i to the end of the line portion that is smaller than the access address. And N random sequence data is used to solve the randomized first read data. The present invention proposes a memory device comprising a flash memory cell array, a P-on-the-sequence gastric material generator, a random circuit, a de-random circuit, and a control circuit. The random sequence data generator is configured to generate at least one random, column-behaved string according to the first seed. Random circuit (4) mixed random sequence data and write flash. The random circuit (4) solves the randomization of the data read from the flash memory = column. The control circuit is configured to control the flash memory cell array and start the random sequence data generation according to the memory access mode. The two circuit: the machine circuit and the de-random circuit are disposed between the page buffer and the input/output pin. In the embodiment, in the mode, one of the memory addresses is: the second seed is the first seed, and in the second mode, the second seed is generated and the random sequence data generator is used to generate the 1+ Random sequence data for the x + x polynomial. 6 201232261 In an embodiment of the invention, the random sequence data generator is configured to output at least one predetermined random sequence data according to the reply of the acceleration signal. The present invention provides a memory system including a memory device and a memory controller. The memory device includes a flash memory cell array, a random sequence circuit, and a mixer. A random sequence circuit is used to generate random sequence data. The mixer is used to mix random sequence data with data written to the flash memory cell array and to de-randomize the data read from the flash memory cell array. The memory controller includes control circuitry ' to control writing and reading data from the flash memory array through the mixer. In one embodiment of the invention, the 'memory system further includes at least one remaining memory device and a random sequence circuit. The at least one remaining memory device includes a flash memory cell array. The random sequence circuit is used to mix the random sequence data with the data to be written to the flash memory cell array and to de-randomize the data read from the flash memory cell array. In an embodiment of the invention, the memory controller further includes an error control circuit for performing an error correction function when reading data from the flash memory cell array. In one embodiment of the invention, the flash memory cell array is a multi-level cell type. θ In one embodiment of the invention, the memory device is embedded in a solid state hard disk card. In one embodiment of the invention, both the memory device and the memory controller are embedded in a solid state hard disk card. 201232261 More Leica and at least one remaining solid state hard drive card. * In the case of the month of the month, the memory system includes the word service number == redundant array controller. The server is used to control the solid state hard disk card = the disk redundant array controller is used to control other solid state hard disk cards, 14 corresponding management functions. I have invented the implementation of the memory, and the memory line further includes means for communicating with a plurality of solid state hard disk cards. Communication. In the embodiment of the present invention, the memory system further includes a pirate for providing between the line processing device and the multi-state hard disk card. In the embodiment of the present invention, the memory system further includes a network connection. Multiple processing devices and multiple solid state hard disk cards. In one embodiment of the invention, the 'memory system further includes a cellular transmitter for communicating with a cellular network. In an embodiment of the invention, the image is captured. The memory system further includes image sensing. The present invention provides a memory device comprising a flash memory cell array, a random sequence data generator, a mixer, and a control circuit. The random sequence data generator is configured to generate at least one random sequence data string based on the first seed. The mixer is used to de-randomize the data read from the flash memory cell array. The control circuit is configured to control access to the flash memory cell array and start the random sequence data generator according to the memory access mode, wherein in a mode, the memory 8 201232261 -----Γ -1 address The portion is used as the first seed and in the second mode the second seed is generated by the random sequence data generator. In one embodiment of the invention, the mixer is further configured to randomize data to be written to the flash memory cell array in a random sequence of data. In one embodiment of the invention, the mixer is configured to receive data read from the flash memory cell array through the page buffer, and the randomized data is output through the input/output pin. In one embodiment of the invention, the control circuit is operative to generate an intermediate seed' based on the first seed' and to generate random sequence data based on the intermediate seed. In one embodiment of the invention, the flash memory cell array includes a flash of a multi-layer cell type, and the mixer is configured to mix multi-value data by bitwise XOR operation. [Embodiment] Hereinafter, the present invention will be described in more detail with reference to the embodiments of the present invention and the accompanying drawings. However, the invention may be embodied in different forms, and the invention is not limited to the embodiments. These embodiments are provided to provide a thorough and complete disclosure of the present invention and the prior art in the field to which the invention pertains. In the 34 illustrations, the size and relative size of each level and region may be exaggerated for convenience of explanation. The same number always corresponds to the same component. / It must be understood that although the first, second or third terms are used to describe different elements, components, regions, layers or parts, these elements, components, regions, classes or parts are not limit. These terms are only used to distinguish one element, component, region, layer, or portion with another element, 201232261, u, and a region, hierarchy, or portion. Thus, a first element, or a portion, or a portion, or a portion, may be referred to as a second element, component, region, layer, or portion that does not depart from the scope of the invention. 1 is a functional block diagram of a flash memory device in accordance with an embodiment of the present invention. Please refer to ®1 1. The memory device includes a memory cell array 100. The memory cell array 1GG has a column (_, whose corresponding word line is: WL) and a row (column whose corresponding bit line is: BL). Memory cell. Each memory cell stores 1 bit of data or 1 bit (multi bi〇 data (M is a positive integer greater than 2). Each memory cell can be in the form of a memory cell with a charge storage layer, such as floating a flip-ring gate, a charge trap layer or a memory cell having a variable resistive element. The form of the memory cell array 100 may be a single-layer (2-dimensional) array structure or a multi-layer array structure. It may also be a 3-dimensional array structure of a vertical type or a stacked type. The memory device may be a flash memory of the (N AND) type. The column selection circuit 200 is controlled by the control circuit 300 and is used for selection. And a driving operation on the column of the memory cell array 100. The control circuit 300 is used to control the overall operation of the flash memory device. The page buffer circuit 400 is controlled by the control circuit 300 and acts like a sense amplifier or write The write driver operates according to the mode of operation. For example, during a read operation, the page buffer circuit 4 is like a sense amplifier, sensing from the selected column connected to the memory cell. Memory cell data. During the stylization, the page buffer circuit 400 can be used as a write driver to drive data into the memory cell connected to the selected column. Page buffer cry 201232261 111 Corresponding seam line or bit churn buffer The memory cell stores multi-bit data, and each page of the page buffer circuit 400 may have more than two latches. (4) Continued * Refer to FIG. 1 'The row selection circuit 500 is controlled by the logic 300. 'Hundred-type molds and wipes through the pre-fresh elements to select row two. Random generator circuit _ (T abbreviated as random; tunneling through the wheel input / output interface 7 〇〇 transmission (example ^ ', to the input /= Output of the output pin or received from the input/output pin. The downtime generator circuit_ is also used to receive and pass through the page buffer circuit 400 in accordance with the control logic. According to the present embodiment, the input/output interface output of the input/output pin is included and the memory is placed. In the embodiment of the present invention, the k machine The generator circuit _ is not only used for the entire page (fuiipage) #料# (for example, domain data, sector data, more than sector data, and less than sector data, etc.), the material is ^^^; In the following, the charge amount of the electric valve device is turned to a voltage of two, == cloth because the adjacent charge "the charge loss is fine (referred to as the word m electric ^ correct access (10) will be subject to riding - track. ^ 1) When '11 201232261^ Poor. Randomization of data (such as 'mixing data with random sequences) will reduce the number of cells that are caused by the line 33. In other words, the heart is cryptic. The state of the distribution is more uniform, and the occurrence of word line coupling is reduced relative to the data (1). In an embodiment of the invention, the operation of the random generator can be selectively performed. For example, the random generator circuit _ is subjected to the operation of its random generator when requested to access the (four) or specific region. 2 is a diagram showing an example of a memory cell array of FIG. 1 composed of all (iv) blocks of all bit line (ABL) memory architectures or odd-even memory architectures. The architecture of the memory cell array is shown in the following example. The NAND (four) memory device includes a memory cell array that is cut into 1024 blocks. The data stored in each block can be erased by (4) or erased by the memory block unit. In the real paste +, the texture block or the memory sub-block is the smallest element of the storage component, and the memory block or the memory sub-block is simultaneously erased. Each memory block, for example, has a column corresponding to a bit line (e.g., a 1 KB bit line). In an embodiment with reference to all bit line architectures, all bit lines of the memory block can be simultaneously selected in the 4-word line selected by the column selection circuit and connected to all during read or program operations. The storage elements of the bit lines can be programmed at the same time. In an embodiment, a plurality of storage elements in the same row are concatenated to form a NAND string. One end of the NAND string is connected to the corresponding bit line through the selection transistor controlled by the word selection line SSL, and 12 201232261 • The X-* controlled selection transistor is connected to the other end. The ground selection line GSL is connected to the universal source line CSL. In another embodiment of the embodiment, the bit lines are divided into even bits, uBLe, and odd bit lines BLg. In the parity bit line, the storage elements on the pass line are programmed at the first time and the storage time in the line and connected to the even lines is programmed. 3 is a functional block diagram of the random generator circuit of FIG. i in accordance with an exemplary embodiment of the present invention. Referring to Figure 3, an exemplary embodiment of the present invention includes a timing generator (10), a selector 62, a virtual random sequence ff (four), a free running cigarette _, and a mixer (4). The resource 庠 包括 包括 、 includes the timing generator 610, the selector 62°, the virtual random sequence generator 630, and the free ;;, 丨 „„ 汉 由 汉 仃 640 640 640 640 640 640 640 640 640 640 640 640 640 640 Preface to Zhao random phase data (4). —Sakiji sequence data with the sequence RS. Mixing 11 (4) is also used to extract data from the _sequence; the data of the port is read, for example, from the memory cell array (10) to generate data for de-randomizing the data. The mixer (4) is used to mix binary units of (4) memory suitable for a single-level (quad) state, and can also be used to transmit multi-bit values by bit (blMV1Se) operation, for example, by bitwise exclusive OR (XOR) operation. , Lina ▲ Shengyi 610 is used to generate the timing signal CLK. The selector 620 G goes into the L number CLK and the read/write enable signal RE/WE - in response to the selection signal (freewheel 13 201232261 line signal) FRS received from the free running detector 64. For example, when the free running signal FRS is activated, the selection 620 will select the timing signal clk from the timing generator 610 as its output L 5 tiger. When the free running signal FRS is prevented from starting, the selection 620 selects the read/write enable signal RE/WE. The signal CLK or RE/WE selected by the selector 62 is supplied to the virtual random sequence generator 63 as a random sequence timing signal CLK_RS to sequentially generate random sequence data RSD in accordance with a predetermined seed. In an exemplary embodiment, the predetermined seed may be comprised of one of a column address, a page address, a block unit, an address, or a sector unit. However, it should be understood that the predetermined method of seeding is not limited to the above. In accordance with a consistent embodiment of the present invention, when requested to access any page, the page address bits are supplied by k to the virtual random sequence generator 630 as a seed. This seed is provided to the virtual random sequence generator 630 as a constant value. The seed used to randomize the first data provided to the mixer 650 or to generate the initial random sequence data is referred to as the first seed. According to an embodiment of the present invention, the column address and row address of the sector unit of the reference page can also be used as an initial seed. In an exemplary embodiment, the virtual random sequence generator 63() can be paired with a shift register and one or more x〇R logic gates. ) to implement. ^ Yes, it is to be understood that the virtual random sequence generator 63 can be composed of a virtual random number (or random number) sequence generator, a cyclic redundancy code (CRC) generator or the like. With continued reference to Figure 3, the free running detector 640 generates a free running signal based on the line offset value! ?!^. In an exemplary embodiment, the row offset value may be 201232261 x i 疋 access the value of the row address provided in the request. According to an embodiment, the row offset value may be zero when requested for a full page material read or write operation. When it is turned into a 7-return, the row address or offset value is not zero. For example, the first access point of the 'page data is determined by the row bit with the address value of zero and the spine of the (4) is determined by the lamp address having a value greater than zero. Here, the material readout position may include the row position of the page buffer circuit 400 or the row position of the page. Similarly, the location where the data is stored according to the access request (or 'access point') can be determined to be different by the row address. Here, the line offset value or the offset address can be used interchangeably. The free running detector 640 includes a counter 641 and a comparator 642. The counter 641 can synchronously operate the timing finger CKL generated by the timing generator 61. The comparator 642 compares the count value of the counter 641 with the line offset value and generates a free running money FRS based on the comparison result. For example, when the initial value of the counter 641 is the same as the line offset value, the free running signal FRS is prevented from starting. When the initial value of the counter (4) is different from the line offset value, the free running signal FRS is activated. In the latter case described above, when the count value of the counter 641 reaches the line offset value, the comparator 642 blocks the start of the free running signal FRS. When a read or write operation and the line offset value is zero, the counter 641 does not operate and the free running signal FRS is prevented from starting. The free running signal FRS is mixed with the instructions - access request and full page wealth. In this condition, the read/write enable signal RE/WE will be selected and the RE/WE switched on the data input/output will be provided to the 15 through the selector 62. 201232261 r Γ Virtual, machine sequence generation 63〇. Under the read/write request, the read/write enable ^ number RE/WE will be provided by (4) to the mixer 65〇. In the case of a read/write operation and the line offset value is not zero, the counter 641 performs "ten number." That is, when the line offset value is different from the first two values of the count ^ 641, the free running detector 64 〇 synchronizes the counting operation with the timing signal clk and starts the free running signal chat. Start free running b Tiger FRS indicates that the access request is related to random data. In this case, the timing generator όΐ 产生 generated timing signal CKL is selected by the selector 62 且 and the timing signal CKL is supplied to the virtual random sequence to generate a cry (four) ' and the virtual random sequence generator (4) is synchronized using the timing sequence Generate random order materials. The operation of generating the initial random sequence data for the randomization of the first bait material is called a free running operation. When the count value reaches the volume offset value, the free running detector _ blocks the free running signal FRS. When the state of the free running signal FRS transitions from the start-up cancer to the start-up prevention state, the input/output (4) read/write enable money RE/WE will change (4), and the read 35 = E will pass through. Selector 63. The virtual random sequence generation j mixer 650 is provided to perform a randomization and de-randomization function. For example, during a read operation, the hybrid 〇 65 〇 logically combines the _ phase data coffee with the randomized data read from the memory cell array through the page buffer _ and the row selection circuit 500 to output the derandomized data to the input. / Output two-sided period. In the write operation, the mixer 650 logically combines the random sequence data RSD with the data provided through the input/output interface, and uses the data of round=201232261 as the randomized data to the row selection circuit 5〇〇, and makes this The combined data is written to the memory cell array 100. Mixer 650 can include logic circuitry, such as XOR gates, to implement additional logic functionality. In the case where byte-unit data is supplied to the mixer 65, the 'random sequence data bits can be logically combined with each of the read or programmed data bits. Free Run ##FRS can have one of active_high level and active-low level depending on whether the requested access is random data access. 4 is a timing diagram illustrating the read operation of a flash memory device in accordance with an exemplary embodiment of the present invention. Read operations can be performed based on the input instructions and the combination of addresses. For example, as shown in FIG. 4, the first instruction 〇〇h, the address C1C2R1R2R3, and the second instruction 3〇h may be sequentially supplied to the flash memory device. The provided address C1C2R1R2R3 may include a row address C1C2 and a column address R1R2R3. Since the row offset value is the row address C1C2 and the row address C1C2 is not zero', the data access is random, and the column address R1R2R3 is used as a seed to generate the initial random sequence data. In addition, when the randomized unit is less than one page, the row address or the sector address can be used as a starting seed to generate an intermediate seed, which is used to generate random sequence data in reverse to de-randomize from the flash memory cell. The data read by the array. After the second instruction 3〇11 is supplied to the flash memory device, the page buffer circuit 400 reads the material from the memory cell array 100 17 201232261 as a response to the control of the control logic 300 in the time interval tR. As shown in Fig. 4, in the time interval tR, the ready/busy signal can be maintained at a low level. Since the line offset value is not zero and is different from the initial value of the counter 641, the free running detector 640 starts the free running signal FRS. That is, the timing CLK No. 5 is selected by the selector 620 and supplied to the virtual random sequence generator 630. The virtual random sequence generator 63 uses the column address R1R2R3 as a seed to generate initial random sequence data. The counter 641 starts counting in accordance with the timing signal CLK after the second command 30h is input. The row address and row offset values are read into comparator 642. When the count value of the counter 641 reaches the line offset value, the comparator 642 blocks the activation of the free running signal FRS. When the free running signal FRS is prevented from being activated, the timing signal CLK is not selected by the selector 620 and the free running operation is stopped. At this time, the virtual random sequence generator 630 is supplied with the initial random sequence data as a seed for randomizing the first data. After the time interval tR, the data of the page buffer circuit 400 (i.e., the randomized data) can be supplied to the random generator circuit through the row selection circuit 500 according to the switching of the read/write enable signal RE/WE. 600. At this time, the virtual random sequence generator 630 synchronizes with the switching of the read/write enable signal RE/WE and sequentially generates the random sequence data RSD. The mixer 650 logically combines the random sequence data RSD with the data selected from the row address C1C2, and the combined data is used as the derandomized data and supplied to the external device through the input/output interface 700. The operation of de-randomization can be repeated until all the data requested to be accessed is output. 201232261
-v *· «· f-I 儲存於頁緩衝電路400的資料可以透過使用指令以及 位址組來額外提供至外部裝置。在此種情況下,:^ 4所 示,就緒/忙碌信號可以被維持於高水平。舉例來說, 第一指令05h、位址C1C2以及第二指令EOh可以被依序 提供至快閃記憶體裝置。此時,被提供的位址只包括行位 址C1C2,且行位址C1C2不為零。初始隨機序列資料rsd 會透過隨機序列產生區塊650的自由運行操作,以及使用 根據先前提供的列位址R1R2R3所決定的種子而被產生, 其本質上同於前述之說明。 如圖4所示,在第二指令E〇h被接收以及經過產生初 始種子的時間區間之後,資料會被輸出。用來準備初始種 子所花費的時間區間(例如,13微秒)會比時間區間tR (例如’ 30微秒)短。 圖5為根據本發明之另一範例實施例所繪示之用以說 明快閃§己憶體裝置的讀取操作的時序示意圖。 讀取操作可以依據輸入的指令以及位址的組合來進 行。舉例來說,如圖5所示,第一指令⑼h、位址 C1C2R1R2R3以及第二指令3〇h可以被依序提供給快閃記 憶體裝置。被提供的位址C1C2R1R2R3可以包括行位址 cic2以及列位址腿如。在本實施例中行位址ac2 為零’且行偏移值為零。因為行偏移值為零,所以資料不 是隨機地存取’且自由運作操作不會被執行。 在第一指令3〇h被提供至快閃記憶體裝置之後 ,在時 間區間tR + ’頁缓衝電路4〇〇將資料從記憶胞陣列1〇〇 201232261ir 讀出作為對控制邏輯300的控制的回應。如圖5所示,在 時間區間tR中,就緒/忙碌信號可以被維持於低水平。 機產生器電路6〇〇依序使用接收到的列位址rir2R3作 為種子以產生隨機序列資料RSD,並邏輯地合併隨機序列 資料RSD與從頁緩衝電路4〇〇讀取的資料。合併後的資料 可以作為解隨機化的資料透過輸入/輸出電路700而被提 供至外部裂置。 圖6為根據本發明之範例實施例所繪示之用以說明快 閃記憶體裝置的寫入操作的時序示意圖。 ^寫入操作可以依據輸入的指令以及位址的組合來進 行。舉例來說,如圖5所示,第一指令8〇h、位址 C1C2R1R2R3以及第二指令1〇h可以被依序提供給快閃記 憶體裝置。被提供的位址C1C2R1R2R3可以包括行位址 C1C2以及列位址R1R2R3。在本實施例中,行位址C1C2 =為零,且行偏移值為行位址clc2的值也不為零。所以 貧料存取為隨機的,並以列位址R1R2R3作為種子來產生 初始隨機序列資料。 因為行偏移值不為零,自由運行偵測器640啟動自由 丁信號FRS。也就是說,時序產生H 610產生的時序信 號CKL被選擇器62〇選擇。且時序信號cKL被提供給虛 ,隨機序列產生n㈣以產生隨機序列資料RSD。當計數 器641的„十數值達到列偏移值時’自由運行债測器"ο阻 止啟動自由運行信號FRS。此時,虛擬隨機序列產生器63〇 20 201232261 * Λ. Λ. ^ 被提供作為隨機化第一資料的初始種子的初始隨機序列資 料。 在一範例實施例中,於寫入操作時,在位址輸入後計 數器641接者開始計數。 如果初始種子的產生結束時’要被程式化的資料會依 據凟取/寫入致能信號RE/WE的切換,並透過快閃記憶體 裝置的輸入/輸出介面700被依序提供給隨機產生器電路 600。此時,虛擬隨機序列產生器63〇會與讀取/寫入致能 信號RE/WE的切換同步並依序產生隨機序列資料RSD。 混合器650邏輯地結合隨機序列資料RSD與透過輸入/輸 出介面電路700提供的資料,以及此結合後的資料會被作 為已隨機化的資料而透過行選擇電路5〇〇被傳遞至頁緩衝 電路400。 解隨機化的操作可以被重複執行直到所有要被程式化 的資料均被傳遞至頁緩衝電路4〇〇為止。之後,如果第二 指令10h被提供至快閃記憶體裝置,如圖6所示,就緒/ 忙碌信號朦從高水平降至低水平。在就緒/忙碌信號_為 低水平的期間,也就是,於時間區間tpGM中,儲存於頁 緩衝電路400的資料(也就是,已隨機化的資料)會被儲 存於記憶胞陣列100。 ^承上所述,雖然被要求對隨機資料存取(或稱,資料 機存取)’利肖偏移純作為行偏移值鱗備初始種子 (或’初始隨機序列資料)來隨機化上述的隨機資料仍是 可行的。 21 201232261 雖然圖6沒有繪示於寫入操作時行偏移值為零的情 況’此時沒有用以產生初始種子的自由運作操作會被進 行。在此情況下’資料以及第二指令10h會隨著位址的輸 入而被依序提供至快閃記憶體裝置。 在一範例實施例中,用以產生初始種子的時間區間會 依據行偏移值而有所區別。因此,在圖4中,於讀取操作 下在資料被取得的時間點,以及在圖6中,於寫入操作下 在資料被提供的時間點,均會依據產生初始種子所花費的 最大時間而被設定。 圖7為根據本發明之一範例貫施例所纟會示之圖1中的 隨機產生器電路的功能方塊圖。 清參照圖7,根據本發明之另一實施例,隨機產生器 電路包括時序產生器610、選擇器620、虛擬隨機序列產生 器630a、自由運行偵測器640a以及混合器650。時序產生 器610、選擇器620以及混合器65〇均與前述之說明相同, 在此不再贅述。 凊參照圖7至圖9’隨機產生器電路6〇〇a的虛擬隨 序歹J產生器630a根據表示加速模式的旗標信號ACC_E 以操作於加速模式或正常模式其中之-。在加速模式; :選擇:預移位隨機序列資料會根據預設的多項式而被 細的4明:ΐ 8所示的多工輸入埠,以下將會對此作更 加速模式中產生初始隨機序列所需的時 *為料)會減少。而#旗標錢ACC E 沒有啟動時’隨機產生器電物Ga會於正常模式下操作 22-v *· «· f-I The data stored in the page buffer circuit 400 can be additionally supplied to the external device by using the instruction and the address group. In this case, the : ready/busy signal can be maintained at a high level as indicated by ^4. For example, the first instruction 05h, the address C1C2, and the second instruction EOh may be sequentially provided to the flash memory device. At this time, the provided address includes only the row address C1C2, and the row address C1C2 is not zero. The initial random sequence data rsd is generated by the free-running operation of the random sequence generating block 650 and using the seed determined according to the previously provided column address R1R2R3, which is essentially the same as described above. As shown in Fig. 4, after the second instruction E〇h is received and the time interval in which the initial seed is generated, the data is output. The time interval (e.g., 13 microseconds) taken to prepare the initial seed will be shorter than the time interval tR (e.g., '30 microseconds). FIG. 5 is a timing diagram illustrating a read operation of a flash CMOS device according to another exemplary embodiment of the present invention. Read operations can be performed based on the input instructions and the combination of addresses. For example, as shown in FIG. 5, the first instruction (9)h, the address C1C2R1R2R3, and the second instruction 3〇h may be sequentially supplied to the flash memory device. The provided address C1C2R1R2R3 may include a row address cic2 and a column address leg. In the present embodiment, the row address ac2 is zero' and the row offset value is zero. Since the row offset value is zero, the data is not randomly accessed' and the free-running operation is not performed. After the first instruction 3〇h is supplied to the flash memory device, the page buffer circuit 4 读出 reads the data from the memory cell array 1〇〇201232261ir as the control of the control logic 300 in the time interval tR + '. Respond. As shown in Fig. 5, in the time interval tR, the ready/busy signal can be maintained at a low level. The machine generator circuit 6 sequentially uses the received column address rir2R3 as a seed to generate a random sequence data RSD, and logically combines the random sequence data RSD with the data read from the page buffer circuit 4A. The combined data can be provided to the external splicing through the input/output circuit 700 as de-randomized data. FIG. 6 is a timing diagram illustrating a write operation of a flash memory device according to an exemplary embodiment of the invention. ^Write operations can be performed based on the input instructions and the combination of addresses. For example, as shown in FIG. 5, the first instruction 8〇h, the address C1C2R1R2R3, and the second instruction 1〇h may be sequentially provided to the flash memory device. The provided address C1C2R1R2R3 may include a row address C1C2 and a column address R1R2R3. In the present embodiment, the row address C1C2 = zero, and the row offset value is not zero for the row address ccl2. Therefore, the poor material access is random, and the initial address data is generated by using the column address R1R2R3 as a seed. Since the line offset value is not zero, the free running detector 640 activates the free signal FRS. That is, the timing signal CKL generated by the timing generation H 610 is selected by the selector 62. And the timing signal cKL is supplied to the virtual, random sequence to generate n (four) to generate the random sequence data RSD. When the tens value of the counter 641 reaches the column offset value, the 'free running debt detector' ο prevents the start of the free running signal FRS. At this time, the virtual random sequence generator 63〇20 201232261 * Λ. Λ. ^ is provided as The initial random sequence data of the initial seed of the first data is randomized. In an exemplary embodiment, at the time of the write operation, the counter 641 picks up after the address is input. If the initial seed is generated, the program is to be executed. The data is switched according to the capture/write enable signal RE/WE and sequentially supplied to the random generator circuit 600 through the input/output interface 700 of the flash memory device. At this time, the virtual random sequence is generated. The device 63 is synchronized with the switching of the read/write enable signal RE/WE and sequentially generates the random sequence data RSD. The mixer 650 logically combines the random sequence data RSD with the data provided through the input/output interface circuit 700. And the combined data is transmitted to the page buffer circuit 400 through the row selection circuit 5 as the randomized data. The randomized operation can be repeatedly performed. All data to be programmed is passed to the page buffer circuit 4. After that, if the second instruction 10h is supplied to the flash memory device, as shown in FIG. 6, the ready/busy signal is lowered from a high level. To the low level, during the time when the ready/busy signal _ is low, that is, in the time interval tpGM, the data stored in the page buffer circuit 400 (that is, the randomized data) is stored in the memory cell array. 100. ^ As stated above, although it is required to access the random data access (or data access), the Lexmark offset is purely used as the row offset value to prepare the initial seed (or 'initial random sequence data') to be random. It is still feasible to implement the above random data. 21 201232261 Although Figure 6 does not show the case where the line offset value is zero during the write operation, the free operation operation for generating the initial seed is performed at this time. In the case, the 'data and the second instruction 10h are sequentially supplied to the flash memory device along with the input of the address. In an exemplary embodiment, the time interval for generating the initial seed is based on the line offset value. Therefore, in Fig. 4, at the time point when the data is acquired under the reading operation, and in Fig. 6, at the time point when the data is supplied under the writing operation, the initial seed is generated. Figure 7 is a functional block diagram of the random generator circuit of Figure 1 in accordance with an exemplary embodiment of the present invention. Referring to Figure 7, another embodiment of the present invention is shown. For example, the random generator circuit includes a timing generator 610, a selector 620, a virtual random sequence generator 630a, a free running detector 640a, and a mixer 650. The timing generator 610, the selector 620, and the mixer 65 are both The description is the same and will not be described here. Referring to Fig. 7 to Fig. 9', the virtual sequence generator 630a of the random generator circuit 6Aa operates in the acceleration mode or the normal mode according to the flag signal ACC_E indicating the acceleration mode. In the acceleration mode; :Select: The pre-shifted random sequence data will be fined according to the preset polynomial: multiplex input 埠 shown in ΐ 8, which will generate the initial random sequence in the more accelerated mode. The time required* will be reduced. When the #flag money ACC E is not activated, the random generator gas Ga will operate in the normal mode.
201232261 表不加速模式的旗標信號ACC_EN的啟動或沒有啟 動是基於快閃記憶體裝置的調節資料來決定的。此外,表 不加速模式的旗標信號acc_en的啟動或沒有啟動是由 控制快閃記憶體裝置的控制器決定的。但是,由先前技術 可以顯而易見表示加速模式的旗標信號ACC_EN的啟動 或〉又有啟動並不限於上述揭露的方法。速度資訊也可以透 過旗4示彳§號的啟動而被決定。 自由運行偵測器640a包括計數器641a、比較器642a 以及除法器643a。計數器641a用來與時序信號CLK同步 操作。除法器643a根據旗標信號ACC—EN以於加速模式 下,作。除法器643a可以直接傳遞行偏移值至比較器642a 或提供將行偏移值除以速度資訊N得到的值給比較器 642a。舉例來說,當旗標信號Α(χ一EN表示為正常模式 時,除法器643a傳送沒有經過修改的行偏移值給除法器 643a。而當旗標信號ACC—EN表示為加速模式時,除法器 643a將行偏移絲以速度魏N並提錄行除法後得到 的值給比較器642a。例如,當行偏移值為1〇〇〇且速产資 訊表示為N-速度時,除法器643a輸出的值為1〇〇_二 比較器642a比較計數器641a的計數值與除法器643& 輸出的值’並根據比較結果以產生自由運行信號阳。兴 例來說,當計數器64U的初始值與除法器643a輸出的 相同時,自由運行信號FRS被阻止啟動。而當計數器他 的初始值與除法器643a輸出的值不同時,自由^ FRS被啟動。在上述的後-種情況下,當計數器⑷& = 23 201232261 數值達到除法器643a輸出的值時,比較器642a會阻止啟 動自由運行信號FRS。然後計數器641a也會停止計數。 圖8為繪示圖7中的虛擬隨機序列產生器630a的示意 圖,以及圖9為由圖7中的虛擬隨機序列產生器630a產生 的初始虛擬隨機序列資料(或,虛擬種子的值)的查找表 清單的示意圖。 凊參照圖8 ’虛擬隨機序列產生器630a包括用於操作 以回應於隨機序列時序信號CLK_RS的多個正反器 FF0〜FF10、用於操作以回應於加速旗標信號ACC_EN的 多個選擇器SEL0〜SEL10,以及耦接狀況如圖8所_示的多 個XOR邏輯閘631〜634。在本實施例中,如圖8所示,虛 擬隨機序列產生器630a滿足多項式xu + χι〇+1且根據旗標 4號ACC_EN來決定於正常模式或加速模式下操作。 當旗標信號ACC一EN的水平表示為正常模式(如,低 水平)時,選擇器SELxx的輸入埠〇的輸入被選擇並被輸 出至正反器FF0〜FF10的輸入埠D。當旗標信號acc_en 在表不加速模式的水平(如,高水平)時,選擇器seLxx 的輸入埠1的輸入被選擇以通過預移位隨機序列資料至正 反器FF0〜FF10的輸入埠D。舉例來說,被選擇的χ1()Λχ〇Α Χ"Χ2' χ1〇Λχ〇Λχ1' χ1〇Αχ〇Λ^ x10~x3 選擇器SEL0〜SEL10。在本發明之實施例巾,如圖8盘圖 9 :示’行偏移值被進—步或被加快輸出,例如,被輸入 ^器SEU以及正反器FF〇的χ1相對,藉此消除 兩個區塊循環以輸出預移位隨機序列資料。 ’、 24 201232261 * V» * 圖9為由虛擬隨機序列產生器產生的範例的隨 列’其具有偏移值(垂直軸)以及具有預定的多項 項式隨機序列資料的階數(水平軸),例如,本實:歹 多項式為ΧΠ+Χΐ°+1。如圖9所示,在正常模式(加 逯度為1)下,依據舦的多項式產生的隨機序 輸出對應至序列階數的各個行偏移值,例如第丨列/第2 歹J以及第3列。在加速模式(加速度大於j )下 隨機序列的行偏移值為進一步的,舉例來說,透過^擇圖 8中^選擇器的輸入埠i,以利用第3列輸出預移位隨機序 列資料,以及減少用於設置初始種子的時間。當行偏移值 依據時序彳§號CLK的切換而增加時,初始種子也會被依序 的產生。雖然在本實施例中說明的加速器的特色在於透過 2個區塊循環以加速隨機序列的產生,然而在習知技術中 已經可以顯而易見其他類似於本實施例的配置以改變加速 器參數的方式。舉例來說,當速度資訊表示為4_速度時, 對應至行偏移值(如,4、8、12等)的初始種子會被依序 的產生。在此需注意的是,與圖8相同,在圖9中,符號 ”Λ"表示XOR操作。 雖然在此說明的本發明的多種實施例會產生對應至偏 移值的隨機序列資料’例如,第Ν個依序產生的隨機序列 資料與對應至第Ν個偏移值的資料混合,此隨機序列資料 以及偏移值會被改變。在本發明之一實施例中,Μ隨機序 列資料被產生,其中,Μ可以是小於Ν的值。例如,Μ為 25 201232261 -----Γιτ 4的隨機序列資料可以適用於偏移值5。因此,Μ的最大 值為Ν。 根據本發明之另一實施例,Μ個隨機序列資料在依據 存取位址以解隨機第一讀取資料後被產生,其中,Μ為從 1到小於存取位址的行部分的結尾的範圍。 圖10為根據本發明之又一實施例所繪示之圖1的隨機 產生器電路的功能方塊圖。 在開始說明以前,在圖1〇的隨機產生器電路6〇〇b中, 與圖3的隨機產生器電路6〇〇中的組成元件的索引號碼相 同的組成元件就具有相同的功能,在此不再贅述。 請參照圖10,隨機產生器電路6〇〇b包括初始種子產 生器670,用以依據行偏移值產生初始種子。虛擬隨機序 列產生器630根據用以產生初始種子的多項式χΐ 1+ χΐ〇+ 1 (如圖9所示)來實作。承上所述,虛擬隨機序列產生器 630會依據預定的條件來產生初始種子的值。於是,如圖8 所示,初始種子產生器670可以實作於硬體上。虛擬隨機 序列產生器630以及初始種子產生器67〇可以組成產生隨 機序列的區塊。 在一貫施例中,傳送至虛擬隨機序列產生器的隨 機序列時序信號CLK_RS可以是在資料輸入/輸出時^ 的讀取/寫入致能彳s號。此外,傳送至虛擬隨機序列產生器 630的隨機序列時序信號CLK—RS也可以是在資料輸入/ 輸出時產生的時序信號。 26 201232261 圖11A為根據本發明之一實施例所綠示之快 二遗機化方法的流程示意圖。圖UB為根據本發^之 一貫=麟示之快閃記憶體裝置的隨機化構想示意圖。 心^驟S1〇()中,存取開始並判斷被要求的存取是否 斷=== = =行位址或偏移值)。如果判 喂取卿級機貝神取時,例如,偏移 ^議之後接續執行步驟測,透過存取他的— ,遺,生器.在產生初始種子之後,於步輸驟: I ★機序列RSI^RSDn+l透過準備好的初始種子而被 =’以及使用隨機序列RSDiARSDn+1進行隨機化或解 隨機化操作。紐’已隨機化的㈣透過頁緩衝電路400 被儲存於陣列_。而已解機化的資料則透過輸人/輸出介 面7〇〇被提供至外部裝置(如,控制器)。 如果被要求的存取動作被判斷為非隨機的資料存取時 (行偏移值為0),則在步驟謂之後接續執行步驟 S130,從第一資料D〇執行隨機化或解隨機化操作,並根 據,各種位址(例如,頁位址、區塊位址或扇區位址等 決定的開始種子產生隨機序列。在此需注 意的是,在此一步驟(S130)中,不需要使用圖3至圖仞 所說明的產生初始種子的操作。然後,已隨機化的資料可 以透過頁緩衝電路1〇〇而被儲存於陣列1〇〇。而以解隨機 化的資料則透過輸入/輸出介面700被提供至外 (如,控制器)。 ° 27 201232261, 及偏移值來解釋隨機存取(例行位址以 μ留c” “广 員取M及寫入快閃記憶體的最小 存取早兀可以為扇區,如程式資料與錯誤更正碼的結合, ^及用於除了第-扇區之相扇區的開始種子與行位址益 關0 ‘… 在本發明之-實施例中,透過混合純行隨機化或解 隨機化不但可以由二進制單元組成,還可以透過逐 或操作以混合多值狀態。 、 圖12為根據本發明之—實關麟示之記憶體系統 的功能方塊圖。 請參照圖12,記憶體系統3〇〇〇包括至少一個快閃記 憶體1000以及控制器2000。快閃記憶體1000在控制器 2000的控制下進行操作並被作為儲存媒體使用。控制器 2000可以用以控制快閃記憶體1〇〇〇。快閃記憶體1〇〇〇可 以包括隨機產生器電路11〇〇。在此需注意的是,在圖12 中,快閃記憶體1000與圖1中的快閃記憶體裝置相同,故 在此不再贅述。此外,控制器2〇〇〇可以用來增加儲存於快 閃記憶體1000的錯誤控制碼資料。 控制器2000可以包括第一介面21 〇〇、第二介面2200、 處理單元2300、緩衝記憶體2400以及錯誤控制電路2500。 第一介面2100用來與外部裝置(如,主機裝置)溝通。第 二介面2200用來與快閃記憶體2200溝通。處理單元2300 28 201232261 上uiypif 用來控制㈣器2_的整體操作。緩 =存於快閃記憶體酬的資料或== 1_讀取的跡錯純機路測依據緩衝記=體 的資料以產生錯誤更正碼資料。此外, ^ 一 =對^閃魏體麵讀取的資料執行錯誤制以及更 正插作。而錯誤更正碼資料可讀儲存於與欲儲存於 心隱體聊的資料相同的頁或被儲存於與快 記憶體1000的資料不同的區域。 仔於决閃 在圖12的記憶體系統中,寫入操作可以包括依據欲儲 ^於快閃記憶體麵的資料以產生錯誤更正碼資料以及 隨機化欲儲存於快閃記憶體1〇〇〇的資料。而讀取操作可以 包括解隨機化讀取的資料以及對已解隨機化的資料執行錯 誤偵測與更正操作。此外,錯誤更正碼資料的隨機化 隨機化為可選擇性的。 — 在本發明之一實施例中,控制器2000的第一介面2 i 〇〇 的形式可以為電腦匯流排標準、儲存匯流排標準以及網際 網路光纖通道協定週邊設備匯流排標準其中之一,或是結 合上述2種以上的標準。電腦匯流排標準包括s_1〇〇匯流 排(S-100 bus)、Meter-Bus、Smbus、Q-bus、工業標準架 構(ISA)、Zorro II、Zorro III、計算機自動量測與控制 (CAMAC )、FASTBUS、LPC、擴展工業標準結構(EISA )、 VME、VXI、NuBus、TURBOcharmel、MCA、Sbus、VLB、 PCI、PXI、惠普壁虎系統連接匯流排(HP GSC bus)、201232261 The activation or non-activation of the flag signal ACC_EN indicating the acceleration mode is determined based on the adjustment data of the flash memory device. In addition, the activation or non-activation of the flag signal acc_en indicating the acceleration mode is determined by the controller controlling the flash memory device. However, it can be apparent from the prior art that the activation or "starting" of the flag signal ACC_EN of the acceleration mode is not limited to the above disclosed method. Speed information can also be determined by the launch of the flag 4 § §. The free running detector 640a includes a counter 641a, a comparator 642a, and a divider 643a. The counter 641a is used to operate in synchronization with the timing signal CLK. The divider 643a is made in the acceleration mode based on the flag signal ACC_EN. Divider 643a may pass the line offset value directly to comparator 642a or provide a value obtained by dividing the line offset value by speed information N to comparator 642a. For example, when the flag signal Α (χ-EN is indicated as the normal mode, the divider 643a transmits the unmodified line offset value to the divider 643a. When the flag signal ACC-EN is indicated as the acceleration mode, The divider 643a adds the value obtained by dividing the line offset line by the velocity and extracting the line to the comparator 642a. For example, when the line offset value is 1 〇〇〇 and the fast-tracking information is expressed as N-speed, the division is performed. The value output by the unit 643a is 1〇〇_two comparator 642a compares the count value of the counter 641a with the value of the divider 643& and according to the comparison result to generate a free running signal yang. For example, when the counter 64U is initialized When the value is the same as that output by the divider 643a, the free running signal FRS is prevented from being activated, and when the initial value of the counter is different from the value output by the divider 643a, the free FRS is activated. In the latter case, When the counter (4) & = 23 201232261 value reaches the value output by the divider 643a, the comparator 642a blocks the start of the free running signal FRS. Then the counter 641a also stops counting. Fig. 8 is a diagram showing the virtual random sequence in Fig. 7. A schematic diagram of the generator 630a, and FIG. 9 is a schematic diagram of a lookup table list of initial virtual random sequence data (or virtual seed values) generated by the virtual random sequence generator 630a of FIG. 7. Referring to FIG. 8 'virtual randomization The sequence generator 630a includes a plurality of flip-flops FF0 FFFF10 for operating in response to the random sequence timing signal CLK_RS, a plurality of selectors SEL0 SELSEL10 for operating in response to the acceleration flag signal ACC_EN, and a coupling condition A plurality of XOR logic gates 631 to 634 as shown in Fig. 8. In the present embodiment, as shown in Fig. 8, the virtual random sequence generator 630a satisfies the polynomial xu + χι〇+1 and is based on the flag No. 4 ACC_EN. It is determined to operate in the normal mode or the acceleration mode. When the level of the flag signal ACC-EN is expressed as the normal mode (e.g., low level), the input of the input port of the selector SELxx is selected and output to the flip-flop FF0. ~FF10 input 埠D. When the flag signal acc_en is at the level of the acceleration mode (eg, high level), the input of the input 埠1 of the selector seLxx is selected to pre-shift the random sequence data to positive The input 埠D of the inverters FF0 to FF10. For example, the selected χ1()Λχ〇Α Χ"Χ2' χ1〇Λχ〇Λχ1' χ1〇Αχ〇Λ^ x10~x3 selectors SEL0 to SEL10. In the embodiment of the invention, as shown in FIG. 8 , FIG. 9 shows that the row offset value is advanced or is outputted, for example, by the input device SEU and the flip-flop FF 〇 1 , thereby eliminating two The block loops to output pre-shifted random sequence data. ', 24 201232261 * V» * Figure 9 is an example of a column generated by a virtual random sequence generator with an offset value (vertical axis) and an order with a predetermined polynomial random sequence data (horizontal axis) For example, the real: 歹 polynomial is ΧΠ + Χΐ ° +1. As shown in FIG. 9, in the normal mode (the degree of addition is 1), the random sequence output according to the polynomial of 舦 corresponds to each row offset value of the sequence order, for example, the third column / the second 歹J and the 3 columns. In the acceleration mode (acceleration greater than j), the row offset value of the random sequence is further, for example, by inputting the input 埠i of the selector in FIG. 8 to output the pre-shift random sequence data by using the third column. And reduce the time used to set the initial seed. When the line offset value is increased according to the switching of the timing 彳§ CLK, the initial seeds are also sequentially generated. Although the accelerator described in this embodiment is characterized by two block loops to accelerate the generation of random sequences, other ways similar to the configuration of the present embodiment to change the accelerator parameters can be apparent in the prior art. For example, when the speed information is expressed as 4_speed, the initial seeds corresponding to the line offset values (e.g., 4, 8, 12, etc.) are sequentially generated. It should be noted here that, like FIG. 8, in FIG. 9, the symbol "Λ" indicates an XOR operation. Although various embodiments of the invention described herein generate random sequence data corresponding to an offset value, for example, The random sequence data generated in sequence is mixed with the data corresponding to the second offset value, and the random sequence data and the offset value are changed. In an embodiment of the present invention, the random sequence data is generated. Wherein, Μ may be a value smaller than Ν. For example, a random sequence data of 2012 25 201232261 ----- Γιτ 4 may be applied to the offset value 5. Therefore, the maximum value of Μ is Ν. According to another aspect of the present invention In an embodiment, the random sequence data is generated after the random first read data is solved according to the access address, wherein Μ is a range from 1 to the end of the line portion of the access address. A functional block diagram of the random generator circuit of FIG. 1 is shown in yet another embodiment of the present invention. Before starting the description, in the random generator circuit 6〇〇b of FIG. 1A, and the random generator of FIG. Components in circuit 6〇〇 The components having the same index number have the same function, and will not be described again here. Referring to FIG. 10, the random generator circuit 6〇〇b includes an initial seed generator 670 for generating an initial seed according to the row offset value. The random sequence generator 630 is implemented according to a polynomial χΐ 1+ χΐ〇 + 1 (shown in Figure 9) for generating an initial seed. As described above, the virtual random sequence generator 630 generates an initial according to predetermined conditions. The value of the seed. Thus, the initial seed generator 670 can be implemented on a hardware as shown in Figure 8. The virtual random sequence generator 630 and the initial seed generator 67 can form a block that produces a random sequence. In the example, the random sequence timing signal CLK_RS transmitted to the virtual random sequence generator may be a read/write enable ss number at the data input/output. In addition, the random sequence transmitted to the virtual random sequence generator 630 The timing signal CLK_RS may also be a timing signal generated at the time of data input/output. 26 201232261 FIG. 11A is a green display of the second virtual machine according to an embodiment of the present invention. Schematic diagram of the process of the method. Figure UB is a schematic diagram of the randomization of the flash memory device according to the consistent = Lin shown in the present invention. In the heartbeat S1〇(), the access starts and determines whether the requested access is broken. === = = row address or offset value. If you are fed to take the level of the machine, for example, after the offset, continue to perform the step test, by accessing his -, legacy, live. After the initial seed is generated, the step is: Step I: The machine sequence RSI^RSDn+l is randomized or derandomized by the prepared initial seed by '' and using the random sequence RSDiARSDn+1. New' has been randomized (4) The page buffer circuit 400 is stored in the array_. The decomposed data is supplied to an external device (e.g., controller) through the input/output interface. If the requested access action is determined to be a non-random data access (the row offset value is 0), then step S130 is followed by the step data, and the randomization or de-randomization operation is performed from the first data D〇. And according to various addresses (for example, page address, block address or sector address, etc., the starting seed determines a random sequence. It should be noted that in this step (S130), it is not required to use The operation of generating the initial seed is illustrated in Figures 3 to 。. Then, the randomized data can be stored in the array through the page buffer circuit 1 and the data descrambled through the input/output. Interface 700 is provided to the outside (eg, controller). ° 27 201232261, and the offset value to explain random access (routine address to μ leave c" "Minimum M and write to flash memory minimum The access can be a sector, such as a combination of program data and error correction codes, and a start seed and row address for the sector other than the first sector. In the case, by randomizing randomization or de-randomization, It can be composed of binary units, and can also be mixed by multi-valued operation by operation. Figure 12 is a functional block diagram of the memory system according to the present invention - Fig. 12, the memory system 3 The 〇〇 includes at least one flash memory 1000 and a controller 2000. The flash memory 1000 operates under the control of the controller 2000 and is used as a storage medium. The controller 2000 can be used to control the flash memory. The flash memory 1〇〇〇 may include a random generator circuit 11〇〇. It should be noted here that in FIG. 12, the flash memory 1000 is the same as the flash memory device of FIG. In addition, the controller 2 can be used to increase the error control code data stored in the flash memory 1000. The controller 2000 can include a first interface 21 〇〇, a second interface 2200, and a processing unit. 2300, buffer memory 2400 and error control circuit 2500. The first interface 2100 is used to communicate with an external device (eg, a host device). The second interface 2200 is used to communicate with the flash memory 2200. 2300 28 201232261 uiypif is used to control the overall operation of (4) device 2_. Slow = stored in flash memory data or == 1_ read trace error pure machine path test based on buffer data = body data to generate Error correction code data. In addition, ^ a = misfiguration of the data read by the decent face and correction of the error. The error correction code data can be stored in the same page as the data to be stored in the chatter. Or stored in an area different from the data of the fast memory 1000. In the memory system of FIG. 12, the writing operation may include generating an error correction code according to the data to be stored in the flash memory surface. Data and randomized data to be stored in the flash memory. The read operation may include de-randomizing the read data and performing error detection and correction operations on the de-randomized data. In addition, randomization of error correction code data is randomized to be optional. - In an embodiment of the present invention, the first interface 2 i 〇〇 of the controller 2000 may be in the form of a computer bus standard, a storage bus standard, and one of the Internet Fibre Channel protocol peripheral bus standards. Or combine the above two or more standards. Computer bus standards include s_1 bus (S-100 bus), Meter-Bus, Smbus, Q-bus, Industrial Standard Architecture (ISA), Zorro II, Zorro III, Computer Automated Measurement and Control (CAMAC), FASTBUS, LPC, Extended Industry Standard Architecture (EISA), VME, VXI, NuBus, TURBOcharmel, MCA, Sbus, VLB, PCI, PXI, HP Gecko System Connection Bus (HP GSC bus),
CoreConnect、InfiniBand、UPA、PCI-X、AGP、PCIe、英 29 201232261π • 1. ΙΑ 特爾快速通道互連(Intel QuickPath Interconnect)以及超 傳輸(Hyper Transport)等標準。儲存匯流排標準可以包 括 ST-506、ESDI、SMD、並行高技術配置(Parallel ΑΤΑ)、 DMA、SSA、HIPPI、USB MSC、FireWire(1394)、串行 ATA( Serial ΑΤΑ )、eSΑΤΑ、小型計算機系統接口( SCSI)、 並行小型計算機系統接口(Parallel SCSI)、序列式SCSI (Serial Attached SCSI)、光纖通道(Fibre Channel)、 iSCSI、SAS、RapidIO以及基於IP位址的光纖通道(FCIP ) 等標準。網際網路光纖通道協定週邊設備匯流排標準可以 包括蘋果桌面匯流排(Apple Desktop Bus )、硬體迴路 (HIL)、樂器數位介面(MIDI)、Multibus、RS-232、 DMX512-A、EIA/RS-422、IEEE-1284、UNI/O、1-Wire、 I2C、SPI、EIA/RS-485、USB、Camera Link、External PCIe、 Light Peak以及多點匯流排(Multidrop Bus )等標準。 圖13為根據本發明之另一實施例所繪示之記憶體系 統的功能方塊圖。 請參照圖13,記憶體系統3000a包括至少一個快閃記 憶體1000a以及控制器2000a。快閃記憶體i〇〇〇a在控制 器2000a的控制下操作並被作為儲存媒體使用。如圖13 所示,快閃記憶體l〇〇〇a不包括上述的隨機產生器電路。 控制器2000a可以用於控制快閃記憶體i〇〇〇a。控制器 2000a也用於隨機化欲儲存於快閃記憶體l〇〇〇a的資料以 及增加錯誤更正碼資料至被隨機化的資料中。控制器 2000a還用來對從快閃記憶體1000a讀取的且已隨機化的 30 201232261 -ri 資料的錯誤執行錯誤偵測與更正操作並解隨機化已隨機化 的資料。 控制器2000a可以包括第一介面21〇〇a、第二介面 2200a、處理單元2300a、緩衝記憶體2400a、錯誤控制電 路2500a以及隨機產生器區塊2600。在此需注意的是,由 於本實施例中的組成元件2l〇〇a、2200a、2300a、2400a以 及2500a均分別與圖12的實施例中的組成元件21〇〇a、 2200a、2300a、2400a以及2500a相同,故在此不再贅述。CoreConnect, InfiniBand, UPA, PCI-X, AGP, PCIe, English 29 201232261π • 1. Standards such as Intel QuickPath Interconnect and Hyper Transport. Storage bus standards can include ST-506, ESDI, SMD, Parallel 高, Parallel S, DMA, SSA, HIPPI, USB MSC, FireWire (1394), Serial ATA (Serial ΑΤΑ), eSΑΤΑ, small computer systems Standards for Interface (SCSI), Parallel SCSI, Serial Attached SCSI, Fibre Channel, iSCSI, SAS, RapidIO, and Fibre Channel over IP Address (FCIP). Internet Fibre Channel Protocol Peripheral Bus Standards can include Apple Desktop Bus, Hardware Loop (HIL), Instrument Digital Interface (MIDI), Multibus, RS-232, DMX512-A, EIA/RS -422, IEEE-1284, UNI/O, 1-Wire, I2C, SPI, EIA/RS-485, USB, Camera Link, External PCIe, Light Peak, and Multidrop Bus. Figure 13 is a functional block diagram of a memory system in accordance with another embodiment of the present invention. Referring to Figure 13, the memory system 3000a includes at least one flash memory 1000a and a controller 2000a. The flash memory i〇〇〇a operates under the control of the controller 2000a and is used as a storage medium. As shown in FIG. 13, the flash memory 10a does not include the random generator circuit described above. The controller 2000a can be used to control the flash memory i〇〇〇a. The controller 2000a is also used to randomize the data to be stored in the flash memory l〇〇〇a and to add the error correction code data to the randomized data. The controller 2000a is also used to perform error detection and correction operations on the error of the 30 201232261 -ri data read from the flash memory 1000a and randomize and randomize the randomized data. The controller 2000a may include a first interface 21a, a second interface 2200a, a processing unit 2300a, a buffer memory 2400a, an error control circuit 2500a, and a random generator block 2600. It should be noted here that the constituent elements 21a, 2200a, 2300a, 2400a, and 2500a in this embodiment are respectively associated with the constituent elements 21A, 2200a, 2300a, 2400a in the embodiment of FIG. 2500a is the same, so it will not be described here.
Ik機產生器區塊2600用來隨機化從緩衝記憶體24〇〇a 中讀出的資料以及解隨機化從快閃記憶體1〇〇〇a中讀出的 資料(也就是,已隨機化的資料)。而隨機產生器區塊26〇〇 也可以依據圖3至圖10的多個實施例中所說明的方法其中 之一來對隨機資料執行隨機化操作,在此不再贅述。錯誤 控制電路2600可以依據隨機產生器區塊25〇〇中的被隨機 化的資料產生錯誤更正碼資料。此外,錯誤控制電路25〇加 也可以依據錯誤更正碼資料對從快閃記憶體1〇〇〇a中讀取 的資料(也就是,被隨機化的資料)執行錯誤偵測與更正 操作。而錯誤更正碼資料可以被儲存於與欲儲存於^閃記 憶體1000a的資料相同的頁或被儲存於與欲儲存於快閃圮 憶體1000的資料不同的區域。 、° 在本實施例中’寫入操作可以包括隨機化欲被儲存於 快閃記憶體1000a的資料,依據被隨機化的資料產生錯誤 更正碼資料,以及儲存被隨機化的資料與錯誤更正碼資才斗 於快閃記憶體1000。此外,寫入操作也可以包括隨機二欲 31 201232261 ―作= = = = = = =也 就是’被隨機化的資料)執行錯誤偵測與=抖(也 功能^為根據她之—實施例輸之固態硬碟的 =參照圖14 ’固態硬碟4_包括儲存媒體侧以及 控制器4·。儲存雜侧透過錄個 器4200’其中各個通道還分別連接多數個非揮發性= 體。母個非揮發性記憶齡置可以由圖 體裝,成。在本實施例中,控制器4勘與圖J = 控制益2000相同。也就是說,資料的隨機化可以在各個非 ==巾執行,遍_ —可以於控制器 此外控制器4200也可以與圖π所示的控制器2〇〇〇a 相同。此時,資料的隨機化以及錯誤_與更正會於控制 器4200中執行。據此,根據偏移位址產生用來隨^化^料 的初始種子為可行的。 圖15為圖14中使用固態硬碟的儲存裝置的功能方塊 圖。圖16丨® 14中使用固態硬碟的儲存飼服器的功能方 塊圖。 在本發明之一實施例中,固態硬碟4〇〇〇用來體現儲存 裝置。請參照圖15,儲存裝置包括多個與圖14所示的固 態硬碟4000相同的固態硬碟4000。在本發明之一實施例 中,固悲硬碟4000也可用來體現儲存伺服器。請參照圖 32 201232261 16 ’儲存伺服ϋ包括多個姻14所㈣關硬碟侧相 同的,態硬碟4_,以及可以控制儲存词服器整體操作的 司,器4000A。更進一纟’儲存伺服器更包括獨立磁碟冗 餘陣列控制1 4GGGB,關立磁碟冗轉脸制器4〇_ 用來根據制於損毀修復的同位(parity)方式對儲存於固 態硬碟4000的資料作同位管理。 、 圖Π至圖19為根據本發明之實施例所繪示之系 意圖。 ^The Ik machine generator block 2600 is used to randomize the data read from the buffer memory 24A and to de-randomize the data read from the flash memory 1a (i.e., randomized) data of). The random generator block 26 can also perform randomization operations on the random data according to one of the methods illustrated in the various embodiments of FIG. 3 to FIG. 10, and details are not described herein again. The error control circuit 2600 can generate error correction code data based on the randomized data in the random generator block 25A. Further, the error control circuit 25 may perform error detection and correction operations on the data read from the flash memory 1A (i.e., the randomized data) based on the error correction code data. The error correction code data can be stored in the same page as the data to be stored in the flash memory 1000a or stored in an area different from the data to be stored in the flash memory 1000. In the present embodiment, the 'writing operation may include randomizing the data to be stored in the flash memory 1000a, generating error correction code data based on the randomized data, and storing the randomized data and the error correction code. The talent is in the flash memory 1000. In addition, the write operation can also include random second desire 31 201232261 - "= = = = = = = that is, 'randomized data" to perform error detection and = shake (also function ^ according to her - embodiment) The solid state hard disk = reference to Fig. 14 'solid state hard disk 4_ includes the storage medium side and the controller 4 ·. The storage side passes through the recorder 4200', wherein each channel is also connected to a plurality of non-volatile = body. The non-volatile memory age can be installed by the figure. In this embodiment, the controller 4 is the same as the figure J = control benefit 2000. That is, the randomization of the data can be performed in each non-= towel. The controller may be the same as the controller 2A shown in Figure π. At this time, the randomization of the data and the error_and corrections are performed in the controller 4200. It is feasible to generate an initial seed for use according to the offset address. Figure 15 is a functional block diagram of the storage device using the solid state hard disk in Figure 14. Figure 16 is a solid state hard disk using a solid state hard disk. A functional block diagram of a storage device. One embodiment of the present invention The solid state hard disk 4 is used to embody the storage device. Referring to Figure 15, the storage device includes a plurality of solid state hard disks 4000 identical to the solid state hard disk 4000 shown in Figure 14. In one embodiment of the present invention The solid hard disk 4000 can also be used to represent the storage server. Please refer to Figure 32 201232261 16 'Storage servo ϋ includes multiple marriages 14 (four) off the same hard disk side, state hard disk 4_, and can control the storage word processor The overall operation of the division, the device 4000A. Further into the 'storage server, including the independent disk redundant array control 1 4GGGB, the open disk redundant face switch 4〇 _ used to make the parity based on damage repair (parity The method performs the parity management on the data stored in the solid state hard disk 4000. Figure 19 to Figure 19 is an illustration of the system according to an embodiment of the present invention.
At印參照圖17並根據上述的實施例,體現儲存裝置的固 態硬碟包括記憶體控制器以及快閃記憶體裝置,且系統 6〇〇包括透過有線或無線方式與主機溝通的儲存裝置 6100。請參照圖18並根據上述的實施例,體現儲存伺服器 的固態硬碟包括資料儲存裝置,且系統7〇〇〇包括透過有線 或無線方式與主機溝通的儲存伺服器71〇〇與72〇〇。更進 一步,請參照圖19並根據上述的實施例,體現郵件伺服器 8100的固態硬碟包括資料儲存裝置。郵件伺服器8100可 以透過郵件常駐程式以郵件協定(p〇st 〇ffice pr〇t〇c〇l, POP )以及簡易電子郵遞協定(Simple Mail Transfer Protocol,SMTP)與郵件程式溝通,且郵件伺服器81〇〇透 過網際網路相互溝通。 圖20至圖24為根據本發明之一實施例所繪示之使用 非揮發性記憶體裝置的其他系統的示意圖。 圖20為適用於本發明之一實施例的快閃記憶體裝置 的峰巢式電話系統的功能方塊圖。請參照圖2〇,峰巢式電 33 201232261 H-lUiypif 話系統包括適應性差動脈碼調變編解媽器電路9202、揚聲 器9203、麥克風9204、分時多工電路92〇6、鎖相迴路電 路9210以及射頻電路9211。適應性差動脈碼調變編解碼 器電路9202用來壓縮聲音以及解壓縮已壓縮的聲音。分時 多工電路9206用來分時多工處理數位資料。鎖相迴路電路 9210用來設定射頻信號的載波頻率。射頻電路9211用來 發送以及接收射頻信號。 此外,峰巢式電話系統還可以包括多種型態的記憶 體,例如非揮發性記憶體裝置92〇7、唯讀記憶體92&以 及靜態存取記憶體9209。非揮發性記憶體裝置9207可以 由圖1所示的快閃記憶體裝置組成,並執行圖3至圖1〇 所示的隨機化與解隨機化操作。唯讀記憶體92〇8用來儲存 程式資料。靜態存取記憶體9209用來作為系統控制微電腦 9212的工作區域或作為暫時性的儲存資料之用。系統控制 微電腦9212為用來控制非揮發性記憶體裝置92〇7的寫入 與讀取操作的處理器。 圖21為適用於本發明之一實施例的快閃記憶體裝置 的s己憶卡的功能方塊圖。舉例來說,記憶卡可以是多媒體 記憶卡(Multimedia Card, MMC)、安全數碼卡(Secure Digital Memory Card,SD card)、多用卡(multiuse card)、Referring to Figure 17 and in accordance with the above-described embodiments, a solid state hard disk embodying a storage device includes a memory controller and a flash memory device, and the system 6 includes a storage device 6100 that communicates with the host via a wired or wireless means. Referring to FIG. 18 and according to the above embodiment, the solid state hard disk embodying the storage server includes a data storage device, and the system 7 includes a storage server 71〇〇 and 72〇〇 communicating with the host through a wired or wireless manner. . Still further, referring to Figure 19 and in accordance with the above-described embodiment, the solid state drive embodying mail server 8100 includes a data storage device. The mail server 8100 can communicate with the mail program through the mail resident program by mail protocol (p〇st 〇ffice pr〇t〇c〇l, POP) and the Simple Mail Transfer Protocol (SMTP), and the mail server 81〇〇 Communicate with each other through the Internet. 20 through 24 are schematic diagrams of other systems using non-volatile memory devices, in accordance with an embodiment of the present invention. Figure 20 is a functional block diagram of a peak-to-cell telephone system suitable for use in a flash memory device in accordance with an embodiment of the present invention. Please refer to Figure 2〇, peak-chamber type electricity 33 201232261 H-lUiypif system includes adaptive poor arterial code modulation and decoding mother circuit 9202, speaker 9203, microphone 9204, time-multiplexed circuit 92〇6, phase-locked loop circuit 9210 and RF circuit 9211. The adaptive poor arterial codec codec circuit 9202 is used to compress the sound and decompress the compressed sound. Time-sharing The multiplex circuit 9206 is used to process digital data in a time-multiplexed manner. The phase locked loop circuit 9210 is used to set the carrier frequency of the radio frequency signal. Radio frequency circuit 9211 is used to transmit and receive radio frequency signals. In addition, the peak-to-chassis telephone system can also include a variety of types of memory, such as non-volatile memory devices 92〇7, read-only memory 92& and static access memory 9209. The non-volatile memory device 9207 can be composed of the flash memory device shown in Fig. 1 and performs the randomization and de-randomization operations shown in Figs. 3 to 1B. Read-only memory 92〇8 is used to store program data. The quiescent memory 9209 is used as a system to control the working area of the microcomputer 9212 or as a temporary storage material. System Control The microcomputer 9212 is a processor for controlling the writing and reading operations of the non-volatile memory devices 92A. Figure 21 is a functional block diagram of a memory card of a flash memory device suitable for use in an embodiment of the present invention. For example, the memory card may be a multimedia memory card (MMC), a secure digital memory card (SD card), a multi-purpose card (multiuse card),
从女全數碼卡(micro_Secure Digital Memory Card, micro-SD card)、記憶條(memoryStiek)、小型安全數碼 卡(compact Secure Digital Memory Card,compact SD card )、識別卡(identification card,ID Card )、個人電腦 34 201232261 儲存卡國際聯盟卡(Personal Computer Memory Card International Association card, PCMCIA card)、固態硬碟 卡(Solid State Disk card,SSD card)、晶片卡(Chip-Card)、 智慧卡以及USB卡等。 請參照圖21,根據本發明之一實施例,記憶卡包括介 面電路9221、控制器9222以及至少一個快閃記憶體裝置 9207。介面電路9221用來作為與外部裝置溝通的介面。控 制益9222包括緩衝記憶體,用來控制記憶卡的操作。快閃 記憶體裝置9207可以由用來產生供隨機資料所用的初始 種子的快閃記憶體裝置組成。控制器9222也可以作為押^ 快閃記憶體裝置9207的寫人以及讀取操作的處理器^別 疋,控制器9222可以透過資料匯流排DATA以及位址匯 流排ADDRE SS輕接於非揮發性記憶體展£92〇7與介面電 路 9221 。 ' +心肩她例的快閃記憶體裝詈 的數位靜態相機的功能方塊圖。請參照圖22 機包括包括機身伽、插槽9302、 等。特別是包括; 用的初始種子_==;== 入插槽9308。 了以*** ,當記憶卡9331***插 路可以與記憶卡9331電 如果記憶卡9331為接觸型離 槽通時’在電路版上的 35 201232261 性接觸。而如果記憶卡931 A非接觸型態,則電路版上的 電子電路可以透過射頻方式與記憶卡9331溝通。 ^ 23為翻圖22的記憶卡的多齡統的示意圖。 請參^® 23 ’記憶卡9331可以適用於⑷視訊攝影 機、(b)電視機、(c)影像裝置、⑷遊戲機、⑷ 電子音樂裝置、⑴峰巢式電話、(g)電腦、(h)個人 數位助理(PDA)、⑴錄音機以及⑴個人電腦 卡國際聯盟卡等。 圖24為適用於本發明之一實施例的快閃記憶體裝置 的影像感測系統的功能方塊圖。 請參照圖24 ’影像感測系統包括影像感測器9332、輸 入/輸出裝置9336、隨機存取記憶體9348、中央處理器9344 以及如本發明之一實施例所示的快閃記憶體裝置9354。在 圖24中的元件,也就是,影像感測器9332、輸入/輸出裝 置9336、隨機存取記憶體9348、中央處理器9344以及快 閃s己憶體襄置9354均透過匯流排9352相互溝通。其中, 各個元件還可以由具有由嵌入於處理器或獨立於處理 外的單晶片組成。 ° 在本發明之一實施例中,記憶胞可以由可變動組抗的 記憶胞組成。可變動組抗的記憶胞的範例以及記憶體裝置 整體已由美國專利第7529124號所揭露,故在此將其整體 合併引用。 本發明之另一實施例中,記憶胞由具有電荷儲存層的 多種胞架構其中之一所組成。由具有電荷儲存層的胞架構 36 201232261 HlUiypif 包括使用電荷陷阱層的電荷陷阱快閃架構(charge trap flash structure)、被陣列堆疊於多階層的堆疊快閃架構 (stack flash structure)、源汲自由架構(s〇urcedrain structure)以及接腳型快閃架構(pin_typeflashstmcture) 等。 具有電荷陷胖快閃架構以作為電荷儲存層的記憶體裝 置已被美國專利第6858906號以及美國公佈第 20040169238號與第20040169238號揭露,故在此將其整 體合併引用。而源汲自由架構已被韓國專利第673〇2〇號所 揭露’故在此將其整體合併引用。 本發明所述之快閃記憶體裝置或記體控制器可以被多 種封裝型態所封裝。舉例來說,本發明所述之快閃記憶體 裝置或η己體控制器可以使用例如層疊封裝(package 〇n Package,PoP )、球閘陣列封裝(Ball grip array,BGA )、 晶片尺寸封裝(Chip scale packages, CSPs )、塑膠晶粒承 載封裝(plastic Leaded Chip Carrier, PLCC )、塑膠雙列式 構裝(Plastic Dual In-Line Package,PDIP)、壓模疊片包 裝(Die in Waffle Pack)、壓模晶圓形式(Die in Wafer Form)、板上晶片封裝(Chip 〇n B〇ard,c〇B )、陶瓷雙 列式封裝(Ceramic Dual In-Line Package,CERDIP)、塑 料公制四方爲平封裝(Plastic Metric Quad Flat Pack, MQFP)、薄型四方扁平封装(Thin Quad Flatpack,tqfp)、 小外型封裝(Small Outline,SOIC)、收縮型小外形封裝 (Shrink Small Outline Package,SSOP)、薄小外型封裝 37 201232261. (Thin Small Outline,TSOP)、薄型四方扁平封装(Thin Quad Flatpack,TQFP)、系統級封裝(System in package, SIP )、多晶片封裝(Multi Chip Package,MCP )、晶圓級 製造封裝(Wafer- level Fabricated Package,WFP)以及晶 圓級堆疊封裝(Wafer-Level Processed Stack Package)箄 封裝型態。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此技㈣,在顿離本發明之 =範圍内,當可作些許之更動與潤飾,因此本發明 範圍當視後附之申請專利範圍所界定者為准。 ° 【圖式簡單說明】 而层Γίί,述’以上以及其他特徵將對變得· 而易見,/、中在各圖式中始終以相同的來 、 的部件’除非有不同的明確說明。/考‘絲不相同 置的=本發明之一實施例所繪示的快閃記憶體裝 圖2為繪示圖1的由所有位元線記憶 憶體塊所組成的記憶胞陣列的二、圖馬記 生器一實施例輯示的圖1他 記憶==;:=示的_明快閃 綠示的用,快 38 201232261 ~r χ \/ λ 圖6為根據本發明之一實施例所繪示的用以說明快閃 e己憶體裝置的寫人操作的時序示意圖。 圖7為根據本發明之另一實施例所繪示的圖1的隨機 產生器電路的功能方塊圖。 圖8為根據本發明之一實施例所繪式的虛擬隨機序列 產生器的示意圖。 圖9為繪示圖7的虛擬隨機序列產生器產生的初始虛 擬隨機序列資料的查找表清單的示意圖。 圖10為根據本發明之又一實施例所繪示的圖1的隨機 產生器電路的功能方塊圖。 圖11A為根據本發明之一實施例所繪示的快閃記憶體 裝置的隨機化方法的流程圖。 圖11B為根據本發明之^一實施例所纟會示的快閃記憶體 裝置的隨機化構想示意圖。 圖12為根據本發明之一實她例所纟會示的記憶體系統 的功能方塊圖。 圖13為根據本發明之另/實施例所繪示的記憶體系 統的功能方塊圖。 圖14為根據本發明之一實施例所繪示的固態硬碟的 功能方塊圖。 圖15為繪示使用圖14的固態硬碟的儲存裝置的功能 方塊圖。 % 圖16為繪示使用圖14的固態硬碟的儲存伺服器 能方塊圖。 ° 39 201232261. *1-IUl^pif 圖17至圖19為根據本發明之一實施例所繪示的系統 示意圖。 圖20至圖24為繪示適用本發明之一實施例的非揮發 性記憶體裝置的其他系統的示意圖。 【主要元件符號說明】 00h、05h、10h、30h、EOh :指令 100 :記憶胞陣列 200 :列選擇電路 300 :控制電路 400 :頁缓衝電路 500 :行選擇電路 600、600a :隨機產生器電路 610 :時序產生器 620 :選擇器 630、630a :虛擬隨機序列產生器 631〜634 :異或邏輯閘 640、 640a :自由運行偵測器 641、 641a :計數器 642、 642a :比較器 643a :除法器 650:混合器 670 :初始種子產生器 700 :輸入/輸出介面 1000、1000a :快閃記憶體 201232261 • Λ. Λ ^ 1100 、 2600a : 2000、2000a、 2100 ' 2100a : 2200、2000a : 2300、2300a : 隨機產生器電路 9222 :控制器 第一介面 第二介面 處理單元 2400、2400a :緩衝記憶體 2500、2500a :錯誤控制電路 3000、3000a :記憶體系統 4000 :固態硬碟 4000A :伺服器 4000B :獨立磁碟冗餘陣列控制器 6000、7000、8000 :系統 6100、4100 :儲存裝置 7100、7200 ··儲存伺服器 8100 :郵件伺服器 9201 :液晶顯示器模組 9202 :適應性差動脈碼調變編解碼器電路 9203 :揚聲器 9204 :麥克風 9205 :鍵盤 9206 :分時多工電路 9207 :非揮發性記憶體裝置 9208 :唯讀記憶體 9209 :靜態存取記憶體 41 201232261 -τ X V 1 ^jjif 9210 :鎖相迴路電路 9211 :射頻電路 9212 :系統控制微電腦 9221 :介面電路 9301 :機身 9302 ··插槽 9303 :鏡頭 9308 :顯示電路 9312 :快門按鈕 9318 :閃控 9331 :記憶卡 9332 :影像感測器 9336 :輸入/輸出裝置 9344 :中央處理器 9348 :隨機存取記憶體 9352 :匯流排 9354 :快閃記憶體裝置 ACC_EN :旗標信號 ADDRESS :位址匯流排 BL、BL0〜BL(m-l):位元線 BLe、BLeO〜BLe(n-l):偶位元線 BLo、BLoO〜BLo(n-l):奇位元線 Cl、C2 :行位址 CLK :時序信號 42 201232261 CLK_RS :隨機序列時序信號 CSL :通用來源線 D0〜Dn+2 :資料 DATA :資料匯流排 FF0〜FF10 :正反器 FRS :自由運行信號 GSL :接地選擇線 及:就緒/忙碌信號From micro-SD card, micro-SD card, memory, memory card Computer 34 201232261 Personal Computer Memory Card International Association card (PCMCIA card), Solid State Disk card (SSD card), chip card (Chip-Card), smart card and USB card. Referring to Figure 21, in accordance with an embodiment of the present invention, a memory card includes a interface circuit 9221, a controller 9222, and at least one flash memory device 9207. The interface circuit 9221 is used as an interface for communicating with an external device. Control Benefit 9222 includes buffer memory for controlling the operation of the memory card. The flash memory device 9207 can be comprised of a flash memory device for generating an initial seed for use with random data. The controller 9222 can also be used as a writer of the flash memory device 9207 and a processor for reading operations. The controller 9222 can be lightly connected to the non-volatile through the data bus DATA and the address bus ADDRE SS. Memory shows £92〇7 with interface circuit 9221. '+ The functional block diagram of the digital still camera of the flash memory of her case. Please refer to Figure 22. The machine includes the body gamma, slot 9302, and so on. In particular, the initial seed used is _==;== into slot 9308. In order to be inserted, when the memory card 9331 is inserted into the plug, it can be electrically connected to the memory card 9331. If the memory card 9331 is in contact type, the slot is on the circuit board 35 201232261. If the memory card 931 A is not in contact type, the electronic circuit on the circuit board can communicate with the memory card 9331 via radio frequency. ^ 23 is a schematic diagram of the multi-aged memory card of Figure 22. Please refer to ^® 23 'memory card 9331 for (4) video camera, (b) television, (c) video device, (4) game console, (4) electronic music device, (1) peak nest phone, (g) computer, (h ) Personal Digital Assistant (PDA), (1) Recorder, and (1) Personal Computer Card International Union Card. Figure 24 is a functional block diagram of an image sensing system suitable for use in a flash memory device in accordance with an embodiment of the present invention. Referring to FIG. 24, the image sensing system includes an image sensor 9332, an input/output device 9336, a random access memory 9348, a central processing unit 9344, and a flash memory device 9354 as shown in one embodiment of the present invention. . The components in FIG. 24, that is, the image sensor 9332, the input/output device 9336, the random access memory 9348, the central processing unit 9344, and the flash memory device 9354 all communicate with each other through the bus bar 9352. . Wherein, each component may also be comprised of a single wafer that is embedded in or external to the processor. ° In one embodiment of the invention, the memory cells may be composed of memory cells of variable group resistance. Examples of the memory cells of the variable group resistance and the memory device are disclosed in U.S. Patent No. 7,529,124, the entire disclosure of which is incorporated herein by reference. In another embodiment of the invention, the memory cell is comprised of one of a plurality of cell structures having a charge storage layer. The cell architecture 36 with the charge storage layer 201232261 HlUiypif includes a charge trap flash structure using a charge trap layer, a stack flash structure stacked by a plurality of layers, and a source free structure. (s〇urcedrain structure) and pin-type flash architecture (pin_typeflashstmcture). A memory device having a charge trapping flash structure as a charge storage layer has been disclosed in U.S. Patent No. 6,685,906, and U.S. Patent Nos. 20040169238 and No. 20040169238, the entireties of each of each of The source-free architecture has been disclosed in Korean Patent No. 673〇2, so it is hereby incorporated by reference in its entirety. The flash memory device or the recorder controller of the present invention can be packaged in a variety of package types. For example, the flash memory device or the n-body controller of the present invention may use, for example, a package package (PoP), a ball gate array (BGA), a wafer size package ( Chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip 〇n B〇ard (c〇B), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Square Package (Plastic Metric Quad Flat Pack, MQFP), Thin Quad Flatpack (tqfp), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Shape package 37 201232261. (Thin Small Outline, TSOP), Thin Quad Flatpack (TQFP), System in package (SIP), Multi-chip package (Multi Chip Package, MCP), Wafer-level Fabricated Package (WFP), and Wafer-Level Processed Stack Package (Package Type). Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any of the skilled artisan (4) may be modified and retouched within the scope of the invention, and thus the scope of the present invention is This is subject to the definition of the scope of the patent application. ° [Simple description of the drawings] and the layers Γίί, the above and other features will become easier to see, and /, in the drawings, the same components will always be the same unless otherwise specified. The flash memory device shown in one embodiment of the present invention is shown in FIG. 2 as a memory cell array composed of all the bit line memory memory blocks of FIG. FIG. 1 is a diagram of an embodiment of the present invention. FIG. 6 is a diagram showing a flashing green display, which is fast. 38 201232261 ~r χ \/ λ FIG. 6 is a diagram showing an embodiment of the present invention. A timing diagram for explaining the write operation of the flash memory device. FIG. 7 is a functional block diagram of the random generator circuit of FIG. 1 according to another embodiment of the present invention. Figure 8 is a schematic illustration of a virtual random sequence generator in accordance with an embodiment of the present invention. 9 is a schematic diagram showing a lookup table list of initial virtual random sequence data generated by the virtual random sequence generator of FIG. 7. FIG. 10 is a functional block diagram of the random generator circuit of FIG. 1 according to yet another embodiment of the present invention. FIG. 11A is a flow chart of a method for randomizing a flash memory device according to an embodiment of the invention. Figure 11B is a schematic illustration of the randomized conception of a flash memory device as shown in an embodiment of the present invention. Figure 12 is a functional block diagram of a memory system as illustrated by one example of the present invention. Figure 13 is a functional block diagram of a memory system in accordance with another embodiment of the present invention. FIG. 14 is a functional block diagram of a solid state hard disk according to an embodiment of the invention. Figure 15 is a functional block diagram showing the storage device using the solid state hard disk of Figure 14. Figure 16 is a block diagram showing the storage server using the solid state drive of Figure 14. ° 39 201232261. *1-IUl^pif Figures 17 through 19 are schematic views of a system in accordance with an embodiment of the present invention. 20 through 24 are schematic views showing other systems of a non-volatile memory device to which an embodiment of the present invention is applied. [Description of main component symbols] 00h, 05h, 10h, 30h, EOh: Command 100: Memory cell array 200: Column selection circuit 300: Control circuit 400: Page buffer circuit 500: Row selection circuit 600, 600a: Random generator circuit 610: timing generator 620: selectors 630, 630a: virtual random sequence generators 631 to 634: exclusive OR logic gates 640, 640a: free running detectors 641, 641a: counters 642, 642a: comparators 643a: dividers 650: Mixer 670: initial seed generator 700: input/output interface 1000, 1000a: flash memory 201232261 • Λ. Λ ^ 1100, 2600a: 2000, 2000a, 2100 ' 2100a: 2200, 2000a: 2300, 2300a: Random generator circuit 9222: controller first interface second interface processing unit 2400, 2400a: buffer memory 2500, 2500a: error control circuit 3000, 3000a: memory system 4000: solid state hard disk 4000A: server 4000B: independent magnetic Disk Redundant Array Controller 6000, 7000, 8000: System 6100, 4100: Storage Device 7100, 7200 · Storage Server 8100: Mail Server 9201: Liquid Crystal Display Module 9202: Adaptability Arterial code modulation codec circuit 9203: speaker 9204: microphone 9205: keyboard 9206: time division multiplexing circuit 9207: non-volatile memory device 9208: read only memory 9209: static access memory 41 201232261 -τ XV 1 ^jjif 9210 : Phase-locked loop circuit 9211 : RF circuit 9212 : System control microcomputer 9221 : Interface circuit 9301 : Body 9302 · · Slot 9303 : Lens 9308 : Display circuit 9312 : Shutter button 9318 : Flash control 9331 : Memory card 9332: Image sensor 9336: Input/output device 9344: Central processing unit 9348: Random access memory 9352: Bus 8354: Flash memory device ACC_EN: Flag signal ADDRESS: Address bus bar BL, BL0~ BL (ml): bit line BLe, BLeO ~ BLe (nl): even bit line BLo, BLoO ~ BLo (nl): odd bit line Cl, C2: row address CLK: timing signal 42 201232261 CLK_RS: random Sequence timing signal CSL: general source line D0~Dn+2: data DATA: data bus FF0~FF10: flip-flop FRS: free running signal GSL: ground selection line and: ready/busy signal
Rl、R2、R3 ··列位址 RE/WE :讀取/寫入致能訊號 RS :隨機序列 RSD、RSD0〜RSDn+2 :隨機序列資料 S100〜S130 :步驟 SEL0〜SEL10 :選擇器 SSL :字串選擇線 tPGM、tR :時間區間 WL、WL0〜WLm-1 :字線 43Rl, R2, R3 ··column address RE/WE: read/write enable signal RS: random sequence RSD, RSD0~RSDn+2: random sequence data S100~S130: steps SEL0~SEL10: selector SSL: String selection line tPGM, tR: time interval WL, WL0 WLWL-1: word line 43
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US13/326,820 US8751729B2 (en) | 2010-12-23 | 2011-12-15 | Flash memory device and memory system including the same |
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TWI471731B (en) * | 2013-03-29 | 2015-02-01 | Mediatek Inc | Memory access method, memory access control method, spi flash memory device and spi controller |
TWI496149B (en) * | 2013-01-31 | 2015-08-11 | Ememory Technology Inc | Flash memory and associated programming method |
TWI548216B (en) * | 2015-07-02 | 2016-09-01 | 威盛電子股份有限公司 | Control chip and control system utilizing the same |
TWI743715B (en) * | 2020-03-24 | 2021-10-21 | 瑞昱半導體股份有限公司 | Method and apparatus for performing data protection regarding non-volatile memory |
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TWI496149B (en) * | 2013-01-31 | 2015-08-11 | Ememory Technology Inc | Flash memory and associated programming method |
TWI471731B (en) * | 2013-03-29 | 2015-02-01 | Mediatek Inc | Memory access method, memory access control method, spi flash memory device and spi controller |
TWI548216B (en) * | 2015-07-02 | 2016-09-01 | 威盛電子股份有限公司 | Control chip and control system utilizing the same |
US10153759B2 (en) | 2015-07-02 | 2018-12-11 | Via Technologies, Inc. | Control chip and control system utilizing the same |
TWI743715B (en) * | 2020-03-24 | 2021-10-21 | 瑞昱半導體股份有限公司 | Method and apparatus for performing data protection regarding non-volatile memory |
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