201228511 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及電路板製作技術，尤其涉及一種具有凹槽之 多層電路板之製作方法。 【先前技#ί】 [0002] 隨著科學技術之進步，印刷電路板在電子產品中得到廣 泛應用。關於電路板之應用請參見文獻Takahashi，Α. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880 5 IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992， 15(4): 418-425。 [0003] 隨著電子產品小型化之要求，對於印刷電路板亦提出了 挑戰。目前之一種技術趨勢是將電子元器件埋置於多層 電路板内，以使構裝於多層電路板之電子元器件不佔用 電子產品内之空間。這種方法需要預先在多層電路板内 形成一凹槽，在凹槽底部設置線路，再將電子元器件組 裝在凹槽内，並與凹槽底部之線路電連接。然而，在製 作多層電路板之過程中，凹槽内容易進入各種藥水，從 而可能造成凹槽底部線路之破損，最後影響電子元器件 之組裝。 [0004] 有鑑於此，提供一種具有較高良率之多層印刷電路板之 製作方法實屬必要。 【發明内容】 [0005] 以下將以實施例說明一種多層電路板之製作方法。 099147118 表單編號A0101 第4頁/共32頁 0992080943-0 201228511 [0006] Ο ο [0007] 一種多層電路板之製作方法，包括步驟：提供一電路基 板，所述電路基板包括基底及形成於基底表面之線路層 ，所述線路層具有相鄰接之組裝區與壓合區；在線路層 之組裝區形成第一防焊層；將保護膠片貼合於第一防焊 層表面；提供第一膠黏片與第一銅箔，所述第一膠黏片 具有與保護膠片對應之第一開口，將第一膠黏片與第一 銅箔壓合於電路基板，並使保護膠片位於第一開口中； 將第一銅箔形成第一線路圖形，所述第一線路圖形具有 與保護膠片對應之第一窗口；提供第二膠黏片與第二銅 箔，並將第二膠黏片與第二銅箔壓合於電路基板，所述 第二膠黏片位於第一線路圖形與第二鋼箔之間；將第二 銅箔形成第二線路圖形，所述第二線路圖形具有第二窗 口，所述第二窗口與保護膠片之邊界對應；在第二線路 圖形表面形成第二防焊層，所述第二防焊層暴露出所述 第二窗口；從第二窗口在第二膠黏片中形成與保護膠片 對應之第二開口，所述第二窗口、第二開口、第一窗口 及第一開口依次連通，共同構成一凹槽，所述保護膠片 暴露於凹槽中；以及去除保護膠片，從而製成一具有凹 槽之多層電路板。 本技術方案之多層電路板之製作方法具有如下優點：首 先，在壓合第一膠黏片、第一銅箔、第二膠黏片與第二 銅箔之過程中，在組裝區之第一防焊層表面形成保護膠 片，如此，可以保護組裝區之線路層，避免組裝區之線 路層受到損傷；其次，先在第一膠黏片中形成了與保護 膠片對應之開口，再壓合第一膠黏片，如此，則避免了 099147118 表單編號Α0101 第5頁/共32頁 0992080943-0 201228511 保護膠片造成壓合後第一銅箔表面凹凸不平之現象，使 得壓合之後之第一銅箔表面非常平整，有利於蝕刻形成 精確之第一線路圖形；再次，由於銅材料之去除較為不 易，而膠黏片較為柔軟，其材料之去除較為容易，本技 術方案中，在將第一銅箔與第二銅箔形成線路圖形之過 程中，形成了與保護膠片對應之第一窗口與第二窗口， 從而5使得保護膠片上方僅有第二勝黏片之材料需要去 除，如此，可以很容易地形成第二開口，從而暴露出保 護膠片，以方便保護膠片之去除；最後，本技術方案採 用在形成線路圖形之過程中形成第一窗口與第二窗口， 而不需額外增加步驟，亦即，本技術方案之製作具有凹 槽之多層電路板之方法步驟較為簡單，製程時間較短， 量產時可具有較高產量與良率。 【實施方式】 [0008] 下面將結合附圖及實施例，對本技術方案提供之多層電 路板之製作方法作進一步之詳細說明。 [0009] 本技術方案實施例提供的多層電路板之製作方法包括以 下步驟： [0010] 第一步，請參閱圖1，提供一電路基板10。所述電路基板 10包括基底11與線路層12。所述基底11可以為單面板、 雙面板或者多層板。在本實施例中，電路基板10為四層 板，基底11為三層板。基底11包括依次設置之第一絕緣 層111、第一導電層112、第二絕緣層113、第二導電層 114、第三絕緣層115及第三導電層116。所述第一導電 層112、第二導電層114及第三導電層116均由導電材料 099147118 表單編號A0101 第6頁/共32頁 0992080943-0 201228511 θ [0011] 如銅製成，且均已形成導電線路圖形。所述第—絕緣層 111、第二絕緣層113及第三絕緣層115均由絕緣材料製 成，例如環氡樹脂、聚醯亞胺等。所述第二絕緣層113位 於第一導電層112與第二導電層114之間。所述第一導電 層112與第二導電層114藉由設置在第二絕緣層U3内之 至少一個第一埋導孔101實現相互電連接，所述至少一個 第一埋導孔101内還填充有塞孔樹脂。所述第三絕緣層 115位於第二導電層114與第三導電層U6之間。所述第 二導電層114與第三導電層116藉由設置在第三絕緣層 115内之至少一個第一盲導孔1〇2實瑰相互電連接。 所述線路層12形成於第一絕緣層U1之表面，亦即，第一 絕緣層111位於第一導電層112與線路層12之間。線路層 12亦可由銅箔製成，且亦形成有導電線路圖形。線路層 12藉由設置在第一絕緣層111内之至少一個第二盲導孔 103與第一導電層11 2電連接。所述線路層12具有相鄰之 組裝區121與壓合區122 »所述組裝區丨21與壓合區122均 分佈有導電線路圖形。所述組裝區121之導電線路圖形包 括至少一條導電線路1211與至少一個導電端子1212，所 述至少一個導電端子1212用於構裝一電子元器件。在本 實施例中，所述壓合區122環繞鄰接在組裝區121周圍。 [0012] 第二步，請參閱圖2，藉由印刷或噴塗之方法在線路層12 之.組裝區121形成第一防焊層13，所述第一防谭層13覆蓋 組裝區121之至少一條導電線路12u，並暴露出至少一個 導電端子1212。另外，第一防焊層】3還可以覆蓋部分位 於組裝區121周圍之壓合區122。亦即，第一防焊層13之 099147118 表單編號A0I01 第7頁/共32頁 0992080943-0 201228511 覆蓋面積可以大於或等於組裝區121之分佈面積。在本實 施例中，第一防焊層13形成在組裝區121之至少一條導電 線路1211表面，還形成在從組裝區121之導電線路圖形暴 露出之第一絕緣層ill之表面，還形成在組裝區121周圍 之線路層12之表面。 [0013] [0014] [0015] [0016] 第二步，請一併參閱圖3與圖4，將保護膠片20貼合於第 一防焊層13之表面。所述保護膠片2〇可以為聚對苯二曱 酸乙二醇酯耐高溫膠帶與聚四氟乙烯耐高溫膠帶。 將保護膠片20貼合於第一防焊層13之表面可以包括步驟 :首先，參閱圖3，在第一防焊層13表面、從第_防焊層 13暴露出之線路層12之表面及從線路層12暴露出之第一 絕緣層111之表面貼合一層保護膠層21。其次以雷射切 J保道膠層21，從而形成一個圍繞組裝區1 21之環形開口 21〇。環形開口 210包圍之保護膠層21即構成了所述保護 膠片20。再次，撕除環形開口 21〇以外之保護膠層以，而 留下環形開口 210以内之保護膠層21 ’如此，即形成了貼 合在第一防焊層13表面之係護膠片20，如圖4所示。 第四步，請參閱圖5 ’提供第一膠黏片14與第一銅箔15 , 所述第-_片14具有與保護膠# 2Q對應之第_開口 。所述第-P扣14G可以藉由沖裁之方式形成。所述第一 開口 140之橫截面積大於或等於保護膠片2()之橫戴面積。 在本實施例中，所述Ll狀㈣面積大於保護膠 片20之橫戴面積。 然後，使貼合在組裝區121之保護膠片20與第一開口 14〇 099147118 表單編號A0101 第δ頁/共32頁 0992080943-0 201228511 [0017] Ο ο [0018] 099147118 相對應，並將第一朦黏片14與第一銅猪15屢合於電路基 板10。即，將第一膠黏片14壓合在線路層12之壓合區 與第銅7自1 5之間，且使得貼合在組裝區1 2;[之保護 膠片20位於第一開口 14〇中。所述第一膠黏片^主要由聚 丙烯類樹脂與玻璃纖維組成。 第五步，請參閱圖6，採用雷射蝕刻或化學蝕刻之方法將 第銅；I5形成第一線路圖形151，並電連接線路層12與 第一線路圖形151。所述第一線路圖形151具有與保護膠 片20對應之第—窗σ15()，所述第―窗口15()與第一開口 140相連通，從而暴露出保護膠片20。在本實施例中，所 述第一窗口 150之橫截面積等於第一開口 140之橫截面積 ，所述線路層12與第一線路圖形ί51藉由設置在第一膠黏 片14内之至少一個第三盲導孔1〇4實現電連接。所述至少 一個第三盲導孔104可以在形成第一線路圖形151之前形 成，且可以藉由以下步驟形成：先藉由定深機械鑽孔工 藝或雷射鑽孔工藝形成至少一個貫穿第一膠黏片14與第 一銅4 15之盲孔；再藉由電鍍工藝在所述至少_個盲孔 内沈積導電材料，從而形成電連接線路層12與第一銅箔 15之所述至少一個第三盲導孔1〇4。如此，在將第一鋼箔 15蝕刻成第一線路圖形151之後，所述至少一個第三盲導 孔104即可起到電連接線路層12與第一線路圖形“I之作 用。 第六步’請參閱圖7，提供第二膠黏片16與第二銅箱17， 並將第二膠黏片16與第二銅镇17壓合於電路基板1〇。即 ，將第二膠黏片16壓合在第一線路圖形151與第二銅箔17 表單編號Α0101 第9頁/共32頁 0992080943-0 201228511 之間。所述第二膠黏片16之材料基本與第一膠黏片14之 材料相同。 [0019] [0020] [0021] [0022] 第七步，請參閱圖8，採用雷射蝕刻或化學蝕刻之方法將 第二銅H17形成第二線路圖形171，並電連接第二線路圖 形171與第一線路圖形151。 所述第二線路圖形171具有第二窗口 17〇，以至少暴露出 第二膠黏片16中與保護膠片2〇之邊界對應之區域。可以 說，保護膠片20之垂直投影位於第二窗口 m之垂直投影 内，或者，保護膠片20之邊界之垂直投影位於第二窗口 Π0之最外邊界之垂直投影内。 在蝕刻時，可以將與保護膠片20對應區域之第二銅箔17 全部蚀刻去除’從而形成-個橫截面積大於或等於保護 膠片20之所述第二窗口170，如圖8所示。在本實施例中 ，保護膠片20之垂直投影位於第二窗口 17〇之垂直投影内 ，所述第二窗口170之橫截面積等於第一窗口 15〇之橫截 面積。 除如實施觸科’在㈣時，亦可舰縣除對應於 保護膝㈣邊界的部分第二㈣17，形成—個與保護膠 片20之邊界對應的環形的第二窗口17()，而並不姓刻去除 環形的第二窗口 170内的第二銅结17。亦即，使得保護膠 片20邊界之垂直投影位於環形的第二窗口 17〇最外邊界之 垂直投影内。 本實施例中，藉由設置在第二膠黏片16之至少一個第四 盲導孔105電連接第二線路圖形m與第一線路圖形151 099147118 表單編號Α0101 第10頁/共32頁 0992080943-0 [0023] 201228511 ，還藉由至少一個第二導通孔1〇6電連接第二線路圖形 171、第一線路圖形151、線路層12及第三導電層116。 [0024] Ο [0025] ❹ 第四盲導孔105與第二導通孔106可以在钱刻第二銅箔17 以第二線路圖形〗71之前製作形成。第四盲導孔1〇5可以 藉由與製作第三盲導孔104相似之步驟製作形成。第二導 通孔106可以藉由以下步驟製作形成：採用機械鑽孔工藝 形成貝穿第二銅箔17、第二膠黏片16、第一線路圖形151 、第一膠黏片14及電路基板10之通孔；藉由電鍍在通孔 孔壁沈積導電㈣；在通孔㈣塞塞孔材料；以及在塞 孔材料表面再次沈積導電材料，從而难成了所述第二導 通孔106。在钱刻第二銅箔丨7 ,形成第二線路圖形171之 後第四盲導孔105就可以起到電連接第二線路圖形171 與第一線路圖形151之作用，第二導通孔106就可以電連 接第二線路圖形17卜第-線路圖形151、線路層12及第 三導電層116。 第八步，請參閱圖9，在第二線路圖形171表面形成第二 防焊層18，並在第二導電層116表面形成第三防焊層 所述第—防焊層18覆蓋第二線路圖形171之表面，還覆蓋 在從第二線路圖形171暴露出之第二膠黏片16之表面。當 然’第二防焊層18暴露出第二窗口 170。所述第三防焊層 19覆蓋第三導電層116之導電線路圖形之表面，還覆蓋從 第三導電層116暴露出之第三絕緣層115之表面。所述第 二防焊層18與第三防焊層19均可以藉由印刷或喷塗之方 法形成。 099147118 表單編號Α0101 第11頁/共32頁 0992080943-0 [0026] 201228511 1 8同時形成外’還可以與第一防焊層1 3同時形成。 [0027] [0028] [0029] [0030] 第九步，請參閱圖10,從第二窗口】70在第二膠黏片16中 形成與保護膠片20對應之第二開口 160，亦即，去除保護 膠片20上方之第二膠黏片16，從而暴露出保護膠片2〇。 所述保護膠片20之垂直投影位於第二開口 16〇之垂直投影 内。第一窗口 170 '第二開口 160、第一窗口 150及第一 開口 140依次連通，共同構成一個凹槽1〇〇，保護膠片2〇 位於凹槽1〇〇中。所述凹槽100用於收容一電子元器件。 在本實施例中，採用以下方法暴露出保護膠片2〇 :以雷 射沿保護膠片20之邊界切割從第二窗口 17〇暴露出之第二 膠黏片16，形成一環形切口，所述環形切口環繞保護膠 片20上方之第二膠黏片16，從而使得該部分被環形切口 環繞之第二耀黏片16自然脫落，從而形成暴露出保護膠 片20之第二開口 16〇。 可以理解，如果第二窗口 1 7Q為環形..窗口時，切割第二谬 黏片16而使得保護膠片20上方之被環形切口環繞之第二 膠黏片16自然脫落時，環形之第二窗口 17〇内未被蝕刻去 除的第二銅箔17亦自然隨之脫落。 另外，本領域技術人員可以理解，第一膠黏片14與第二 膠黏片16在壓合之過程中，可能會出現溢膠之現象，即 ，可能使得部分第一膠黏片14之材料與部分第二膠黏片 16之材料溢流至第一開口 140内，甚至流至保護膠片2〇表 面在形成第一開口 16 0後，可以藉由鑷子或其他工具剝 離這部分材料。 099147118201228511 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit board manufacturing technique, and more particularly to a method of fabricating a multilayer circuit board having a recess. [Previous technology #ί] [0002] With the advancement of science and technology, printed circuit boards have been widely used in electronic products. For application of the circuit board, please refer to the literature Takahashi, Α. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880 5 IEEE Trans , on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 418-425. [0003] With the demand for miniaturization of electronic products, challenges have also been placed on printed circuit boards. A current technology trend is to embed electronic components in a multi-layer circuit board so that electronic components mounted on the multi-layer circuit board do not occupy space in the electronic product. This method requires a groove to be formed in the multilayer circuit board in advance, a circuit is provided at the bottom of the groove, and the electronic component group is mounted in the groove and electrically connected to the line at the bottom of the groove. However, in the process of manufacturing a multi-layer circuit board, various kinds of syrups are easily entered in the grooves, which may cause breakage of the circuit at the bottom of the groove, and finally affect the assembly of the electronic components. In view of the above, it is necessary to provide a method of fabricating a multilayer printed circuit board having a high yield. SUMMARY OF THE INVENTION [0005] Hereinafter, a method of fabricating a multilayer circuit board will be described by way of embodiments. 099147118 Form No. A0101 Page 4 / Total 32 Page 0992080943-0 201228511 [0007] A method for fabricating a multilayer circuit board, comprising the steps of: providing a circuit substrate comprising a substrate and a surface formed on the substrate a circuit layer having an adjacent assembly area and a nip area; forming a first solder resist layer in the assembly area of the circuit layer; bonding the protective film to the surface of the first solder resist layer; providing the first glue a first copper sheet having a first opening corresponding to the protective film, the first adhesive sheet and the first copper foil being pressed onto the circuit substrate, and the protective film is located at the first opening Forming a first line pattern, the first line pattern having a first window corresponding to the protective film; providing a second adhesive sheet and the second copper foil, and the second adhesive sheet The second copper foil is pressed against the circuit substrate, the second adhesive sheet is located between the first circuit pattern and the second steel foil; the second copper foil is formed into the second circuit pattern, and the second circuit pattern has the second window , the second window and the protective glue Corresponding to the boundary of the sheet; forming a second solder mask on the surface of the second line pattern, the second solder mask exposing the second window; forming a corresponding protective film from the second window in the second adhesive sheet a second opening, the second window, the second opening, the first window and the first opening are sequentially connected to each other to form a groove, the protective film is exposed in the groove; and the protective film is removed, thereby forming a Multi-layer circuit board with grooves. The manufacturing method of the multi-layer circuit board of the technical solution has the following advantages: first, in the process of pressing the first adhesive sheet, the first copper foil, the second adhesive sheet and the second copper foil, the first in the assembly area The surface of the solder resist layer forms a protective film, so that the circuit layer of the assembly area can be protected and the circuit layer of the assembly area is damaged; secondly, an opening corresponding to the protective film is formed in the first adhesive sheet, and then the first part is pressed. An adhesive sheet, thus avoiding 099147118 Form No. 1010101 Page 5 / Total 32 Page 0992080943-0 201228511 Protective film causes unevenness of the surface of the first copper foil after pressing, so that the first copper foil after pressing The surface is very flat, which is favorable for etching to form a precise first line pattern; again, since the removal of the copper material is relatively difficult, and the adhesive sheet is relatively soft, the removal of the material is relatively easy. In the technical solution, the first copper foil is used. In the process of forming a line pattern with the second copper foil, a first window and a second window corresponding to the protective film are formed, so that 5 has only the second winning sheet above the protective film. The material needs to be removed, so that the second opening can be easily formed to expose the protective film to facilitate the removal of the film. Finally, the technical solution adopts the process of forming the first window and the second window in the process of forming the circuit pattern. There is no need to add additional steps, that is, the method of manufacturing the multi-layer circuit board with the groove of the technical solution is simple, the process time is short, and the production and the yield can be high. [Embodiment] [0008] Hereinafter, a method for fabricating a multilayer circuit board provided by the present technical solution will be further described in detail with reference to the accompanying drawings and embodiments. [0009] The first step of referring to FIG. 1 provides a circuit substrate 10. The circuit substrate 10 includes a substrate 11 and a wiring layer 12. The substrate 11 can be a single panel, a double panel or a multilayer panel. In the present embodiment, the circuit substrate 10 is a four-layer board, and the substrate 11 is a three-layer board. The substrate 11 includes a first insulating layer 111, a first conductive layer 112, a second insulating layer 113, a second conductive layer 114, a third insulating layer 115, and a third conductive layer 116 which are sequentially disposed. The first conductive layer 112, the second conductive layer 114, and the third conductive layer 116 are all made of conductive material 099147118 Form No. A0101 Page 6 / Total 32 Page 0992080943-0 201228511 θ [0011], such as copper, and have been formed Conductive line pattern. The first insulating layer 111, the second insulating layer 113, and the third insulating layer 115 are each made of an insulating material such as a ring-ring resin, a polyimide or the like. The second insulating layer 113 is located between the first conductive layer 112 and the second conductive layer 114. The first conductive layer 112 and the second conductive layer 114 are electrically connected to each other by at least one first buried via 101 disposed in the second insulating layer U3, and the at least one first buried via 101 is further filled. There is a plug resin. The third insulating layer 115 is located between the second conductive layer 114 and the third conductive layer U6. The second conductive layer 114 and the third conductive layer 116 are electrically connected to each other by at least one first blind via hole 1〇2 disposed in the third insulating layer 115. The wiring layer 12 is formed on the surface of the first insulating layer U1, that is, the first insulating layer 111 is located between the first conductive layer 112 and the wiring layer 12. The wiring layer 12 can also be made of copper foil and also formed with a conductive trace pattern. The wiring layer 12 is electrically connected to the first conductive layer 11 2 by at least one second blind via 103 disposed in the first insulating layer 111. The circuit layer 12 has an adjacent assembly area 121 and a nip area 122. The assembly area 丨21 and the nip area 122 are each distributed with a conductive line pattern. The conductive trace pattern of the assembly area 121 includes at least one conductive trace 1211 and at least one conductive terminal 1212 for mounting an electronic component. In the present embodiment, the nip 123 surrounds the periphery of the assembly area 121. [0012] In the second step, referring to FIG. 2, a first solder resist layer 13 is formed on the assembly area 121 of the circuit layer 12 by printing or spraying, and the first anti-tamer layer 13 covers at least the assembly area 121. A conductive line 12u exposes at least one of the conductive terminals 1212. In addition, the first solder resist layer 3 may also cover a portion of the nip region 122 located around the assembly area 121. That is, the first solder mask layer 13 099147118 Form No. A0I01 Page 7 of 32 0992080943-0 201228511 The coverage area may be greater than or equal to the distribution area of the assembly area 121. In the present embodiment, the first solder resist layer 13 is formed on the surface of the at least one conductive trace 1211 of the assembly region 121, and is also formed on the surface of the first insulating layer ill exposed from the conductive trace pattern of the assembly region 121, and is also formed on the surface. The surface of the wiring layer 12 around the assembly area 121. [0016] [0016] In the second step, referring to FIG. 3 and FIG. 4 together, the protective film 20 is attached to the surface of the first solder resist layer 13. The protective film 2 can be a polyethylene terephthalate high temperature resistant tape and a polytetrafluoroethylene high temperature resistant tape. The bonding of the protective film 20 to the surface of the first solder resist layer 13 may include the steps of: first, referring to FIG. 3, on the surface of the first solder resist layer 13, the surface of the wiring layer 12 exposed from the first solder resist layer 13 and A protective layer 21 is adhered to the surface of the first insulating layer 111 exposed from the wiring layer 12. Next, the rubber layer 21 is cut by a laser to form an annular opening 21 围绕 surrounding the assembly area 121. The protective film layer 21 surrounded by the annular opening 210 constitutes the protective film 20. Again, the protective adhesive layer other than the annular opening 21〇 is removed to leave the protective adhesive layer 21' inside the annular opening 210. Thus, the protective film 20 attached to the surface of the first solder resist layer 13 is formed, such as Figure 4 shows. In the fourth step, referring to FIG. 5', a first adhesive sheet 14 and a first copper foil 15 are provided, and the first-sheet 14 has a first opening corresponding to the protective adhesive #2Q. The first-P button 14G can be formed by punching. The cross-sectional area of the first opening 140 is greater than or equal to the cross-sectional area of the protective film 2(). In this embodiment, the L1-shaped (four) area is larger than the cross-sectional area of the protective film 20. Then, the protective film 20 attached to the assembly area 121 is made to correspond to the first opening 14〇099147118, the form number A0101, the δ page, the total of 32 pages 0992080943-0 201228511 [0017] ο ο [0018] 099147118, and will be the first The 朦 adhesive sheet 14 and the first copper pig 15 are repeatedly assembled on the circuit substrate 10. That is, the first adhesive sheet 14 is pressed between the nip of the circuit layer 12 and the copper 7 from 15 and is attached to the assembly area 1 2; [the protective film 20 is located at the first opening 14 〇 in. The first adhesive sheet is mainly composed of a polypropylene resin and glass fibers. In the fifth step, referring to FIG. 6, the copper is formed by laser etching or chemical etching; I5 forms a first line pattern 151, and electrically connects the circuit layer 12 and the first line pattern 151. The first line pattern 151 has a first window σ15() corresponding to the protective film 20, and the first window 15() communicates with the first opening 140 to expose the protective film 20. In this embodiment, the cross-sectional area of the first window 150 is equal to the cross-sectional area of the first opening 140, and the circuit layer 12 and the first line pattern ί51 are at least disposed in the first adhesive sheet 14. A third blind via hole 1〇4 is electrically connected. The at least one third blind via 104 may be formed before the first trace pattern 151 is formed, and may be formed by forming at least one through the first glue by a deep mechanical drilling process or a laser drilling process. a bonding hole 14 and a blind hole of the first copper 4 15; and depositing a conductive material in the at least one blind hole by an electroplating process to form the at least one of the electrical connection layer 12 and the first copper foil 15 Three blind guide holes 1〇4. Thus, after the first steel foil 15 is etched into the first line pattern 151, the at least one third blind via 104 can function as the electrical connection layer 12 and the first line pattern "I. Step 6" Referring to FIG. 7, a second adhesive sheet 16 and a second copper box 17 are provided, and the second adhesive sheet 16 and the second copper strip 17 are pressed against the circuit substrate 1A. That is, the second adhesive sheet 16 is used. Pressing between the first line pattern 151 and the second copper foil 17 form number Α0101, page 9 / total 32 pages 0992080943-0 201228511. The material of the second adhesive sheet 16 is substantially the same as that of the first adhesive sheet 14 [0021] [0022] In the seventh step, referring to FIG. 8, the second copper H17 is formed into a second line pattern 171 by laser etching or chemical etching, and electrically connected to the second The line pattern 171 and the first line pattern 151. The second line pattern 171 has a second window 17〇 to expose at least an area of the second adhesive sheet 16 corresponding to the boundary of the protective film 2〇. The vertical projection of the film 20 is located within the vertical projection of the second window m, or the boundary of the protective film 20 The vertical projection is located in the vertical projection of the outermost boundary of the second window Π 0. During etching, the second copper foil 17 corresponding to the protective film 20 can be completely etched away to form a cross-sectional area greater than or equal to the protective film. The second window 170 of 20 is as shown in Fig. 8. In the embodiment, the vertical projection of the protective film 20 is located in the vertical projection of the second window 17, and the cross-sectional area of the second window 170 is equal to The cross-sectional area of a window 15 。. In addition to the implementation of the contact (in the fourth), the ship county can also form a ring corresponding to the boundary of the protective film 20 except for the second (four) 17 corresponding to the boundary of the protective knee (four). The second window 17() does not remove the second copper junction 17 in the annular second window 170. That is, the vertical projection of the boundary of the protective film 20 is located perpendicular to the outermost boundary of the annular second window 17 In the embodiment, the second line pattern m and the first line pattern 151 are formed by at least one fourth blind via 105 disposed on the second adhesive sheet 16 . Form number Α 0101 Page 10 / Total 32 pages 099208094 3-0 [0023] 201228511, the second line pattern 171, the first line pattern 151, the wiring layer 12, and the third conductive layer 116 are also electrically connected by at least one second via hole 1〇6. [0024] Ο [0025] The fourth blind via 105 and the second via 106 can be formed before the second copper foil 17 is formed by the second line pattern 71. The fourth blind via 1〇5 can be formed by using the third blind via 104. A similar step is formed. The second via hole 106 can be formed by forming a second copper foil 17, a second adhesive sheet 16, a first line pattern 151, and a first adhesive layer by a mechanical drilling process. a through hole of the sheet 14 and the circuit substrate 10; depositing conductive (4) on the wall of the through hole by electroplating; plugging the hole material in the through hole (4); and depositing a conductive material on the surface of the plug hole material, thereby making it difficult to become the second Via hole 106. After the second copper foil 丨7 is formed, the fourth blind via 105 can electrically connect the second line pattern 171 with the first line pattern 151, and the second via 106 can be electrically The second line pattern 17 is connected to the first line pattern 151, the line layer 12, and the third conductive layer 116. In the eighth step, referring to FIG. 9, a second solder resist layer 18 is formed on the surface of the second line pattern 171, and a third solder resist layer is formed on the surface of the second conductive layer 116. The first solder mask layer 18 covers the second line. The surface of the pattern 171 also covers the surface of the second adhesive sheet 16 exposed from the second line pattern 171. Of course, the second solder mask 18 exposes the second window 170. The third solder resist layer 19 covers the surface of the conductive trace pattern of the third conductive layer 116 and also covers the surface of the third insulating layer 115 exposed from the third conductive layer 116. Both the second solder resist layer 18 and the third solder resist layer 19 can be formed by printing or spraying. 099147118 Form No. Α0101 Page 11 of 32 0992080943-0 [0026] 201228511 1 8 Simultaneously forming the outer side can also be formed simultaneously with the first solder resist layer 13. [0030] [0030] [0030] In the ninth step, referring to FIG. 10, a second opening 160 corresponding to the protective film 20 is formed in the second adhesive sheet 16 from the second window 70, that is, [0028] The second adhesive sheet 16 above the protective film 20 is removed to expose the protective film 2 . The vertical projection of the protective film 20 is located within the vertical projection of the second opening 16''. The first window 170', the second opening 160, the first window 150 and the first opening 140 are sequentially connected to form a recess 1 〇〇, and the protective film 2 〇 is located in the recess 1 。. The groove 100 is used to house an electronic component. In the present embodiment, the protective film 2 is exposed by cutting the second adhesive sheet 16 exposed from the second window 17 by laser along the boundary of the protective film 20 to form an annular slit, the ring The slit surrounds the second adhesive sheet 16 above the protective film 20 such that the second flared sheet 16 surrounded by the annular slit naturally falls off, thereby forming a second opening 16〇 exposing the protective film 20. It can be understood that if the second window 1 7Q is a ring-shaped window, the second adhesive sheet 16 is cut so that the second adhesive sheet 16 surrounded by the annular slit above the protective film 20 naturally falls off, the second window of the ring The second copper foil 17 which has not been removed by etching in 17 turns naturally also falls off. In addition, those skilled in the art can understand that during the process of pressing the first adhesive sheet 14 and the second adhesive sheet 16, there may be a phenomenon of overflowing, that is, a material which may make part of the first adhesive sheet 14 The material of the portion of the second adhesive sheet 16 overflows into the first opening 140, and even flows to the surface of the protective film 2 after the first opening 16 0 is formed, and the portion of the material can be peeled off by the tweezers or other tools. 099147118
表單編號A010I 第12頁/共32頁 0992080943-0 201228511 [0031] [0032] Ο ❹ [0033] 第十步，可以藉由真空吸附或人工作業方法去除暴露出 之保護膠片20，從而暴露出所述第一防焊層13及所述至 少一個導電端子1212。此時，即形成了具有凹槽100之多 層電路板10a，所述多層電路板10a可用於構裝一個電子 元器件。 第十一步，請參閱圖11，在線路層12之組裝區121構裝一 個電子元器件30，所述電子元器件30收容於凹槽100内。 在本實施例中，藉由以下步驟實現電子元器件30之構裝 :首先，提供一所述電子元器件30，所述電子元器件30 可以為主動元件，亦可以為被動元件，例如，可以為晶 片。所述電子元器件30具有至少一個導電接點31，所述 至少一個導電接點31與所述至少一個導電端子1212相對 應。導電接點31可以為焊盤、引腳、端子或其他接觸元 件。其次，將所述電子元器件30放置於凹槽100内，並使 所述至少一個導電接點31與所述至少一個導電端子1212 電連接，從而實現電子元器件30與線路層12之電連接。 在本實施例中，導電接點31藉由焊球32與導電端子1212 電連接。再次，在凹槽100内，在電子元器件30與多層電 路板10a之間填充封裝材料33，從而，穩定固定電子元器 件30並保護焊球32。如此，即形成了組裝有電子元器件 30之多層電路板結構10b。 當然，本領域技術人員可以理解，在電路基板10設置複 數組裝區121，則可製成具有複數凹槽100之多層電路板 10a，並進一步製成包括複數電子元器件30之多層電路板 結構10b。 099147118 表單編號A0101 第13頁/共32頁 0992080943-0 201228511 [0034] [0035] 另外，在本實施例中，多層電路板l〇a與多層電路板結構 ⑽都為六層板。當需要製作其他層數之多層電路板. 與多層電路板結構10b時，可以採用不同層數之電路基板 1〇還可以在電路基板10上複數次層壓膠黏片與銅箔。 〇如®而要製作人層電路板與人層電路板結構時，可 以採用四層之電路基板1G ’並在電路基㈣之兩側都依 :壓合上第一膠黏片14、第一銅羯15 '第二膠黏片“及 第二銅箱17，如此，則可構成八層電路板與八層電路板 結構。 本技術方案之多層電路板之製作方法具有如下優點：首 先在壓合第一膠黏片14、第一銅箔15、第二膠黏片16 與第二銅羯17之過程中，在組裝區121之第-防焊層13表 面形成保護膠片20，如此，可以保護組裝區121之線路層 12，避免組裝區121之線路層12受到損傷；其次，先在第 一膠黏片14中形成了與保護膠片2〇對應之開口，再壓合 第一膠黏片14，如此，則避免了保護膠片2〇造成壓合後 第一銅箔15表面凹凸不平之現象，使得壓合之後之第一 銅箔15表面非常平整，有利於蝕刻形成精確之第—線路 圖形151 ;再次，由於銅材料之去除較為不易，而膠黏片 較為柔軟，其材料之去除較為容易，本技術方案中在 將第一銅箔15與第二銅箔17形成線路圖形之過程中形 成了與保護膠片20對應之第一窗口 15〇與第二窗口 17〇， 從而，使得保護膠片20上方僅有第二膠黏片16之材料需 要去除，如此’可以很容易地形成第二開口 1 6 〇，從而暴 露出保護膠片20，以方便保護膠片20之去除；最後，本 099147118 表單編號A0101 第14頁/共32頁 0992080943-0 201228511 [0036] G [0037] [0038] [0039] ❹ [0040] [0041] [0042] [0043] 技術方案採用在形成線路圖形之過程中形成第一窗口 150 與第二窗口 1 70，而不需額外增加步驟，亦即，本技術方 案之製作具有凹槽100之多層電路板10a之方法步驟較為 簡單，製程時間較短，量產時可具有較高產量與良率。 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本 案技藝之人士援依本發明之精神所作之等效修飾或變化 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本技術方案實施例提供之電路基板之示意圖。 圖2係本技術方案實施例提供之在電路基板上形成第一防 焊層之示意圖。 圖3係本技術方案實施例提供之在電路基板上形成保護膠 層之示意圖。 圖4係本技術方案實施例提供之在電路基板上形成保護膠 片之示意圖。 圖5係本技術方案實施例提供之在電路基板上壓合第一膠 黏片與第一銅箔之示意圖。 圖6係本技術方案實施例提供之將第一銅箔形成第一線路 圖形之示意圖。 圖7係本技術方案實施例提供之在電路基板上壓合第二膠 黏片與第二銅箔之示意圖。 099147118 表單編號A0101 第15頁/共32頁 0992080943-0 201228511 [0044] 圖8係本技術方案實施例提供之將第二銅结形成第二線路 圖形之示意圖。 [0045] 圖9係本技術方案實施例提供之在電路基板上形成第二防 焊層之示意圖。 [0046] 圖1 0係本技術方案實施例提供之電路基板暴露出保護膠 片後之示意圖。 [0047] 圖11係本技術方案實施例提供之在電路基板之凹槽構裝 一個電子元器件後之示意圖。 [0048] 【主要元件符號說明】 電路基板：10 [0049] 基底：11 [0050] 線路層：12 [0051] 第一絕緣層： 111 [0052] 第一導電層： 112 [0053] 第二絕緣層： 113 [0054] 第二導電層： 114 [0055] 第三絕緣層： 115 [0056] 第三導電層： 116 [0057] 第一埋導孔： 101 [0058] 第一盲導孔： 102 [0059] 第二盲導孔： 103 表單編號A0101 099147118 第16頁/共32頁 0992080943-0 201228511 [0060]組裝區：121 [0061] 壓合區：122 [0062] 導電線路：1211 [0063] 導電端子：1212 [0064] 第一防焊層：13 [0065] 第三防焊層：19 [0066] 保護膠片：20 〇 [0067] 保護膠層：21 [0068] 環形開口 ： 210 — [0069] 第一膠黏片：14 [0070] 第一銅箱：15 [0071] 第一開口 ： 140 [0072] 〇 第一線路圖形：151 [0073] 第一窗口 ： 150 [0074] 第三盲導孔：104 [0075] 第二膠黏片：16 [0076] 第二銅箔：17 [0077] 第二線路圖形：171 [0078] 第二窗口 ： 170 099147118 表單編號A0101 第17頁/共32頁 0992080943-0 201228511 [0079] 第四 盲導孔 :105 [0080] 第二 導通孔 ：106 [0081] 第二 防焊層 ••18 [0082] 第二 開口： 160 [0083] 凹槽 ：100 [0084] 電子元器件 ：30 [0085] 導電 接點： 31 [0086] 焊球 ：32 [0087] 封裝材料· 33 [0088] 多層 電路板 ：10a [0089] 多層 電路板結構：10b 099147118Form No. A010I Page 12 / Total 32 Page 0992080943-0 201228511 [0031] [0032] In the tenth step, the exposed protective film 20 can be removed by vacuum adsorption or manual operation, thereby exposing the The first solder resist layer 13 and the at least one conductive terminal 1212 are described. At this time, a plurality of layers of the circuit board 10a having the recesses 100 are formed, which can be used to construct an electronic component. In the eleventh step, referring to FIG. 11, an electronic component 30 is mounted in the assembly area 121 of the circuit layer 12, and the electronic component 30 is received in the recess 100. In this embodiment, the electronic component 30 is configured by the following steps: First, the electronic component 30 is provided, and the electronic component 30 may be an active component or a passive component, for example, For the wafer. The electronic component 30 has at least one conductive contact 31, the at least one conductive contact 31 corresponding to the at least one conductive terminal 1212. Conductive contacts 31 can be pads, pins, terminals or other contact elements. Next, the electronic component 30 is placed in the recess 100, and the at least one conductive contact 31 is electrically connected to the at least one conductive terminal 1212, thereby electrically connecting the electronic component 30 and the circuit layer 12. . In the present embodiment, the conductive contacts 31 are electrically connected to the conductive terminals 1212 by solder balls 32. Again, in the recess 100, the encapsulating material 33 is filled between the electronic component 30 and the multilayer circuit board 10a, thereby stably fixing the electronic component 30 and protecting the solder balls 32. Thus, the multilayer circuit board structure 10b in which the electronic component 30 is assembled is formed. Of course, those skilled in the art can understand that, when the plurality of assembly areas 121 are disposed on the circuit substrate 10, the multi-layer circuit board 10a having the plurality of recesses 100 can be fabricated, and the multi-layer circuit board structure 10b including the plurality of electronic components 30 can be further formed. . 099147118 Form No. A0101 Page 13 of 32 0992080943-0 201228511 [0035] Further, in the present embodiment, the multilayer circuit board 10a and the multilayer circuit board structure (10) are both six-layer boards. When it is necessary to fabricate a multilayer circuit board of other layers. With the multilayer circuit board structure 10b, a different number of circuit boards can be used. It is also possible to laminate the adhesive sheet and the copper foil several times on the circuit substrate 10. For example, when a human layer circuit board and a human layer circuit board structure are to be fabricated, a four-layer circuit substrate 1G' can be used and on both sides of the circuit base (four): the first adhesive sheet 14 is pressed together, first The copper crucible 15 'second adhesive sheet' and the second copper box 17 can form an eight-layer circuit board and an eight-layer circuit board structure. The manufacturing method of the multi-layer circuit board of the technical solution has the following advantages: firstly under pressure In the process of combining the first adhesive sheet 14, the first copper foil 15, the second adhesive sheet 16, and the second copper sheet 17, a protective film 20 is formed on the surface of the first solder resist layer 13 of the assembly area 121, so that The circuit layer 12 of the assembly area 121 is protected to avoid damage to the circuit layer 12 of the assembly area 121. Secondly, an opening corresponding to the protective film 2〇 is formed in the first adhesive sheet 14, and then the first adhesive sheet is pressed. 14. In this way, the phenomenon that the surface of the first copper foil 15 after the pressing of the protective film 2 is uneven is prevented, so that the surface of the first copper foil 15 after pressing is very flat, which is favorable for etching to form an accurate first line pattern. 151; Again, because the removal of copper material is not easy, and the adhesive It is relatively soft, and the removal of the material is relatively easy. In the technical solution, the first window 15 〇 and the second window corresponding to the protective film 20 are formed in the process of forming the first copper foil 15 and the second copper foil 17 into a line pattern. 17〇, so that only the material of the second adhesive sheet 16 above the protective film 20 needs to be removed, so that the second opening 16 〇 can be easily formed, thereby exposing the protective film 20 to facilitate the protection of the film 20 Finally, this 099147118 form number A0101 page 14 / total 32 page 0992080943-0 201228511 [0036] [0039] [0039] [0040] [0043] [0043] The technical solution is adopted in The first window 150 and the second window 170 are formed in the process of forming the circuit pattern without additional steps, that is, the method of manufacturing the multi-layer circuit board 10a having the groove 100 of the present technical solution is relatively simple, and the process time is simple. Shorter, it can have higher yield and yield when mass production. In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above is only the preferred embodiment of the present invention. In this way, the scope of the patent application in this case is not limited. Any equivalent modifications or variations made by those skilled in the art to the spirit of the present invention should be included in the scope of the following patent application. 1 is a schematic diagram of a circuit substrate provided by an embodiment of the present technical solution. FIG. 2 is a schematic diagram of forming a first solder resist layer on a circuit substrate according to an embodiment of the present technical solution. FIG. 3 is a circuit board provided by an embodiment of the present technical solution. FIG. 4 is a schematic diagram of forming a protective film on a circuit substrate according to an embodiment of the present technical solution. FIG. 5 is a schematic view showing the first adhesive sheet and the first copper foil laminated on the circuit substrate according to an embodiment of the present technical solution. FIG. 6 is a schematic diagram of forming a first line pattern of a first copper foil according to an embodiment of the present technical solution. Fig. 7 is a schematic view showing the second adhesive sheet and the second copper foil laminated on the circuit substrate according to the embodiment of the present invention. 099147118 Form No. A0101 Page 15 of 32 0992080943-0 201228511 [0044] FIG. 8 is a schematic diagram of forming a second line pattern by forming a second copper junction according to an embodiment of the present technical solution. 9 is a schematic diagram of forming a second solder resist layer on a circuit substrate according to an embodiment of the present technical solution. 10 is a schematic diagram of the circuit substrate provided by the embodiment of the present technical solution after the protective film is exposed. 11 is a schematic diagram of the embodiment of the present invention after the electronic component is mounted on the recess of the circuit substrate. [Major component symbol description] Circuit substrate: 10 [0049] Substrate: 11 [0050] Circuit layer: 12 [0051] First insulating layer: 111 [0052] First conductive layer: 112 [0053] Second insulating Layer: 113 [0054] Second conductive layer: 114 [0055] Third insulating layer: 115 [0056] Third conductive layer: 116 [0057] First buried via: 101 [0058] First blind via: 102 [ 0059] Second blind via: 103 Form number A0101 099147118 Page 16 of 32 0992080943-0 201228511 [0060] Assembly area: 121 [0061] Press area: 122 [0062] Conductive line: 1211 [0063] Conductive terminal : 1212 [0064] First solder mask: 13 [0065] Third solder mask: 19 [0066] Protective film: 20 〇 [0067] Protective layer: 21 [0068] Ring opening: 210 - [0069] An adhesive sheet: 14 [0070] First copper box: 15 [0071] First opening: 140 [0072] 〇 First line pattern: 151 [0073] First window: 150 [0074] Third blind via: 104 [0075] Second adhesive sheet: 16 [0076] Second copper foil: 17 [0077] Second line graphic: 171 [0078] Second window: 170 09914 7118 Form No. A0101 Page 17 of 32 0992080943-0 201228511 [0079] Fourth blind via: 105 [0080] Second via: 106 [0081] Second solder mask • 18 [0082] Second opening : 160 [0083] Groove: 100 [0084] Electronic component: 30 [0085] Conductive contact: 31 [0086] Solder ball: 32 [0087] Packaging material · 33 [0088] Multilayer circuit board: 10a [0089] Multi-layer circuit board structure: 10b 099147118
表單編號AOltH 第18頁/共32頁 0992080943-0Form Number AOltH Page 18 of 32 0992080943-0