201227522 六、發明說明： 【發明所屬之技術領域】 本發明係有關達成處理器裝置與週邊裝置進行存取時 的效率化之技術。 本發明係有關例如在FA(Factory Automation)系統 中，達成處理器裝置與週邊裝置進行存取時的效率化之相 關技術。 【先前技術】 在一般之FA系統中，其主控（master)裝置係下達指令 給從動（slave)裝置，從動裝置則將各種狀態資訊響應給主 控裝置。 指令或響應之處理雖以固定的時間間隔而進行，但特 別是在動作控制系統的領域中，自相當於主控裝置的動作 控制器裝置（以下，記載為控制器）傳送的資料，送達相當 於從動裝置的伺服放大裝置（以下，記載為伺服放大器）， 而至驅動伺服馬達為止的時間愈短，或，自彳司服放大器傳 送資料於控制器的時間愈短，愈能作高精確度之馬達控制。 在此，將自控制器傳送於伺服放大器之用以驅動馬達 之控制資料設為指令資料。 此外，將自伺服放大器傳送於控制器之馬達的位置或 速度等之狀態資料設為響應資料。 於本說明書中係舉-例說明將以伺服放大器為首之^ 機器内部的資料傳送予以高速化之方法。 此外’以下舉進行資料傳送之機器的_例說明祠服放 323068 3 201227522 大器。 將伺服放大器内部之一般性構成表示於第5圖。 1 為伺服放大器，2 為 CPU(Central Processing Unit)，4 為通信用 IC(Integrated Circuit)，5 為馬達控 制用IC，6為馬達，7為網路。 通信用IC4係具備用以儲存指令資料或響應資料的通 信用缓衝器41。 網路7的前方為控制器，伺服放大器1係經由網路7 而自控制器接收指令資料。 在伺服放大器1的内部中，通信用IC3係自網路7接 收指令資料。 該指令資料係由CPU 2讀取。 CPU 2係因應於需求而進行指令資料的演算，並將指 令資料傳送至馬達控制用IC5。 馬達控制用IC5係藉由自CPU 2接收到的指令資料而 驅動馬達6。 此外，伺服放大器1係經由網路7而將響應資料傳送 至控制器。 在伺服放大器1的内部中，馬達控制用IC5係將馬達 6的位置或速度等狀態資訊通知CPU 2，CPU 2則因應於需 求而進行演算並製作成響應資料。 CPU 2係將響應資料寫入通信用IC4。 繼而說明有關於CPU 2和通信用IC4的傳送資料之時 序0 4 323068 201227522 通信用IC4係以固定的時間間隔自網路7接收指令資 料’並將指令資料儲存於通信用緩衝器41。 而且，CPU 2係以固定的時間間隔自通信用1(：4(通信 用緩衝器41)讀取指令資料。 同樣地’ CPU 2係以固定的時間間隔將響應資料寫入 通信用IC4(通信用緩衝器41)，通信用IC4則以固定的時 間間隔將指令傳送於網路。 在此，CPU 2和通信用IC4其傳送接收資料的時間之 間隔、以及通信用IC4與網路7傳送接收資料的時間之間 隔（大約數十微秒至數宅秒）並不一定需要^___致。 相較於CPU 2的存取性能，一般而言通信用IC4的存 取響應性能較低。 特別是自CPU 2對通信用IC4進行讀取存取（read access)時’CPU 2需等待直至通信用IC4準備好資料為止， 其間CPU 2無法進行其他的處理而形成浪費時間之情形。 專利文獻1係揭示有將CPU之對ROM (Read Only Memory) 的存取達成高速化之方法，若將專利文獻1中設為R〇M的 部份置換成通信用1C時’則亦能考慮將專利文獻1的技術 應用於第5圖的構成。 (先前技術文獻） (專利文獻） 專利文獻1 :日本特開2008-117414號公報 【發明内容】 (發明欲解決的課題） 5 323068 201227522 在專利文獻1中，當將記憶體介面電路裝置予以配置 於CPU和ROM之間，且對構成較CPU更廣的資料匯流排寬 度之1個以上的ROM進行存取時能期待其功效。 但，本說明書中所設想之通信用1C，一般而言其係和 CPU有相同的資料匯流排寬度，或較CPU為狹窄的資料匯 流排寬度，即使運用專利文獻1的技術亦無法期待其功效。 本發明係有鑑於如此之情形而完成者，其主要之目的 在於縮短以預定的時間間隔讀取儲存於通信用缓衝器的資 料之處理器裝置之存取時間，並改善處理器裝置的處理效 率。 (解決課題之手段） 本發明之加速器裝置係連接於處理器裝置、以及儲存 所接收的接收資料之通信用缓衝器，該加速器裝置係具有： 接收資料讀取部，其係在開始時序開始進行從前述通 信用緩衝器之規定資料尺寸量的接收資料之讀取，其中， 前述開始時序為在以預定的時間間隔重覆來到的前述處理 器裝置的讀取時序之前，以自前述通信用緩衝器讀取前述 規定資料尺寸的資料所需要之緩衝器讀取時間為基礎而得 者，且為在前述處理器裝置的讀取時序之前完成前述規定 資料尺寸量的接收資料之讀取者；以及 接收資料輸出部，其係在前述處理器裝置的讀取時序 來到之時間點，將經由前述接收資料讀取部所讀取之接收 資料，輸出至前述處理器裝置。 (發明之功效） £；： 6 323068 201227522 來到時’201227522 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a technique for achieving efficiency in accessing a processor device and peripheral devices. The present invention relates to a technique for achieving efficiency in accessing a processor device and a peripheral device, for example, in an FA (Factory Automation) system. [Prior Art] In a general FA system, a master device issues an instruction to a slave device, and the slave device responds to various status information to the master device. The processing of the command or the response is performed at a fixed time interval. However, in the field of the motion control system, the data transmitted from the motion controller device (hereinafter referred to as the controller) corresponding to the master device is equivalently delivered. The servo amplifier device of the slave device (described below as a servo amplifier) has a shorter time until the servo motor is driven, or the shorter the time is, the faster the data is transmitted from the servo amplifier to the controller. Motor control. Here, the control data for driving the motor from the controller to the servo amplifier is set as the command data. In addition, the status data of the position or speed of the motor transmitted from the servo amplifier to the controller is set as the response data. In the present specification, a method of speeding up data transfer inside a machine, such as a servo amplifier, will be described. In addition, the following is a description of the machine for data transmission. 323068 3 201227522. The general configuration inside the servo amplifier is shown in Fig. 5. 1 is a servo amplifier, 2 is a CPU (Central Processing Unit), 4 is a communication IC (Integrated Circuit), 5 is a motor control IC, 6 is a motor, and 7 is a network. The communication IC 4 is provided with a credit buffer 41 for storing command data or response data. The front of the network 7 is a controller, and the servo amplifier 1 receives command data from the controller via the network 7. In the inside of the servo amplifier 1, the communication IC 3 receives command data from the network 7. This command data is read by the CPU 2. The CPU 2 calculates the command data in response to the demand and transmits the command data to the motor control IC 5. The motor control IC 5 drives the motor 6 by the command data received from the CPU 2. Further, the servo amplifier 1 transmits the response data to the controller via the network 7. In the servo amplifier 1, the motor control IC 5 notifies the CPU 2 of status information such as the position or speed of the motor 6, and the CPU 2 performs calculation based on the demand and creates a response data. The CPU 2 writes the response data to the communication IC 4. Next, the timing of transmitting data to the CPU 2 and the communication IC 4 will be described. 0 4 323068 201227522 The communication IC 4 receives the command data from the network 7 at a fixed time interval and stores the command data in the communication buffer 41. Further, the CPU 2 reads the command data from the communication 1 (: 4 (communication buffer 41) at a fixed time interval. Similarly, the CPU 2 writes the response data to the communication IC 4 at a fixed time interval (communication) With the buffer 41), the communication IC 4 transmits the command to the network at regular time intervals. Here, the CPU 2 and the communication IC 4 transmit and receive the data at intervals, and the communication IC 4 and the network 7 transmit and receive. The time interval of the data (about tens of microseconds to several seconds) does not necessarily need to be ^___. Compared with the access performance of the CPU 2, the communication response performance of the IC4 for communication is generally low. When the CPU 2 performs read access to the communication IC 4, the CPU 2 waits until the communication IC 4 prepares the data, and the CPU 2 cannot perform other processing to cause a waste of time. Patent Document 1 The method of speeding up the access of the CPU to the ROM (Read Only Memory) is disclosed. If the part of the patent document 1 is replaced by the communication 1C, the patent document can also be considered. The technique of 1 is applied to the configuration of Fig. 5. (Prior Art Document) (Patent Document) Patent Document 1: JP-A-2008-117414 SUMMARY OF THE INVENTION (Problems to be Solved by the Invention) 5 323068 201227522 In Patent Document 1, when a memory interface circuit device is arranged It is expected to be effective when accessing one or more ROMs constituting a data bus width wider than the CPU between the CPU and the ROM. However, the communication 1C as contemplated in the present specification is generally The system and the CPU have the same data bus width, or a data bus width narrower than the CPU, and the effect cannot be expected even if the technique of Patent Document 1 is used. The present invention is completed in view of such a situation, and the main The purpose is to shorten the access time of the processor device that reads the data stored in the communication buffer at predetermined time intervals, and to improve the processing efficiency of the processor device. (Means for Solving the Problem) The accelerator device of the present invention is connected And a processor buffer, and a communication buffer for storing the received data, the accelerator device having: a receiving data reading unit The reading of the received data from the predetermined data size amount of the communication buffer is started at the start timing, wherein the start timing is before the read timing of the processor device that is repeated at predetermined time intervals. The buffer reading time required to read the data of the predetermined data size from the communication buffer is based on the read data of the predetermined data size before the read timing of the processor device And a received data output unit that outputs the received data read by the received data reading unit to the processor device at a time when the reading timing of the processor device comes. (Effect of invention) £;: 6 323068 201227522 When coming
裝置並不須自資料讀取速度遲緩的通信用緩衝 器裝置，故處理器 用緩衝器讀取接收 根據+ inn 取時序之 資料’而能縮短處理器裝置之存取時間，並改善處理器震 置的處理效率。 【實施方式】 (實施形態1) 本實施形態係說明縮短以固定的時間間隔進行與通信 用IC之資料的接收傳送之CPU的存取時間，並改善cpu的 處理效率之例。 第1圖係表示本實施形態之伺服放大裝置1的構成例。 1為伺服放大裝置（以下，記載為伺服放大器）。 2為處理器裝置之CPU(或微電腦）。 3為記憶體加速器（以下，記載為加速器裝置或加遠 器）。 4為通信用1C’具備用以儲存指令資料或響應資料的 5為馬達控制用1C。 通仏用緩衝器41。The device does not need a communication buffer device whose data reading speed is slow, so the processor reads and receives the data according to the +inn timing, and can shorten the access time of the processor device and improve the processor. Processing efficiency. [Embodiment] (Embodiment 1) This embodiment describes an example in which the access time of the CPU for receiving and transmitting data to and from the communication IC at a fixed time interval is shortened, and the processing efficiency of the CPU is improved. Fig. 1 is a view showing an example of the configuration of the servo amplifier device 1 of the present embodiment. 1 is a servo amplifier (hereinafter referred to as a servo amplifier). 2 is the CPU (or microcomputer) of the processor device. 3 is a memory accelerator (hereinafter referred to as an accelerator device or a remote device). 4 is a motor control 1C for storing 1C' for storing command data or response data. The buffer 41 is used overnight.
繼而參照第4圖而說明本實施形態之加速器3的構成 在苐4圖中，接收資料讀取部31係自通信用緩衝器 323〇68 7 201227522 41讀取指令資料（接收資料之例）。 如後所述，CPU 2係以預定的時間間隔之讀取時序而 重覆進行讀取。 接收資料讀取部31係設定有自通信用缓衝器41讀取 規定資料尺寸量的資料所需要的時間（緩衝器讀取時間）。 此外，接收資料讀取部31係於開始時序開始自通信用 緩衝器41讀取規定資料尺寸量的指令資料，其中，該開始 時序係為在CPU 2的讀取時序之前，根據緩衝器讀取時間， 在CPU 2的讀取時序之前結束規定資料尺寸量的指令資料 之讀取之開始時序。 更具體而言，接收資料讀取部31係將自CPU 2的讀取 時序起回溯加總緩衝器讀取時間和預定的保護時間（guard time)後的時間之時序設為開始時序。 保護時間係例如緩衝器讀取時間的1/10以下。 此外，接收資料讀取部31係在CPU 2的讀取時序到來 之時間點結束指令資料之讀取。 如此，本實施形態之接收資料讀取部31係於趕上CPU 2的讀取時序之範圍内，儘可能延遲從通信用緩衝器41的 讀取，以便能將最新的指令資料輸出於CPU 2。 接收資料緩衝器32係暫時儲存接收資料讀取部31自 通信用緩衝器41所讀取之指令資料。 接收資料輸出部33係於CPU 2的讀取時序，將由接收 資料讀取部31所預先讀取，並儲存於接收資料缓衝器32 的指令資料輸出至CPU 2。 8 323068 201227522 •器時11 34係對接收資料讀取部31通知從通信用缓衝 器41靖取指令資料之開始時序。 t苐5圖係藉由計時器34的計時通知而接收資料讀 為以n通ϋ緩衝器41讀取指令資料時之構成例，當 靖通信用IC4的插斷為契機而以接收資料讀取部31 ° ”資料的情形時，則亦可不用設置計時器34。 外，以來自通信用IC4的插斷為契機而以接收資料 =，部31讀取指令資料時’在通信用IC4接收指令資料之 用接收=貝料讀取部31係先將緩衝器讀取時間通知給通信 且於通k用IC4侧根據緩衝器讀取時間將讀取開 始時序進行計時。 傳送資料輸入部35係自CPU 2輸入響應資料（傳送資 料之例）。 •傳送資料緩衝器36係暫時儲存傳送資料輸入部35所 輸入的響應資料。 傳送資料寫入部37係依各預定的時間間隔，將儲存於 傳送貧料緩衝器36的響應資料寫入通信用緩衝器41。 繼而就本實施形態之伺服放大器1的動作例，首先說 明指令資料之接收時的動作例。 網路7的前方為控制器，伺服放大器1係經由網路7 而自控制器接收指令資料。 在词服放大器1的内部中，指令資料係從網路7而由 通信用IC4接收，並保持於通信用IC4内部的通信用缓衝 器41。 9 323068 201227522 於預定的時刻（計時器通知時），或藉由自通信用IC4 彺加速器3的插斷通知，加速器3的接收資料讀取部31即 自通仏用IC4的通信用緩衝器41讀取該指令資料，並保持 於加速+器3内部的接收資料緩衝器32。 、 接著，在預定的時刻，CPU 2係經由加速器3而於通 信用IC4進行讀取存取，而實際上，加速器3的接收資料 輸出部33係將指令資料輸出至cpu 2的資料匯流排。 繼而CPU 2係因應需求而對所接收之指令資料進行演 算等，並將指令資料傳送至馬達控制用IC5。 馬達控制用IC5係藉由自CPU 2接收之指令資料而驅 動馬達6。 又’由於可料想加速器3會同時進行來自Cpu 2的讀 取存取或寫入存取、以及加速器3本身之往通信用IC4的 。買取存取或寫入存取’故以j?PGA(Field-Programmable Gate Array)等之硬體來構裝加速器為佳。 繼而說明響應資料之傳送時的動作例。 伺服放大器1係經由網路7而將響應資料傳送於控制 器。 在伺服放大器1的内部中，馬達控制用IC5係將馬達 6的位置或速度等狀態資訊通知CPU 2，CPU 2則因應於需 求而進行演算並作成響應資料。 CPU 2雖係於預定的時刻’經由加速器裝置3而進行 往通信用IC4的寫入存取，但實際上係由加速器3的傳送 資料輸入部35輸入來自CPU 2的響應資料，並暫時保持於 323068 201227522 傳送資料緩衝器36。 之後加迷器3的傳送 響應資科寫入通信用iC4。 入部37則將暫時保持的 以上係說明冑送指令 係使用第2 圖說明CPU]加:和響應資料時的動作，以下 指令資科所需要之時間 3、以及通信用ic4收發 收發響應資料所需要之時^或疒繼而使用第3圖說明 :先，使用第2圖說: ^令資料係藉由自c 的傳送。 行讀取存取而進行資料傳送。S σ速器3對通信用IC4進 在第2圖中’ Trl係 時之讀取存取時間。 σ逮器3讀取指令資料 亦Ρ ’ Tr 1係加速器3的接收眘 料輸出至CPU 2所需要之時間心㈣出部33將指令資Next, the configuration of the accelerator 3 of the present embodiment will be described with reference to Fig. 4. In Fig. 4, the received data reading unit 31 reads the command data (an example of received data) from the communication buffer 323 〇 68 7 201227522 41. As will be described later, the CPU 2 repeats the reading at the read timing of the predetermined time interval. The received data reading unit 31 sets the time (buffer reading time) required to read the data of the predetermined data size amount from the communication buffer 41. Further, the received data reading unit 31 reads the command data of the predetermined data size amount from the communication buffer 41 at the start of the sequence, and the start timing is read from the buffer before the read timing of the CPU 2. Time, the start timing of reading of the command data of the predetermined data size amount is completed before the reading timing of the CPU 2. More specifically, the received data reading unit 31 sets the timing of the time from the reading timing of the CPU 2 back to the total buffer reading time and the predetermined guard time as the start timing. The guard time is, for example, 1/10 or less of the buffer reading time. Further, the received data reading unit 31 ends the reading of the command data at the time point when the reading timing of the CPU 2 comes. As described above, the received data reading unit 31 of the present embodiment delays the reading from the communication buffer 41 as much as possible within the range of the read timing of the CPU 2, so that the latest command data can be output to the CPU 2. . The received data buffer 32 temporarily stores the command data read by the received data reading unit 31 from the communication buffer 41. The received data output unit 33 outputs the command data read in advance by the received data reading unit 31 and stored in the received data buffer 32 to the CPU 2 in accordance with the reading timing of the CPU 2. 8 323068 201227522 • The device 11 11 notifies the reception data reading unit 31 of the start timing of the command data from the communication buffer 41. The t苐5 diagram is a configuration example in which the received data is read by the timer 34 and the instruction data is read by the n-pass buffer 41. When the interrupt of the IC4 is interrupted, the data is read by the received data. In the case of the 31 ° ” data, the timer 34 may not be provided. In addition, when the command data is received by the interrupt from the communication IC 4 and the command data is read by the unit 31, the command is received at the communication IC 4 . Data reception = The material reading unit 31 first notifies the buffer reading time to the communication, and the ON-based IC 4 side counts the reading start timing based on the buffer reading time. The transmission data input unit 35 is self-contained. The CPU 2 inputs the response data (an example of the transmission data). The transmission data buffer 36 temporarily stores the response data input from the transmission data input unit 35. The transmission data writing unit 37 stores the transmission data at each predetermined time interval. The response data of the lean buffer 36 is written in the communication buffer 41. Next, an operation example of the servo amplifier 1 according to the present embodiment will be described first, and an operation example at the time of receiving the command data will be described. The amplifier 1 receives command data from the controller via the network 7. In the inside of the word amplifier 1, the command data is received from the network 7 and received by the communication IC 4, and is held in the communication buffer inside the communication IC 4 The device 41. 9 323068 201227522 The communication data reading unit 31 of the accelerator 3 communicates with the communication IC 4 at a predetermined time (when the timer is notified) or by the insertion notification from the communication IC 4 彺 accelerator 3 . The buffer 41 reads the command data and holds it in the reception data buffer 32 inside the acceleration + device 3. Then, at a predetermined timing, the CPU 2 performs read access to the communication IC 4 via the accelerator 3, and Actually, the received data output unit 33 of the accelerator 3 outputs the command data to the data bus of the cpu 2. Then, the CPU 2 calculates the received command data according to the demand, and transmits the command data to the motor control. IC5. The motor control IC5 drives the motor 6 by the command data received from the CPU 2. Also, it is expected that the accelerator 3 will simultaneously perform read access or write access from the CPU 2, and acceleration. It is preferable that the device 3 itself is used for the communication IC 4 to purchase an access or write access. Therefore, it is preferable to construct an accelerator by a hardware such as a field-programmable gate Array (JPA). The servo amplifier 1 transmits the response data to the controller via the network 7. In the servo amplifier 1, the motor control IC 5 notifies the CPU 2 of the status information such as the position or speed of the motor 6, and the CPU 2 The CPU 2 performs the calculation and generates the response data in response to the demand. The CPU 2 performs the write access to the communication IC 4 via the accelerator device 3 at the predetermined time, but is actually input by the transmission data input unit 35 of the accelerator 3. The response data from the CPU 2 is temporarily held at the 323068 201227522 transmission data buffer 36. After that, the transmission of the adder 3 is transmitted to the iC4 for communication. In the entry unit 37, the above-mentioned instructions for the above-mentioned instructions are used to describe the operation of the CPU] plus and the response data, and the time required for the following command is 3, and the communication ic4 needs to transmit and receive the response data. At the time, ^ or 疒 then use the third figure to illustrate: First, use the second picture to say: ^ Let the data be transmitted by c. Line read access for data transfer. The S sigma converter 3 enters the read access time for the communication IC 4 in the 'Trl system' in Fig. 2. σ catcher 3 read command data Ρ ‘ Tr 1 system accelerator 3 receives caution time output to CPU 2 required time (four) output 33 will command
Tr2係加速器3自通作用ΤΓ/Ι > 時間。 用⑽項取指令資料時之讀取 亦即，Tr2係加速器3的接收資 緩衝器41讀取指令資料所需要之時間(緩t31自通信用 加和Tr2分別為複數次的讀取 ^續取時間）。 此外，Tg為保護時間。 之口計時間。 保護時間Tg係只要根據加速器3 31將最後的户a眘祖 接枚資料讀取部 時間、^ Γ存於接緩衝器32所1 = Μ及接收資料輪出部33自接收 “要之 初的指令資料所需要之時間作決定即可 器32讀取 323068 11 201227522 亦即，設成於保護時間Tg之間，可進行接收資料讀取 部31的最後的指令資料之往接收資料緩衝器32的儲存、 接收資料輸出部33之從接收資料緩衝器32之最初的指令 資料之讀取、並往CPU 2之輸出。 加速器3為了讀取指令資料而於事前決定存取之通信 用IC4的位址（通信用缓衝器41的位址）和資料尺寸，並由 CPU 2設定於加速器3。 如第2圖所示，加速器3的接收資料讀取部31係由 CPU 2的讀取時序起回溯加總讀取存取時間Tr2和保護時 間Tg後的時間（Tr2 + Tg)之時序，開始進行指令資料之讀 取0 如此，通信用IC4的存取響應性能低，CPU 2對通信 用IC4進行讀取存取時係需要Tr2的時間，但藉由加速器 3於事前自通信用IC4讀取之方式，則CPU 2之讀取存取 時間為Trl即可。 繼而作為讀取存取之時序，CPU 2係藉由計時器等以 Tr_cycle的時間間隔，經由加速器3而對通信用IC4進 行讀取存取。 加速器3讀取存取於通信用IC4的時序係可考慮幾個 方法。 其中一個為和CPU 2相同地，藉由計時器等而決定對 通信用IC4的讀取時序之方法。 另一個為通信用IC4對加速器3插斷通知來自網路7 的指令資料接收結束，並將此作為觸發器而加速器3即自 12 323068 201227522 通信用IC4進行讀取存取之方法。 又，通信用IC4係於自網路7接收指令資料之正後， 加速器3只要自通信用IC4讀取指令資料，並於其正後進 行來自CPU 2的讀取存取，則能縮短自通信用1C接收指令 資料之後至CPU 2進行讀取為止的時間，且能縮短自控制 器傳送指令資料至伺服放大器驅動馬達為止之時間。 若為後者之插斷的方法，則如此之要件可判斷能輕易 對應者。 在此，說明有關於資料的更新和分割。 在CPU 2自加速器3讀取指令資料之時序、相同地加 速器3自通信用IC4讀取指令資料之時序，係分別具有無 法自前次讀取的指令資料更新之可能性。 此時，直接輸出前次的指令資料的方法在伺服控制系 統的資料傳送係一般性的考慮方法。 但，在進行讀取之中，自某個位址的文字而更新為新 的資料（資料之分割）並不妥，加速器3或通信用IC4必須 在3面緩衝器等保證資料的完整性。 以上，係有關於指令資料的傳送，繼而使用第3圖說 明有關於響應資料的傳送。 響應資料係自CPU 2寫入加速器3，進而藉由自加速 器3寫入通信用IC4而進行資料的傳送。 在第3圖中，Twl係CPU 2將響應資料寫入加速器3 時之寫入存取時間。The Tr2 system accelerator 3 is self-acting ΤΓ/Ι > time. When reading the command data with the item (10), that is, the time required for the receiving buffer 41 of the Tr2 accelerator 3 to read the command data (slow t31, the self-communication plus Tr2 is a plurality of readings, respectively) time). In addition, Tg is the protection time. The time is counted. The protection time Tg is as long as the last household a ancestor receives the data reading unit time according to the accelerator 31, and stores it in the connection buffer 32 1 = Μ and the receiving data rounding unit 33. The time required for the command data is determined. The device 32 reads 323068 11 201227522, that is, between the guard times Tg, the last command data of the received data reading unit 31 can be received to receive the data buffer 32. The storage/reception data output unit 33 reads the first command data from the received data buffer 32 and outputs it to the CPU 2. The accelerator 3 determines the address of the communication IC 4 to be accessed in advance in order to read the command data. The address of the communication buffer 41 and the data size are set by the CPU 2 to the accelerator 3. As shown in Fig. 2, the received data reading unit 31 of the accelerator 3 is backtracked from the reading timing of the CPU 2. When the total reading time Tr2 and the time after the protection time Tg (Tr2 + Tg) are added, the reading of the command data is started. Thus, the access response performance of the communication IC 4 is low, and the CPU 2 performs the communication IC 4 on the communication IC 4 . When reading access requires Tr2 However, by the accelerator 3 being read from the communication IC 4 in advance, the read access time of the CPU 2 is Tr1. Then, as the timing of the read access, the CPU 2 is Tr_cycle by a timer or the like. At the time interval, the communication IC 4 is read and accessed via the accelerator 3. The timing at which the accelerator 3 reads and accesses the communication IC 4 can be considered in several ways. One of them is the same as the CPU 2, and the timer is used. The method of determining the read timing of the communication IC 4 is determined. The other is that the communication IC 4 interrupts the acceleration of the accelerator 3 to notify the end of the instruction data reception from the network 7, and this is used as a trigger, and the accelerator 3 is from 12 323068 201227522. The communication IC 4 performs a read access method. Further, after the communication IC 4 receives the command data from the network 7, the accelerator 3 reads the command data from the communication IC 4 and performs the CPU 2 from the communication IC 4 The read access can shorten the time from when the communication 1C receives the command data to the CPU 2, and the time from when the controller transfers the command data to the servo amplifier drive motor can be shortened. In the method of interrupting, the requirements can be easily judged. Here, the update and division of the data are described. The timing at which the CPU 2 reads the command data from the accelerator 3 is the same as that of the accelerator 3 self-communication. The timing of the IC4 read command data has the possibility of updating the command data that cannot be read from the previous time. At this time, the method of directly outputting the previous command data is a general consideration of the data transfer system of the servo control system. However, in the reading, it is not appropriate to update the new data (the division of the data) from the text of an address, and the accelerator 3 or the communication IC 4 must ensure the integrity of the data in the buffer on the 3 side. The above is related to the transmission of the command material, and then the use of the third figure illustrates the transmission of the response data. The response data is written from the CPU 2 to the accelerator 3, and the data is transferred by writing the communication IC 4 from the accelerator 3. In Fig. 3, Twl is the write access time when the CPU 2 writes the response data to the accelerator 3.
Tw2係加速器3將響應資料寫入通信用IC4時之寫入 13 323068 201227522 存取時間。When the Tw2 accelerator 3 writes the response data to the communication IC 4, the access time is 13 323068 201227522.
Twl和Tw2係分縣複數切以存取之合計時間。 如此’通U IC4的存取響應性能低，Gpu 2於對通 信用IC4進行寫入存取時係需要Tw2的時間，但藉由加 速器3而暫時保持響應資料之方式’貝，]CPU 2之寫入存取 時間為T w 1即可。 繼而作為寫人存取之時序，CPU 2係藉由計時器等以 TW—的㈣_ ’經由加速器3而對通信用IC4進 行寫入存取。 又，一般而言，Tw_cycie和第2圖之Tr—cycle的 時間間隔為相同。 加速器3係於從CPU 2有寫入存取時，同時保持有資 料和位址，藉此而能掌握之後要進行寫人存取的通信用似 的位址。 或者亦可考慮和指令資料的讀取時相同，加速器3為 了寫入響應資料，而於事前決定存取的通信用IC4的位址 (通信用緩衝器41的位址）和資料尺寸，並從cpu2而設定 於加速器3之方法。 決定加速器3寫入存取於通信用iC4的時序之方法和 讀取時相同，有於加速器3内部具有計時器，以和Tw__ cycle相同的時間間隔，使加速器3自動地存取於通信用 IC4之方法。 或者’考慮以依各Tw—cycle的來自CPU 2之寫入存 取作為觸發器’依次使加速器3將從CPU 2寫入之響應資 14 323068 201227522 料寫入通信用IC4之方法。 如上述，CPU 2進行指令資料的讀取存取 裝置3將於事前自通信用IC4所讀取之指令資料如迷器 2之資料匯流排，藉此而能縮短cpu 2之讀取存於CPU 同樣地，CPU 2於進行響應資料的寫入存^取時間。 器3係暫時接收響應資料，並於之後加迷器3將日響廣力= 寫入通信用IC4,藉此而能縮短cpu 2之寫入存取音日應『貝料 又，本發明並不限定於所揭示之形態，例：，=。 態1雖係以在加速器3内部具有緩衝器為前提而 〔 亦可考慮於加速器3的外部具有用以暫時性保存指令資料 或應用資料的記憶體之形態。 中之說明雖為說明竭、統的伺服放大裝置 η二存取於通信用IC4時之存取時間的縮短之方 式，但本方式之運用對象之裝置並不限定飼服放大裝置。 通俨用I e進本-實Π祕說明在具有以預定的相間隔對 通仏用ic進仃请取存取之cpu的機器 用IC的中間之加逮器係從通信用IC於事前續 取存取時，將加速器所持有之資料 二送回至㈣，藉此而能縮短cpu的外部㈣ 施形態係說明於具有以預定的時間間隔對 用^的中Η 存取之咖的機器中，位於⑽和通信 用ic的中間之加逮器係暫時保持來自c 由加速器將資料寫人通信用IC，藉此而迅速結束⑽側的 323068 15 201227522 匯流排處理（bus transaction)，而能縮短CPU的外部10 存取時間之方法。 【圖式簡單說明】 第1圖係表示實施形態1的伺服放大裝置的構成例圖。 第2圖係說明實施形態1的伺服放大裝置之指令資料 傳送時序圖。 第3圖係說明實施形態1的伺服放大裝置之響應資料 傳送時序圖。 第4圖係表示實施形態1的加速器裝置3的構成例圖。 第5圖係表示一般的祠服放大裝置的構成例圖。 【主要元件符號說明】 1 伺服放大裝置（伺服放大器） 2 CPU 3 加速器裝置（加速器） 4 通信用1C 5 馬達控制用1C 6 馬達 7 網路 31 接收資料讀取部 32 接收資料缓衝器 33 接收資料輸出部 34 計時器 35 傳送資料輸入部 36 傳送資料緩衝器 37 傳送資料寫入部 41 通信用緩衝器 16 323068Twl and Tw2 are counted by the county to cut the total time of access. In this way, the access response performance of the U IC 4 is low, and the Gpu 2 requires Tw 2 for writing access to the communication IC 4, but the response data is temporarily held by the accelerator 3 'Bei,> CPU 2 The write access time is T w 1 . Then, as the timing of the write access, the CPU 2 writes and accesses the communication IC 4 via the accelerator 3 by TW-(4)_' via a timer or the like. Also, in general, the time interval between Tw_cycie and Tr-cycle in Figure 2 is the same. The accelerator 3 is provided with a data address and an address while having a write access from the CPU 2, whereby the communication-like address to be accessed by the writer can be grasped. Alternatively, the accelerator 3 may determine the address (the address of the communication buffer 41) and the data size of the communication IC 4 to be accessed in advance in order to write the response data. The method of setting the accelerator 2 to cpu2. The method of determining the timing at which the accelerator 3 writes and accesses the communication iC4 is the same as that in the case of reading, and there is a timer inside the accelerator 3, and the accelerator 3 is automatically accessed to the communication IC 4 at the same time interval as the Tw__cycle. The method. Alternatively, a method of causing the accelerator 3 to write the response value 14 323068 201227522 written from the CPU 2 to the communication IC 4 in order to cause the write access from the CPU 2 as a trigger for each Tw-cycle is considered. As described above, the CPU 2 performs the command data reading and accessing device 3 to read the command data read from the communication IC 4 in advance, such as the data bus of the genre 2, thereby shortening the reading of the cpu 2 to the CPU. Similarly, the CPU 2 performs a write time for the response data. The device 3 temporarily receives the response data, and then adds the megaphone 3 to write the communication IC 4, thereby shortening the write access sound of the cpu 2, and the present invention It is not limited to the disclosed form, for example: =. The state 1 is assumed to have a buffer inside the accelerator 3 (it is also conceivable that the outside of the accelerator 3 has a form of memory for temporarily storing command data or application data. Although the description has been made to explain the shortening of the access time when the servo amplifier device η2 accesses the communication IC 4, the device to be used in the present embodiment is not limited to the feed device. In the middle of the machine IC, the IC is used in the middle of the IC for the CPU that has access to the cpu at the predetermined interval. When the access is taken, the data held by the accelerator is sent back to (4), whereby the external portion of the CPU can be shortened. (4) The configuration is described in a machine having a coffee access to the middle of the user at a predetermined time interval. In the middle, the adder in the middle of (10) and the communication ic temporarily holds the data from the accelerator to write the communication IC, thereby quickly ending the 323068 15 201227522 bus transaction on the (10) side, and A method of shortening the external 10 access time of the CPU. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an example of the configuration of a servo amplifier device according to a first embodiment. Fig. 2 is a timing chart showing the transmission of a command data of the servo amplifier device of the first embodiment. Fig. 3 is a timing chart showing the response data transmission of the servo amplifier device of the first embodiment. Fig. 4 is a view showing an example of the configuration of the accelerator device 3 of the first embodiment. Fig. 5 is a view showing an example of the configuration of a general clothing amplifying device. [Description of main component symbols] 1 Servo amplifier (servo amplifier) 2 CPU 3 Accelerator device (accelerator) 4 Communication 1C 5 Motor control 1C 6 Motor 7 Network 31 Receive data reading unit 32 Receive data buffer 33 Receive Data output unit 34 timer 35 transmission data input unit 36 transmission data buffer 37 transmission data writing unit 41 communication buffer 16 323068