TW201218320A

TW201218320A - Nonvolatile memory having raised source and drain regions

Info

Publication number: TW201218320A
Application number: TW100139194A
Authority: TW
Inventors: Yi-Ying Liao
Original assignee: Macronix Int Co Ltd
Priority date: 2006-07-10
Filing date: 2007-07-10
Publication date: 2012-05-01
Also published as: TW200805637A; TWI360201B; CN101106136A; CN101106137A; CN102097127A; TWI365512B; TW200807726A; CN101106139A; TW200805583A; CN102064198A; TWI349337B; TWI336941B; TW200805575A; TWI364112B; CN101106138A

Abstract

The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

Description

201218320 六、發明說明：【發明所屬之技術領域】本發明是有關於非揮發性記憶體，I特制是有有一變化通道區介面之非揮發性記憶體，變化通道區2具例如是一舉升之源極與汲極或一凹入通道區。介面【先前技術】基於著稱為EEPROM與快閃體之的電氣可程式化與可抹除非揮發性記憶體技術何=結構於各種的現代化應用。複數個記憶體單元 EKPROM與快閃記憶體所使用。當積體電、。構係為時，關於基於電荷捕捉介電層之記憶體單元結構要性係逐漸興起，此乃因為可調尺^㈣ :之，。基於電荷捕捉介電層之記憶體單元結構包= 言如工業名稱PHINES，S0N0S或皿〇 ===:_:電荷捕捉介電層二單元之臨限電壓會择力:貝二。J負電荷被捕捉時’記憶體電荷捕捉層移除負料而^體單元之臨限電_藉由從物"非揮純氮化物單^構是平面的，以使氧化 -乳^·乳化物（⑽〇)結構形成於基板之表面上。缺而’运種平面的結構係與較差的 ^ ‘、、、程式化及抹除操作以及古。、此.回功率明;^ YEH，C：值相關。這種結構係說 ^ . 人，’，腿順4新之低功率程式化/ 矛、…。、每單元有2_Bit之快閃記憶體有兩位元 201218320 TW319IPA-D (PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory)”，電子裝置會議，2002 年， IEDM '02. Digest. International，8-11，2002 年 12 月，頁數：931 - 934 。因此，需要修改此習知之非揮發性氮化物單元結構之平面結構，以處理一個或多個缺點。【發明内容】具有舉升之源極與汲極區之非本發明係有關於一種揮發性記憶體。單元積體電路=八^提出一種非揮發性記憶及複數個介電，構儲存結構、源極與沒極區發性記憶體單=體;=:構荷以控制由非各種不同的實施例中，兀Α夕重位TG。提結構或—奈米曰子，，°構之材料係為一電荷離，通道區係㈡區係由1道區，部分。在缺乏電場之情極與㈣區之電路鐵個部分，以克服這:!電::結構電氣隔離轉 =電荷儲存結構與通道二;構:介電結構係至少. #構與1極電Μ源之間。3少部分位於電< 道區二介電結構之-部_ 第二端結束於極;二:間部分，』 201218320201218320 VI. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory, and a special non-volatile memory having a channel region is changed, and the channel region 2 is, for example, a lift. Source and drain or a recessed channel area. Interface [Prior Art] Based on the so-called EEPROM and flash, the electrically programmable and erasable unless volatile memory technology is structured in a variety of modern applications. Multiple memory cells are used by EKPROM and flash memory. When the body is electric,. When the structure is , the structure of the memory cell structure based on the charge trapping dielectric layer is gradually emerging, because of the adjustable ruler ^ (4): Memory cell structure package based on charge trapping dielectric layer = words such as industrial name PHINES, S0N0S or dish 〇 ===: _: charge trapping dielectric layer 2 unit threshold voltage will choose: Bei. When the J negative charge is captured, the 'memory charge trapping layer removes the negative material and the body unit's power is limited. By using the material, the non-volatile pure nitride structure is planar, so that the oxidation-milk ^· The emulsion ((10) 〇) structure is formed on the surface of the substrate. The lack of 'the structure of the plane is poor with ^ ‘, ,, stylized and erase operations and ancient. , this. return power Ming; ^ YEH, C: value correlation. This structure is said to be ^. People, ', legs down 4 new low power stylized / spear, .... Each unit has 2_Bit flash memory with two yuan 201218320 TW319IPA-D (PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory)", Electronic Device Conference, 2002, IEDM '02. Digest. International, 8-11, December 2002, pp. 931 - 934. Therefore, there is a need to modify the planar structure of this conventional non-volatile nitride cell structure to address one or more disadvantages. SUMMARY OF THE INVENTION A non-volatile memory with a source and a drain region of a lift is related to a volatile memory. A unitary body circuit=eight^ proposes a non-volatile memory and a plurality of dielectrics, a structure, and a source structure. Pole and immersed area memory single = body; =: construction load to control by various non-different embodiments, 兀Α 重 heavy TG. Lifting structure or - nano scorpion, ° material structure For a charge separation, the channel zone (2) is composed of a zone, part. In the absence of an electric field and the circuit part of the (four) zone, to overcome this:! Electricity:: structural electrical isolation = charge storage structure and Channel 2; structure: dielectric structure is at least. #结构与第一极.3 least partially positioned between a source of electrical Μ < electrical configuration of the channel region via two - _ pole ends at the second end portion; II: an intermediate portion, "201218320

麗▼»-/»〆孱D 由於源極妓極㈣絲升_ 疋積體電路之一基板，所以此介平X『生记體早之中間部分，且此介面之第二端& #結束於源極區分。為了實施此介面，舉升之源極區^間4 的實施例係位於多晶矽或磊晶矽中。 °° 種不同某些實施例包含數個間隙壁，其分離被舉升之源極與汲極區與電荷儲存結構及介電結構。汗土板於各種不同的實施例中，非揮 _ 路係為或- N娜結構早痛電根據本發明之一第二方面，接屮—刀單元積體電路之製造方法，包含以下^非揮發性記憶體存結-，，由非揮發性記憶體單元積體電路IT存： ==種不:的/施例[電荷儲存_ 料係為-電荷捕捉結構或一 ^何錯紅構之材 1)至少邱八# w 不未日日體尨構。介電結構係·· )主/。卩刀位於電荷儲存結構與—通道區科位於電荷财子結構與一閉極電壓源之間曰；’-)至此陣ί::::::結構與一個或多個介電結構之後，在此陣列發性記憶體單元之沒極與源極區。在陣列t之非揮體單元之通道區係延伸在此各非揮發性=單，之汲極與源極㈣。形成 ^體早兀之汲極與源極區之步驟包含：材料層至積體電路之一基板，以使汲極與源極 5 201218320丽▼»-/»〆孱D Since the source bungee (four) wire rises _ one of the substrate of the snubber circuit, this mediation X "the middle part of the biographer, and the second end of this interface &# End with source differentiation. To implement this interface, the embodiment of the raised source region 4 is located in a polysilicon or epitaxial germanium. °° Different Embodiments Some embodiments include a plurality of spacers that separate the raised source and drain regions from the charge storage structure and dielectric structure. In various embodiments, the sweat plate is a non-swing system or a N-n structure early pain. According to a second aspect of the present invention, the method for manufacturing the integrated circuit of the turret-knife unit includes the following Volatile memory storage -, , by non-volatile memory cell integrated circuit IT: == species: / example [charge storage _ material system - charge trapping structure or a faulty red structure Material 1) At least Qiu Ba # w No day and day. Dielectric structure ··) Main /. The file is located between the charge storage structure and the channel region between the charge structure and a closed voltage source; '-) to this array of ί:::::: structures and one or more dielectric structures, The immersed and source regions of the array of memory cells. The channel region of the non-swept unit of the array t extends here in each non-volatile = single, the drain and the source (four). The step of forming the drain and source regions of the body early includes: a material layer to a substrate of the integrated circuit to make the drain and the source 5 201218320

TW3191PA-D 區被舉升離開基板。各種不同的實施例添加一多晶矽層或一磊晶矽層，以形成舉升之源極與汲極。其中，關於此陣列之各非揮發性記憶體單元，一介面分離所述一個或多個介電結構之一部分與通道區，此介面之一第一端結束於源極區之一中間部分，且此介面之一第二端結束於汲極區之一中間部分。某些實施例形成數個間隙壁，用以分離被舉升離開基板之源極與汲極區與電荷儲存結構及介電結構。某些實施例形成一介電材料層，用以分離位元線與字元線，並將這些字元線形成為閘極電壓源。於各種不同的實施例中，非揮發性記憶體單元積體電路係為一 NOR結構或一 NAND結構之一部分。於本發明之其他實施例中，至少部分位於電荷捕捉結構與通道區之間之介電結構包含如揭露於此之一 ΟΝΟ結構。為了對本發明之上述及其他方面有更佳的暸解，下文特舉範例性實施例，並配合所附圖式，作詳細說明如下：【實施方式】第1圖係為一非揮發性記憶體單元之示意圖，非揮發性記憶體單元在源極與汲極區之間具有一凹入通道。閘極102，在多數實施例中為部分之字元線，具有一閘極電壓Vg。於某些實施例中，閘極結構包含一材料，其功函數大於N型石夕之本徵功函數，或大於約4.1 eV，且最好是大於約4.25 eV，包含譬如大於約5 eV。代表性的 6 201218320 1 丨T / 1 1 閘極材料包含？型 ^ 屬及材料。適合本發日aa三=化鈦、鉑與其他高功函麩金其他材料包含:金明之實施例之具有相當高的功函黎之 (Ni)與鈷（C〇);金屬入包含但不限於釕(Ru)、銦（Ir)、鎞金屬氮化物；以另=其包含但不限於釕-鈦與鎳-鉢； (RU〇2)。高功函數閘極材:二：比:包含但不限於氧牝釘較高的電子隨穿、生比典型的N型多晶硬閘極之1^型多日日日外，極之注人^切作為外介電廣本發明之實施例使用供：在3.l5eV左右。因此，具有一注入阻障，其高“ 3 u、供v外介電層用之持料，德且最好是高於約4ev。關於且^ 例如高於約3.4eV，多晶矽閘極，其注入阻二θ—虱化矽外介電層之p蜇含二氧化矽外介電層之二型：^ a W，且相對於異有生之收數的單元之間夕曰曰石夕間極之單元而言，戶斤雇介電結構_係Π減少大約2伏特。另"電結構_係位 =何錯存結構】〇6之厚^ 性介電材料包含構106與通道區又之一氧化矽與氨氣一有大約2至】〇亳氺之料，其包含Μρ錢矽，或其他類如w 如十承#舌如氧化鋁（Ai2〇3)。員似的向介電常數材The TW3191PA-D area is lifted off the substrate. Various embodiments add a polysilicon layer or an epitaxial layer to form the source and drain of the lift. Wherein, with respect to each of the non-volatile memory cells of the array, one interface separates one of the one or more dielectric structures from the channel region, and one of the first ends of the interface ends in an intermediate portion of the source region, and The second end of one of the interfaces ends in an intermediate portion of one of the drain regions. Some embodiments form a plurality of spacers for separating the source and drain regions lifted off the substrate from the charge storage structure and the dielectric structure. Some embodiments form a layer of dielectric material for separating the bit lines and word lines and forming the word lines as a gate voltage source. In various embodiments, the non-volatile memory cell integrated circuit is part of a NOR structure or a NAND structure. In other embodiments of the invention, the dielectric structure at least partially between the charge trapping structure and the channel region comprises, as disclosed herein, a structure. In order to better understand the above and other aspects of the present invention, the following exemplary embodiments, together with the accompanying drawings, are described in detail as follows: [Embodiment] FIG. 1 is a non-volatile memory unit. In schematic, the non-volatile memory cell has a recessed channel between the source and drain regions. Gate 102, in most embodiments a partial word line, has a gate voltage Vg. In some embodiments, the gate structure comprises a material having a work function greater than an intrinsic work function of the N-type, or greater than about 4.1 eV, and preferably greater than about 4.25 eV, including, for example, greater than about 5 eV. Representative 6 201218320 1 丨T / 1 1 Gate material included? Type ^ genus and material. Suitable for this day aa three = titanium, platinum and other high work function bran gold other materials include: Jin Ming's example has a fairly high work letter Li (Ni) and cobalt (C〇); metal into the inclusion but not It is limited to ruthenium (Ru), indium (Ir), ruthenium metal nitride; and other = it includes but is not limited to ruthenium-titanium and nickel-ruthenium; (RU 〇 2). High-power function gate material: two: ratio: including but not limited to oxygen yt nails, higher electrons are worn, and the ratio of typical N-type polycrystalline hard gates is more than one day. ^Cut as an external dielectric widely used in the embodiment of the present invention: at about 3.15 eV. Therefore, it has an implantation barrier, which is high "3 u, the holding material for the v external dielectric layer, and preferably is higher than about 4 ev. Regarding and ^, for example, higher than about 3.4 eV, the polysilicon gate, Injecting the second layer of the p蜇-containing ytterbium oxide outer dielectric layer of the θθ-虱矽矽 external dielectric layer: ^ a W, and the 相对曰曰夕相对相对相对相对相对相对In the case of the pole unit, the system employs a dielectric structure _ system Π reduced by about 2 volts. Another " electrical structure _ system = what is the structure of the fault 〇 6 thick ^ dielectric material contains structure 106 and the channel area One of the cerium oxide and the ammonia gas has a material of about 2 to 〇亳氺, which contains Μρ矽, or other types such as w, such as ten-bearing, such as alumina (Ai2〇3). Constant material

电何儲存結構】^ J 體單元所儲存> t 諸存電荷以控n 是會導電狀態。較先之實J非揮發性記憶荷儲存結構。較新二曰曰石夕，以使内儲電荷狀：姥存結構與夺平曰躺、實施例之電$從D κ展遍及此電不水晶體結構。、电何储存結電荷鑛存於電行 Χ新的實施例不像货’、、' 電荷捕捉電何儲存結構之特定位置"像導電材料，會將错以啟動不同位置Electrical storage structure] ^ J body unit stored > t stored charge to control n is conductive. The first real J non-volatile memory storage structure. The newer 曰曰曰曰夕 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , What is stored? The charge is stored in the electric line. The new embodiment is not like the goods ', 'the charge trapping electricity, the specific position of the storage structure', like the conductive material, will be wrong to start different positions.

S 7 201218320S 7 201218320

TW3191PA-D 之電荷儲存結構以儲存分別的邏輯狀態。代表性的電荷捕捉結構包含具有大約3至9奈米之厚度之氮化石夕。源極區11〇具有一源極電壓Vs，而汲極區112具有 -沒極電壓Vd。源極區11〇與祕區112在多數的實施例中為部分之位兀線’且其特徵為一接面深度12〇。本體區 122在多數的實施例中是—基板或—井，且具有一本體電壓Vb。為因應被施加至閘極1〇2、源極11〇、汲極ιΐ2及本體122之適當的偏壓配置，形成一通道114電連接源極 110與汲極112。源極與汲極區116之上邊緣係高於在通道114與介電結構108之間的介面118。然而，在通道114與介電結構 108之間的介面118維持在源極與汲極區之下邊緣上方。因此，在通道114與介電結構1〇8之間之介面118結束於源極區11 〇與汲極區112之中間區域。源極區110與汲極區Π2之上邊緣係與本體區122之上邊緣排成一線。因此，第丨圖之非揮發性記憶體單元係為凹入通道之實施例。第2圖係為一非揮發性記憶體單元之示意圖，非揮發性記憶體單元具有舉升離半導體基板之源極區與汲極區。第1圖與第2圖之非揮發性記憶體單元實質上是類似的。然而’源極區210與汲極區212之上邊緣係位於本體區122之上邊緣的上方。因此，第2圖之非揮發性記憶體單元係為舉升之源極與沒極之實施例。在通道2 μ與介電結構208之間之介面218仍然結束於源極區21〇與汲極區 212之中間區域。源極區21 〇與汲極區212之特徵為一接 8 201218320 面深度220。第3A圖係為在具有凹人通道之_發性記憶體單元中，電子彳之閘極注入至電荷儲存結構之示意圖。問極區302具有-10V之開極電壓％。源極區3〇4具有·或浮動之源極電壓Vs。沒極區鳩具有爾或淨動之汲極電壓W。本體區3〇8具有_之本體電壓vb。第3B圖係為在具有舉升之祕區魏極區之非揮發性記憶體單元中，電子從閘極注人至電荷儲存結構之示意圖。第3B圖之偏壓配置係類似於第3 a圖。第4A圖係為在具有凹人通道之非揮發性記憶體單元中’電子從基板注人至電荷儲存結構之示意圖。間極區402具有i 〇V之閘極電壓％。源極區4〇4臭有-ιόν或洋動之源極電壓Vs。汲極區4〇6具有或泮動之汲極電壓w。本體區倾具有_1GV之本體電壓^。第4B圖係為在具有舉升之源極區與没極區之非揮發性記憶體單元巾，電子從基板Μ至電荷料結構之示意圖。第4Β圖之偏壓配置係類似於第4八圖。 ”第二圖广為在具有凹入通道之非揮發性記憶體單元中，㈣（banc^-band)熱電子注人至電荷儲存結構之示意 f 2具有！〇V之問極電壓Vg。p+型源極區5〇4 八有-5V之源極電壓Vs。㈣沒極區5〇6具有㈧或浮動之沒極電壓w’型本體區508具有〇v之本體電壓第5B。圖係為在具有舉升之源極區與沒極區之非揮發性記憶體單元中，帶間熱電子注人至電荷儲存結構之示意 201218320The charge storage structure of the TW3191PA-D stores the respective logic states. A representative charge trapping structure comprises a nitride nitrite having a thickness of between about 3 and 9 nanometers. The source region 11A has a source voltage Vs, and the drain region 112 has a -polar voltage Vd. The source region 11 and the secret region 112 are part of the tantalum line ' in most embodiments and are characterized by a junction depth of 12 〇. The body region 122, in most embodiments, is a substrate or well and has a bulk voltage Vb. A channel 114 is electrically connected to the source 110 and the drain 112 in response to a suitable biasing configuration applied to the gate 1, the source 11, the drain, and the body 122. The upper edge of the source and drain regions 116 is higher than the interface 118 between the channel 114 and the dielectric structure 108. However, the interface 118 between the channel 114 and the dielectric structure 108 is maintained above the lower edge of the source and drain regions. Therefore, the interface 118 between the channel 114 and the dielectric structure 1 结束 8 ends in the middle region between the source region 11 〇 and the drain region 112. The edge regions of the source region 110 and the drain region 2 are aligned with the upper edge of the body region 122. Thus, the non-volatile memory cell of the first diagram is an embodiment of a recessed channel. Figure 2 is a schematic illustration of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate. The non-volatile memory cells of Figures 1 and 2 are substantially similar. However, the upper edge of the source region 210 and the drain region 212 are located above the upper edge of the body region 122. Therefore, the non-volatile memory cell of Figure 2 is an embodiment of the source and the immersion of the lift. The interface 218 between the channel 2μ and the dielectric structure 208 still ends in the middle region of the source region 21A and the drain region 212. The source region 21 〇 and the drain region 212 are characterized by a connection 8 201218320 face depth 220. Fig. 3A is a schematic view showing the injection of the gate of the electron germanium into the charge storage structure in the dummy memory cell having the concave human channel. The polarity region 302 has an open voltage % of -10V. The source region 3〇4 has a floating source voltage Vs. The immersive zone has a 汲 or 汲汲电压 voltage W. The body region 3〇8 has a body voltage vb of _. Fig. 3B is a schematic diagram of electrons from a gate to a charge storage structure in a non-volatile memory cell having a Weiji region in the lift zone. The bias configuration of Figure 3B is similar to Figure 3a. Figure 4A is a schematic illustration of the electron injection from the substrate to the charge storage structure in a non-volatile memory cell having a concave human channel. The interpole region 402 has a gate voltage % of i 〇V. Source region 4〇4 odor There is -ιόν or oceanic source voltage Vs. The bungee region 4〇6 has or has a rake voltage w. The body region has a body voltage of _1 GV. Figure 4B is a schematic illustration of the electrons from the substrate to the charge structure in a non-volatile memory cell towel having raised source regions and non-polar regions. The bias configuration of Figure 4 is similar to Figure 4-8. The second figure is widely used in a non-volatile memory cell with a recessed channel. (4) (banc^-band) The hot electron injection into the charge storage structure shows that the f 2 has a voltage Vg of 〇V. The source region 5〇4 八 has a source voltage Vs of -5V. (4) The immersion region 5〇6 has (8) or the floating immersed voltage w' type body region 508 has 本体v body voltage 5B. In the non-volatile memory cell with the raised source region and the non-polar region, the inter-band hot electron injection to the charge storage structure is illustrated 201218320

TW3191PA-D 圖。第5B圖之偏壓配置係類似於第5A圖。第6A圖係為在具有凹入通道之非揮發性記憶體單元中，通道熱電子注入至電荷儲存結構之示意圖。開極區602具有10V之開極電壓Vg〇n+型源極區6〇4 具有-5V之源極電壓Vs。n+型汲極區6〇6具有〇v之汲極電壓Vd〇p型本體區608具有〇v之本體電壓Vb。第6B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，通道熱電子注入至電荷儲存結構之示^ 圖。第6B圖之偏壓配置係類似於第6a圖。第7A圖係為在具有凹入通道之非揮發性記憶體單元中，基板熱電子注入至電荷儲存結構之示意圖。閘極區702具有10V之閘極電壓Vg^+型源極區7〇4 具f 0V之源極電壓vs。n+型汲極區7〇6具有〇v之汲極電壓Vd。N型本體區708具有_6V之本體電壓Vb。p型井區710具有-5V之井電壓Vw。源極區7〇4與汲極區7〇6 係位於此井區710中，而井區位於本體區中。第7B圖係為在具有舉升之源極與汲極區之非揮發性記憶體單元中，基板熱電子注入至電荷儲存結構之示意圖。第7B圖之偏壓配置係類似於第7a圖。第8A圖係為在具有凹入通道之非揮發性記憶體單元中，電洞從閘極注入至電荷儲存結構之示意圖。閘極區802具有10V之閘極電壓Vg。源極區8〇4具有-ιόν或浮動之源極電壓Vs。汲極區8〇6具有_l〇v或浮動之汲極電壓Vd。本體區808具有_i〇V之本體電壓vb。第8B圖係為在具有舉升之源極區與汲極區之非揮發 201218320TW3191PA-D diagram. The bias configuration of Figure 5B is similar to Figure 5A. Figure 6A is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. The open region 602 has an open voltage of 10 V. The Vg〇n+ type source region 6〇4 has a source voltage Vs of -5V. The n+ type drain region 6〇6 has a drain of 〇v. The voltage Vd〇p type body region 608 has a body voltage Vb of 〇v. Figure 6B is a diagram showing the injection of channel hot electrons into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. The bias configuration of Figure 6B is similar to Figure 6a. Figure 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 702 has a gate voltage of 10 V. The source region 7 〇 4 has a source voltage vs of f 0V. The n+ type drain region 7〇6 has a drain voltage Vd of 〇v. The N-type body region 708 has a body voltage Vb of _6V. The p-type well region 710 has a well voltage Vw of -5V. The source region 7〇4 and the drain region 7〇6 are located in the well region 710, and the well region is located in the body region. Figure 7B is a schematic illustration of the injection of hot electrons into the charge storage structure of the substrate in a non-volatile memory cell having raised source and drain regions. The bias configuration of Figure 7B is similar to Figure 7a. Figure 8A is a schematic illustration of the injection of a hole from a gate to a charge storage structure in a non-volatile memory cell having a recessed channel. The gate region 802 has a gate voltage Vg of 10V. The source region 8〇4 has -ιόν or a floating source voltage Vs. The drain region 8〇6 has _l〇v or a floating drain voltage Vd. The body region 808 has a body voltage vb of _i 〇V. Figure 8B is the non-volatile in the source and bungee regions with lifts 201218320

1 vv^ t y i rn-O 性記憶體單元中，電洞從閘極注入至電一立圖。第8B圖之偏壓配置係類似於第8a圖' 、、、°之7^思第9A圖係為在具有凹入通道之非揮發性記中，電洞從基板注入至電荷儲存結構之示意圖。- 間極區902具有· 1 〇v之蘭搞蕾段v 、有10 V戋、、孚動之湄朽Φ厂 ^ g。源極區904具 ΐ之汲Γ 汲極區906具有_或浮第體具有卿之本體電壓vb。性記憶體單元中，電洞從‘：源極區？汲極區之非揮發圖。第圖之偏m 土，入至電荷儲存結構之示意當置係類似於第9A圖。第10Α圖係為在具有凹元中，帶間熱電甸、、之非揮發性記憶體單間極區100^入至電荷儲存結構之示意圖。 1004具有5V之塬極之閘極電壓Vg。n+型源極區或浮動之沒極電髮、V塱Vs。n+型汲極區1006具有〇v 電壓Vb。型本體區咖具有〇v之本體第ι〇Β圖係為發性記憶體單元中T册/、有舉升之源極區與汲極區之非揮意圖。第10B _之偏=熱電洞注入至電荷儲存結構之示第11A _係為且己置係類似於第10A圖。 4 ’通道熱電詞之非揮發性記憶體單閘極區11〇2息電荷儲存結構之示意圖。 1104具有GVt原極電之閘極電壓Vg卞型源極區之汲極電壓Vd。二VS。計型汲極區11〇6具有π 第11B _係為在具:1108具有0V之本體電壓Vb。 *' 牛升之源極區與及極區之非揮 2012183201 vv^ t y i rn-O In the memory unit, the hole is injected from the gate to the power. The biasing configuration of FIG. 8B is similar to that of FIG. 8a, FIG. 9A, and FIG. 9A is a schematic diagram of the hole being injected from the substrate into the charge storage structure in the non-volatile memory having the concave channel. . - The interpolar region 902 has a 1 〇v lan lei section v, a 10 V 戋, and a moving 湄 Φ factory ^ g. The source region 904 has a crucible region 906 having a _ or a floating body having a bulk voltage vb. In the memory unit, the hole is from the ‘: source area? Non-volatile map of the bungee zone. The illustration of the partial m soil in the figure, into the charge storage structure, is similar to Figure 9A. The figure 10 is a schematic diagram of the non-volatile memory single-electrode region of the inter-band thermocouple, which has a concave element, into the charge storage structure. 1004 has a gate voltage Vg of 5V. n+ type source region or floating immersed electric hair, V塱Vs. The n+ type drain region 1006 has a 〇v voltage Vb. The type of ontology area has the body of 〇v. The first 〇Β diagram is the T-volume of the priming memory unit, and the non-swing of the source area and the bungee area. The 10B _ bias = hot hole injection into the charge storage structure shows that the 11A _ system is and the system is similar to Figure 10A. 4 ′ channel thermoelectric non-volatile memory single gate region 11〇2 information schematic diagram of charge storage structure. 1104 has a gate voltage Vd of the GVt primary gate voltage Vg卞 source region. Two VS. The metering drain region 11 〇 6 has π 11B _ is a body voltage Vb having 0V at 1108. *' The source area of Niu Sheng and the non-wave area of the pole area 201218320

TW3191PA-D 發性記憶體單元中，通道熱電洞注入至電荷儲存結構之示意圖。第11B圖之偏壓配置係類似於第11A圖。第12A圖係為在具有凹入通道之非揮發性記憶體單元中，基板熱電洞注入至電荷儲存結構之示意圖。問極區1202具有-10V之問極電壓Vg。p+型源極區 1204具有0V之源極電壓Vs。p+型汲極區1206具有0V 之汲極電壓Vd°P型本體區1208具有6V之本體電壓Vb。 N型井區1210具有5 V之井電壓V w。源極區12 04與;及極區1206係位於井區1210中，而井區1210位於本體區1208 中〇第12B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，基板熱電洞注入至電荷儲存結構之示意圖。第12B圖之偏壓配置係類似於第12A圖。第13A圖係為在具有凹入通道之非揮發性記憶體單元中，用以讀取儲存於電荷儲存結構之右側之資料之一反向讀取操作之示意圖。In the TW3191PA-D priming memory cell, the channel thermowell is injected into the charge storage structure. The bias configuration of Figure 11B is similar to Figure 11A. Fig. 12A is a schematic view showing the injection of a substrate thermowell into a charge storage structure in a non-volatile memory cell having a recessed channel. The polarity region 1202 has a voltage Vg of -10V. The p+ type source region 1204 has a source voltage Vs of 0V. The p+ type drain region 1206 has a drain voltage of 0 V. The P type body region 1208 has a body voltage Vb of 6V. The N-type well region 1210 has a well Vv of 5 V. The source region 12 04 and the polar region 1206 are located in the well region 1210, and the well region 1210 is located in the body region 1208. The 12B map is a non-volatile memory in the source region and the bungee region with lift. In the body unit, a schematic diagram of the substrate thermowell injected into the charge storage structure. The bias configuration of Figure 12B is similar to Figure 12A. Figure 13A is a schematic illustration of one of the reverse reading operations for reading data stored on the right side of the charge storage structure in a non-volatile memory cell having a recessed channel.

問極區13 02具有3 V之問極電壓Vg。n+型源極區 1304具有1.5 ν'之源極電壓Vs ° 型 >及極區1306具有0"V 之汲極電壓Vd°P型本體區1308具有0V之本體電壓Vb。第13B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，用以讀取儲存於電荷儲存結構之右側之資料之反向讀取操作之示意圖。第13B圖之偏壓配置係類似於第13A圖。第14A圖係為在具有凹入通道之非揮發性記憶體單元中，用以儲存位於電荷儲存結構之左側之資料之反向讀 12 201218320 取操作之示意圖。間極區14〇2 |古”，The polarity region 13 02 has a voltage Vg of 3 V. The n+ type source region 1304 has a source voltage Vs ° type of 1.5 ν' and the pole region 1306 has a threshold voltage of 0 V. The P type body region 1308 has a body voltage Vb of 0V. Figure 13B is a schematic illustration of a reverse read operation for reading data stored on the right side of the charge storage structure in a non-volatile memory cell having raised source and drain regions. The bias configuration of Figure 13B is similar to Figure 13A. Figure 14A is a schematic illustration of the reverse read 12 201218320 operation of storing data located on the left side of the charge storage structure in a non-volatile memory cell having a recessed channel. Inter-polar zone 14〇2 | ancient",

1404具有0V之源極ί厂之閘極電壓Vg°n+型源極區之汲極電壓VdQp ^查Vs°n+型汲極區1406具有L5V 第14B圖係^體區1408具有〇V之本體電壓Vb。發性記憶體、在具有舉升之雜區與祕區之非揮資料之反向讀取操/以儲存位於電荷儲存結構之左側之似於第14A®。、之不意圖。第14β圖之偏壓配置係類弟 15Α圖信;在+ 元中，用以讀取儲;^具有凹人通道之非揮發性記憶體單間讀取操作之示意^電荷儲存結構之右側之資料之-帶閘極區15〇2 1古1404 has a source of 0V ί factory gate voltage Vg °n + type source region of the drain voltage VdQp ^ Vs °n + type bungee region 1406 has L5V Figure 14B system body area 1408 has 〇V body voltage Vb. The priming memory, the reverse read operation with the non-swept data of the lifted and secret areas, is stored on the left side of the charge storage structure and is similar to the 14A®. Not intended. The bias configuration of the 14th figure is the 15th letter of the class; in the + element, the reading is used; the non-volatile memory of the non-volatile memory with the concave channel is shown in the figure of the right side of the charge storage structure. - with gate region 15〇2 1 ancient

1504具有浮動之源搞 '之閘極電壓Vg。η+型源極區之汲極電壓VdQp^。/壓VS。η+型汲極區1506具有2V 第15B圖係為t體區1508具有0V之本體電壓Vb。發性記憶體單元中Y具有舉升之源極區與汲極區之非揮之資料之-帶間讀^讀取儲存於電荷儲存結構之右側係類似於第15A ^。术作之不意圖。第15B圖之偏壓配置元中第16A圖係為右，用以儲存位於二有凹入通道之非揮發性記憶體單取操作之示意圖。、“何儲存結構之左侧之資料之帶間讀閘極區1602具有 1604具有2 v之源極·二之閘極電壓Vg。n+型源極區之汲極電壓别士 I S。n+型汲極區1606具有浮動第16B圖係A體區1608具有0V之本體電壓Vb。，、為在具有舉狀源極區歧極區之非揮 2012183201504 has a floating source to engage in 'gate voltage Vg. The drain voltage VdQp^ of the η+ type source region. / pressure VS. The n + -type drain region 1506 has a 2V picture 15B which is a t body region 1508 having a body voltage Vb of 0V. In the memory cell, Y has the non-volatile data of the source region and the drain region of the lift - the inter-band read is read and stored on the right side of the charge storage structure, similar to the 15A ^. The intention is not intended. In Figure 15B, the bias configuration is shown in Figure 16A as the right, for storing the non-volatile memory single access operation in the two recessed channels. The inter-band read gate region 1602 of the data on the left side of the storage structure has 1604 having a source voltage of 2 v and a gate voltage Vg. The n+ type source region has a drain voltage of IS. n+ type 汲The pole region 1606 has a floating body 16B, and the body region 1608 has a body voltage Vb of 0 V. , and is a non-volatile 201218320 having a source region.

TW3191PA-D 發性記憶體單元中，用以儲存位於電荷儲存結構之左側之資料之帶間讀取操作之示意圖。第16B圖之偏壓配置係類似於第16A圖。由於結合之垂直與橫向電場之緣故，流經非揮發性記憶體單元結構之帶間電流以高準確度決定電荷儲存結構之特定部分之電荷儲存狀態。較大的垂直與橫向電場導致較大的帶間電流。一種偏壓配置係被應用至各種不同的端子，以使這些能帶彎曲到足以在非揮發性記憶體單元結構中導致帶間電流，同時將在非揮發性記憶體單元節點之間之電位差保持為足夠低，以使程式化或抹除不會產生。於偏壓配置之例子中，非揮發性記憶體單元結構係相對於主動源極區或汲極區與本體區被逆向偏壓，產生逆向偏壓之接面。此外，閘極結構之電壓導致這些能帶彎曲成足以使帶間隧穿經由非揮發性記憶體單元結構而產生。在其中一個非揮發性記憶體單元結構節點（於多數的實施例中是源極區或汲極區）中之高摻雜濃度。其中此結構節點具有所產生之空間電荷區域之高電荷密度，以及此空間電荷區域在短距離内之電壓改變，係有助於產生急遽的能帶彎曲。位於逆向偏壓之接面之一側上之此價帶之電子經由被禁止的間隙遂穿至在逆向偏壓之接面之另一側上之傳導帶，並向下漂移至勢能丘(potential hill)，更深入至逆向偏壓之接面之N型節點。類似地，電洞漂移過勢能丘，遠離逆向偏壓之接面之N型節點，並朝向逆向偏壓之接面之P 型節點。閘極區之電壓控制位於電荷儲存結構附近之逆向偏 14 201218320 麗 ·»/ I / l 1 厂壓之接面之部分之電壓。當閘極結構之電壓變成更負時，位於電荷儲存結構之附近之逆向偏壓之接面之此部分之電壓變成更負，導致二極體結構中之更深的能帶彎曲。因為以下（1)與（2)之至少某些組合之結果，更多帶間電流會流動：（1)在彎曲能帶之一側之被佔據的電子能階與彎曲能帶之另一側之未被佔據的電子能階之間漸增重疊量；以及（2) 在被佔據的電子能階與未被佔據的電子能階之間之更狹小之阻絕寬度（Sze，Physics of Semiconductor Devices, 1981)。儲存於電荷儲存結構上之淨負或淨正電荷更進一步影響能帶彎曲度。依據高斯定律，當負電壓相對於逆向偏壓之接面被施加至閘極區時，較強電場係由靠近具有相當高的淨負電荷之電荷儲存結構之部分之逆向偏壓之接面之部分所經歷。類似地，當正電壓相對於逆向偏壓之接面被施加至閘極區時，較強電場係由靠近具有相當高的淨正電荷之電荷儲存結構之部分之逆向偏壓之接面之部分所經歷。關於讀取之不同的偏壓配置以及關於程式化與抹除之偏壓配置顯示出慎重之平衡。關於讀取，在逆向偏壓之接面節點之間之電位差不應導致載荷子之實質上的數目通過一介電材料至電荷儲存結構並影響電荷儲存狀態（亦即，程式化邏輯位準）。相較之下，關於程式化與抹除，在逆向偏壓之接面節點之間之電位差足以導致載子之實質上的數目通過一介電材料並藉由帶間熱載子注入來影響電荷儲存狀態。 201218320In the TW3191PA-D, the schematic diagram of the inter-band read operation for storing data located on the left side of the charge storage structure. The bias configuration of Figure 16B is similar to Figure 16A. Due to the combination of the vertical and transverse electric fields, the current between the strips flowing through the non-volatile memory cell structure determines the charge storage state of a particular portion of the charge storage structure with high accuracy. Larger vertical and transverse electric fields result in larger currents between the bands. A biasing configuration is applied to a variety of different terminals to bend the bands sufficiently to cause current between the strips in the non-volatile memory cell structure while maintaining the potential difference between the non-volatile memory cell nodes Be low enough so that stylization or erasure does not occur. In the bias configuration example, the non-volatile memory cell structure is reverse biased relative to the active source region or the drain region to the body region, creating a junction of the reverse bias. In addition, the voltage of the gate structure causes these bands to bend enough to cause interband tunneling through the non-volatile memory cell structure. The high doping concentration in one of the non-volatile memory cell structure nodes (in the majority of the embodiments, the source or drain regions). The structural node has a high charge density in the space charge region generated, and the voltage change of the space charge region in a short distance is helpful for generating an acute band bend. The electrons of the valence band on one side of the junction of the reverse bias are punctured to the conduction band on the other side of the junction of the reverse bias via the forbidden gap and drift down to the potential energy hill (potential) Hill), deeper into the N-type node of the junction of the reverse bias. Similarly, the hole drifts over the potential energy hill away from the N-junction of the junction of the reverse bias and faces the P-type junction of the junction of the reverse bias. The voltage control of the gate region is located in the vicinity of the charge storage structure. 14 201218320 丽 ·» / I / l 1 The voltage of the junction of the factory. When the voltage of the gate structure becomes more negative, the voltage at the portion of the junction of the reverse bias located near the charge storage structure becomes more negative, resulting in a deeper band bend in the diode structure. As a result of at least some of the following combinations of (1) and (2), more current between the bands will flow: (1) the occupied electron energy level on one side of the bending energy band and the other side of the bending energy band The increasing overlap between the unoccupied electron energy levels; and (2) the narrower barrier width between the occupied electron energy level and the unoccupied electron energy level (Sze, Physics of Semiconductor Devices, 1981). The net negative or net positive charge stored on the charge storage structure further affects the band curvature. According to Gauss's law, when the junction of the negative voltage and the reverse bias is applied to the gate region, the stronger electric field is connected by the reverse bias of the portion of the charge storage structure having a relatively high net negative charge. Partial experience. Similarly, when a positive voltage is applied to the gate region with respect to the reverse bias, the stronger electric field is the portion of the junction of the reverse bias that is close to the portion of the charge storage structure having a relatively high net positive charge. Experienced. The different bias configurations for reading and the biasing configuration for stylization and erasing show a careful balance. With respect to reading, the potential difference between the junction nodes of the reverse bias should not cause a substantial number of charge carriers to pass through a dielectric material to the charge storage structure and affect the charge storage state (ie, the programmed logic level). . In contrast, with respect to stylization and erasing, the potential difference between the junction nodes of the reverse bias is sufficient to cause a substantial number of carriers to pass through a dielectric material and affect the charge by inter-band hot carrier injection. Storage status. 201218320

TW3191PA-D 第17圖係具有一凹入通道之一非揮發性記憶體單元陣列之製造流程圖，其顯示第19至23圖之製程步驟之各種可能的組合。第17圖揭露下述的處理流程組合：第19 與22圖；第19與23圖；第20與22圖；第20與23圖；第21與22圖；以及第21與23圖。這些組合伴隨著後端處理。第18A與18B圖係為具有舉升之源極區與汲極區之非揮發性記憶體單元陣列之製造流程圖。第18A圖係具有舉升之源極區與汲極區之一 NOR非揮發性記憶體單元陣列之製造流程圖，其顯示第24至27 圖之製程步驟之各種可能的組合。第18A圖揭露下述的處理流程組合：第24、25與27圖；以及第24、26與27圖。這些組合伴隨著後端處理。第18B圖係具有舉升之源極區與汲極區之一 NAND 非揮發性記憶體單元陣列之製造流程圖，其顯示第28至 30圖之製程步驟之各種可能的組合。第18B圖揭露下述的處理流程組合：第28與29圖；以及第28與30圖。這些組合伴隨著後端處理。第19A至19C圖係為在第22或23圖之前，在具有凹入通道之非揮發性記憶體單元中，用以形成一溝槽之製程步驟。於第19A圖中，氧化物1910係沈積於基板1900 上。光阻係被沈積並圖案化，且被圖案化之光阻係用以依據光阻圖案來移除氧化物之數個部分。於第19B圖中，殘留的光阻1922保護殘留的氧化物1912。殘留的光阻係被移除，且未被氧化物覆蓋的基板係被蝕刻。於第19C圖中， 201218320TW3191PA-D Figure 17 is a manufacturing flow diagram of a non-volatile memory cell array having a recessed channel showing various possible combinations of process steps of Figures 19-23. Figure 17 discloses the following combinations of process flows: Figures 19 and 22; Figures 19 and 23; Figures 20 and 22; Figures 20 and 23; Figures 21 and 22; and Figures 21 and 23. These combinations are accompanied by backend processing. 18A and 18B are manufacturing flow diagrams of a non-volatile memory cell array having lifted source and drain regions. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18A discloses the following combination of process flows: Figures 24, 25 and 27; and Figures 24, 26 and 27. These combinations are accompanied by backend processing. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. Figure 18B discloses the following combination of process flows: Figures 28 and 29; and Figures 28 and 30. These combinations are accompanied by backend processing. 19A to 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel before the 22nd or 23rd. In Figure 19A, oxide 1910 is deposited on substrate 1900. A photoresist is deposited and patterned, and the patterned photoresist is used to remove portions of the oxide in accordance with the photoresist pattern. In Figure 19B, the remaining photoresist 1922 protects the residual oxide 1912. The residual photoresist is removed and the substrate not covered by the oxide is etched. In Figure 19C, 201218320

• »* j * y I j n-D 溝槽1930係被餘刻至未被氧化物1912覆蓋的基板簡中。第20A至20E圖係為在第22或23圖以前，在非揮發性記憶體單元中形成—溝槽之前，用以縮小一閑極長度之製知步驟。第20A至20C圖係類似於第19A至19C圖。於第20D圖中’-間隙壁2_係沈積至此溝槽中，殘留較小溝槽觀。於第2〇E时，溝槽之底部旁之間隙蔗部分係被触刻’殘留下間隙壁2〇42。此種閘極長度比例啁整可留下相較於第19圖之較小閘極長度。第21A至21E圖係為在第22或23圖以前，在非揮《杜6己憶體單it中形成-溝槽之前，用以擴大_閘極長度之製程步驟。第21A至21B圖係類似於第19A至19B圖。於第21C圖中’殘留的被圖案化之光阻係被移除，露出圖案化之氧化物1912。於第21D圖中，此被圖案化之氧化物係被蝕刻’殘留下較小的被圖案化之氧化物2112。於第圖中，溝槽2132係被蝕刻凹入至未被氧化物以^覆 '-的之基板1900中。此種閘極長度縮小會留下相較於第 19圖之較長的閘極長度。，第22A至22K圖係為在第19、20或21圖以後之結，製程步驟，用以形成一 N〇R非揮發性記憶體單元陣列，每個NOR非揮發性記憶體單元位於—溝射，以使每個非揮發性圮憶體單元具有一凹入通道。在第22A圖中，例如Ο Ν Ο層之介電材料與電荷儲存結構2 2 $ 〇係形成於溝槽 :，從而殘留下較小溝槽2232。在第22β圖中，沈積例二多晶石夕之閘極材料2260。在第22c圖中，閘極材料係被钱 17 201218320• »* j * y I j n-D Trench 1930 is engraved into a substrate that is not covered by oxide 1912. 20A to 20E are diagrams for forming a step of reducing the length of a idler before forming a groove in the non-volatile memory cell before the 22nd or 23rd. Figures 20A through 20C are similar to Figures 19A through 19C. In Fig. 20D, the '-gap wall 2' is deposited into this trench, leaving a small trench view. At the second 〇E, the gap between the bottom of the groove and the cane portion is etched to 'remaining the lower gap 2'42. This gate length ratio adjustment can leave a smaller gate length than in Figure 19. 21A to 21E are process steps for enlarging the length of the gate before the formation of the trench in the non-repetition. Figures 21A through 21B are similar to Figures 19A through 19B. The remaining patterned photoresist is removed in Figure 21C to expose patterned oxide 1912. In Figure 21D, the patterned oxide is etched to leave a smaller patterned oxide 2112. In the figure, the trench 2132 is etched into the substrate 1900 which is not covered by the oxide. This reduction in gate length will result in a longer gate length than in Figure 19. 22A to 22K are the junctions after the 19th, 20th or 21th, and the process steps for forming an N〇R non-volatile memory cell array, each NOR non-volatile memory cell being located in the trench Shoot so that each non-volatile memory unit has a concave channel. In Fig. 22A, a dielectric material such as a Ο Ο layer and a charge storage structure 2 2 〇 are formed in the trenches, thereby leaving a smaller trench 2232. In the 22th figure, the second example of the polycrystalline stone gate material 2260 is deposited. In Figure 22c, the gate material is money 17 201218320

1 WJIVI^A-D 刻，從而殘留下閘極材料2262在溝槽之内部。在第22d 圖中，例如SiN之介電材料2270係沈積於閘極材料2262 上。在第22E圖中，此介電材料係被蝕刻，而殘留下介電材料2272在溝槽之内部。在第22F圖中，殘留的被圖案化之氧化物係被移除。於此時點，閘極材料2262與氧化物2272之堆疊上升高於基板之表面。在第22(}圖;^，離子植入法形成源極區2280與汲極區2282。在第22H圖中，沈積例如HDP氧化物之氧化物229〇。在第221圖中，例如藉由CMP、回浸（dip-back)或回蝕來移除覆蓋氧化物 2272之過剩的氧化物。在第22J圖中，移除氧化物 2272 ° 在第22K圖中，沈積額外閘極材料而形成閘極區2264。第23A至23E圖係為在第19、20或21圖以後之結束製程步驟，用以形成一 NAND非揮發性記憶體單元陣列，每個NAND非揮發性記憶體單元位於一溝槽中，以使母個非揮發性s己憶體單元具有一凹入通道。在第Μ a圖中，例如ΟΝΟ層之介電材料與電荷儲存結構225〇係形成於溝槽中’從而殘留下較小溝槽2232。在第23Β圖中，沈積例如多晶矽之閘極材料2260。在第23C圖中，過剩的閘極材料係例如藉由CMP而被移除，從而暴露〇Ν〇層。在第23D圖中，殘留的被圖案化之氧化物係被移除。於此時點，閘極材料2262上升高於基板之表面。在第23Ε圖中，離子植入法形成源極區2380與汲極區2382。第24Α至24D圖係為在第25或26圖以前之開始製知步驟，用以形成在一 NOR陣列中之一非揮發性記憶體單元之舉升之源極區與汲極區。在第24A圖中，例如όνο 2012183201 WJIVI^A-D is engraved so that the lower gate material 2262 remains inside the trench. In Fig. 22d, a dielectric material 2270 such as SiN is deposited on the gate material 2262. In Fig. 22E, the dielectric material is etched while the remaining dielectric material 2272 remains inside the trench. In Figure 22F, the remaining patterned oxide is removed. At this point, the stack of gate material 2262 and oxide 2272 rises above the surface of the substrate. In the 22nd}th, the ion implantation method forms the source region 2280 and the drain region 2282. In the 22H image, for example, an oxide 229〇 of the HDP oxide is deposited. In FIG. 221, for example, by CMP, dip-back or etch back to remove excess oxide overlying oxide 2272. In Figure 22J, oxide 2272 is removed. In Figure 22K, additional gate material is deposited to form Gate region 2264. The 23A to 23E diagram is the process step after the 19th, 20th or 21th step to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell is located at In the trench, such that the parent non-volatile simon cell has a recessed channel. In the Figure a, a dielectric material such as a germanium layer is formed in the trench with the charge storage structure 225. A smaller trench 2232 remains. In Figure 23, a gate material 2260 such as polysilicon is deposited. In Figure 23C, excess gate material is removed, for example by CMP, to expose the germanium layer. In Figure 23D, the remaining patterned oxide is removed. At this point, the gate The pole material 2262 rises higher than the surface of the substrate. In the 23rd, the ion implantation forms the source region 2380 and the drain region 2382. The 24th to 24D diagrams are the steps before the 25th or 26th. a source region and a drain region for forming a non-volatile memory cell in a NOR array. In Figure 24A, for example, όνο 201218320

1 vv j 1 7 I r rv-D 層之介電材料與電荷儲存結構2410係沈積於基板2400 上。在第24B圖中’沈積例如多晶矽之閘極材料，例如 SiN之氮矽化合物材料係沈積於閘極材料上，而形成光刻 (photolithographic)結構’殘留下 siN 2430、多晶矽 2420 與ΟΝΟ 2412之堆疊。在第24C圖中，形成間隙壁2440。在第24D圖中，蝕刻間隙壁，而殘留下間隙壁侧壁2442。第25Α至25Β圖係為在第24圖以後且在第27圖以前之結束製程步驟，其使用磊晶矽以形成在一 N〇Il陣列中之一非揮發性記憶體單元之舉升之源極區與汲極區。在第25Α圖中’沈積蠢晶石夕2550。在第25Β圖中，離子植入法形成源極區2560與汲極區2562。第26Α至26C圖係在第24圖以後且在第27圖以前之結束製程步驟’其使用多晶矽以形成在一 NOR陣列中之一非揮發性記憶體單元之舉升之源極區與汲極區。在第 26A圖中，沈積多晶矽2650。在第26B圖中，回蝕此多晶矽以留下多晶矽2652。在第26C圖中，離子植入法形成源極區2 6 6 0與 >及極區2662。第27A至27D圖係在第25或26圖以前之結束製程步驟’用以形成一 NOR非揮發性記憶體單元陣列，每個 NOR非揮發性記憶體單元都具有舉升之源極區與沒極區。在第27A圖中，沈積例如HDP氧化物之介電材料，而覆蓋包含間隙壁側壁與氮矽化合物材料2430之結構。在第27B圖中，例如藉由CMP、回浸(dip-back)或回蝕來移除覆蓋氮矽化合物材料2430之過剩的氧化物，而殘留下氧化物2772圍繞間隙壁側壁。在第27C圖中，移除氮1 vv j 1 7 I r rv-D layer dielectric material and charge storage structure 2410 are deposited on substrate 2400. In Fig. 24B, 'the deposition of a gate material such as polysilicon, such as a NiN bismuth compound material, is deposited on the gate material to form a photolithographic structure' residual SiN 2430, polysilicon stack 2420 and ΟΝΟ 2412 stacked. . In Fig. 24C, a spacer 2440 is formed. In Fig. 24D, the spacer is etched while the lower spacer sidewall 2442 remains. The 25th to 25th drawings are the process steps after the 24th and before the 27th, which use the epitaxial germanium to form a source of lifting of one of the non-volatile memory cells in an array of N〇I1. Polar zone and bungee zone. In the 25th picture, the deposit of stupid crystal stone 2550. In the 25th panel, the ion implantation method forms the source region 2560 and the drain region 2562. Figures 26 to 26C are after the 24th and before the 27th process, the process step 'which uses polysilicon to form the source region and the drain of one of the non-volatile memory cells in a NOR array. Area. In Figure 26A, polycrystalline germanium 2650 is deposited. In Figure 26B, the polysilicon is etched back to leave polysilicon 2652. In Fig. 26C, ion implantation forms source regions 2 6 60 and > and polar regions 2662. 27A to 27D are the process steps before the 25th or 26th drawing to form a NOR non-volatile memory cell array, each NOR non-volatile memory cell has a source region of lift and no Polar zone. In Fig. 27A, a dielectric material such as HDP oxide is deposited to cover the structure including the spacer sidewalls and the yttrium compound material 2430. In Fig. 27B, the excess oxide covering the yttrium compound material 2430 is removed, for example, by CMP, dip-back or etch back, while the remaining oxide 2772 surrounds the sidewall of the spacer. In Figure 27C, remove nitrogen

201218320 TW3I9IPA-D 石夕化合物材料2430。在第27D圖中，沈積額外閘極材料以形成閘極區2722。第28A至28D圖係為在第29或30圖以前之開始製程步驟，用以形成一 NAND非揮發性記憶體單元陣列，每個NAND非揮發性記憶體單元具有舉升之源極區與汲極區。在第28A圖中，例如ΟΝΟ層之介電材料與電荷結構2810係沈積於基板2800上。在第28Β圖中，^ :子如多晶矽之閘極材料，形成光刻結構，而殘留下多^，例 2820與ΟΝΟ 2812之堆疊。於第28C圖中，开？忐ΒΒ曰夕 Μ τ形成一間隙帶 2840。於第28D圖，蝕刻此間隙壁，而殘留下間隙辟側= 第29Α至29Β圖係為在第28圖以後之結束製裎牛驟，其使用磊晶矽以形成一 NAND非揮發性記憶體„„ 列，每個NAND非揮發性記憶體單元都具有舉升之源與汲極區。在第29A圖中，沈積磊晶矽2950。在第圖中，離子植入法形成源極區2960與沒極區2962。第30A至30C圖係為在第28圖以後之結束製_果驟，其使用多晶矽以形成一 NAND非揮發性記憶體單元^ 列，每個NAND非揮發性記憶體單元都具有舉升之源極區與汲極區。第30A至30C圖係為在第24圖以後且在第二圖以前之結束製程步驟，其使用多晶矽以形成在— 陣列中之一非揮發性記憶體單元之舉升之源極區與汲極區。在第30A圖中’沈積多晶矽3050。在第3〇b圖中，回蝕多晶矽以留下多晶矽3052。在第30C圖中，離子植人法形成源極區3060與汲極區3062。 20 201218320 一第31圖係為具有如揭露於此之變化通道區介面之例示的非揮發性記憶體積體電路之方塊圖。積體電路3150包含位於半導體基板上之非揮發性記，體單^之—記憶體陣列·。陣列遍之每個記憶體單元具有一變化通道區介面，例如凹入通道區，或舉升之 f極區歧極區。陣列3⑽之記憶體單元可能是個別的早兀，。其互相連接成一陣列，或互相連接成多重陣列。列解3101係連接至複數條字元線31〇2，其沿著記憶體陣列3100之列配置。行解碼器31〇3係連接至複數條位元線3104,其沿著記憶體陣列31〇〇之行配置。於匯流排聽上之，址係提供至行解碼器31〇3與列解碼器3ι〇ι。感測放大器與資料輸入結構31〇6係經由資料匯流排⑽而連接至行解碼器3103。資料係經由資料輸入線3111，而從積體電路3150上之輸入/輸出蜂，或從在積體電路⑽ 之内部或外部之其他資料源提供至方塊31〇6中之資料輸入結構。資料係經由資料輸出線3115而從.方塊上之感測放大器提供至積體電路315〇上之輸入/輸出蜂，或提供至在積體電路3150之内部或外部之其他資料目標。一偏壓配置狀態機器3109控制偏壓配置供應電壓3·(例如抹除確認與程式化確認電壓）之施加，以及用以程式化、抹除及讀取記憶體單元之配置。第32圖係為在源極區與沒極區之間具有一凹入通道之:非，發性記憶體單元之示意圖，藉以使下介電結構具有三層薄ΟΝΟ結構。此結構類似第丨圖之非揮發性記慎體單元，但是此介電結構108(在電荷儲存結構1〇8與通道 201218320201218320 TW3I9IPA-D Shi Xi Compound Material 2430. In Figure 27D, an additional gate material is deposited to form a gate region 2722. 28A to 28D are process steps starting before the 29th or 30th drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region and a lift Polar zone. In Fig. 28A, a dielectric material such as a germanium layer and a charge structure 2810 are deposited on the substrate 2800. In the 28th picture, ^: a gate material such as a polysilicon, forming a lithographic structure, and leaving a stack of more, for example, 2820 and ΟΝΟ 2812. In the picture 28C, open?忐ΒΒ曰夕 Μ τ forms a gap belt 2840. In Fig. 28D, the spacer is etched, and the residual gap is turned off = the 29th to 29th is the yak step after the 28th drawing, which uses the epitaxial germanium to form a NAND non-volatile memory. „„ Columns, each NAND non-volatile memory unit has a source of lift and a bungee zone. In Figure 29A, epitaxial germanium 2950 is deposited. In the figure, the ion implantation method forms a source region 2960 and a non-polar region 2962. 30A to 30C are diagrams ending at the end of Fig. 28, which use polysilicon to form a NAND non-volatile memory cell column, each NAND non-volatile memory cell having a source of lift Polar zone and bungee zone. 30A to 30C are process steps after FIG. 24 and before the second figure, which use polysilicon to form a source region and a drain of a non-volatile memory cell in the array. Area. Polycrystalline germanium 3050 is deposited in Fig. 30A. In Figure 3b, the polysilicon is etched back to leave the polysilicon 3052. In Fig. 30C, the ion implantation method forms the source region 3060 and the drain region 3062. 20 201218320 A 31 is a block diagram of a non-volatile memory volume circuit having an exemplary channel region as disclosed herein. The integrated circuit 3150 includes a non-volatile memory on the semiconductor substrate. Each of the memory cells of the array has a varying channel region interface, such as a recessed channel region, or a raised f-pole region. The memory cells of array 3 (10) may be individual early. They are interconnected in an array or interconnected into multiple arrays. The column solution 3101 is connected to a plurality of word line lines 31〇2 which are arranged along the memory array 3100. The row decoder 31〇3 is connected to a plurality of bit lines 3104 which are arranged along the line of the memory array 31. In the bus, the address is provided to the row decoder 31〇3 and the column decoder 3ι〇ι. The sense amplifier and data input structures 31〇6 are connected to the row decoder 3103 via the data bus (10). The data is supplied to the data input structure in block 31〇6 via the data input line 3111 from the input/output bee on the integrated circuit 3150 or from other sources internal or external to the integrated circuit (10). The data is supplied from the sense amplifier on the block to the input/output bee on the integrated circuit 315 via the data output line 3115, or to other data targets inside or outside the integrated circuit 3150. A bias configuration state machine 3109 controls the application of the bias configuration supply voltage 3 (e.g., erase verify and stylized verify voltage) and the configuration for programming, erasing, and reading the memory cells. Figure 32 is a schematic diagram of a non-emissive memory cell having a recessed channel between the source region and the non-polar region, whereby the lower dielectric structure has a three-layered thin crucible structure. This structure is similar to the non-volatile scrambling unit of the figure, but the dielectric structure 108 (in the charge storage structure 1〇8 and the channel 201218320

TW319IPA-D 區114之間）係被三層薄ΟΝΟ結構3208所置換。ΟΝΟ結構3208具有一小電洞隧穿阻絕位障，例如少於或等於大約4.5 eV，或最好是少於或等於大約1.9 eV。ΟΝΟ結構 3208之接近例示的厚度範圍係如下。關於下氧化物：<20 埃，5-20埃，或< 15埃。關於中間的氮化物：< 20埃或 10-20埃。關於上氧化物：<20埃或15-20埃。第32圖之記憶體單元之某些實施例係以SONONOS或能帶間隙工程 (BE)-SONOS表示。三層薄ΟΝΟ結構3208之各種不同的實施例之額外細節係揭露於美國專利申請案號 11/324,540，其於此併入作參考。第33圖係為具有舉升離半導體基板之源極區與汲極區之非揮發性記憶體單元之示意圖，藉以使下介電結構具有三層薄ΟΝΟ結構3208。综上所述，雖然本發明已以範例性實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍内，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。【圖式簡單說明】第1圖係為一非揮發性記憶體單元之示意圖，非揮發性記憶體單元在源極區與汲極區之間具有一凹入通道。第2圖係為一非揮發性記憶體單元之示意圖，非揮發性記憶體單元具有舉升離半導體基板之源極區與汲極區。第3Α圖係為在具有凹入通道之非揮發性記憶體單元 S- 22 201218320The TW319IPA-D zone 114 is replaced by a three-layer thin structure 3208. The germanium structure 3208 has a small hole tunneling stop barrier, such as less than or equal to about 4.5 eV, or preferably less than or equal to about 1.9 eV. The approximate thickness range of the ΟΝΟ structure 3208 is as follows. Regarding the lower oxide: < 20 angstroms, 5-20 angstroms, or < 15 angstroms. Regarding the intermediate nitride: < 20 angstroms or 10-20 angstroms. Regarding the upper oxide: < 20 angstroms or 15-20 angstroms. Some embodiments of the memory cell of Figure 32 are represented by SONONOS or Bandgap Engineering (BE)-SONOS. Additional details of various embodiments of the three-layered thin crucible structure 3208 are disclosed in U.S. Patent Application Serial No. 11/324,540, the disclosure of which is incorporated herein by reference. Figure 33 is a schematic illustration of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate, whereby the lower dielectric structure has a three-layered germanium structure 3208. In the above, the present invention has been described above by way of example embodiments, and is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a non-volatile memory cell having a concave channel between a source region and a drain region. Figure 2 is a schematic illustration of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate. The third diagram is a non-volatile memory unit with a recessed channel. S- 22 201218320

I VV 里 7 1 1 /~\_D 中，電子從閘極注入至電荷儲存結構之示意圖。第3B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，電子從閘極注入至電荷儲存結構之示意圖。第4A圖係為在具有凹入通道之非揮發性記憶體單元中，電子從基板注入至電荷儲存結構之示意圖。第4B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，電子從基板注入至電荷儲存結構之示意圖。第5A圖係為在具有凹入通道之非揮發性記憶體單元中，帶間（band-to-band)熱電子注入至電荷儲存結構之示意圖。第5B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，帶間熱電子注入至電荷儲存結構之示意圖。第6A圖係為在具有凹入通道之非揮發性記憶體單元中，通道熱電子注入至電荷儲存結構之示意圖。第6B圖係為在具有舉升之源極淤與汲極區之非揮發性記憶體單元中，通道熱電子注入至電荷儲存結構之示意圖。第7A圖係為在具有凹入通道之非揮發性記憶體單元中，基板熱電子注入至電荷儲存結構之示意圖。第7B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，基板熱電子注入至電荷儲存結構之示意圖。 23 201218320In I VV 7 1 1 /~\_D, a schematic diagram of electrons injected from the gate to the charge storage structure. Figure 3B is a schematic illustration of the injection of electrons from a gate into a charge storage structure in a non-volatile memory cell having raised source and drain regions. Figure 4A is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 4B is a schematic illustration of the injection of electrons from a substrate into a charge storage structure in a non-volatile memory cell having lifted source and drain regions. Figure 5A is a schematic illustration of band-to-band hot electron injection into a charge storage structure in a non-volatile memory cell having a recessed channel. Fig. 5B is a schematic view showing the injection of hot electrons between the bands into the charge storage structure in the nonvolatile memory unit having the lifted source region and the drain region. Figure 6A is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. Figure 6B is a schematic illustration of the channel hot electron injection into the charge storage structure in a non-volatile memory cell having lifted source and drain regions. Figure 7A is a schematic diagram of the substrate's hot electron injection into the charge storage structure in a non-volatile memory cell having a recessed channel. Fig. 7B is a schematic view showing the injection of hot electrons into the charge storage structure of the substrate in the non-volatile memory cell having the lifted source region and the drain region. 23 201218320

TW3191PA-D 第8A圖係為在具有凹入通道之非揮發性記憶體單元中，電洞從閘極注入至電荷儲存結構之示意圖。第8B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，電洞從閘極注入至電荷儲存結構之示意圖。第9A圖係為在具有凹入通道之非揮發性記憶體單元中，電洞從基板注入至電荷儲存結構之示意圖。第9B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，電洞從基板注入至電荷儲存結構之示意圖。第10A圖係為在具有凹入通道之非揮發性記憶體單元中，帶間熱電洞注入至電荷儲存結構之示意圖。第10B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，帶間熱電洞注入至電荷儲存結構之示意圖。第11A圖係為在具有凹入通道之非揮發性記憶體單元中，通道熱電洞注入至電荷儲存結構之示意圖。第11B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，通道熱電洞注入至電荷儲存結構之示意圖。第12A圖係為在具有凹入通道之非揮發性記憶體單元中，基板熱電洞注入至電荷儲存結構之示意圖。第12B圖係為在具有舉升之源極區與汲極區之非揮發性記憶體單元中，基板熱電洞注入至電荷儲存結構之示意圖。 24 _第】3a圖係為在具有凹凡中，用以讀取錯存於電〉道之非揮發性記憶體單向讀取操作之示意圖。。子、、告構之右倒之資料之—反第】3B圖係為在具有兴發性記憶體單元中，用以二源、極區與沒極區之非揮之資料之反向讀取操作之亍立R子於電荷儲存結構之右側铱不思圖。弟14A圖係為在具有凹、 2中’用以儲存位於電荷非揮發性記憶體單取操作之示意圖。構之左側之資料之反向讀第14B圖係為在具有舉并考:性5己憶體單元中，用以儲存也:、極區與汲極區之非揮資料之反向讀取操作之示意圖。；電荷儲存結構之左側之弟15Α圖係為在具有凹入、凡中’用以讀取儲存於 =道之非揮發性記憶體單間讀取操作之示意圖。何儲存結構之右側之資料之-帶第15B圖係為在且有發性記憶體單元令，用以讀極區與汲極區之非揮之貧料之—帶間讀取操土^電荷錯存結構之右側广聯位於電荷儲存非揮發性記憶體單取刼作之示意圖。之左側之資料之帶間讀第16B圖係為在|有兴發性記憶體單元中，用以館^位於:極區與沒極區之非揮資料之帶間讀取操作之示意圖。、電荷錯存結構之左側之第Π圖係具有—凹入通道之非揮發性記憶體單元 201218320TW3191PA-D Figure 8A is a schematic diagram of a hole injected into a charge storage structure from a gate in a non-volatile memory cell having a recessed channel. Figure 8B is a schematic illustration of the injection of a hole from a gate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. Figure 9A is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 9B is a schematic illustration of the injection of a hole from a substrate into a charge storage structure in a non-volatile memory cell having a lifted source region and a drain region. Figure 10A is a schematic illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having recessed channels. Fig. 10B is an illustration of the injection of inter-band thermoelectric holes into a charge storage structure in a non-volatile memory cell having a raised source region and a drain region. Figure 11A is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having recessed channels. Figure 11B is a schematic illustration of the injection of channel thermowells into a charge storage structure in a non-volatile memory cell having raised source and drain regions. Fig. 12A is a schematic view showing the injection of a substrate thermowell into a charge storage structure in a non-volatile memory cell having a recessed channel. Figure 12B is a schematic illustration of the implantation of a substrate thermowell into a charge storage structure in a non-volatile memory cell having raised source and drain regions. 24 _第图3a is a schematic diagram of a non-volatile memory unidirectional read operation for reading inaccurate memory. . The sub-, the right-handed data of the confession - the anti-theft] 3B picture is the reverse reading operation of the non-swing data of the two sources, the polar region and the immersed region in the singular memory unit It is not the case that the R is on the right side of the charge storage structure. Figure 14A is a schematic diagram of the operation of storing a non-volatile memory in a recessed, 2'. The reverse reading of the data on the left side of the structure is shown in Fig. 14B as a reverse reading operation for storing non-volatile data in the polar region and the bungee region. Schematic diagram. The left side of the charge storage structure is a schematic diagram of a read operation for reading a non-volatile memory stored in the = channel with a recess. The data on the right side of the storage structure - with the 15B picture is the presence and absence of the memory unit command, used to read the non-volatile material of the polar region and the bungee region - read the soil The right side of the storage structure is located in the schematic diagram of the charge storage non-volatile memory. Inter-band reading of the data on the left side Fig. 16B is a schematic diagram of the inter-band reading operation of the non-volatile data in the polar region and the non-polar region in the | The left side of the charge-dissipating structure has a non-volatile memory unit with a concave channel. 201218320

TW3191PA-D 陣列之製造流程圖，其顯示第19至23圖之製程步驟之各種可能的組合。第18A圖係具有舉升之源極區與汲極區之一 NOR非揮發性記憶體單元陣列之製造流程圖，其顯示第24至27 圖之製程步驟之各種可能的組合。第18B圖係具有舉升之源極區與汲極區之一 NAND 非揮發性記憶體單元陣列之製造流程圖，其顯示第28至 30圖之製程步驟之各種可能的組合。第19A至19C圖係為在第22或23圖之前，在具有凹入通道之非揮發性記憶體單元中，用以形成一溝槽之製程步驟。第20A至20E圖係為在第22或23圖以前，在非揮發性記憶體單元中形成一溝槽之前，用以縮小一閘極長度之製程步驟。第21A至21E圖係為在第22或23圖以前，在非揮發性記憶體單元中形成一溝槽之前，用以擴大一閘極長度之製程步驟。第22A至22K圖係為在第19、20或21圖以後之結束製程步驟，用以形成一 NOR非揮發性記憶體單元陣列，每個NOR非揮發性記憶體單元位於一溝槽中，以使每個非揮發性記憶體單元具有一凹入通道。第23A至23E圖係為在第19、20或21圖以後之結束製程步驟，用以形成一 NAND非揮發性記憶體單元陣列，每個NAND非揮發性記憶體單元位於一溝槽中，以使每個非揮發性記憶體單元具有一凹入通道。 26 201218320 1J l / 丨丨第24A至24D圖係為在第25或26圖以前之開始製程步驟，用以形成在一 NOR陣列中之一非揮發性記憶體單元之舉升之源極區與汲極區。第25A至25B圖係為在第24圖以後且在第27圖以前之結束製程步驟，其使用磊晶矽以形成在一 NOR陣列中之一非揮發性記憶體單元之舉升之源極區與汲極區。第26A至26C圖係在第24圖以後且在第27圖以前之結束製程步驟，其使用多晶矽以形成在一 NOR陣列中之一非揮發性記憶體單元之舉升之源極與汲極區。第27A至27D圖係在第25或26圖以前之結束製程步驟，用以形成一 NOR非揮發性記憶體單元陣列，每個 NOR非揮發性記憶體單元都具有舉升之源極區與汲極區。第28A至28D圖係為在第29或30圖以前之開始製程步驟，用以形成一 NAND非揮發性記憶體單元陣列，每個NAND非揮發性記憶體單元具有舉升之源極區與汲極區。第29A至29B圖係為在第28圖以後之結束製程步驟，其使用磊晶矽以形成一 NAND非揮發性記憶體單元陣列，每個NAND非揮發性記憶體單元都具有舉升之源極區與没極區。第30A至30C圖係為在第28圖以後之結束製程步驟，其使用多晶矽以形成一 NAND非揮發性記憶體單元陣列，每個NAND非揮發性記憶體單元都具有舉升之源極區與汲極區。第31圖係為具有如揭露於此之變化通道區介面之例 27 201218320A manufacturing flow diagram of the TW3191PA-D array showing various possible combinations of process steps of Figures 19-23. Figure 18A is a manufacturing flow diagram of a NOR non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 24-27. Figure 18B is a manufacturing flow diagram of a NAND non-volatile memory cell array having one of the source and drain regions of the lift, showing various possible combinations of the process steps of Figures 28-30. 19A to 19C are process steps for forming a trench in a non-volatile memory cell having a recessed channel before the 22nd or 23rd. 20A to 20E are process steps for reducing the length of a gate before forming a trench in the non-volatile memory cell before the 22nd or 23rd. 21A to 21E are process steps for expanding a gate length before forming a trench in the non-volatile memory cell before the 22nd or 23rd. 22A to 22K are process steps after the 19th, 20th or 21th step to form a NOR non-volatile memory cell array, each NOR non-volatile memory cell is located in a trench, Each non-volatile memory cell is provided with a recessed channel. 23A to 23E are process steps after the 19th, 20th or 21th step to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell is located in a trench, Each non-volatile memory cell is provided with a recessed channel. 26 201218320 1J l / 丨丨 24A to 24D are the process steps beginning before the 25th or 26th figure to form the source region of a non-volatile memory cell in a NOR array. Bungee area. 25A to 25B are process steps after FIG. 24 and before FIG. 27, which use epitaxial germanium to form a source region of a non-volatile memory cell in a NOR array. With the bungee area. 26A to 26C are process steps after Fig. 24 and before Fig. 27, which use polysilicon to form the source and drain regions of a non-volatile memory cell in a NOR array. . 27A through 27D are process steps before the 25th or 26th drawing to form a NOR non-volatile memory cell array, each NOR non-volatile memory cell having a source region and a lift Polar zone. 28A to 28D are process steps starting before the 29th or 30th drawing to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region and a lift Polar zone. 29A to 29B are process steps after the 28th drawing, which use epitaxial germanium to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source of lift District and Wuji District. 30A to 30C are process steps ending after FIG. 28, which use polysilicon to form a NAND non-volatile memory cell array, each NAND non-volatile memory cell having a source region of lift Bungee area. Figure 31 is an example of a channel region interface as disclosed herein.

TW319IPA-D 示的非揮發性記憶體積體電路之方塊圖。第32圖係為在源極區與汲極區之間具有一凹入通道之一非揮發性記憶體單元之示意圖，藉以使下介電結構具有三層薄ΟΝΟ結構。第33圖係為具有舉升離半導體基板之源極區與汲極區之非揮發性記憶體單元之示意圖，藉以使下介電結構具有三層薄ΟΝΟ結構。【主要元件符號說明】 102 > 302 、 402 、 502 、 602 、 702 、 802 、 902 、 1002 、 1102 、 1202 、 1302 、 1402 、 1502 、 1602 、 2264 、 2722 :閘極/閘極區 104 ：介電結構 106 ：電荷儲存結構 108 ：電荷儲存結構/介電結構 110、210、304、404、804、904、1204、2280、2380、 2560、2660、2960、3060 :源極/源極區 112、212、306、406、806、906、1206、2282、2382、 2562、2662、2962、3062 :汲極區/沒極 114、214 :通道區/通道 116 :源極與汲極區 118 :介面 120 :接面深度 122 :本體/本體區 208 :介電結構 28 201218320Block diagram of the non-volatile memory volume circuit shown in TW319IPA-D. Figure 32 is a schematic illustration of a non-volatile memory cell having a recessed channel between the source region and the drain region, whereby the lower dielectric structure has a three-layered germanium structure. Figure 33 is a schematic diagram of a non-volatile memory cell having a source region and a drain region lifted off the semiconductor substrate, whereby the lower dielectric structure has a three-layered thin crucible structure. [Major component symbol description] 102 > 302, 402, 502, 602, 702, 802, 902, 1002, 1102, 1202, 1302, 1402, 1502, 1602, 2264, 2722: gate/gate region 104: Electrical structure 106: charge storage structure 108: charge storage structure/dielectric structure 110, 210, 304, 404, 804, 904, 1204, 2280, 2380, 2560, 2660, 2960, 3060: source/source region 112, 212, 306, 406, 806, 906, 1206, 2282, 2382, 2562, 2662, 2962, 3062: bungee region/dipole 114, 214: channel region/channel 116: source and drain region 118: interface 120 : junction depth 122: body/body region 208: dielectric structure 28 201218320

1 vv j 里；7 里 i r\-D 218 ··介面 220 :接面深度 308、408、808、908、1208 :本體區 504、1104 : p+型源極區 506、1106 : p+型没極區 508、708、1108 : N 型本體區 604、704、1004、1304、1404、1504、1604 : n+型源極區 606、706、1006、1306、1406、1506、1606 : n+型及極區 608、1008、1308、1408、1508、1608 : P 型本體區 710、1210 :井區 1900、2400、2800 :基板 1910、1912、2112、2290、2772 :氧化物 1922 :光阻 1930、1932、2232 :溝槽 2040、2042、2440、2840 :間隙壁 2250 :介電材料與電荷儲存結構 2260、2262 :閘極材料 2270、2272 :介電材料 2410 :介電材料與電荷儲存結構 2412 ： ΟΝΟ 2420、2650、2652、2820、3050、3052 :多晶矽 2430 : SiN/氮石夕化合物材料 2442、2842 .間隙壁側壁 29 2012183201 vv j; 7 ri ir\-D 218 · interface 220: junction depth 308, 408, 808, 908, 1208: body region 504, 1104: p + source region 506, 1106: p + type immersion region 508, 708, 1108: N-type body regions 604, 704, 1004, 1304, 1404, 1504, 1604: n+-type source regions 606, 706, 1006, 1306, 1406, 1506, 1606: n+-type and polar regions 608, 1008, 1308, 1408, 1508, 1608: P-type body regions 710, 1210: well regions 1900, 2400, 2800: substrates 1910, 1912, 2112, 2290, 2772: oxide 1922: photoresist 1930, 1932, 2232: trench Slots 2040, 2042, 2440, 2840: spacer 2250: dielectric material and charge storage structure 2260, 2262: gate material 2270, 2272: dielectric material 2410: dielectric material and charge storage structure 2412: ΟΝΟ 2420, 2650, 2652, 2820, 3050, 3052: polycrystalline germanium 2430: SiN/nitrogen compound material 2442, 2842. spacer sidewall 29 201218320

TW3191PA-D 2550、2950 :磊晶矽 2810 :電荷儲存結構 2812 ： ΟΝΟ 3100 :記憶體陣列 3101 :列解碼器 3102 :字線 3103 :行解碼器 3104 :位元線 3105 :匯流排 3106 :感測放大器與資料輸入結構 3107 :資料匯流排 3108 :偏壓配置供應電壓 3109 :偏壓配置狀態機 3111 :資料輸入線 3115 :資料輸出線 3150 :積體電路 3208 : ΟΝΟ 結構 30TW3191PA-D 2550, 2950: epitaxial germanium 2810: charge storage structure 2812: ΟΝΟ 3100: memory array 3101: column decoder 3102: word line 3103: row decoder 3104: bit line 3105: bus 3106: sensing Amplifier and data input structure 3107: data bus 3108: bias configuration supply voltage 3109: bias configuration state machine 3111: data input line 3115: data output line 3150: integrated circuit 3208: ΟΝΟ structure 30

Claims

201218320 七、申請專利範圍：種特發性記㈣單元積體電路，咖單元積體電4::==控制由該非揮㈣二源極區與一汲極區，以—通道區分離；以及個或多個介電結構’至少部分位於該與该通道區之間，且至少部分位啫存、，'。構極電壓源之間，其中： …厂，何：存結構與一間道區^Γ分離該—個或多個介電結構之—部分與該通該介面ί之—第—端結束於該源極區之中間部分，且 1面之一第二端結束於該沒極區之中間部分；其中該介面之該第一端結束於該源極 71 0亥介面之該第二端結束於該沒極區之中間部八. 揮發緣與汲極區之上邊緣“該非成-線。％體電路之-基板之上邊緣實質上排細彻，其中該電荷 _.二=:='項_^ 八4·如巾請專利範圍第1項所述之電路，其中至少 ς位於該電荷捕捉結構與該通道區之間之該介電結構°包一下氧化矽層； ―中間氮化矽層’位於該下氧化矽層上； 31 201218320 TW3I9IPA-D 一上氧化矽層，位於該中間氮化矽層上 5.如申請專利範圍第4項所述之電路，化矽層具有大約5至20埃之厚度。 ^ 6.如申請專利範圍第4項所述之電路，氮化矽層具有大約10至20埃之厚度。 7. 如申請專利範圍第4項所述之電路，化矽層具有大約15至2〇埃之厚度。 8. 如申請專利範圍第4項所述之電路，結構之電洞隧穿阻絕位障少於或等於19 。其中該下氧其中該中間其中該上氧其中該介電 32201218320 VII, the scope of application for patents: a special feature (4) unit integrated circuit, the unit of electricity 4:: = = control by the non-wing (four) two source regions and a drain region, separated by - channel region; One or more dielectric structures 'at least partially located between the channel region and at least partially located, '. Between the constituent voltage sources, wherein: ..., the factory: the storage structure and a road area, the separation of the one or more dielectric structures - the portion and the interface - the end - the end a middle portion of the source region, and a second end of the one end ends in a middle portion of the non-polar region; wherein the first end of the interface ends at the second end of the source 71 The middle part of the immersion zone is eight. The edge of the volatility and the upper edge of the bungee zone "this non-form-line. The upper body circuit - the upper edge of the substrate is substantially fine, where the charge _. two =: = 'item _ The circuit of claim 1, wherein at least the dielectric structure between the charge trapping structure and the channel region comprises a layer of ruthenium oxide; Located on the lower yttrium oxide layer; 31 201218320 TW3I9IPA-D an upper yttrium oxide layer on the intermediate tantalum nitride layer 5. The circuit of claim 4, the ruthenium layer has about 5 to 20 angstroms Thickness. ^ 6. The circuit described in claim 4, the tantalum nitride layer has about 10 The thickness of 20 angstroms. 7. The circuit according to claim 4, wherein the ruthenium layer has a thickness of about 15 to 2 angstroms. 8. The circuit of the structure of claim 4, the structure of the hole The tunneling barrier is less than or equal to 19. wherein the oxygen is in the middle of which the oxygen is present, wherein the dielectric 32