TW201214515A - System and method for manufacturing three dimensional integrated circuit - Google Patents

Abstract

System and method for manufacturing three-dimensional integrated circuits are disclosed. In one embodiment, the method includes providing an imaging writer system that includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays, receiving mask data to be written to one or more layers of the three-dimensional integrated circuit, processing the mask data to form a plurality of partitioned mask data patterns corresponding to the one or more layers of the three-dimensional integrated circuit, assigning one or more SLM imaging units to handle each of the partitioned mask data pattern, and controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the one or more layers of the three-dimensional integrated circuits in parallel. The method of assigning performs at least one of scaling, alignment, inter-ocular displacement, rotational factor, or substrate deformation correction.

Description

201214515 六、發明說明： 【發明所屬之技術領域】 本發明涉及積體電路之製造。#言之’本發明侧於一種製 二維(3-D)積體電路之糸統及方法。 本申凊案為2009年5月29日提出申請之第12/475,114號 美國正式專射請案之部分延，並依美國專利法第12〇條主 張該正式專利申請案之優先權。該第12/475，114號錢正式專利 申請案主張麵年12月17日提出申請之第12/337，剛號美國 ，式專利申請案之優先權，而該第12/33?，5()4號美國正式專利申 請案則主張2_年9月23日提出申請之第61錢伽號美國臨 時專利中請案「光學成像寫人系統」之優先權。本中請案亦主張 2010年9月3日提出申請之第61/379, 732號美國臨時專利申請 案「製造三維频電路H缺方法」之優先權。 申請案之全勒容，在灿_之方式併人本文。 【先前技術】 受惠於半導體積體電路⑽技術之突飛猛進，動態矩陣液 晶電視（A聽TV)及電腦顯示器之製程已有長足進步。近年 來’液晶電視及電腦顯示器之尺寸不斷放大，但價格則逐漸大眾 化。 就半導體1C而言，各技術世代係由電路設計規則中之關鍵 尺寸㈣加以㈣。隨著技術世代之演進，新世代K之圖徵關 201214515 鍵尺寸目標值逐漸縮小’誤差容許度亦更趨嚴格。但就平板顯示 器（FH))而言’各技術世代係依照製程中所用基板之實體尺寸加 以分類。例如’FPD分別於2005、2007及2009年進入第六代（G6)、 第八代（G8)及第十代（G10)’其對應之基板尺寸（公厘X公厘） 分別為 1500x1800、2160x2460 及 2880x3080。 無淪是半導體1C或FPD基板，其微影製程所面臨之挑戰均 為如何一方面加大產品之尺寸，一方面使產品平價化；但兩者之 製程卻戴然不同。1C業界之一主要挑戰，係於直徑300公厘之晶 圓上形成具有小關鍵尺寸之圖徵，其目標為儘可能提高電晶體之 女裝數畺，俾使相同大小之晶片具有更佳功能。然而，FpD業界 之一主要挑戰係儘可能加大可處理之矩形基板尺寸，因為生產線 上所能處理之FPD基板愈大，贿能製造之電視或顯示器愈大， 且成本愈低。為提高效能，__般液晶電視及顯示器之設計均採用 較為複雜之薄膜電晶體⑽），但TFT之關鍵尺寸目標值仍停留 在相同，規格範_。從某-觀點而言，FpD製程之—主要挑戰， 係各世代之單位時間產出量均具有合理之成本效益，而其 :一Γ重ί之考量因素係令製程良率達到獲利水準’同時維持適 菖之製程窗口。 習知用於製造FPD之微影技術係由製造ic之微 =率:ΓίΓ用之微影曝光卫具大多為步進式及/或掃描ΐ 一二、、·，其中從光罩至基板之投影比例共有二比一（縮小）鱼 一比一兩種。為將光罩_投影至基板，光罩本身韻依可接受 201214515 之關鍵尺寸規格製造。FPD之光罩製程與半導體IC之光軍製程類 似，不同之處在於··製造半導體ic所用之光罩尺寸約為每邊^ 公厘（約6英吋），而製造FPD所用之光罩，其每邊尺寸在一實 例十可為祕每邊尺寸之八倍左右，即每邊超過一公尺。 睛參閱第la圖’圖情示一用以將光罩圖案掃描至FpD基 板之投影曝光工具習知_。贿構所狀料光駐要為高^ 短弧汞（Hg)燈。入射之照明光經由反射鏡1〇2反射後，依序通 過光罩104及投影透鏡1〇6，最後到達FpD基板1〇8。然而，若欲 以第la®所示之習知鮮式曝光工具架構為新世代之_進行微 〜製知，必須解決光罩尺寸日益加大之問題。以第八代卿為例， 其光罩尺柏為麵公厘x 紐，㈣八代餘之面麵 為其四倍。由於TFT之關鍵尺寸規格在3微米删之範圍内，如 何在每邊超過兩公尺之第八代基板上控制m之關鍵尺寸實乃一 大挑戰；相較於在直徑3GG公厘之梦晶圓上微影製印先進ic圖案 並控，其規格，前者難度更高。FPD f界所須解決之問題，係如 何以符。成本效狀方式建造出翻於新世代_之光罩式曝光 -同時保留可接叉之微影製程能力區限（又稱製程窗口）。 若欲減少FPD曝光__鍵尺寸不__致之情形，方法之一 係使用^曝光法’其巾標稱曝缝係衫個依適纽例分配之 曝光刀里所域’而每—曝光分量則制親波長之照明，並搭 配對應之郷魏喊成掃缺錢。此祕光工錢包含多於 -個投影親，但僅配有單―照縣源，其原因在於必須使用以 201214515 千瓦⑽）計之高輸出功率娜汞燈照明光源。至於選擇曝光波 長之方式，雜絲處絲射之縣鏡。在—實财，此多波 長曝光法可降低第八代基板上關鍵尺寸均— 影響，故可使雜倾之透毅_讀。 ^之負面 在使用多波長曝光法時’必須為光罩本身訂定較嚴格之關鍵 尺寸目標值及驗尺寸均—度。在_實例中，TFT光罩之關鍵尺 寸誤差谷許值小於⑽奈米，此數值遠小於光罩_尺寸標稱目 標值3微麵需之縣容紐。這躲使用财曝光工具架構的 製程方式而言，較易於掌控FPD微影製程之製程窗口。然而，對 FPD光罩_尺寸規格之要求愈嚴，將使原本即所費不貲之光罩 組愈加昂貴。在某些情況下，為第八代卿製作關鍵光罩之成本 極高，且備貨期甚長。 ★習知方法之另-問題在於，姻大型光罩時不易進行瑕絲 度管控。以大型光罩進行乡魏光之郷製辦，即使—開始使 用全無瑕紅鮮’驗仍有可㈣猶害之贼。若製程有產 生瑕狀虞’ ^但良率將受鄉響，料成本亦隨之提高。 第lb圖綠示習知曝光工具之另一種架構。如帛化圖所示， 該曝光工具包含光源11G、第-投影透鏡112、光罩114、第二投 ’5V透鏡116、晶圓118及晶圓平台⑽。吾人可控制光源11〇，使 其光線經由第一投影透鏡112射至光罩114，其中該光罩含有待 成像於晶圓118之圖案。部分光線將被光罩114阻擔，而部分光 線則可通過光罩114並穿透第二投影透鏡116，致使晶圓⑽曝 201214515 光。通過光罩114之光線將使晶圓ία之蚊區域曝光，從而產 生一組對應於光罩122上所形成之冗設計圖案之圖案影像。 請注意，該晶圓係固定於晶圓平台⑽上，而該晶圓平台則 可在吾人之控制下沿箭頭所示方向移動。在一習知步進系統中， 光源11G可為藍色可見光或近紫外光，第—投影透鏡112、光罩 114與第二投影透鏡116係固定不動，至於晶目118及用以固定 該晶圓之晶圓平台120則可移動，俾使晶圓118上之不同區域曝 光。此步進祕可驗製造解析精度達丨至3微米之設計圖案， 例如可製造小尺寸光罩、發光二極體⑽），以及***與更早 世代之平板顯示器。在-習知掃描系統中，光源11()、第一投影 透鏡112及第二投影透鏡116均固定不動，而光罩114、晶圓ιΐ8 及用以固定該晶圓之平台則均可㈣，以便使晶圓ιΐ8 上之不_域曝光。相較於步進系統，掃描系統處理大尺寸光罩 及平板顯示ϋ之效雜高，但其價格雜高。掃描祕大多用於 製造基板甚大之第六代或更新世代之平板顯示器。 第lc至le _示習知曝光工具狀光罩之多種方式，以及 習知曝光工具如何使鮮對準以進行曝光。在第&圖中係令光罩 130與基板晶圓132保持接觸，故此系統—般稱為接觸式對準系 統。在第M圖中’光罩13G係狀於鄰近基板晶圓132之位置， ^此系a㈣為接近式對準祕。f知接觸式對㈣統與接近 準系統大多用於製造印刷電路板、觸麵板(25至40微求）、 發光二極體（3至5微米）及太陽能板（> 100微米），至於接觸 201214515 式對準系統與接近式對㈣狀缺闕包減法處理高解析度之 設計圖案、翹曲之晶圓或大於4吋之基板。 第1e圖繪示一習知投影式對準系統，其於光罩130與基板 晶圓132之間另設有一投影透鏡131。此系統大多用於製造$至 10微米之電路。此種投影式對準系統較適合以大尺寸之光罩製造 平板顯示器之彩色濾、光片，但大尺寸光罩之價格甚高。因此^若 無法接受較S之群成本’ _投影式鮮彡賴造印刷電路板 及發光二極體便無成本效益可言。 第2圖繪示製造光罩之曝光工具之習知架構。在此曝 光工具架構中，射向分光鏡2〇4之照明光2〇2將局部反射並穿過 傅利葉透鏡208以照亮空間光調變器（SLM) 2G6。此成像光經反 射後’依序通過傅利葉透鏡2〇8、分光鏡2〇4、傅利葉濾光鏡21〇 及縮小透鏡212，最後到達空白光罩基板216。光罩資料214係以 電子方式傳送至空間光調變1! 2G6，咖設定微鏡像素。反射光 在空白光罩基板2i6上產生亮點，而空白光罩基板216上無反射 光處則形成暗點。藉由控制及編排反射光，即可將鮮資料圖案 轉移至空白光罩基板216上。 八 請注意，在此祕光X具架射，綱光⑽崎曲以便垂 ^射入空間_變11。此折蚊絲與曝光絲路徑形成τ 字形。此娜光纟統除使用高神之照明光料，亦須使用具有 南縮小比率之投影透鏡，藉以提高鮮職寫人之準確度與精 度。基本上’透鏡縮小比率約為100比1。使用具有高縮小比率 201214515 之技〜透鏡時’單—空間光調變器晶片所產生之曝光區域甚小。 工間光调變器之晶片實體尺寸約為一公分，經縮小1〇〇倍後，空 間光調變器之寫入區域約為100微米。若欲以此極小之寫入區域 寫完-”第人代FPD光罩’其所f時間甚長。 另^知方法係以多道雷射光束循序照射空間光調變器。此 ^道光束係由單—照明雷射光源經旋轉式多面反射鏡反射而成。 夕道照明光束可在特定時制產生多重曝光，因而提高光罩寫入 速度。在一實例中，以此方法寫完一片第八代FPD光罩約需20小 時°由於S人時間偏長，控麵H並維持其機械及電子運作之成 本亦隨之增加，進而拉高其FPD鮮成品之成本。若將此曝光工 具應用於第十代或更新世代之FPD光罩，則製造成本恐將更高。 為降低製作少量·時之光罩成本，另—習知方法所用之曝 紅具架構係以_之如光靖器為光I。此枝係將光罩圖 案讀入空間光調變财’使其顯現所s之光罩圖案，如此一來便 賴使用實體光罩。換言之，此咖郎光機器之功能可取代 貫體光罩’從而節省光罩縣。祕紅具之賴而言，此方法 基本上與鮮式投料統並無二致。細，若與實縣罩相比， 此空間光調變器光罩之影像品質較低，不符合™製程之圖案規 格要求。 第6, 906, 779號美國專利（以下簡稱第，779號專利）則揭露 另一種製造糾ϋ之習知方法，财法係_—雜式製程對網 狀基板進行同步微影曝光。簡言之，第’?79號專利係將光罩圖案 10 201214515 曝光至成捲之基板上。另一種習知之捲軸式微影製程可參見Se Hyun Ahn等人之專文「用於撓性塑膠基板之高速捲軸式奈米壓模 k影術（Hight-Speed Roll-to-Roll) Nanoimprint Lithography on Flexible Plastic Substrates)」（广取命Μ β Co. KGaA，¥einhew’ r 先進材料（AdvancedMateria】s) j，2{)他， 20，第2044-2049頁）（以下簡稱Ahn專文）。 然而，上述兩種習知方法限用預定尺寸之光罩，而光罩尺寸 則實質限縮可製造之撓性顯示器之大小。第，779號專利及Ahn專 文所述驾知方法之另一問題在於，若欲達到適當之微影製印效 果曝光過程中必須將成捲之基板拉平。如此一來，基板表面之 平整度將遜於-般液晶電視縣姻之硬式賴基板。應用此種 光罩式微影技術時，焦深（D0F)會因基板表面不平而受限，因 此上述1知方法恐難以开)成關鍵尺寸為5微米或以下之τα圖 徵。若欲使TFT顯示器之解析度達一定水準，則m光罩圖徵之 關鍵尺寸須為3微米左右。 在製造未來世代’時所可能面臨之上述各種挑戰，乃肇因 於FPD業界亟須降低成本，而主要動機之一，係令新世代產品之 製程具有成本效益。微影技術賴—方轉持產出效率，一方面 確保產品良率逐代提升。欲達此目的，必須加大微影製程之製程 窗口，並減少製程碱，以目應日益增大之卿基板。—如前述， 現有曝缸具架構之缺點甚多，其中—主要缺點係與光罩之使用 有關，亦即光罩尺寸過大，導致光罩之製造不符成本效益。由於 11 201214515 光罩尺寸勢必_加大錢献未麵代 【發明内容】 於幻以在微影製財將光料料圖案施用 激= 法。在—實施财，本發明之成«統包含複 3 變器（⑽成像單元，其中各灿成像單元包含- 或夕個照明光源、一杏多個斜進 鑛❹做影歧及複數 〜t 兄/L 光線從該—或多個照明光源投射至對應之 β/_夕^〜透1%。此成像㈣尚包含—肋控倾等SLM成像 ==’該_可在各SLM _元__入一 基版之U純程中，分別織轉SLM成像單元。 貫知例中，種製造—三維積體電路之方法包含下列 =LM=:具有複數個則成像單元之成像寫入系統，其中該 穑㈣❹Γ疋係排列成一或多個平行陣列；接收待寫入該三維 傭庫;或多層之光罩資料；處理該光罩資料，俾形成複數 輯應於_賴物彻辦料圖案；指 2 一或多個SLM成像單元負責處理各分區光罩資料圖幸；以及控 成像單元，俾將該等分區光罩資料圖案精寫入該三 維積體電路之該一或多層。 201214515 區光罩資__二：!===，對該等分 2光罩資料圖案進行對準狀態修正， 荦二 見點間距修正，其中各分區光罩資料圖 2刀以罩進行轉_子修正，其料分區光罩資料 圖案均有-對應之轉動因子修正動作；以及根據像 ==光罩資料圖案進行基板變形修正，其二 罩資料圖案均有―對應之基板變形修正動作。控制該等SLM成像 早几之步驟包含：針對各SLM成像單元，使其對應之分區光罩資 料圖案獨立於該成像寫人系統中其他SLM成像單元而曝光。 、在另-實施例中，-種在一印刷電路板（PCB)上平行製造 複圖案之方法包含下列步驟：提供一具有複數個SLM成 像單元之成像寫入系統，其中該等SLM成像單元係排列成一或多 個平行_ ;提供—已劃分出複數區域之印刷電路板，其中各區 域均包含-待製造之設計圖案；接收待寫人該印刷電路板該複數 區域之光m處職鮮請，俾職減個對應於該印刷 。電路板該複數區域之分區縣㈣贿；指派―❹個SLM成像 單元負責處理各分區光罩資料_，其情述指派包含至少執行 13 201214515 下列其中之—：縮放比例修正、對準狀態修正、視關距修正、 轉動因子修正與基板翹曲修正；以及控制該等slm成像單元，俾 將該等分區光罩資料_平行寫人該印刷電路板之職數區域。 在另-實施财’—種_部分晶圓之製造方法包含下列步 驟··提供:具有複數個SLM成像單元之成像寫人系統，其中該等 SLM成像單元係制成—❹辨行提供—或多個待加工 製造之部分晶圓；接收光罩資料，其中該光罩係供寫入該一 =多個部分晶圓之基板；處理該光罩㈣以形成複數個分區光罩 貧料_，該等分區鮮資料圖㈣對應於該—或多個部分晶圓 之基板；指派—或多個SLM成像單元負減理各分區光罩資料圖 案’其中所述指派包含至少執行下列其中之一：縮放比例修正、 對準狀態修正、視關轉正、轉_子修正與基她曲修正； 以及控制該等SLM成像單元，俾將該等分區光軍資料圖案平行寫 入該一或多個部分晶圓之基板。 ‘”’ 在另一實施例中，一種平行製造複數個發光二極體（LED) 之方法包含下列步驟：提供—具有複數個SLM成像單元之成像寫 入系統’其中該等SLM成像單元係排列成—或多個平行陣列；提 供一或多個對應於該等待製造之LED之基板；接收光罩資料其 中該光罩資料係供寫人該—或多個對應於該等咖之基板；處理 該光罩資料以形成概個分區光罩㈣随，料分區光罩 圖，係對應於料LED之該-❹個基板；指派—❹個⑽成 像早兀負責處理各分區光單資料圖案；以及控制該等μ成像單 201214515 元，俾將該等分區光罩資料圖案平行寫入該等LE：D之該一或多個 基板。 處理該光罩資料之步驟至少包含下列其中之一：處理該光罩 資料以形成複數個分區光罩資料圖案，其中該等分區光罩資料圖 案係對應於該等led之該一或多個基板，且為相同之設計；以及 處理該光罩資料以形成複數個分區光罩資料圖案，其中該等分區 光罩負料_係對應於該等led之該-或多個基板，且為不同: »又计。控制s亥專SLM成像單元之步驟至少包含下列其中之一债 測各SLM成像單元相關基板上各局部區域之變形狀況，並根據各 基板上各局部區域之變形狀況調整對應SLM成像單元之焦點；偵 測各SLM成像單元相關基板上各局部區域之轉動誤差，從而決定 對應分區鮮賴_之轉祕正因子，並將轉轉祕正因子 應用於各SLM絲單元糊基板之各局部區域所對應之分區光罩 資料圖案；以及_各SLM成像單元侧基板上各局部區域因基 板變形所造成之_扭曲，從而決定對應分區光料料圖案之圖 案修正因子，並將該等_修正因子細於各Μ成像單元相關 基板之各局部區域所對應之分區光罩資料圖案。 在另-實施例巾’-種執行自動光學檢查之方法包含下列步 驟：提供-具有複數個SLM成像單元之成像寫人系統，直中該等 SLM成像單元係排列成一或多個平行陣列；提供一或多個待檢查 之圖案化基板；將該-或多個_化基板劃分為複數區域；接收 對應於該-或多麵案化基板之參考光罩資料；處理該參考光罩 201214515 資料以形成複數個分區光罩資料圖案，該等分區光罩資料圖案係 對應於該一或多個圖案化基板之該複數區域；利用該等SLM成像 單元擷取該一或多個圖案化基板該複數區域之資訊；以對應之複 數個分區光罩資料圖案為參照聽，分析該複數輯之資訊，從 而產生檢查結果；以及將該等檢查結果儲存於一記憶體裝置中。 分析該複數區域之資訊之步驟包含：檢查該一或多個圖案化 基板之該複數區域與對應之複數個分區光罩資料圖案是否有所差 異，以及若在該一或多個圖案化基板之一或多個區域中找出差 異，則在該-或多侧案化基板中辨識出該—或多個區域以便修 復。 ’ 檢查差異之步·少包含下列其中之—：輯應之複數個分 區光罩禮圖案為參照縣，檢錢—或多侧案化基板之該複 數區域是否出現基姻案扭曲，若在該—衫個_化基板之一 或多個區域中發現基板圖案扭曲，則在該—或多個圖案化基板中 辨識出該-或多個區域以便修復；檢查該—或多個圖案化基板之 該複數輯是奸含^應㈣在基板上之㈣電路元件，若在該 或夕個圖案化基板之一或多個區域中發現不應出現之額外電路 元件，則在該-或多個_化基板中辨識出該—或多個區域以便 修復；檢錢-或多侧案化基板之顧域衫缺漏本應出 現在基板上之電路元件，若在該—或多侧案化基板之一或多個 區域中發現缺漏之電路元件，則在該—❹侧案化基板中辨識 出該-或多個區域以便修復；以及檢查該—或多侧案化基板之 201214515 該複數區域衫出現外來雜而不當影響酸，若在該—或多個 圖案化基板之-或多個區域發現外來微粒，則在該—或多個圖案 化基板中辨識出該一或多個區域以便修復。 錢行自動光學檢查之方法尚包含下列步驟：在該—或多個 圖案化_之該-或多個顯識為須予以修復之區域上，重新塗 佈基板光阻；在該-或多個圖案化基板之該—❹個經辨識為須 予以修復之區域上，執行圖案之重建；利職等SLM成像單元， 重新檢查該-或多侧案化基板之該—或多個_識為須予以修 復之區域；以及根據該重新檢查所得之資訊，更新該等檢查結果。 該執行自動光學檢查之方法尚包含下列步驟：在該一或多個 圖案化基板之該複數區域上，重新塗佈基板光阻；在該一或多個 圖案化基板之該複數區域上，執行圖案之重建；利用該等SLM成 像單元，重新檢查該一或多個圖案化基板之該複數區域；以及根 據該重新檢查所得之資訊，更新該等檢查結果。 【實施方式】 本發明提供一種製造三維(3-D)積體電路之系統及方法。以 下之說明，係為使熟習此項技藝之人士得以製作及應用本發明。 本文有關特定實施例及應用方式之說明僅供例示之用，熟習此項 技藝者可輕易思及多種修改及組合該等範例之方式。本文所述之 基本原理亦適用於其他實施例及應用而不悖離本發明之精神與範 17 201214515 圍因此’本發明並不限於本文所描述及繪示之範例，而應涵蓋 符合本文所述原理及技術特徵之最大範圍。 在以下之详細說明中，部分内容之呈現係透過流程圖、邏輯 方塊圖，及其他可於電腦系統中執行之資訊運算步驟之圖示。在 本文中，任-程序、電腦可執行之步驟、邏輯方塊及流程等，均 係由-或多道步驟或指令所組成之自相—致之序列，其目的係為 達成預定之結果。料步驟係指實際操控物理量之步驟，而物理 里之形式則包含可於電腦系統中儲存、轉移、結合、比較，及以 其他方式操控之f性、磁性或無線電訊號。在本文巾，該些訊號 有時以位7C、數值、元素、符號、字元、項、號碼或類似名稱稱 之。各步驟之執行者可為硬體、軟體、|赠，或以上各項之組合。 本發明之實施例使用以空間光調變器（SLM)為基礎之影像 投射裝置。可供使狀SLM f彡像投射方式共有兩種…種係透過 數位微鏡裝置（DMD)，另-細係透過栅狀· (GLV)裝置，兩 種裝置均可以微機電（MEM)製造法製成。 第3圖繪示-根據本發明實施例之數位微鏡裝置範例。在此 範例中’標號302為單- DMD晶片，而標號3〇4則為該DMD晶片 之放大簡化圖。若欲將膽用作空間光調變器，可令腦中之微 鏡傾斜至岐角度（大多約為±1〇m。）。讎之微鏡鏡面對 入射照明光之反射性極尚。各微鏡可由下方之電晶體控制器使其 傾斜（如標號306所示）或維持原本位置不變（如標號3〇8所示）。 在一實施例中，DMD之間距可為約14微米，而微鏡之間距可為約 201214515 1微未。單—"D1WF)曰ρ ϊ 曰曰片上之像素數可為1920 X 1〇8〇個微鏡像素， 此一像素數可與高晝質電視⑽TV)之顯示器規格相容。 /第4圖、”a *根據本發明實施例之励投影系統。在此範例 中’微鏡共有三種狀態：υ傾角約為·。之「啟動」狀態4〇2 ; 2\未傾斜之「持平」狀態撕；以及3)傾角約為-Η)。之「關閉」 狀心406。在第4 ®中’光源備所在位置係與麵形成_2〇。之 =度’當此光源射出光束時，處於「啟動」狀態（或二進制中之 「1」）之微鏡將反射該歧，使其直接穿過投影透鏡·，因而 在顯示器基板上形成亮點。至於「持平」狀態及「關閉」狀態（或 二進制中之「0」）之微鏡，其反射光束將有所偏斜（其角度分別 為約-20及-40°) ’並落在該投影透鏡之聚光錐之外。換言之， 後兩種狀態之微鏡之反射光並不會穿過投影透鏡41〇，因此，顯 不器基板上將形成暗點。由於微鏡之反射光無法以目視方式分 解，吾人可將一組投射出之亮點及暗點依適當比例組合，以形成 灰階。此方法可利用百萬種灰色調與色彩，投射出逼真之影像。 請注意，來自「持平」狀態微鏡之較高級數繞射光及來自「關 閉」狀態微鏡之第二級繞射光仍可進入該投影透鏡之聚光錐，並 產生吾人所不樂見之閃光，進而降低影像對比度。根據本發明之 實施例，可利用一精確瞄準及聚焦之高強度照明光源提高像素之 繞射效率’藉以將DMD成像寫入系統之投影光學設計最佳化。 根據本發明之其他實施例’ GLV係另一種投射影像之方法。 GLV裝置之頂層係一呈線性排列之材料層，又稱帶狀元件 19 201214515 (ribbon)纟具有極佳之反雛。在—實施财，料帶狀元件 之長度可為⑽至麵微米，寬度可為1至10微米，間距可為 〇·5 «。基本上’ GLV之成像機構係利用可操控之動態繞射光 柵’其作用如同相位調變器。GLV裝置可包含一組共六條帶狀元 件’其經交替折曲後便形成動態繞射光柵。 第5圖為-剖視圖，顯示本發明實施例中一 glv裝置之鏡面 反射狀態及繞概祕例。當GLV帶狀元件共面時（如標號5〇2 所示）’人射光將產生鏡面反射，亦即繞射級數為卜當二射光 射至-組交替折曲之帶狀元件（如標號5()4所示）時，強烈之士 1 級繞射光及偏弱之〇級繞射光將形錢射_々齡q級繞射 光與±1級繞射光其中之-，即可產生高對比之反射影像。換言之， 若物鏡重_躺有〇級或:U域射光，料會軸任何景綠。 W與_不同之處在於，GLV視野中所形成之整個影像係以逐條 知描方式建構而成，因為雜㈣m件光栅可—次形成— 條線狀繞射影像。 ^ 吾人可由第1圖與第2圖之相關說明得知，為達單位時間之 產量要求，必須搭配如習知系統所之高功率照明光源。在— 範例中係使用神達千瓦顧之高鍾弧絲，而在另—範例中 則_高功率之準分子雷射。由於使用高功率之照明光源，照明 光程須來自遠處以減少所生之熱能，且須經折曲以產生適當之照 明效果。此一設計將照明系統與SLM成像系統分為兩獨立:了 且光程係與透鏡垂直。 20 201214515 為突破習知系統與方法之限 構避免使職辨之0H 、，’道（之曝光工具架 一元均明 成像透鏡。此系,縣使賊辨 ^奸控㈣及 射照明光源，料⑽此料紐_红極體雷 々奴具日H〜 。尤處理里較低’但若增加成像單元 之I二、早位時間之曝光處理量。使用小型SLM成像單元 可以該等單元構成不同尺寸之陣列以利不同之成 在-_貫例中係以超過_個上述小型 =，其單位時間之寫入處理量高於現有多波光 工具架構。 第6圖繪示-根據本發明實施例之小型slm成像單元範例。 在此範例中，該小型SLM成像單元包含空間光調變器.一組 微鏡_ 一❹個酬光糊、—❹個對準光源6Q8，及投 影透鏡610。照明光源刪可採用波長小於伽奈米之藍光或近 紫外光LED <二極體雷射。對準光源_可採用非光化雷射源或 LED以便輯透·行對纽解調整。投影透鏡⑽可採用縮 小比率為5X或皿之透鏡。如第6 _示，照明光源咖及對準 光源6G8均位於該投影透鏡之聚光錐之外。在此實施例中，可使 用數值孔徑Μ為G.25且解像力約為丨微米之市售透鏡 。較低之 Μ值可確錄佳統⑽F)。在—微影製程實例巾，光阻關鍵尺 寸目標值為1微来，透鏡Μ值為〇. 25，則焦深大於5. 〇微米。 解析度及絲之計算錄^#_URayleigh㈤放恤）： 21 201214515 最小圖徵解析度外U / NA) 焦深=k2 (入/ ΝΑ2) λ為曝光波長。在一使用龄酸樹脂 ki介於0. 5與0. 7之間，而k2則介 其中k’k2為製程能力因子， 化學光阻之微f彡餘實例中， 於〇. 7與0· 9之間。201214515 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to the manufacture of an integrated circuit. The invention resides in a system and method for making a two-dimensional (3-D) integrated circuit. This application is part of the 12/475,114 US officially filed application filed on May 29, 2009, and the priority of the official patent application is claimed in accordance with Article 12 of the US Patent Law. The official patent application No. 12/475, 114 claims the application of the 12th/337th of December 17th, the priority of the US patent application, and the 12th/33th, 5th ( The No. 4 US official patent application claims the priority of the "Optical Imaging Writer System" in the US Provisional Patent No. 61, which was filed on September 23, 2nd. The present application also claims the priority of the U.S. Provisional Patent Application No. 61/379,732, filed on Sep. 3, 2010, entitled "Method of Manufacturing a Three-Dimensional Frequency Circuit H." The full content of the application is in the way of Can. [Prior Art] Thanks to the rapid advancement of the semiconductor integrated circuit (10) technology, the process of dynamic matrix liquid crystal television (ATV) and computer display has made great progress. In recent years, the size of LCD TVs and computer monitors has been continuously enlarged, but prices have become more popular. In the case of Semiconductor 1C, each technology generation is based on the critical dimensions (4) in the circuit design rules (4). With the evolution of the technology generation, the chart of the new generation K is closed. The 201214515 key size target value is gradually reduced. The error tolerance is also stricter. However, in the case of flat panel displays (FH), the various technology generations are classified according to the physical dimensions of the substrates used in the process. For example, 'FPD entered the sixth generation (G6), eighth generation (G8) and tenth generation (G10) in 2005, 2007 and 2009 respectively. The corresponding substrate size (mm x mm) is 1500x1800, 2160x2460 respectively. And 2880x3080. Nothing is a semiconductor 1C or FPD substrate. The challenge of the lithography process is how to increase the size of the product on the one hand and make the product cheaper on the other hand; but the process of the two is different. One of the major challenges in the 1C industry is the formation of small critical dimensions on wafers up to 300 mm in diameter, with the goal of maximizing the number of women in the transistor and enabling better performance of wafers of the same size. . However, one of the major challenges in the FpD industry is to maximize the size of the rectangular substrate that can be processed, because the larger the FPD substrate that can be processed on the production line, the larger the TV or display that can be manufactured, and the lower the cost. In order to improve the performance, __like LCD TVs and monitors are designed with more complex thin-film transistors (10)), but the critical size target values of TFTs remain the same. From a certain point of view, the main challenge of the FpD process is that the unit time output of each generation has a reasonable cost-effectiveness, and its consideration: the consideration of the factor is to make the process yield reach the profit level' At the same time maintain an appropriate process window. The lithography technology used in the manufacture of FPD is manufactured by the ic micro-rate: 微 Γ Γ 微 曝光 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 大多 ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ ΐ The projection ratio has two to one (shrinking) fish one to two. In order to project the reticle onto the substrate, the reticle itself is manufactured to the critical dimensions of 201214515. The FPD mask process is similar to that of the semiconductor IC. The difference is that the size of the mask used to make the semiconductor ic is about ± mm per side (about 6 inches), and the mask used to make the FPD, The size of each side of one side can be about eight times the size of each side of the secret, that is, more than one meter per side. Referring to the first drawing, a projection exposure tool for scanning a mask pattern onto an FpD substrate is known. The light of the bribe is stationed as a high-short-arc mercury (Hg) lamp. The incident illumination light is reflected by the mirror 1〇2, sequentially passes through the mask 104 and the projection lens 1〇6, and finally reaches the FpD substrate 1〇8. However, if the structure of the conventional exposure tool shown in the first la® is to be made for the new generation, it is necessary to solve the problem of increasing the size of the mask. Take the eighth generation of Qing as an example, the mask of the cypress is the face of the x-key, and the (four) of the eight generations is four times. Since the critical dimension specification of TFT is within the range of 3 micrometers, how to control the critical dimension of m on the eighth generation substrate of more than two meters on each side is a big challenge; compared to the dream crystal of 3 GG in diameter The lithography on the circle is printed and controlled by the advanced ic pattern. The specifications are more difficult. The question to be solved in the FPD f world is how to do it. The cost-effective way to create a reticle-type exposure that turns over the new generation - while retaining the lithographic process capability limit (also known as the process window). If you want to reduce the FPD exposure __ key size is not __ caused by the situation, one of the methods is to use the ^ exposure method 'the towel nominally exposed stitching shirt according to the appropriate example of the distribution of the exposure knife in the domain' and each exposure The component is the illumination of the pro-wavelength, and the corresponding Wei Wei shouts into the money. This secret light contains more than one projection pro, but only with a single source, because the high output power of the mercury lamp illumination source of 201214515 kW (10) must be used. As for the way of selecting the exposure wavelength, the county mirror of the silk is shot. In the real money, this multi-wavelength exposure method can reduce the key size of the eighth-generation substrate, so that it can make the misunderstanding _ read. ^The Negative When using the multi-wavelength exposure method, the stricter critical size target value and the uniformity of the dimensions must be set for the mask itself. In the _ example, the critical dimension error of the TFT mask is less than (10) nanometer, which is much smaller than the county capacity of the mask _ size nominal target value of 3 micro-faces. In terms of the process of using the financial exposure tool architecture, it is easier to control the process window of the FPD lithography process. However, the stricter requirements for the FPD reticle size specifications will make the mask set that was originally costly more expensive. In some cases, the cost of producing a key mask for the eighth generation is extremely high and the stocking period is very long. ★ Another method of the conventional method - the problem is that it is not easy to control the silk thread when the large mask is used. With a large mask to carry out the township Wei Guangzhi, even if you start using the whole red-free red, you can still (4) the thief. If the process produces a sputum 虞 ' ^ but the yield will be affected by the township, the cost of the material will also increase. The lb diagram shows another architecture of the conventional exposure tool. As shown in the diagram, the exposure tool includes a light source 11G, a first projection lens 112, a reticle 114, a second projection '5V lens 116, a wafer 118, and a wafer platform (10). The light source 11〇 can be controlled so that its light is directed through the first projection lens 112 to the reticle 114, wherein the reticle contains a pattern to be imaged on the wafer 118. Part of the light will be blocked by the reticle 114, and part of the light will pass through the reticle 114 and penetrate the second projection lens 116, causing the wafer (10) to expose 201214515 light. The light passing through the reticle 114 will expose the mosquito area of the wafer ία, thereby producing a set of pattern images corresponding to the redundant design pattern formed on the reticle 122. Note that the wafer is attached to the wafer platform (10), and the wafer platform can be moved under the control of the arrow in the direction indicated by the arrow. In a conventional stepping system, the light source 11G can be blue visible light or near-ultraviolet light, and the first projection lens 112, the reticle 114 and the second projection lens 116 are fixed, and the crystal lens 118 is used to fix the crystal. The wafer platform 120 is movable to expose different areas of the wafer 118. This step-by-step design enables the design of designs with resolutions up to 3 microns, such as small-sized masks, light-emitting diodes (10), and flat-panel displays from the fourth and earlier generations. In the conventional scanning system, the light source 11 (), the first projection lens 112 and the second projection lens 116 are fixed, and the mask 114, the wafer ι 8 and the platform for fixing the wafer are all (4). In order to expose the area on the wafer ΐ8. Compared with the stepping system, the scanning system handles large-size reticle and flat panel display, but its price is high. Scanning secrets are mostly used to make flat-panel displays of the sixth or new generation of substrates. The lc to le _ show various ways of exposing the tool-like reticle, and how the conventional exposure tool aligns the immersion for exposure. In the & diagram, the reticle 130 is held in contact with the substrate wafer 132, so the system is generally referred to as a contact alignment system. In the Mth picture, the mask 13G is tied to the position adjacent to the substrate wafer 132, and the system a(4) is a close alignment. f. Contact type pairs (4) system and proximity system are mostly used in the manufacture of printed circuit boards, touch panels (25 to 40 micro-seeking), light-emitting diodes (3 to 5 micrometers) and solar panels (> 100 micrometers). For contact with the 201214515-type alignment system and the proximity pair (four)-shaped defect-free package subtraction process for high-resolution design patterns, warped wafers or substrates larger than 4 inches. FIG. 1e illustrates a conventional projection alignment system in which a projection lens 131 is further disposed between the reticle 130 and the substrate wafer 132. Most of this system is used to make circuits from $10 to 10 microns. Such a projection alignment system is more suitable for manufacturing a color filter and a light sheet of a flat panel display with a large-sized photomask, but the size of the large-sized photomask is very high. Therefore, if it is impossible to accept the cost of the group of S, it is not cost-effective to make a printed circuit board and a light-emitting diode. Figure 2 illustrates a conventional architecture for an exposure tool for making a reticle. In this exposure tool architecture, the illumination light 2〇2 directed at the beam splitter 2〇4 will be partially reflected and passed through the Fourier lens 208 to illuminate the spatial light modulator (SLM) 2G6. After the imaged light is reflected, it passes through the Fourier lens 2〇8, the beam splitter 2〇4, the Fourier filter 21〇, and the reduction lens 212, and finally reaches the blank mask substrate 216. The mask data 214 is electronically transmitted to the spatial light modulation 1! 2G6, and the micro-mirror is set by the coffee. The reflected light produces a bright spot on the blank mask substrate 2i6, and a dark spot is formed on the blank mask substrate 216 without reflection. The fresh material pattern can be transferred to the blank mask substrate 216 by controlling and arranging the reflected light. Eight Please note that in this secret light X with a frame, the outline light (10) is so curved that it can be injected into the space _ change 11. This fold line forms a zigzag shape with the path of the exposed filament. In addition to the use of high-definition lighting materials, this Na-light system must also use a projection lens with a reduction ratio of the south to improve the accuracy and precision of the writer. Basically, the lens reduction ratio is about 100 to 1. When using a lens with a high reduction ratio of 201214515, the exposure area produced by the single-space optical modulator wafer is very small. The physical size of the wafer of the inter-work optical modulator is about one centimeter. After being reduced by a factor of 1, the writing area of the spatial light modulator is about 100 micrometers. If you want to write this very small writing area - "the first generation of FPD reticle" has a very long time. Another method is to sequentially illuminate the spatial light modulator with multiple laser beams. It is formed by a single-illuminated laser source reflected by a rotating polygon mirror. The illumination beam can generate multiple exposures at a specific time, thereby increasing the writing speed of the mask. In an example, the method is written in this way. The eight-generation FPD mask takes about 20 hours. Due to the long time of the S-person, the cost of controlling the H and maintaining its mechanical and electronic operations has also increased, which in turn has increased the cost of its FPD fresh products. In the 10th generation or newer generation of FPD reticle, the manufacturing cost is likely to be higher. In order to reduce the cost of making a small amount of reticle, the other method used in the conventional method is to use the luminaire For the light I. This branch reads the mask pattern into the space light and changes it into a hood pattern, so that the physical mask is used. In other words, the function of the coffee machine can replace The cross-section of the mask, thus saving the mask county. This method is basically the same as the fresh feeding system. Fine, if compared with the real county cover, the image quality of the spatial light modulator mask is low, and does not meet the requirements of the TM process specification. US Patent No. 906, No. 779 (hereinafter referred to as "the 779 patent") discloses another conventional method of manufacturing entanglement, and the financial system _-heterogeneous process performs synchronous lithography exposure on the mesh substrate. In short, The '79 patent exposes the reticle pattern 10 201214515 to a roll of substrate. Another conventional scroll lithography process can be found in Se Hyun Ahn et al. "High-speed reel type for flexible plastic substrates. "Hight-Speed Roll-to-Roll" Nanoimprint Lithography on Flexible Plastic Substrates)" (Growing the fate of β Co. KGaA, ¥einhew' r Advanced Materials (Advanced Materia) s) j, 2{) He, 20, pp. 2044-2049) (hereinafter referred to as Ahn's article). However, the two conventional methods described above are limited to a reticle of a predetermined size, and the reticle size substantially limits the size of the flexible display that can be manufactured. Another problem with the method of driving described in the '779 patent and the Ahn article is that the substrate to be rolled must be flattened during the exposure process in order to achieve proper lithographic printing. As a result, the flatness of the surface of the substrate will be inferior to that of the LCD TV. When such a reticle lithography technique is applied, the depth of focus (D0F) is limited by the unevenness of the surface of the substrate, so that the above-mentioned method may be difficult to open into a τα pattern having a critical dimension of 5 μm or less. If the resolution of the TFT display is to be at a certain level, the critical dimension of the m-mask will be about 3 microns. The above-mentioned challenges that may arise in the manufacture of future generations are due to the fact that the FPD industry does not need to reduce costs, and one of the main motivations is to make the process of the new generation products cost-effective. The lithography technology relies on the efficiency of output to ensure the improvement of product yield from generation to generation. In order to achieve this goal, it is necessary to increase the process window of the lithography process and reduce the process alkali to meet the increasing number of substrates. - As mentioned above, the existing aqueduct architecture has many shortcomings. Among them, the main disadvantage is related to the use of the reticle, that is, the reticle size is too large, resulting in the manufacture of the reticle being inconsistent with cost. Due to the 11 201214515 mask size is bound to increase the amount of money not to face the face of the invention [invention] in the illusion to apply the light material pattern in the lithography method. In the implementation of the financial system, the invention comprises a complex 3 transformer ((10) imaging unit, wherein each of the can image units comprises - or an illumination source, an apricot multiple oblique into the mine to make a difference and a plural ~ t brother /L rays are projected from the - or multiple illumination sources to the corresponding β/_ ̄ ̄ 〜 1%. This imaging (4) still contains - rib control and other SLM imaging == 'This _ can be in each SLM _ yuan __ In the U-pass process of the basic version, the SLM imaging unit is separately woven. In the example, the method of manufacturing the three-dimensional integrated circuit includes the following =LM=: an imaging writing system having a plurality of imaging units, wherein The 穑(4) ❹Γ疋 series are arranged in one or more parallel arrays; receiving the three-dimensional servant to be written; or multiple layers of reticle data; processing the reticle data, forming a plurality of complexes in the _ _ _ _ _ _ _ _ _ 2 one or more SLM imaging units are responsible for processing the mask data of each partition; and controlling the imaging unit, and writing the pattern of the mask mask data to the one or more layers of the three-dimensional integrated circuit. __2:!===, alignment correction for the aliquot 2 mask data pattern荦 见 见 间距 间距 , , , , , , 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距 间距The substrate deformation correction is performed, and the two mask data patterns have corresponding substrate deformation correction actions. The steps of controlling the SLM imaging include: for each SLM imaging unit, the corresponding partition mask data pattern is independent of the imaging. The other SLM imaging unit in the human system is exposed for exposure. In another embodiment, the method of manufacturing a complex pattern in parallel on a printed circuit board (PCB) includes the steps of: providing an image with a plurality of SLM imaging units a writing system, wherein the SLM imaging units are arranged in one or more parallel _; providing - a printed circuit board having a plurality of regions divided, wherein each region includes a design pattern to be manufactured; and the printed circuit is received by a person to be written The board of the plural area of the light m job, please reduce the number of jobs corresponding to the printing. The board of the plural area of the district county (four) bribe; assigned "one SLM imaging The element is responsible for processing the mask data of each partition_, and the expression of the emotion includes at least performing 13 201214515 among the following:: scaling correction, alignment state correction, viewing distance correction, rotation factor correction, and substrate warpage correction; and controlling the Waiting for the slm imaging unit, the partition mask data is written in parallel to the job area of the printed circuit board. In the other implementation method, the manufacturing method of the wafer includes the following steps: An imaging writer system of SLM imaging units, wherein the SLM imaging units are made to provide a plurality of wafers to be processed, or to receive reticle data, wherein the reticle is for writing a substrate of a plurality of partial wafers; processing the photomask (4) to form a plurality of partitioned masks, wherein the partitioned data maps (4) correspond to the substrate of the one or more partial wafers; The SLM imaging unit negatively reduces each partition reticle data pattern' wherein the assignment comprises performing at least one of: scaling correction, alignment correction, visual correction, rotation _ sub-correction and base correction Correction; and controlling the plurality of SLM imaging units, and the like serve the army of partitioned data pattern written to the substrate parallel to the one or more portions of the wafers. In another embodiment, a method of fabricating a plurality of light emitting diodes (LEDs) in parallel includes the steps of: providing an imaging writing system having a plurality of SLM imaging units, wherein the SLM imaging unit is arranged Forming one or more parallel arrays; providing one or more substrates corresponding to the LEDs to be manufactured; receiving reticle data wherein the reticle data is for the writer or a plurality of substrates corresponding to the coffee; processing The reticle data is formed to form a partial zonal mask (4), and the material partition reticle pattern corresponds to the substrate of the material LED; the assignment--one (10) imaging is early to process the pattern of each partition light sheet; Controlling the μ imaging sheets 201214515, and writing the partition mask data patterns in parallel to the one or more substrates of the LE: D. The step of processing the mask data includes at least one of the following: processing the The mask data to form a plurality of partial mask mask data patterns, wherein the partition mask data patterns correspond to the one or more substrates of the LEDs, and are of the same design; and processing the mask data to Forming a plurality of partitioned mask data patterns, wherein the partition masks are corresponding to the one or more substrates of the LEDs, and are different: ». The step of controlling the SLM imaging unit is at least Include one of the following to measure the deformation condition of each local area on the substrate of each SLM imaging unit, and adjust the focus of the corresponding SLM imaging unit according to the deformation state of each local area on each substrate; and detect each substrate on the SLM imaging unit The rotation error of the local area, thereby determining the correct positive factor of the corresponding partition, and applying the transfer corrective factor to the partition mask data pattern corresponding to each partial area of each SLM wire unit paste substrate; The local area on the side substrate of the SLM imaging unit is distorted by the deformation of the substrate, thereby determining the pattern correction factor of the corresponding partitioned light material pattern, and the _ correction factor is finer than each partial area of each substrate of the imaging unit The corresponding mask reticle data pattern. The method of performing an automatic optical inspection in another embodiment includes the following steps: providing - having a plurality of SLMs An imaging writer system of a unit, wherein the SLM imaging units are arranged in one or more parallel arrays; one or more patterned substrates to be inspected are provided; and the - or a plurality of substrates are divided into a plurality of regions; Receiving reference mask data corresponding to the- or multi-faceted substrate; processing the reference mask 201214515 data to form a plurality of partition mask data patterns, wherein the partition mask data patterns correspond to the one or more patterns The plurality of regions of the substrate are obtained by using the SLM imaging unit to capture information of the plurality of regions of the one or more patterned substrates; and the plurality of partitioned mask data patterns are referenced to analyze the information of the plurality of frames. And generating the inspection result; and storing the inspection result in a memory device. The step of analyzing the information of the plurality of regions comprises: inspecting the plurality of regions of the one or more patterned substrates and the corresponding plurality of partition masks Whether the data pattern is different, and if a difference is found in one or more regions of the one or more patterned substrates, in the - or multi-sided substrate The knowledge that - in order to repair or more regions. 'The steps to check the difference · Less include the following -: The complex number of mask masks for the collection should be referenced to the county, check the money - or the multiple areas of the substrate, whether the base case distortion occurs, if - the substrate pattern distortion is found in one or more regions of the slab, and the - or more regions are recognized in the - or the plurality of patterned substrates for repair; checking the - or the plurality of patterned substrates The plurality of circuit elements are (4) circuit elements on the substrate, and if additional circuit elements that should not appear in one or more regions of the patterned substrate are found, the one or more The area or the plurality of areas are identified in the substrate for repair; the money-receiving or multi-sided substrate of the substrate is missing from the circuit component on the substrate, if one of the substrate or the multi-sided substrate Or the missing circuit component in the plurality of regions, the one or more regions are identified in the ❹-side substrate for repair; and the inspection or the multi-sided substrate is 201214515. Miscellaneous, improperly affecting acid, if - a plurality of patterned substrates or - one or more regions found that foreign particles, then in this - one or more of the identified region or patterned substrates for repair. The method of automatic optical inspection of the money line further comprises the steps of: recoating the substrate photoresist in the area or the plurality of regions where the patterning is to be repaired; in the one or more The patterning of the substrate is performed on the area identified as being repaired, and the reconstruction of the pattern is performed; the SLM imaging unit such as the profit and the like, re-examining the - or the multi-side substrate of the substrate or the plurality of The area to be repaired; and the results of the inspections are updated based on the information obtained from the re-examination. The method of performing an automated optical inspection further comprises the steps of: recoating the substrate photoresist on the plurality of regions of the one or more patterned substrates; performing on the plurality of regions of the one or more patterned substrates Reconstruction of the pattern; re-examining the plurality of regions of the one or more patterned substrates using the SLM imaging units; and updating the inspection results based on the information obtained from the re-examination. [Embodiment] The present invention provides a system and method for manufacturing a three-dimensional (3-D) integrated circuit. The following description is made to enable those skilled in the art to make and use the invention. The descriptions of the specific embodiments and the manner of application herein are for illustrative purposes only, and those skilled in the art can readily appreciate various modifications and combinations of the examples. The basic principles described herein are also applicable to other embodiments and applications without departing from the spirit and scope of the present invention. The present invention is not limited to the examples described and illustrated herein, but should be The maximum range of principles and technical features. In the following detailed description, a portion of the content is presented through a flowchart, a logical block diagram, and other illustrations of information processing steps that can be performed in a computer system. In this document, any program, computer executable steps, logic blocks and processes, etc., are sequences of self-consistent steps consisting of - or multiple steps or instructions for the purpose of achieving a predetermined result. The material step refers to the actual manipulation of physical quantities, while the physical form includes f-, magnetic or radio signals that can be stored, transferred, combined, compared, and otherwise manipulated in a computer system. In this document, the signals are sometimes referred to as bits 7C, values, elements, symbols, characters, terms, numbers, or the like. The performers of the various steps may be hardware, software, gift, or a combination of the above. Embodiments of the present invention use a spatial projection device based on a spatial light modulator (SLM). There are two types of SLM f image projection methods available: the digital transmission through the digital micromirror device (DMD) and the fine transmission through the grid (GLV) device, both of which can be fabricated by the micro-electromechanical (MEM) method. production. Figure 3 is a diagram showing an example of a digital micromirror device in accordance with an embodiment of the present invention. In this example, 'label 302 is a single-DMD wafer, and reference numeral 3〇4 is an enlarged simplified view of the DMD wafer. If you want to use the gallbladder as a spatial light modulator, you can tilt the micromirrors in your brain to the 岐 angle (mostly about ±1〇m). The micro-mirror mirror is extremely reflective to the incident illumination. Each micromirror can be tilted (as indicated by reference numeral 306) by the underlying transistor controller or maintained at the original position (as indicated by reference numeral 3-8). In one embodiment, the distance between the DMDs can be about 14 microns, and the distance between the micromirrors can be about 201214515 1 micro. Single-"D1WF)曰ρ ϊ The number of pixels on the 可 可 可 can be 1920 X 1 〇 8 微 micro-mirror pixels, which can be compatible with the display specifications of high-quality TV (10) TV). / Fig. 4, "a * The excitation projection system according to the embodiment of the present invention. In this example, the 'micromirror has three states: the inclination angle is about · · the "starting" state 4 〇 2; 2 \ untilted" "flat" state tear; and 3) inclination is about -Η). "Close" 406. In the 4th ®, the position of the light source is formed at _2〇. = degree 'When the light source emits a beam, the micromirror in the "on" state (or "1" in the binary) will reflect the difference and pass it directly through the projection lens, thus forming a bright spot on the display substrate. For the "flat" state and the "off" state (or "0" in the binary), the reflected beam will be deflected (the angles are about -20 and -40° respectively) and fall on the projection. Outside the condenser cone of the lens. In other words, the reflected light from the micromirrors of the latter two states does not pass through the projection lens 41, and therefore, a dark spot will be formed on the display substrate. Since the reflected light of the micromirror cannot be visually decomposed, we can combine a set of projected bright and dark points in appropriate proportions to form a gray scale. This method uses millions of shades of gray and color to project a realistic image. Please note that the higher-order diffracted light from the "flat" state micromirror and the second-order diffracted light from the "off" state micromirror can still enter the concentrating cone of the projection lens and produce a flash that we are not happy with. , which reduces image contrast. In accordance with an embodiment of the present invention, a high intensity illumination source for precise aiming and focusing can be utilized to increase the diffraction efficiency of the pixels' to optimize the projection optical design of the DMD imaging writing system. According to other embodiments of the invention, GLV is another method of projecting images. The top layer of the GLV device is a linearly arranged layer of material, also known as a ribbon element. 19 201214515 (ribbon) 纟 has an excellent anti-feeding. In the implementation, the length of the strip element can be (10) to the surface micron, the width can be 1 to 10 microns, and the pitch can be 〇·5 «. Basically, the 'GLV imaging mechanism utilizes a steerable dynamic diffraction grating' that acts like a phase modulator. A GLV device can comprise a total of six strip elements 'which are alternately flexed to form a dynamic diffraction grating. Fig. 5 is a cross-sectional view showing a mirror reflection state and a bypass example of a glv device in the embodiment of the present invention. When the GLV strip elements are coplanar (as indicated by the label 5〇2), the human light will produce a specular reflection, that is, the diffraction order is a band-like component that is alternately flexed to the group. When 5()4), the strong man's 1st-order diffracted light and the weaker-level diffracted light will shoot the _ 々 age q-order diffracted light and ±1 order diffracted light, which can produce high contrast. Reflected image. In other words, if the objective lens is _ lying on the level or: U-field light, the material will be any green. The difference between W and _ is that the entire image formed in the GLV field of view is constructed in a one-by-one manner, because the (four) m-piece grating can be formed in a line-by-line diffraction image. ^ We can see from the relevant descriptions in Figures 1 and 2 that in order to meet the production requirements per unit time, it is necessary to match the high-power illumination source as in the conventional system. In the example, the God of Kilowatts is used, and in the other example, the high-powered excimer laser. Due to the use of high power illumination sources, the illumination path must be from a distance to reduce the heat generated and must be flexed to produce the proper illumination. This design divides the illumination system into two independent SLM imaging systems: and the optical path is perpendicular to the lens. 20 201214515 In order to break through the limitations of the conventional systems and methods, avoid the identification of the 0H, '' (the exposure tool holder is a uniform imaging lens. This department, the county makes the thief discriminate and control (four) and shoot the illumination source, (10) This material _ red body Thunder shacks day H ~. Especially in the process of 'lower, but if the imaging unit I 2, the early exposure time of the exposure time. Using small SLM imaging unit can make these units different The array of sizes is different in the case of -_ the above-mentioned small size =, the write processing amount per unit time is higher than the existing multi-wave optical tool architecture. FIG. 6 is a diagram - according to an embodiment of the present invention Example of a small slm imaging unit. In this example, the small SLM imaging unit includes a spatial light modulator. A set of micromirrors _ a retort, a aligning source 6Q8, and a projection lens 610. The light source can be selected from blue light or near-ultraviolet light LED < diode laser with wavelength less than gamma. Aligning light source _ non-lighting laser source or LED can be used for fine-tuning and alignment adjustment. Projection lens (10) A lens with a reduction ratio of 5X or a dish can be used. In the sixth embodiment, the illumination source and the alignment source 6G8 are located outside the concentrating cone of the projection lens. In this embodiment, a commercially available lens having a numerical aperture Μ G.25 and a resolution of about 丨 micron can be used. The lower value can be recorded in Jiatong (10)F). In the lithography process example, the target value of the photoresist key dimension is 1 micro, and the lens value is 〇. 25, the focal depth is greater than 5. 〇 micron. Resolution and calculation of silk ^#_URayleigh (five): 21 201214515 Minimum sign resolution outside U / NA) Depth of focus = k2 (in / ΝΑ 2) λ is the exposure wavelength. In an age-old acid resin ki between 0.5 and 0.7, and k2 is where k'k2 is the process capability factor, in the micro-f remaining examples of chemical photoresist, Yu. 7 and 0· Between 9.

形狀因數之要求，照明光源可為藍光、近紫外光LED 極體雷射。另為達足夠之照明強度，本案之一設計實 例使用多個照明光源，且該等照明光源侧繞SLM並靠近SLM表 面。Μ可為具有適當光學透鏡設計之麵細。在二例中 基板處之目触明強度目標值以有效統曝光波長計，可達每平 方公分10至100毫瓦。 在此曝光工具_範例巾，各小型成像祕之電子控制板外 殼均符合-指定之小形狀隨。為便於賴及散熱，此外殼係位 於SLM之頂部且遠離照明光源。單一小型s[j成像單元之實體尺 寸取決於所需之成像效能及可社市t元件，例如投影透鏡、⑽ 或二極體魏_絲’以及難/對準狀二極體雷射，各元 件均須有其散熱空間。或者亦可使用訂製元件，錢—步降低單 - Μ成像單元實體尺寸之形狀因數。—訂製之SIJ成像單元， 其二維剖面尺寸可小至5公分X 5公分左右；以市售現成元件構 成之SLM成像單元’其二維剖面尺寸則約為1〇公分X 1〇公分。 22 201214515 、就第十代FPD製程而言，典型之基板尺寸為公厘χ3ΐ3〇 若使用小型SLM成像單元，則整個系統可能包含數百個排 列成平行陣列之小型SLM成像單元。第7 _示一根據本發明實 施例之SLM成像單元平行陣列範例。在此範例甲係由_至_ 個Μ成像單元平行陣列⑽、704、706、708等）同時進行成 像寫入，且各平行陣列可包含複數個SLM成像單元。 、根據本發明之實施例，在計算單位時間之曝光處理量時，可 = -SLM光罩寫入系統之已知單位時間處理量實例（例如以讓 △厘X 1500公厘之光罩曝光2〇小時）作為計算起始點。單位時 間處理1取決於基板所在平面之照㈣度^在本範射，若照明 強度為每平方公分50 €瓦⑽或二㈣雷射光源均可提供此照 明強度），標稱曝光能量為30毫焦耳/平方公分-秒，則曝光時 間為約G.6秒。在另一範例中，曝光工具係採高功率照明光源， 因此，板處之照明強度為每平方公分至少咖毫瓦；此光罩式步 進/掃描系統之單位時間處理量約為每小時50片第八代to基 板：在-範例中，若將高功率與低功率照明光源同時納入考量， 2位時間預估處理量為每小時25至副片基板，端視各平行陣 降之SLM成像單綠度而定。此—陣列式平行曝絲 性具有競爭優勢。 第8圖係第7圖所示SLM成像單元平行陣列之俯視圖。在此 】歹1 ’各列或各行可分別代表—SLM成像單元平行陣列，且各 平行陣列可包含複數個則成像單元。微影製程之良率與製 23 201214515 程窗口息息相關。製程窗口在此係指相互搭配且可製印出符合規 格之圖徵關鍵尺寸之焦點設定範圍及曝光量設定範圍。換言之， 製程窗口愈有彈性，則其料之失焦設定值及/祕光量設定值 愈為寬鬆。較大之製程窗口有助於提高產品良率。然而，隨著基 板尺寸逐代加大，微影製程之製程窗口則愈變愈小，主要原因在 於較大、較溥之基板材料也較容易彎曲及垂陷。為解決此一問題， 必須嚴格規範基板材料之厚度及表面均勻度。就光罩式曝光工具 而言，若曝光區域單邊大於約兩公尺，*僅需耗f極大成本方可 維持全區之均勻度及；|、點控制，在技術上亦有其困難度。曝光工 具須能執行舰及_之局部及全面最佳化，方可落實製程窗口 之設定值。 第8圖所示之平行陣肩光祕即可解虹制題，因為各 小型SLM成像單元均可局部最佳化，以便在其個難紐域内產 生最佳之到及難效果。如此—來便可確保各μ成像單元之 曝光區域均有較佳之製程窗口，而各Μ成像單元之最佳 改善整體之製程窗口。 ^第9圖係對比習知單一透鏡投影***之製程窗口與本發 施例中陣列式成像系統之局部最佳化製程窗口。第9圖左側 知單一透鏡投影系統9〇2必須調整至如點線所示之折衷隹平面 904。圖中實線_代表基板表面之實際剖面形狀，雙箭頭^ _代表單-透鏡為圖案成像時之最佳焦點設定範圍雙= 24 201214515 戈表各成像透鏡所對應之基板表面剖面形狀最大變化範 圍’而兩條點虛物分職表焦點細之上下限。 如第9圖所不’對習知單一透鏡投影系統而言，圖中大尺寸 基板之料幅射能已超出透鏡之難制，且焦點奴範圍之 中心點可祕㈣適祕基板彎㈣面之峰部及谷部，因而限縮 整體製程窗口。第9圖右側所示之改良式投影系統則使用排成陣 歹^之成像單元，其中成像單元912之焦點914可為個別成像區 而單獨調整’因此’各焦點設定範圍（如雙圓頭線段916所示） 均妥適位於f、點㈣之上下__。除可鋪各雜區之焦點 外’各成像單元亦可調整其卿，使卿均勻度優於單一透鏡系 統調整照·之效果。是以，使轉列式之祕單元纽可提供 較佳之製程窗口。 第10圖繪不本發明實施例中一種將基板局部不平處最佳化之 方法。在此範例中已侧出基板表面形狀不平之區域，如標號臓The shape factor requires that the illumination source be a blue, near-ultraviolet LED polar body laser. In addition to achieving sufficient illumination intensity, one of the design examples in this case uses multiple illumination sources that are wrapped around the SLM and close to the SLM surface. Μ can be a thin surface with a suitable optical lens design. In the two cases, the target intensity value at the substrate is 10 to 100 mW per square centimeter in terms of effective exposure wavelength. In this exposure tool _ sample towel, each small imaging secret electronic control board shell is in accordance with the specified small shape. To facilitate heat dissipation, the housing is located on top of the SLM and away from the illumination source. The physical size of a single small s[j imaging unit depends on the imaging performance required and the t-components such as projection lenses, (10) or diodes, and hard/aligned diodes, each Components must have their space for heat dissipation. Alternatively, a custom component can be used, which reduces the form factor of the physical dimensions of the single-inch imaging unit. - The custom SIJ imaging unit has a 2D cross-sectional dimension as small as 5 cm x 5 cm; the SLM imaging unit with commercially available off-the-shelf dimensions has a 2D cross-section of approximately 1 cm x 1 cm. 22 201214515 For a tenth generation FPD process, a typical substrate size is χ3ΐ3〇. If a small SLM imaging unit is used, the entire system may contain hundreds of small SLM imaging units arranged in parallel arrays. Fig. 7 shows an example of a parallel array of SLM imaging units according to an embodiment of the present invention. In this example, the image is written simultaneously by _to_ Μ Μ imaging unit parallel arrays (10), 704, 706, 708, etc., and each parallel array may comprise a plurality of SLM imaging units. According to an embodiment of the present invention, when calculating the exposure processing amount per unit time, an example of the known unit time processing amount of the -SLM mask writing system can be used (for example, to expose the mask of Δ X X 1500 mm 2 〇 hours) as the starting point for calculation. Unit time processing 1 depends on the plane of the substrate (four degrees) ^ In this model, if the illumination intensity is 50 € watts (10) or two (four) laser source per square centimeter can provide this illumination intensity), the nominal exposure energy is 30 Millijoules per square centimeter - second, the exposure time is about G. 6 seconds. In another example, the exposure tool utilizes a high power illumination source such that the illumination intensity at the panel is at least one milliwatt per square centimeter; the reticle step/scan system has a throughput per unit time of approximately 50 per hour. The eighth generation of to substrate: In the example, if high-power and low-power illumination sources are taken into consideration at the same time, the 2-bit time prediction processing capacity is 25 to sub-substrate per hour, and the SLM imaging of each parallel array is considered. Single green. This—array parallel wire exposure has a competitive advantage. Figure 8 is a plan view of a parallel array of SLM imaging units shown in Figure 7. Here, each column or row may represent a parallel array of SLM imaging units, and each parallel array may include a plurality of imaging units. The yield of the lithography process is closely related to the process. In this case, the process window means that the focus setting range and the exposure amount setting range of the key dimensions conforming to the specifications can be printed. In other words, the more flexible the process window is, the more relaxed the set value of the out-of-focus and/or the amount of the secret light. Larger process windows help increase product yield. However, as the size of the substrate increases from generation to generation, the process window of the lithography process becomes smaller and smaller. The main reason is that the larger and more sturdy substrate material is more likely to bend and sag. In order to solve this problem, the thickness and surface uniformity of the substrate material must be strictly regulated. In the case of a reticle type exposure tool, if the exposure area is more than about two meters on one side, * only need to consume a very large cost to maintain the uniformity of the whole area; |, point control, technically difficult . The exposure tool must be able to perform partial and full optimization of the ship and _ to implement the set values of the process window. The parallel shoulder light shown in Figure 8 solves the problem of rainbow, because each small SLM imaging unit can be partially optimized to produce the best and most difficult results in its difficult field. In this way, it is ensured that the exposed areas of each μ imaging unit have a better process window, and each imaging unit optimally improves the overall process window. Fig. 9 is a comparison of a process window of a conventional single lens projection system with a partially optimized process window of the array imaging system of the present embodiment. The left side of Fig. 9 shows that the single lens projection system 9〇2 must be adjusted to the compromise plane 904 as shown by the dotted line. The solid line _ in the figure represents the actual cross-sectional shape of the substrate surface, and the double arrow ^ _ represents the optimal focus setting range when the single-lens is used for pattern imaging. Double = 24 201214515 The maximum variation range of the surface profile of the substrate surface corresponding to each imaging lens of the Ge meter 'And the two points of the virtual object division table focus on the upper and lower limits. As shown in Fig. 9, for the conventional single lens projection system, the radiation energy of the large-size substrate in the figure has exceeded the difficulty of the lens, and the center point of the focus slave range is secret. (4) The substrate is curved (four) The peaks and valleys thus limit the overall process window. The improved projection system shown on the right side of Fig. 9 uses an imaging unit arranged in an array, wherein the focus 914 of the imaging unit 912 can be individually adjusted for individual imaging zones, so each focus setting range (e.g., double rounded line segments) 916) are properly located above f, point (four) __. In addition to the focus of the various areas, the imaging units can also adjust their brightness to make the uniformity better than that of a single lens system. Therefore, the stellar secret unit can provide a better process window. Fig. 10 is a view showing a method of optimizing the local unevenness of the substrate in the embodiment of the present invention. In this example, the area of the surface of the substrate is not flat, such as the label 臓

所示。-微調式之最佳化方法係將-焦點平均程序應用於二SLM 成像單元所對應之局部不平整曝光區域以及該SLM成像單元附近 之SLM成像單元所對應之區域。該不平整區域附近可納入此平均 程序之成像單元愈多’則整體最佳化之效果愈佳。熟習此項技藝 之人士當知，本發明之成像系統亦可利用其他平均技術以提高整 片基板上之影像均勻度。 θ 在-實施例中，以薄膜電晶體（TFT)為基礎之液晶顯示器 (LCD)係使用以下所述之光罩資料格式。請注意，吾人雖可利用 25 201214515 階2式資料串流格式GDSII將光罩·交予製造業者 ’但此種光 貝料格式可能不太_於本案之平行SLM祕系統。若欲將階 層式之光罩資料扁平化’可使料f之⑽軟齡式，但光罩資 料在扁平化之後’尚須進—步處理。本案之_式平行成像寫入 系、先若搭配適w之光罩資料結構，將可形成高品質之影像。 、，就本案之_式平行成像寫人緣而言，光罩資料結構經扁 平化之後’尚需分縣預定大小之區塊，方可妥適或均勻傳送至 各SLM成像單tl。絲資料結構内之資訊不但明訂各光罩資料區 塊相對於其對應成像單元之放置位置，亦明訂橫跨多個成像單元 之圖徵應如何分#j。若欲賴雜放置位置是碰職調，可檢 視相鄰成料元所對應之相鄰鮮資料區塊之相關光罩資料处 構。 、σ 第11 _示本發明實施例中光罩龍結構之—制方式。在 此範例中’先將-包含多層光罩資料實例丨⑽之階層式光罩資料 敘述爲平化，使其形成扁平化光罩資料測。然後將此財化光 罩資料1104分割為多個分區光罩資料圖案，其中一分區光罩資料 圖案在圖巾細陰诞域11Q6表示。此陰f彡區域刪亦出現在 第11圖下方以點線劃分之九宮格中，成為其正中央之方塊。相鄰 成像單元之間須奴夠之光罩圖案重疊部分（即圖中之水平及垂 直長條部分1108)，方可確保邊界周圍之圖案能均勻融合。九宮 格中之每—方塊分別代表即將由-或多個SLM成像單元成像之一 分區光罩資料_。根據本發明之實關，分區光罩資料包含第 26 201214515 組辨識疋及第二組辨識元，其中第一組辨識元係用於辨識一⑽ 成像單元中微鏡像素過多之狀態（run七⑽ditiQns)，而第二 組辨識元則用於辨識- SLM成像單元中微鏡像素不足之狀態 (run-out conditions)。若兩SLM成像單元間之區域出現過多像 素，即為微鏡像素過多之狀態；若㊉SLM成像單元間之區域出現 像素不錢象’職纖像素不足之狀態。各分區光罩資料圖案 係傳送至對應之SLM成像單元進行處理，再由各SLM成像單元將 相關之分區光罩資料圖案寫人預定之重疊區域。各Μ成像單元 在寫入時均以相鄰之SLM成像單元為參考依據，俾雜影像融合 度及均勻度均符合設計準則。分區光罩資料圖案可經最佳化以便 進行平行加總曝光，進而提雨圖徵關鍵尺寸之一致性。使用平行 加總曝光法可降低不利於關鍵尺寸一致性之各種製程變數。進行 加總曝光時，若微鏡像素之曝光數足夠，可去除因使用二極體雷 射而產生之高斯斑點。 第12圖繪示一根據本發明實施例之平行陣列加總曝光法。此 方法先將光罩資料逐列送至各SLM成像單元，再依序照亮對應於 各列光罩資料之成列微鏡像素，其間係從各列微鏡像素之一端開 始，次第照亮至另一端。在一範例中，此方法係從方塊1201開始， 先照亮其最下方之一列微鏡像素；然後移至方塊1202 ,照亮其倒 數第二列微鏡像素；接著在方塊1203中，照亮其倒數第三列微鏡 像素。此方法接續處理方塊1204、1205、1206及1207，並照亮 其對應列之微鏡像素’然後進入方塊1208，照亮此範例中之最後 27 201214515 -列微鏡像素（即方塊最上方之一列微鏡像素）。此一逐列 照亮微鏡像素之程序將周而復始以完成對應之曝光動作，進而將 圖案寫入基板。由於縣微鏡之速度絲，特徵職可經由快速 之逐舰練序多次曝光，朗達到標稱曝光量為止。質言之， 此-圖案寫入程序係由複數個微鏡像素之個別曝光加總而成。吾 人可利用相同之加總曝光程序，並以相互協調之速度及方向移動 基板平台’從而完成整片基板之寫入作業。 ^、圖所7F之逐列她方式僅為―_，若欲使各成像單元 依=兀成平仃加總曝光中之局部或細部曝光，亦可採用其他猶環 方式。在其他實施财，亦可以行或斜向之行/顺單位，循序 進灯以有效it成平行加總曝光。此外亦可發展出其他加總方式， ，如=兩相鄰SLM成像單元交錯進行逐列照亮之程序，或同時以 夕個貝料列為起始列，分別沿多個方向進行，藉此提高微影製印 之效能’但可能尚需搭配平台之進—步移動。 若在大量生產之情況下使轉列式平行曝光法，可内建一定 ^冗餘度絲錯度赌止製程情。換言之，曝光控制常式-旦 SLM成像單元故障，將關閉故障之成像單元，並將其 夕重新分配至—或多個相鄰之成像料，以便由該等相鄰 ^單Td祕光任務，最後再卸除完祕光之基板。此—曝 程持續進行’直到整批基板完成曝光為止。而整個流 之^準為、進仃，直到成像效缺單位時間處理量均達到可接受 28 201214515 第13圖繪示本發明實施例中一種於成像寫入系統内形成冗 餘度之方法。在此範例中，成像單元212 —經發現故障，隨即關 閉。在相鄰之八個成像單元中，可擇一取代成像單元212。在此 情況下，原本由成像單元212負責之區域須待其他區域曝光完畢 後才完成寫入。 若因基板翹曲或垂陷導致兩相鄰SLM成像單元成像扭曲，該 兩SLM成像單元之間將形成微尺度之不匹配邊界（局部與局部之 間）。此不匹配邊界在第14圖中以標號14〇2表示，其中資料圖 案有部分超出框線區域外’此時重疊區助之圖餘合便需最佳 化。第14圖繪示一根據本發明實施例之楔形邊界融合法。如第 14圖所示，此方法開啟位於所選邊界末端14〇4之微鏡像素，而 此邊界末端1404則與相鄰之成像單元寫入區域刚重疊，俾使 兩區相互匹配。m概藝之人士應可瞭解，亦可以其他方式 選擇性開啟所需位置之微鏡像素，藉此達成邊界融合之目的。 根據本發明之某些實_，糾㈣或互觀方式開啟相鄰 重疊邊界間之敎織像素，村達融合之效果。根縣發明之 其他實施例，若在進行逐行照亮之加總曝絲料，搭配開啟琴 疋位置之像素，則其融合效果更佳。 此外，為使本案之陣列式平行成像系統達到預定之對準 度’本案之方法將鮮程序依序分為多個精確度等級。第—^ 等級強調整體之對轉確度，而次—對料關將目標2 29 201214515 階精準度。本案之方法㈣ 級之精確度。 ®下而上之程序，達成所需等 在一範例中共分三種精確度等級：單元透鏡之放置、透鏡中 ^微調’以及微鏡成像#料之操控。第15 _示本發明實施例 中種將SLM成像單元排成陣列Shown. The fine-tuning optimization method applies a focus-focusing procedure to the local uneven exposure area corresponding to the two SLM imaging units and the area corresponding to the SLM imaging unit in the vicinity of the SLM imaging unit. The more imaging units that can be included in this averaging procedure near the uneven area, the better the overall optimization. Those skilled in the art will recognize that the imaging system of the present invention may also utilize other averaging techniques to improve image uniformity across the substrate. θ In the embodiment, a thin film transistor (TFT) based liquid crystal display (LCD) uses the reticle data format described below. Please note that although we can use the 2012 20121515 2 data stream format GDSII to hand over the mask to the manufacturer's, this kind of optical material format may not be too much in the parallel SLM secret system of this case. If you want to flatten the grading of the reticle data, you can make the material (10) soft-aged, but the reticle material is flattened. In this case, the parallel imaging writing system of the case can be combined with the reticle data structure of the appropriate w to form a high-quality image. In the case of the parallel imaging of the case, the reticle data structure is flattened and then the block of the predetermined size of the county is required to be properly or evenly transmitted to each SLM imaging unit. The information in the silk data structure not only specifies the placement position of each mask data block relative to its corresponding imaging unit, but also how the image of the multiple imaging units should be divided into #j. If the placement position is to be touched, the relevant mask data structure of the adjacent fresh data block corresponding to the adjacent material element can be examined. σ 11 shows the method of the hood dragon structure in the embodiment of the present invention. In this example, the hierarchical mask data including the multilayer mask data example (10) is described as flattened to form a flattened mask data measurement. Then, the financial reticle data 1104 is divided into a plurality of partition reticle data patterns, wherein a partition reticle data pattern is indicated in Fig. 11Q6. This yin area is also shown in the square of the nine squares, which is divided by the dotted line below the 11th figure, and becomes the square in the center. The overlap of the reticle pattern between the adjacent imaging units (i.e., the horizontal and vertical strip portions 1108 in the figure) ensures that the pattern around the border is uniformly fused. Each of the nine squares—the squares represent one of the masked masks that will be imaged by one or more SLM imaging units. According to the practice of the present invention, the partition mask data includes the 26th 201214515 group identifier and the second group of identification elements, wherein the first group of identification elements is used to identify a state in which one (10) imaging unit has too many micromirror pixels (run seven (10) ditiQns And the second set of identification elements is used to identify the micro-mirror pixel-run state in the SLM imaging unit. If there are too many pixels in the area between the two SLM imaging units, it is a state in which the micromirror pixels are too much; if there is a pixel in the area between the ten SLM imaging units, the pixels are incapable of being in a state of insufficient pixels. Each of the zone reticle data patterns is transmitted to the corresponding SLM imaging unit for processing, and the associated stencil material patterns are written by the respective SLM imaging units into predetermined overlapping areas. Each imaging unit is based on the adjacent SLM imaging unit when writing, and the blending degree and uniformity of the noisy image are in accordance with the design criteria. The masked mask data pattern can be optimized for parallel total exposure, which in turn enhances the consistency of critical dimensions. The use of parallel total exposure reduces various process variables that are not conducive to critical dimensional consistency. When the total exposure is performed, if the number of exposures of the micromirror pixels is sufficient, Gaussian spots due to the use of the diode laser can be removed. Figure 12 illustrates a parallel array sum exposure method in accordance with an embodiment of the present invention. In this method, the mask data is first sent to each SLM imaging unit column by column, and then the array of micromirror pixels corresponding to each column of mask data is sequentially illuminated, starting from one end of each column of micromirror pixels, and the second illumination is performed. To the other end. In one example, the method begins at block 1201 by first illuminating one of the lowest row of micromirror pixels; then moving to block 1202 to illuminate its penultimate column of micromirror pixels; then, in block 1203, illuminating Its third last column of micromirror pixels. The method continues to process blocks 1204, 1205, 1206, and 1207, and illuminates its corresponding column of micromirror pixels' and then proceeds to block 1208, illuminating the last 27 201214515 - column micromirror pixels in the example (ie, one of the topmost columns of the block) Micromirror pixel). This step-by-step process of illuminating the micromirror pixels will be repeated to complete the corresponding exposure action, thereby writing the pattern to the substrate. Due to the speed of the county micro-mirror, the characteristic job can be exposed multiple times through the rapid ship-by-ship process, and the lang reaches the nominal exposure. In a nutshell, this pattern writing process is a combination of individual exposures of a plurality of micromirror pixels. We can use the same total exposure procedure and move the substrate platform at a coordinated speed and direction to complete the writing of the entire substrate. ^, Figure 7F is her only way to __, if you want to make each imaging unit 兀 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 局部 。 。 。 。 。 。 In other implementations, it is also possible to perform a line or a diagonal line/shun unit, and sequentially follow the lights to effectively add parallel exposures. In addition, other methods of summing up may also be developed, such as = two adjacent SLM imaging units are interleaved for column-by-column illumination, or simultaneously with a cemetery column as a starting column, respectively, in multiple directions, thereby Improve the performance of lithography printing, but it may still need to be matched with the advancement of the platform. If the parallel parallel exposure method is used in the case of mass production, a certain degree of redundancy can be built in. In other words, the exposure control routine - once the SLM imaging unit fails, will shut down the failed imaging unit and redistribute it to - or multiple adjacent imaging materials, so that by the adjacent Td secret light mission, Finally, the substrate of the secret light is removed. This - the exposure continues until 'the entire batch of substrates is exposed. The entire flow is normalized until the imaging effect is achieved. The processing time is acceptable. 28 201214515 FIG. 13 illustrates a method for forming redundancy in the imaging writing system in the embodiment of the present invention. In this example, imaging unit 212 is detected to be faulty and then turned off. Among the eight adjacent imaging units, the imaging unit 212 may be replaced. In this case, the area originally occupied by the imaging unit 212 is not required to be completed until the other areas are exposed. If the two adjacent SLM imaging units are image-distorted due to substrate warpage or sag, a micro-scale mismatch boundary (between local and local) will be formed between the two SLM imaging units. This mismatch boundary is indicated by the reference numeral 14〇2 in Fig. 14, in which the data pattern is partially outside the area of the frame line, and the overlap of the overlap area is optimized. Figure 14 illustrates a wedge boundary fusion method in accordance with an embodiment of the present invention. As shown in Fig. 14, this method turns on the micromirror pixels at the end of the selected boundary 14〇4, and the boundary end 1404 just overlaps with the adjacent imaging unit write region, so that the two regions match each other. Anyone who knows the art should be able to understand the other way to selectively open the micromirror pixels in the desired position to achieve the purpose of boundary fusion. According to some embodiments of the present invention, the correction (four) or the mutual view mode turns on the twitch pixels between adjacent overlapping boundaries, and the effect of the village fusion. According to other embodiments of the invention of the root county, if the total exposed silk material is illuminated line by line, and the pixel of the position of the piano is opened, the fusion effect is better. In addition, in order to achieve the predetermined alignment of the array-type parallel imaging system of the present invention, the method of the present invention sequentially divides the fresh program into a plurality of precision levels. The first-^ level emphasizes the overall correctness of the turn, while the second----the target is the target 2 29 201214515 order accuracy. The accuracy of the method (4) of this case. ®Bottom-up procedure, achieving the required, etc. In one example, there are three levels of accuracy: placement of the unit lens, fine-tuning in the lens, and manipulation of the micro-mirror imaging. 15th - showing an embodiment of the present invention, the SLM imaging unit is arranged in an array

成旱到之方法。此方法可將複數個SLM 以雷早Π 體放置準確度控制在數公厘之範圍内。然後再 t _整各ω成像單Μ投影透鏡總成之位置，使其達 2米等級之精確度。欲達此—目的，可利魏氖雷射（或其他 ^光化對準光源）將透鏡中心對準平台上之已知參考位置。最後 再控制微鏡’使其達到奈米等級之對準精確度。 根據本發明之實施例，曝光對準程序可包含下列步驟： —(1)利用平口上之已知參考位置，校準陣列中各⑽成像單 =之透鏡巾心。如此—來便可參照實體透鏡_，建立—組 陣列格點。 (2)在寫人第—光罩層時’由於基板上尚未印出任何對準記 就’基板係以機械方式鱗，且主要依賴平台之精確度。 ⑶基板麵先叙解層取得遍布基板之對準記號 ，而此 些對準記號可崎應之SLM成像單元麟。如此—來便可參照基 板上之實際景W象位置，建立一格點圖。 、⑷比較兩格點圖⑽成像單元本身之格點圖以及從基板 測得之微影製印對準記號格_)，進而建立可引導平台移動之 格點圖配對數學模型。 201214515 ⑸在範例中係針對第十代基板建構一包含The method of becoming a drought. This method can control a plurality of SLMs within a few millimeters of Ray's placement accuracy. Then t _ align the position of each ω imaging single-lens projection lens assembly to a precision of 2 meters. To achieve this, the Rayleigh laser (or other actinic alignment source) aligns the center of the lens to a known reference position on the platform. Finally, the micromirror is controlled to achieve the alignment accuracy of the nanometer level. In accordance with an embodiment of the present invention, the exposure alignment procedure can include the following steps: - (1) Calibrating each of the (10) imaging sheets in the array using the known reference locations on the flat ports. In this way, the solid lens _ can be referenced to establish a set of array lattice points. (2) When writing the human-photomask layer, the substrate is mechanically scaled because it has not been printed on the substrate, and the substrate is mainly dependent on the accuracy of the platform. (3) The substrate surface is first explained to obtain alignment marks throughout the substrate, and these alignment marks can be used by the SLM imaging unit. In this way, a grid map can be created by referring to the actual scene position of the substrate. (4) Comparing the two grid maps (10) the grid map of the imaging unit itself and the lithography alignment marker _) measured from the substrate, and then establishing a lattice model of the grid map that can guide the movement of the platform. 201214515 (5) In the example, the construction of a tenth generation substrate is included.

2400 個 SLM 成像單元之陣列，而平台之最大水平（X)或垂直⑺移動距離 、'勺為120《厘’此移動距離亦納入格點_對之計算中。請注音， 此平台移動距離甚短，因此相較於光罩式曝光工具在為第十代基 板成像時，其平台之移動距離須達基板之全寬及全長，本案之二 ’、有技術上之優勢。由於第十代基板重量可觀，若能縮短平台 負重移動之距離，將可提高祕運作之精確度。 ⑹為微調至次财#級之解精確度，本案之方法將修正 因子内建於傳送至_雜單元之鮮·+。換言之，各成像 早π之修正因何能互不_，t視各成像單元在基板上成像之 相對位置而此外，由於各基板之翹曲狀況不同，修正因子也 可能隨基板而變化。各基板之彎曲狀況可於曝光前先行倾。 第16 _示本發明實施例中—種製造撓性顯示器之無光罩 成像寫入系統範例。如第16圖所示，無光罩成像寫入系統刪 係由-或多個SLM成像單元陣列所組成，其中單一 成像單元 以標號1602表示。該-或多個SLM成像單元陣列可依特定應用之 需要1成特定形狀’如_。在另—實施例中，該無光罩成像 寫入系統可用於製造非撓性顯示器。 …第π圖繪示-根據本發明實施例之SLM成像單元。該則 成像單元包含藍光及紅光二極體雷射17〇2、孔口 17〇4、透鏡 1706、球面鏡1708、安裝於印刷電路板1712上之_ i7i〇、光 束收集裝置（beamdump)1714、分光鏡1716、電荷_合元件⑽） 31 201214515 攝影機1718以及透鏡總成1720。藍光及紅光二極體雷射㈣進 -步包含-個紅光雷射二極體（非統性）1722及四個藍光雷射 二極體（光化性）1723、Π24、1725與1726。該等雷射;2極體之 排列方式可如第17 ®所示。位於中央之紅光雷射二極體屬於非光 化性’主要係於初始無奴時作解或畔之用，至於四個屬 於光化性之藍光雷射二極體_於曝光。該等魏二極體之數量 及排列方式，亦可視雷射二極體之封裝大小而採用不同設計，只 要其照度均勻即可。在另-範例巾’亦可细光纖束傳輸該 光化照明。在此情況下，各雷射二極體係照射於光纖束之一端， 再由光纖將光化光線傳送至光纖束之另—端出光。在其他實施例 中，亦可以LED取代一極體雷射。若採用此一設計，可將多個藍 光LED緊密靠攏以提供均勻之照明強度，另將多個紅光LED分別 置於可供對準及初始對焦之位置。在此範例中，藍光及紅光二極 體雷射1702所發出之光線依序穿過孔口 17〇4及透鏡17〇6，然後An array of 2400 SLM imaging units, and the maximum horizontal (X) or vertical (7) moving distance of the platform, and the 'spoon is 120 PCT'. This moving distance is also included in the calculation of the grid point _. Please note that the movement distance of this platform is very short. Therefore, when the illuminating type exposure tool is used to image the 10th generation substrate, the moving distance of the platform must reach the full width and the full length of the substrate. The second case of this case is technically The advantage. Due to the considerable weight of the 10th generation substrate, if the distance of the platform load is shortened, the accuracy of the secret operation will be improved. (6) In order to fine-tune the accuracy of the sub-level #, the method of this case will be built into the fresh-+ of the _cell. In other words, the correction of each imaging early π can not depend on each other, t depending on the relative position of each imaging unit on the substrate, and in addition, the correction factor may vary with the substrate due to the different warpage conditions of the substrates. The bending condition of each substrate can be tilted before exposure. Fig. 16 shows an example of a photomask writing system for manufacturing a flexible display in an embodiment of the invention. As shown in Fig. 16, the reticle imaging writing system is composed of - or a plurality of SLM imaging unit arrays, wherein a single imaging unit is indicated by reference numeral 1602. The array of one or more SLM imaging units can be in a particular shape ' such as _ depending on the particular application. In another embodiment, the matte imaging writing system can be used to fabricate non-flexible displays. ... Figure π shows an SLM imaging unit in accordance with an embodiment of the present invention. The imaging unit includes a blue and red diode laser 17〇2, an aperture 17〇4, a lens 1706, a spherical mirror 1708, an _i7i〇 mounted on the printed circuit board 1712, a beam dump device 1714, Beam splitter 1716, charge-combining element (10) 31 201214515 Camera 1718 and lens assembly 1720. Blue and red diode lasers (4) Step-by-step includes a red laser diode (non-conformity) 1722 and four blue laser diodes (actinic) 1723, Π24, 1725 and 1726 . These lasers; the arrangement of the 2 poles can be as shown in Figure 17®. The red-lighted laser diode located in the center is non-photogenic. It is mainly used for the initial solution or the use of the slave, as for the four actinic blue laser diodes. The number and arrangement of the Wei diodes can also be designed differently depending on the package size of the laser diode, as long as the illumination is uniform. The illuminating illumination can also be transmitted in a thin fiber bundle on another sample towel. In this case, each of the laser diode systems is irradiated to one end of the fiber bundle, and then the optical fiber is transmitted by the optical fiber to the other end of the fiber bundle. In other embodiments, an LED can also be substituted for a polar laser. With this design, multiple blue LEDs can be brought closer together to provide uniform illumination intensity, and multiple red LEDs can be placed separately for alignment and initial focus. In this example, the light emitted by the blue and red diode laser 1702 sequentially passes through the aperture 17〇4 and the lens 17〇6, and then

…、射至球面鏡1708 ’再由球面鏡1708反射至DMD 1710。該DMD 可利用其不同狀態之微鏡，將光線直接反射至光束收集裝置 1714 ’抑或使光線經由透鏡總成1720而照射於基板。形成於基板 上之影像將向上反射，穿過透鏡1720與分光鏡1716，最後到達 CCD攝影機1718。 第18圖繪示本發明實施例中一種使用SLM成像單元線性陣 列之捲軸式無光罩微影法。在此範例中，SLM成像單元1802係排 成單一線性陣列，如第18圖所示。基板1804可在吾人之控制下， 32 201214515 沿基板移動方向（X方向）義’而SLM祕單元臓之線性陣 列則可在吾人之控制下，於基板⑽4所在之平面上，沿著垂直於 該基板移動方向之方向（Y方向）來_動。吾人可調整該⑽ 成像單元祕陣狀曝光，使其隨著基板捲動而同步處理基板 1804之特定區域。如此一來便可控制該SLM絲單元線性陣列， 使其為大於該SLM成像單元線性陣列之基板成像。第18圖所示之 成像寫人系統不但可控制該等SLM成像單元，使其沿基板移動方 向移動’亦可使其垂直於基板移動方向而移動，故可突破第咖 號專利及Ahn專额述習知方法對實體光罩尺寸之限制。 第19圖繪示本發明實施例中一種使用s〇I$料元二維陣 列之捲軸式無光罩微影法。第19嶋崎視方式繪示Μ成像單 元二維陣列1902 ’其中每-關代表—SLM成像單元。類似於第 18圖所示之範例，第19圖中之基板⑽4可在吾人之控制下沿χ 方向移動’而SLM成像單元二維陣列⑽2則可在吾人之控制下， 於基板1904所在之平面上’沿γ方向往復機。吾人可調整該 SLM成像單元二維陣列之曝光，使其隨著基板捲動而同步處理基 板1904之特定區域，如此一來便可控制該Μ成像單元二維陣 列，使其為大於該SLM成像單元二維陣列之基板成像。因此，第 19圖所示之成像寫入系統可突破第779號專利及Ahn專文所述習 矣方去Sf實H光罩尺寸之限制。請注意，在某些實施例巾，該⑽ 成像單元二維陣列可以交錯或非交錯之方式排列。 33 201214515 第20圖緣示本發明實施例中一種利用無光草微影法為多種 不同尺寸之基板成像之方法。與第19圖所示之方法類似，第2〇 圖中之成像寫入系統亦使用一 SLM成像單元二維陣列2002。SLM 成像單元二轉列證可在吾人之㈣下，自動連續接收並處理 成像負料，因此，此成像寫入系統若以無縫方式載入不同之Τρτ 光罩Η料，便可切換不同之基板設計圖案；相較之下，第，號 專利及Ahn專文所述之習知方法則須停止運作以便更換不同光 罩。在第20®所示範财，基板包含不同尺寸之基板設計圖案， 如標號2006、2_、_、麗及聰所示，而當基板捲動時， SLM成像單元二維陣列2〇〇2可即時處理該等不同尺寸之基板設計 圖案。 第21圖繪示本發明實施例中一種依照基板表面局部狀況定 位各SLM成像單元之方法。此範例之方法係於曝光過程中檢視基 板表面21G4之不平整度，並據此調整SLM絲單元線性陣列 第21圖係以詩大方式顯示基板2104之不平整度，藉此突 顯本方去將各SLM成像單元調整至最佳高度之優點。透過調整各 SLM成像單疋之最佳高度’自_焦時便可雜點調整至預定解 析度關鍵尺寸丨至5微麵f之紐範_。本方法之細節容後 述。 在—範例中，為微影製印以TFT為基礎之太陽能板（PV 卿⑴’最小隨嶋尺寸可能超過5G微米。在此郷製印解析 度關内’吾人往往將喷墨印刷法視為—成本較低之選擇。但嘴 34 201214515 墨印刷法之-主要缺點在於，墨水_有可能造成贼，此為小 滴墨水流之副作用。喷墨印刷法原本即不如微影製程乾淨，或許 可用於微影製印光翔徵，但不宜以此形成電路_線元件；喷 墨印刷法主要翻於製印非電路麵線之資訊讀取。以捲轴微影 製印法製造主動式TFT元件時，尺寸可縮放之SU成像單元陣列 由於疋件良率較高，仍為健之無光罩式微影技術方案。此方法 係透過放大投奴成無光罩式成像；^言之，SLM成像單元之曝 光透鏡並非縮小物鏡而係放大物鏡，此放大物鏡可在吾人之控制 下’將產品圖徵尺寸從25微米放大至數百微米。 /為能在未必騎平整之基板各處轉最雜錄態，方法之 -係於曝光過財監視並職SLM成像單元之缝。第22圖繪示 本發明實施财-種侧像素無之方法。若欲監·點，可利 用可穿透魏之監賴影細轉光巾之影像，紐分析所擷取 之明暗像素影像，並與職之曝細案比較，以取得失焦程度之 一相對度量。第22圖所示範例為—對明暗像素⑽2斑22〇4) 及其準焦⑽6與22G8)與失餘態⑽^朗暗交界處之 過渡圖案而言’輯準焦之明暗像素呈現對比度相雜大之過渡 圖案’而該對失焦之明暗像侧呈賴糊之過渡_，1中模糊 過渡之程度可以珊方式對應於絲之程度。在其他範例中，吾 人可I現並分析影像巾之卽鮮。由於触誤差優先降低較高 之，間頻率，吾人在擷取影像後，僅需比較影像t高頻成分之損 失置即可評估失焦之程度。另—方法係監視並分析—組明暗圖案 35 201214515 定之影像具有最高對比度， 之影像_度’其巾使岐佳焦點設; 而對比度之損失則對齡失焦之程度。 上述方法雖可有效㈣對鏡差之大小，但卻無法指明誤罢..., the shot to the spherical mirror 1708' is then reflected by the spherical mirror 1708 to the DMD 1710. The DMD can utilize its different states of micromirrors to reflect light directly to the beam collecting device 1714' or to illuminate the substrate via the lens assembly 1720. The image formed on the substrate will be reflected upward, through lens 1720 and beam splitter 1716, and finally to CCD camera 1718. Figure 18 is a diagram showing a scroll type reticle lithography method using a linear array of SLM imaging units in an embodiment of the present invention. In this example, the SLM imaging units 1802 are arranged in a single linear array, as shown in FIG. The substrate 1804 can be controlled by us, 32 201214515 along the substrate moving direction (X direction), and the linear array of the SLM module can be under the control of the substrate, on the plane of the substrate (10) 4, along the vertical The direction of the substrate moving direction (Y direction) is moved. The (10) imaging unit secret array exposure can be adjusted to simultaneously process a particular area of the substrate 1804 as the substrate is rolled. In this way, the linear array of SLM wire units can be controlled to image a substrate larger than the linear array of the SLM imaging unit. The imaging writer system shown in Fig. 18 can not only control the SLM imaging unit to move along the substrate moving direction, but also move it perpendicular to the substrate moving direction, so it can break through the No. 1 patent and Ahn quota. The conventional method limits the size of the physical mask. Fig. 19 is a view showing a scroll type reticle lithography method using a two-dimensional array of s〇I$ elements in an embodiment of the present invention. The 19th 嶋 视 方式 绘 Μ Μ Μ Μ imaging unit two-dimensional array 1902 'where each-off representative - SLM imaging unit. Similar to the example shown in Fig. 18, the substrate (10) 4 in Fig. 19 can be moved in the χ direction under the control of the person', and the two-dimensional array (10) 2 of the SLM imaging unit can be under the control of the person, on the plane where the substrate 1904 is located. On the 'reciprocating machine along the gamma direction. The exposure of the two-dimensional array of the SLM imaging unit can be adjusted to simultaneously process a specific area of the substrate 1904 as the substrate is rolled, so that the two-dimensional array of the imaging unit can be controlled to be larger than the SLM imaging. Substrate imaging of a two-dimensional array of cells. Therefore, the image writing system shown in Fig. 19 can break through the limitations of the Sf real H mask size as described in the patent No. 779 and the Ahn article. Note that in some embodiments, the (10) two-dimensional array of imaging elements may be arranged in an interlaced or non-interlaced manner. 33 201214515 Figure 20 illustrates a method of imaging a plurality of substrates of different sizes using the matte grass lithography method in an embodiment of the present invention. Similar to the method shown in Fig. 19, the image writing system of Fig. 2 also uses a two-dimensional array 2002 of SLM imaging units. The SLM imaging unit II transfer certificate can automatically receive and process the imaging negative material continuously under our (4). Therefore, if the imaging writing system loads different Τρτ mask materials in a seamless manner, it can switch differently. The substrate design pattern; in contrast, the conventional methods described in the No. Patent and Ahn articles must be discontinued in order to replace the different masks. In the 20th model, the substrate contains different substrate design patterns, as indicated by the labels 2006, 2_, _, and Li and Cong. When the substrate is scrolled, the SLM imaging unit 2D array 2〇〇2 can be instantly The substrate design patterns of the different sizes are processed. Figure 21 is a diagram showing a method of locating each SLM imaging unit according to the local condition of the surface of the substrate in the embodiment of the present invention. The method of this example is to examine the unevenness of the substrate surface 21G4 during the exposure process, and adjust the linear array of the SLM wire unit according to FIG. 21 to display the unevenness of the substrate 2104 in a poetic manner, thereby highlighting the The advantages of each SLM imaging unit adjusted to the optimum height. By adjusting the optimum height of each SLM imaging unit, the noise can be adjusted from the _ focus to the predetermined resolution key size 丨 to 5 micro-face f. The details of this method are described later. In the example, TFT-based solar panels are printed for lithography (PV qing (1)' minimum size may exceed 5G micrometers. In this case, the printing resolution is within the 'we often see inkjet printing as - The choice of lower cost. But the mouth 34 201214515 Ink printing method - the main disadvantage is that the ink _ may cause thieves, this is a side effect of the droplet ink flow. The inkjet printing method is not as clean as the lithography process, perhaps available In the lithography system, it is not suitable to form the circuit_line component; the inkjet printing method mainly turns to the information reading of the non-circuit surface of the printing. The active TFT component is manufactured by the reel lithography method. At the same time, the size-scalable SU imaging unit array is still a matt lithography technology solution due to the high yield of the device. This method is based on the magnification of the maskless imaging; in other words, SLM imaging The exposure lens of the unit is not a narrowing objective lens but a magnifying objective lens. This magnifying objective lens can enlarge the product image size from 25 micrometers to hundreds of micrometers under the control of our people. / It can turn the most miscellaneous in the substrate that does not necessarily ride flat. Recording, party The method is based on the exposure of the financial monitoring and monitoring of the SLM imaging unit. Figure 22 illustrates the method of implementing the financial side of the invention. If you want to monitor the point, you can use the penetration of Wei Zhizhi to change the light. The image of the towel, the bright and dark pixel image captured by the New Analysis, and compared with the exposure case to obtain a relative measure of the degree of defocus. The example shown in Figure 22 is - for the light and dark pixels (10) 2 spots 22 〇 4) And its quasi-focal (10) 6 and 22G8) and the transitional pattern at the intersection of the lost state (10) and the dark boundary, 'the transitional pattern of the bright and dark pixels of the quasi-focus is mixed with the contrast pattern', and the pair of defocusing The transition of the paste _, the degree of the fuzzy transition in 1 can correspond to the degree of silk. In other examples, we can analyze and analyze the freshness of the image towel. Since the touch error has a higher priority, the frequency is higher. After capturing the image, we only need to compare the loss of the high-frequency component of the image t to estimate the degree of defocus. The other method is to monitor and analyze the group of light and dark patterns. 35 201214515 The image has the highest contrast, and the image _ degree' has a good focus. The loss of contrast is the degree of defocusing. Although the above method can effectively (four) the size of the mirror, but can not specify the mistake

_’/，'〜q p又雙攝影機興物鏡間之有效光程。就 -階近似而言’改變透鏡在攝影機側之焦距（23&圖中之D與 二比例改變fl之效果相同。欲使焦點產生此-變化，可將攝影機 前後振動、或—振動之反射鏡反射影像，或者如第23a圖所 示’使光線通過—轉盤’其中該轉盤具有複數個厚度及/或折射 率不同之扇形部分’俾使有效絲產生所需之變化。上述轉盤即 圖式中之第一光程差（0PD)調變器2316及第二〇ro調變器 2326。此外，亦可利用一附有反射鏡之圓盤反射影像，其中該圓 盤具有複數個不同高度之扇形部分。 第23a圖繪示本發明實施例中一種可即時偵測SLM成像單元 焦點之裝置範例。如第23a圖所示’該裝置包含成像光源2302、 分光鏡2304、物鏡2306，以及物鏡2306之外殼2308。成像光源 23〇2之一範例如第17圖所示，包含元件17〇2至1714。該裝置亦 36 201214515 包含第-攝影感測器231〇 (以下亦簡稱攝影機或感測器）、第一_’/, '~q p and the effective optical path between the two cameras. In terms of the -order approximation, 'change the focal length of the lens on the camera side (23 & D in the figure has the same effect as the two ratio change fl. To make this focus change, the camera can be vibrated back and forth, or - the mirror of vibration Reflecting the image, or as shown in Figure 23a, 'passing the light through the turntable' where the turntable has a plurality of sectors of varying thickness and/or refractive index', causing the desired change in the effective filament. The first optical path difference (0PD) modulator 2316 and the second 〇ro modulator 2326. In addition, the image may be reflected by a disk with a mirror having a plurality of sectors of different heights. Figure 23a is a diagram showing an example of an apparatus for instantly detecting the focus of an SLM imaging unit in an embodiment of the present invention. As shown in Fig. 23a, the apparatus includes an imaging light source 2302, a beam splitter 2304, an objective lens 2306, and an objective lens 2306. The housing 2308. The imaging light source 23〇2, as shown in FIG. 17, includes the components 17〇2 to 1714. The device is also included in the 201214515, including the first-photo sensor 231〇 (hereinafter also referred to as a camera or a sensor). ,the first

馬達2312第-折射盤2314及第一 0PD調變器2316。第-0PD 調變器2316可由-圓形光學裝置2317所形成，該圓形光學裝置 2317可具有複數個扇形部分（如標號2318所示）。各扇形部分 係以具有不同折射率之材料製成，或者係以具有相同折射率但不 同厚度之材料製成，其中該等不同厚度可形成光程差。 另-種判定焦點調整方向之方法係利用兩台攝影機以不同 之光程長度擷取影像，如第23b與23c圖所示。第23b與23c圖 繪示本發明實施例中另兩種可即時_ SLM成像單元焦點之裝置 範例。除帛23a目所示元件外’此兩裝置範例尚包含第二攝影感 測器2322(以下亦簡稱攝影機或感測器）及第二〇pD調變器2326。 第23c圖尚包含第二0PD調變器2330。第二與第三〇pd調變器 2326、2330之構造可與第- OPD調變器2316類似。使用該兩攝 影感測器2310與2322時，可對應置該兩具有不同折射率之〇pD 調變器2316與2326以決定焦點調整方向。在另一實施例中，該 兩不同OPD調變器2316與2326之實施方式僅係將對應之攝影機 2310與2322設於不同距離處。 第23b與23c圖所示之範例分別檢查第一攝影感測器與第二 攝影感測器之影像’藉以比較並分析焦點調整方向，然後調整焦 點設定，以使兩攝影感測器所測得之失焦程度相等，如此一來便 可確保最佳對焦狀態係由兩攝影感測器間之一光程差決定。第一 及第二攝影感須彳器係透過互補之焦點偏移量觀測基板，以決定目 37 201214515 k、點之方向方法則不以上下移動物鏡之方式調整焦點， 而係將第三0PD調變器233〇置於物鏡23()6之外殼謂上方進 而透過改變有效光程長度之方式調整焦點。 焦點之即時監視與調整包含下列步驟： 1) 將基板表面與物鏡之間距設定在對焦範圍内。 2) 首先卩#光化照明成像並擷取此影像，此步驟不會對 曝光用之感光㈣造成任何破壞。換言之，彻非統照明設定 初始焦點，然後配合調整物鏡，以達最佳對焦狀態。 3) 曝光平台-旦開始沿基板之移動方向（X方向）移動，即 開始光化曝光。 4) 在光化照明下監視所擷取之影像，並配合調整物鏡。 5) 請注意，每次調整焦點之動作係以上一個曝光位置之最 佳曝光狀態為依據，但卻用於下一個曝光位置。 6) =康fl與f2之光程差量測值，決定物鏡之調焦幅度。 -如前述，吾人可在曝光過程中姻—或多台攝影機即時監 控影像之寫人。透過微鏡像素加總曝光法，每—影像圖案均由多 個DMD微鏡像素曝光而成。此曝光法在初始曝光階段原本即具有 較大之對餘差裕度，因為每—微鏡像素所提供之曝光僅為所需 總曝光能量之-小部分；而後在進行像素加總曝光時，尚可即時 調整各SLM成像單元之焦點。在寫入由暗區包圍之獨立「孔狀」 圖案（如第24圖所示）或由亮區包圍之獨立「島狀」圖案時，此 對焦秩差讀尤為重要，其原因在於上述兩麵徵随在吾人擾 38 201214515 動焦點設定之過程中缺少影像之變化，故不易於初始階段奴直 最佳對焦狀態，須财次曝光後村蚊其最佳對綠態。八 在另-範例中’前述之自動對焦機構可用於「焦點加總曝光」 以擴大整體辣。第25圖繪示本發明實施例巾―種透過像素加總 曝光法改善統之方法。在第25騎减财，吾人可在像素加 總曝光過程巾祕輕最佳曝光奴，如此—來便可透過焦深範 圍内之不同最佳聽狀態完成像素加祕光。經由此—方式，最 終之影像圖案係利用多種焦點設定共同曝光而成，而該等焦 點设定2502亦將擴大整體之最終焦深25Q4。 第26a與26b圖綠示本發明實施例中利用重疊區域接合相鄰 成像區之方法。第26a圖顯示兩相鄰成像區26〇2、26〇6及其對應 之SLM 2604、2608。兩相鄰成像區2602與26〇6間之區域定義為 重豐區域2610。SLM 2604之成像範圍可跨越理論邊界2612並延 伸至成像區2606内之使用者自訂邊界2614 (虛線），而SLM 26〇8 之成像範圍同樣可跨越理論邊界2612並延伸至成像區26〇2内之 另-使用者自訂邊界2616 (虛線）。由於重疊區域261q同時涵 蓋在SLM 2604與2608之成像範圍内，此方法可利用該兩相鄰成 像區中之某一區補償另一區之不一致性，例如位置上之不匹配或 曝光量之差異。 第26b圖顯不另兩相鄰成像區2622、2626及JL對麻之SLM 2624、2628。在此範例中，該兩SLM及其對應之成像區均採水平 设置’而非如第26a圖所示之垂直設置。第26a與26b圖中重疊 39 201214515 區域之走向雖然不同，但均可應用類似之技術。在其他實施例中， 水平重疊區域之處理方式亦可與垂直重疊區域不同。與第26a圖 類似，兩相鄰成像區2622、2626間之區域定義為重疊區域2630， 其中SLM 2624之成像範圍可跨越理論邊界2632並延伸至成像區 2626内之使用者自訂邊界2634 (虛線），而SLM 2628之成像範 圍同樣可跨越理論邊界2632並延伸至成像區2622内之另一使用 者自訂邊界2636 (虛線）。 若欲在重疊區域2630内成像，可令兩SLM 2624及2628之 成像強度朝彼此遞減。折線2638與折線2639 (虛線）分別概略 顯示SLM 2624與2628之成像強度。在重疊區域2630中，SLM 2624 之強度從完整強度漸變至零，而SLM 2628之強度則從零漸變至完 整強度。請注意，在此範例中，若理論邊界實質對齊成像區之實 際漸變段（例如兩者之距離在50奈米以内），則可產生良好之成 像效果。 自動化光學檢查（AOI)可應用於積體電路（iC)、印刷電路 板（PCB)及平板顯示器（FPD)之製造。以當前最先進之超大型 積體電路（VLSI)製程*言，其設計規範巾之驗線寬已達深紫 外光（DUV)曝照波長之若干分之一，約為193奈米。若欲確保 PCB、FPD及類似線寬等級之電子裝置之生產良率，則A〇I乃製程 中之一關鍵步驟。例如’ AOI可用於檢查線寬、捕捉遠小於目標 線寬之微粒、偵測基板表面之污染狀況，並找出缺漏、扭曲或多 餘之圖案。 201214515 Α0Ι可以多種方法判定一 pcB是否符合產品品質規範。第一 種方法係將’Α0Ι所得之影像與一已知參考圖案（又稱pCB黃金參 考標準）之影像進行比對。第二種方法翁所齡之影像圖案與 已知且預先儲存之良好PCB影像及劣等PCB影像進行比對。第三 種方法係触自第二種方法，並_統計學之_輯技術。詳 言之’第三種方法之輯縣包含—已知黃金參考標準及多個不 σ格度輕重有別之劣等pCB影像，如此一來便可在容許些微偏差 之條件下進行統計學判定。 就PCB及使用類似基板與類似線寬等級之電子裝置而言，腿 之主要目的健助使用者迅速判定不合袼之根本原因，以便及早 修正’避免大量電路板發生相同問題，同時亦可快速淘汰無法使 用之瑕'疵零件，進而確保產品之整體出貨品質。受限於成本、資 源與時間因素，若非為了特定工程目的，否則pcB之瑕庇品絕少 达修。在-般量產生產線中，此等瑕,疵品可能均標示為淘汰品。 另就FPD及使用類似基板與類似線寬等級之電子裝置而言， 貫& Α0Ι之目的同樣係為執行各項檢查，例如彳貞測微粒、污染狀 况及不應出現之圖案瑕疵。在各類圖案瑕疵中，肌(即曰文 「斑」）係指對比低但可目視察覺並影響目視效果之拍頻干擾圖 案。其他類型之圖案瑕疵則包括圖案缺漏、額外多出之圖案，或 兩者兼有；以上三者均會造成圖案畸變。 在處理尺寸甚大之基板時，廳之硬體機構可採用不同之配 置方式。例如，原本為掃描及擷取基板不同位置之影像而以高架 201214515 方式安胁-㈣飾之χ〜γ軌道平台上之攝賴，可改為沿水 平方向緊麟成n於雜描整塊絲之方式齡基板沿著 垂直於該觸影機之方向水平軸，並從τ方完全通過該列攝影 機。基板以此單_向方式軸時，其雜速度可麟與影像掏 取速率-致’其位置村轉在朗娜機τ方之錢範圍内。 此外，各攝影機可擷取上萬條掃描線影像，且各像素線可具有8 位元之像素，其他細_不予詳述。在—範财，可使用解析度 為7. 5微米之攝影機檢查線寬為8至1〇微米之TFT彩色遽光片 面板產品。若所缝查之錢更ΐ，例如錄查1至3微米之TFT 陣列’則可使用解析度更高之攝影機。在此例中，線寬將接近照 明波長’故讀量及影像處理之演算法㈣配合調整。 -南解析度面板產品若為視覺傳達方面之應用，則任何目視 可見之瑕納將導致無法出貨。然而，由於製造新世代產品所需 之基板愈來愈大’基板㈣價格賴之上揚，吾人實有必要針對 經由顧檢出瑕紅所有面板進行修復，而非將高價之基板材料 報廢。因此’瑕疲修復已成為FPD及類似電子裝置之—重要製程 步驟。 以第十代FPD之基板為例，一解決方案係透過顧找出瑕藏 所在位置，然後修復_以去除械。由絲板尺寸甚大，可達 2. 88x3. G8 a尺’右以人工方式修復斜分困難，最好能以機器 人進行自動化修復。吾人可設置機器人，使其自動執行各種瑕疵 U復工序’例如去除表面外來微粒、以雷射爛或強力氣流移除 42 201214515 讀之圖案’以及在職稀疏處局部沉積與製軸容之薄膜以增 ，缺漏之部分κ案。以上工辆可透過賴運算法執行。顯可 提供精確之位置、定義待修復之區域、制職職之類型（例 如缺漏或多餘），並與預定之參考圖案進行比對，因此，後續須 處理之問題即為如何從兼有缺漏_及多餘_之畸變圖案瑕 疵中重建所需之圖案。 …在找出畸顏紐，若欲去除法及局㈣膜沉積法 進订圖案之重建，就初級影像處理而言，必須先辨識圖案之哪些 部分出現缺漏及/或出現不應有之多餘圖案。為此，可利用一懸 成像單元棘贼影像，並使所擷取之影像與原始光罩圖案產生 關聯。詳言之，可利用—SLM成像單元陣列執行影像掃描，但該 等SLM成像單元僅擷取圖案影像而未實際進行曝光。或者，可在 ϋ系財安裝單-SLM成像單元。該做系統在完成瑕鋪 型之分析’並判定有必要進行後續之瑕錄視及分類後，將命令 該額外設置之SLM成像單元執行上述動作。在第脱圖之左侧圖 式中’兀件2810已判定為一瑕疲’詳言之則為兩平行矩形咖 間之-多餘圖案。在第28c圖之右側圖式中，瑕疲_經判定 後已從原始光罩上移除（以虛線間之白色區域表示）。 根據本發明之實施例，另一種在綱後重建圖案之方法係利 用SLM成像單元在出現贼之局部區域以無光軍成像法修復圖 案。此成像法須搭配光阻之局部或全面重塗。若須局部重塗，光 43 201214515 佈於部分區域，隨即顯影。但若基板上有 建，最好整塊基板均重贿上級。 ㈣㊉要重 此方法類餘單_肖義之微歸程，料 瑕賴案需再次成像以達圖案重建之目的。此方法可以單:SLM 成像早几或-SLM成像單元陣列完成再次圖案化，其首 對準已圖案化之區域’-如以SLM成像單元執行光罩對準之動 作。但錢局部成躲而言，此對準動作係對準前次之光罩層， 而非如首次微影曝光時可將光罩圖案平行寫人。詳言之，在重曰 圖案時係對準已完成侧之光罩層圖案，因此，所對準之光罩圖 案可能在外觀上已與原光罩圖案不同，端視其實際經歷之製程條 件而定。重建_時驗製程條件列人考量因素，方能使重建後 之圖案與周遭圖案更加匹配。換言之，重新成像時須納入製程修 正因子，例如將重建圖案區放大或縮小。 在第28d圖中’左側之瑕，疵圖案已力口入一已知製程修正因 子，右側圖式則顯示瑕_案之成像對準關聯性，亦即以瑕疲所 在位置實騎見之職與先前娜之贼圖案槪。位於右侧圖 式中央之J ϋ色區域2820顯示對準關聯性甚高，故可精禮判 定瑕疲位置（即圖案重建位置）。在將製程條件因子納入重建之 影像後，即可進行無光罩曝光以完成局部圖案之重建。 第27a與27b圖繪示本發明實施例中量測及使用相鄰SLM成 像單元中心間之視點間距之方法。在第27a圖所示實施例中係使 用四個排成一列之SLM。視點間距（I0D)係兩相鄰SLM中心間之 44 201214515Motor 2312 first-refractive disk 2314 and first 0PD modulator 2316. The -0PD modulator 2316 can be formed by a circular optical device 2317 that can have a plurality of sectors (as indicated by reference numeral 2318). Each of the sector portions is made of a material having a different refractive index, or is made of a material having the same refractive index but different thicknesses, wherein the different thicknesses can form an optical path difference. Another method for determining the direction of focus adjustment is to use two cameras to capture images at different path lengths, as shown in Figures 23b and 23c. Figures 23b and 23c illustrate two other examples of devices that can be focused on the SLM imaging unit in an embodiment of the invention. Except for the components shown in Fig. 23a, the two device examples further include a second photographic sensor 2322 (hereinafter also referred to as a camera or sensor) and a second 〇pD modulator 2326. Figure 23c also includes a second OFDM modulator 2330. The configuration of the second and third 〇pd modulators 2326, 2330 can be similar to the epoch-OPD modulator 2316. When the two photo sensors 2310 and 2322 are used, the two 〇pD modulators 2316 and 2326 having different refractive indices can be correspondingly arranged to determine the focus adjustment direction. In another embodiment, the implementation of the two different OPD modulators 2316 and 2326 merely sets the corresponding cameras 2310 and 2322 at different distances. The examples shown in Figures 23b and 23c respectively examine the images of the first photographic sensor and the second photographic sensor to compare and analyze the focus adjustment direction, and then adjust the focus setting so that the two photographic sensors measure The degree of defocus is equal, so that the best focus state is determined by the optical path difference between the two photographic sensors. The first and second photographic sensory devices observe the substrate through the complementary focus offset to determine the direction of the target. The method of adjusting the focus is not to move the objective lens, but the third 0PD is adjusted. The transducer 233 is placed above the outer casing of the objective lens 23 () 6 to adjust the focus by changing the effective optical path length. The immediate monitoring and adjustment of the focus includes the following steps: 1) Set the distance between the substrate surface and the objective lens within the focus range. 2) Firstly, illuminate the illumination and capture the image. This step will not cause any damage to the exposure (4). In other words, the backlight is set to the initial focus, and then the objective lens is adjusted to achieve the best focus. 3) The exposure platform starts to move along the moving direction of the substrate (X direction), that is, the actinic exposure is started. 4) Monitor the captured image under actinic illumination and adjust the objective lens. 5) Please note that each time the focus adjustment is based on the best exposure status of the above exposure position, it is used for the next exposure position. 6) = The optical path difference measurement of Kang fl and f2 determines the focusing range of the objective lens. - As mentioned above, we can monitor the image writers instantly during the exposure process or by multiple cameras. Through the micro-mirror pixel total exposure method, each image pattern is exposed by a plurality of DMD micro-mirror pixels. This exposure method originally has a large margin margin in the initial exposure phase because the exposure provided by each micromirror pixel is only a small portion of the total exposure energy required; then, when performing pixel total exposure, The focus of each SLM imaging unit can be adjusted instantly. This focus-rank difference reading is especially important when writing a separate "hole-like" pattern surrounded by dark areas (as shown in Figure 24) or a separate "island-like" pattern surrounded by bright areas, because of the above two sides. There is a lack of image change in the process of setting the focus of the 201264415 moving focus. Therefore, it is not easy to get the best focus state in the initial stage, and it is necessary to have the best green state after the financial exposure. Eight In another example, the aforementioned autofocus mechanism can be used for "focus plus exposure" to expand the overall spicy. Fig. 25 is a view showing a method for improving the system by the pixel total exposure method according to the embodiment of the present invention. In the 25th ride to save money, we can use the best exposure slave in the pixel exposure process, so that you can complete the pixel plus secret light through different best listening states in the depth of focus. In this way, the final image pattern is jointly exposed using a plurality of focus settings, and the focal point setting 2502 will also enlarge the overall final depth of focus 25Q4. The 26a and 26b diagrams illustrate a method of joining adjacent imaging regions using overlapping regions in an embodiment of the invention. Figure 26a shows two adjacent imaging zones 26〇2, 26〇6 and their corresponding SLMs 2604, 2608. The area between the two adjacent imaging regions 2602 and 26〇6 is defined as the rich region 2610. The imaging range of the SLM 2604 can span the theoretical boundary 2612 and extend to the user-defined boundary 2614 (dashed line) within the imaging zone 2606, while the imaging range of the SLM 26〇8 can also span the theoretical boundary 2612 and extend to the imaging zone 26〇2 The other - user-defined boundary 2616 (dashed line). Since the overlap region 261q is simultaneously covered in the imaging ranges of the SLMs 2604 and 2608, the method can utilize one of the two adjacent imaging regions to compensate for the inconsistency of another region, such as a mismatch in position or a difference in exposure. . Figure 26b shows two adjacent imaging zones 2622, 2626 and JL on the SLM 2624, 2628. In this example, the two SLMs and their corresponding imaging zones are both horizontally set instead of the vertical settings as shown in Figure 26a. Overlapping in Figures 26a and 26b 39 201214515 Although the direction of the region is different, similar techniques can be applied. In other embodiments, the horizontal overlap region may be treated differently than the vertical overlap region. Similar to Fig. 26a, the region between two adjacent imaging regions 2622, 2626 is defined as an overlap region 2630, wherein the imaging range of the SLM 2624 can span the theoretical boundary 2632 and extend to a user-defined boundary 2634 within the imaging region 2626 (dashed line The imaging range of the SLM 2628 can also span the theoretical boundary 2632 and extend to another user-defined boundary 2636 (dashed line) within the imaging zone 2622. If imaged within the overlap region 2630, the imaging intensities of the two SLMs 2624 and 2628 can be diminished toward each other. The fold line 2638 and the fold line 2639 (dashed line) schematically show the image intensities of the SLMs 2624 and 2628, respectively. In the overlap region 2630, the intensity of the SLM 2624 is ramped from full strength to zero, while the intensity of the SLM 2628 is ramped from zero to full intensity. Note that in this example, if the theoretical boundary is substantially aligned with the actual transition of the imaging zone (for example, the distance between the two is within 50 nm), a good imaging effect can be produced. Automated Optical Inspection (AOI) can be applied to the fabrication of integrated circuits (iC), printed circuit boards (PCBs), and flat panel displays (FPDs). According to the current state-of-the-art VLSI process, the line width of the design specification towel has reached a fraction of the wavelength of the deep ultraviolet (DUV) exposure, which is about 193 nm. If you want to ensure the production yield of PCBs, FPDs and similar line-width electronic devices, then A〇I is one of the key steps in the process. For example, AOI can be used to check line widths, capture particles that are much smaller than the target line width, detect contamination on the substrate surface, and find missing, distorted, or redundant patterns. 201214515 Α0Ι can determine whether a pcB meets the product quality specifications in a variety of ways. The first method compares the image obtained by 'Α0Ι with the image of a known reference pattern (also known as the pCB gold reference standard). In the second method, the image pattern of Weng's age is compared with known and pre-stored good PCB images and inferior PCB images. The third method is based on the second method, and the _statistics technique. In detail, the third method of the county contains - known gold reference standards and a number of inferior pCB images that are not σ σ, so that statistical determination can be made under conditions that allow for slight deviations. For PCBs and electronic devices that use similar substrates and similar line width grades, the main purpose of the leg is to help users quickly determine the root cause of the inconsistency, so as to early fix 'avoid the same problem with a large number of boards, and also quickly eliminate Use the '瑕 parts to ensure the overall quality of the product. Subject to cost, resource and time factors, if not for specific engineering purposes, the PCB's refuge is rarely repaired. In the general production line, these defects may be marked as obsolete. In the case of FPDs and electronic devices that use similar substrates and similar line width grades, the purpose of the & Α Ι Ι Ι is also to perform various inspections, such as speculating particles, contamination, and patterns that should not occur. Among the various types of designs, the muscle (ie, the "plaque") refers to the beat interference pattern that is low in contrast but visually perceptible and affects the visual effect. Other types of patterns include pattern missing, extra patterns, or both; all of the above can cause pattern distortion. When dealing with very large substrates, the hardware mechanism of the hall can be configured differently. For example, the original image of the different positions of the substrate for scanning and capturing is protected by the high-rise 201214515- (4) χ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ γ The age of the substrate is along a horizontal axis perpendicular to the direction of the illuminator and passes completely through the column camera from the τ side. When the substrate is in the single-axis mode, its miscellaneous speed and image capturing rate--the position of the substrate is within the range of the money of the Lanna machine. In addition, each camera can capture tens of thousands of scan line images, and each pixel line can have 8-bit pixels, and other details are not detailed. In the case of Fancai, a TFT color stencil panel product with a line width of 8 to 1 μm can be inspected using a 7.5-micron camera. If the money you are checking is more ambiguous, such as recording a 1 to 3 micron TFT array, you can use a higher resolution camera. In this case, the line width will be close to the illumination wavelength', and the reading and image processing algorithm (4) will be adjusted. - If the South Resolution Panel product is for visual communication applications, any visually visible Cannes will result in an inability to ship. However, as the number of substrates required to make new generations of products has grown larger. The price of the substrate (four) has risen. It is necessary for us to repair all the panels that have been detected by the blush, rather than scrapping the high-priced substrate materials. Therefore, fatigue repair has become an important process step for FPDs and similar electronic devices. Taking the substrate of the 10th generation FPD as an example, a solution is to find out where the shoal is located and then repair _ to remove the device. The size of the silk plate is very large, up to 2. 88x3. G8 a ruler right to repair the oblique points manually, it is best to automate the repair by the robot. We can set up robots to automatically perform various 瑕疵U complex processes, such as removing surface foreign particles, removing lasers or strong airflow, and the pattern of local deposition and shafting at the job sparse. The missing part of the κ case. The above vehicles can be executed by the Lai algorithm. It can clearly provide the exact location, define the area to be repaired, the type of job (such as missing or redundant), and compare it with the predetermined reference pattern. Therefore, the problem to be dealt with later is how to get the gap. And the pattern of the necessary distortion is reconstructed in the distortion pattern. ...in finding out the distortion, if you want to remove the method and the (4) film deposition method to rebuild the pattern, in terms of primary image processing, you must first identify which parts of the pattern are missing and/or there are unwanted patterns. . To this end, a suture image of the imaging unit can be utilized and the captured image is associated with the original reticle pattern. In particular, image scanning can be performed using the SLM imaging unit array, but the SLM imaging unit only captures the pattern image without actually exposing it. Alternatively, a single-SLM imaging unit can be installed in the system. After the system performs the analysis of the shop type and determines that it is necessary to perform subsequent recording and classification, the SLM imaging unit that instructs the additional setting performs the above actions. In the diagram on the left side of the first figure, 'the piece 2810 has been judged to be a squeaky'. In detail, it is a redundant pattern between two parallel rectangles. In the right diagram of Figure 28c, the fatigue _ has been removed from the original reticle after the determination (indicated by the white area between the dashed lines). In accordance with an embodiment of the present invention, another method of reconstructing a pattern after the scene utilizes the SLM imaging unit to repair the pattern in a localized area of the thief in the absence of a light image. This imaging method must be combined with partial or total recoating of the photoresist. If partial recoating is required, light 43 201214515 is placed in a partial area and developed. However, if there is a built-in substrate, it is preferable that the entire substrate is heavily bribed. (4) Ten must be heavy This method class balance sheet _ Xiao Yi's micro-return, it is necessary to re-image to achieve the purpose of pattern reconstruction. This method can be single: SLM imaging early or - SLM imaging unit array completes re-patterning, with the first alignment of the patterned area' - such as performing a mask alignment operation with the SLM imaging unit. However, in the case of partial hiding of the money, the alignment action is directed to the previous mask layer, rather than the hood pattern being written in parallel as in the first lithography exposure. In detail, when the pattern is repeated, the pattern of the mask layer on the completed side is aligned. Therefore, the aligned mask pattern may be different in appearance from the original mask pattern, depending on the actual process conditions. And set. Reconstruction _ time-test process conditions are considered in order to make the reconstructed pattern more closely match the surrounding pattern. In other words, the process correction factor must be included in the re-imaging, such as zooming in or out of the reconstructed pattern area. In the picture on the left side of the 28d picture, the 疵 pattern has been forced into a known process correction factor, and the right picture shows the image alignment correlation of the 瑕_ case, that is, the position of the squatting position With the thief pattern of the former Na. The J color area 2820 located in the center of the right figure shows that the alignment is very high, so the position of the fatigue (ie, the pattern reconstruction position) can be determined. After incorporating the process condition factor into the reconstructed image, a maskless exposure can be performed to complete the reconstruction of the partial pattern. Figures 27a and 27b illustrate a method of measuring and using the viewpoint spacing between centers of adjacent SLM imaging units in an embodiment of the present invention. In the embodiment shown in Figure 27a, four SLMs arranged in a row are used. Viewpoint spacing (I0D) is between two adjacent SLM centers.

向量值距離。舉例而言，I〇D-x係SLM 2702與SLM 2704兩者中 心間之距離；同樣地’ I〇D-y係SLM 2702與SLM 2706兩者中心 間之距離。在第27b圖中，整個成像區係分割為一網格中之多個 子區，如子區2708、2710、2712及2714。各子區對應於-SLM 之成像區。在此例中，用以為子區27〇8及271〇成像之兩SLM間 之視點間距經量測為IOD-x，用以為子區271〇及2714成像之兩 SLM間之視點間距經量測為I〇D—y。一旦測得系統中對應ω間 之I0D，系統即可利用此訊息進行校準，並產生用以控制系統中 各SLM曝光方式之光罩資料。透過I〇D之應用，即便各SLM並非 位於其成賴之巾央，祕仍可湘IGD製備光罩資料，從而補 償SLM在系統中之任何對準誤差。 第28a與28b圖繪示本發明實施例中成像寫入系統量測及修 正對準狀態之方法。在第28a圖中，部分SLM係經轉動，例如SLM 1與SLM 3係略向右轉，SLM 5、6、8係略向左轉，而SIJ成像 單元7、9則略向右轉（所有轉動幅度在圖中均誇大表示）。此 等轉動誤差可於常規之⑽設定m賴作#巾彳貞得並加以 判定。在此例中，轉動修正因子經量測為0SLM。一旦測得系統中 各SLM之0SLM，系統即可利用此資訊進行校準，並產生用以控制 系統中各SLM曝光方式之光罩資料。透過轉動修正因子之應用， 即便各SLM相對於其成像區之方位並不完全準確，系統仍可利用 轉動修正因子製備光罩資料，從而補償SLM在方位上之任何誤 差舉例而5，SLM #7 2803其成像區之轉動修正因子經量測為 45 201214515 在製備光罩資料時，系統將納入此等轉動修正因子，並產 生對準之光罩資料2804。 第28b圖繪示本發明實施例中之一圖案識別同形對準法。在 此例示方法中可以多個預定圖案作為地標，俾以圖案識別為基礎 擁取對準目標之影像。舉例而言，可沿成像區之邊緣使用加號（+) 2805作為邊界之識別符號。此外，可以既有之設計圖案（即圖中 之E及F) 2807標示相鄰SLM間成像區之角落。根據本發明之實 施例，SLM可同步尋找對準目標。一旦使用對準目標，系統便可 求得一組修正因子，例如偏移量、轉動修正量、及縮放因子。若 有足夠之額外對準記號，更可計算出非線性畸變（例如軸線彎曲 或梯形畸變）之修正量。系統可據以產生光罩資料，進而利用上 述之修正i子’使所需之醜纖解鮮記狀實際量測位 置。 過去四十年來，互補式金屬氧化物半導體（CMOS)之設計尺 寸在摩爾定律（M〇〇re’s Law)之驅使下不斷縮小，使IC元件製 造商得以在烟之⑼面納，縣元件世代之更迭而加入愈來 愈多功能或電晶體，同時提高元件之操作頻率，並降低整體之晶 片成本。但經濟效益終已到達極限。由於縮小CM〇s尺寸之技術 難度已愈來愈高，若欲製造小於2〇奈米之次世代元件，所需之 資本投資已非業界—般賴所能負擔。纽微影曝光工具一項而 言’職之升級成本可能連業界龍頭都望之怯步。為如成本較 低之方式軸提升祕效能及尺指,!、化之目標，抑或為了落實 46 201214515 入超越摩爾疋律」之概念，業界已於十年前開始注重系統之整 合’而非一味增加電晶體密度。 近來’透過石夕通孔（TSV)互連而實現之三維封裝技術已提 供一種可突破摩爾定律之尺寸縮小途徑。三維封裳技術使異質整 合具有可行性，.㈣使吾人得以在空_小之雖體内整 ㈣、邏輯、記憶體及臟感測器等元件。三維封裝技術既不同 =統單晶片⑽），亦不同於「超越摩爾定律」之概念；系統 二曰曰片係不斷增加二維晶片面積内之電晶體數量，而「超越摩爾 定律」之概念則須將設計尺寸縮小至極致。三維封裝技術之資本 投資門榼較低，對諸如智慧型行動裝置等次世代消費性裝置之製 造商而言，其經濟效益極具吸引力。其實，上述裝置早已成為三 維封裝技術之主要推動力之一。在強大之市場需求帶動下，儘管 =景氣衰退，業界仍快速開發出三維系統整合封裝所需之各種 製&工具、製程及技術。 三維封裝技術共有兩種，-種稱為「三_ (Si)整合」， 維1α合」’雨者皆以石夕通孔為基礎，但各 去了提^t]造難度。三㈣整合技術又稱為晶圓鍵合，此方 法可k供較佳之電性效能，且 低，單位時間產出量聰高。4低’產品之高度與重量亦較 密产1二整目^可㈣曾加數蝴_⑽s影像感測器之 也、度。奴達此目的’可以r給 之相關應用也可使用三維糾技術搭配料孔。記憶體 且技術，藉以縮小產品所佔面積，同 201214515 時滿足提高記憶體密度之嚴格要求。第29a至29d圖繪示本發明 實施例中之三維積體電路無光罩平行製造法。第29a圖共顯示三 種形成矽通孔之方式，亦即先鑽孔（via-first)、製程中鑽孔 (via-middle)及後鑽孔（via-last);顧名思義，三者分別表示 矽通孔係於1C製造完成前、製造過程中及製造完成後形成。在 第29a圖之範例中’二種類型之碎通孔均以剖面圖顯示。無論何 種類型之矽通孔（深灰色），其通孔圖案皆先透過微影技術形成， 然後於矽基板上蝕刻出一深溝，並以披覆方式在溝内填入導電金 屬，如銅。接著研磨矽基板之背面，使基板逐漸變薄，終致使矽 逍孔露出於基板背面。如此一來，露出之矽通孔便可直接連接至 具有相配矽通孔設計之另一晶片。 矽通孔之設計規則係以「直徑/間距」及「高寬比」（即深 度與直徑之比）訂定之。在一範例中，直徑/間距比可為50/250 微米，高寬比則為5:1。在另一範例中，直徑/間距比可縮小為 10/100微米，高寬比為10:1 ;或直徑/間距比為5/5〇微米，高 寬比為16:1 ;或直徑/間距比為3/5〇微米，高寬比為16:1 ;或 直控/間距比為1/2G微米’高寬比為2()]。就圖案之微影形成 技術及蝕刻技術而言，上述直徑/間距比屬於合理範圍，但深溝 被覆技術則尚雜合鮮雜。為提供絲之製紅序，實有必 要改良既有開發流程’例如提升通孔形成技術之電性可靠度、改 善對嚴重f曲/_之薄晶圓之處财式、提高熱能f理二率， 及改進堆疊晶片之測試方式等。 48 201214515 方法之-躲料孔製轉料職賴合，_，晶粒良 率卻可能受到“影響。例如，若—具有許多良品晶粒之晶圓在 完成後鑽孔製織輯報廢，_晶粒㈣之影響甚大。另一方 法係直接與另-晶片接合，但此另—晶片可能係由另一業者設 計，且未必係由相容之半導職_造而成。 再-方法細傳統製程製作le .⑻並駐測試之 ，以便與 其他晶片互連。此方法做料有料孔之鶴巾介層，並將ic 晶片黏附於此中介層上，之後再行職。中介層可树或玻璃製 之基板材料，其形狀/尺寸則類似碎晶圓或矩形之玻璃基板。中 介層之作用絲載具有大量輸出八軒及高密度路由線（自封 裝體至PCB)之1C。此種被動中介層並未設置主動元件，可由代 工廠或以外包方式另行製造。 第29b圖係-中介層實施例之剖面圖，其中一特定應用積體 電路（ASIC)邏輯晶片與一動態隨機存取記憶體（DRAM)晶片 堆疊體係⑽☆置’且接合闕_被動巾介層。在該誦堆叠 體之各記憶體晶片之間可使用另一類型之矽通孔。 右欲在主動巾介層上軸贿，亦即餅通孔之圖案形成於 1C兀件晶圓上，可利用SLM陣列（Array 〇f SLMs，以下縮寫為 AOS)無光罩直接成像工具搭配整合元件製造商⑽）或代工礙 之既有曝紅具’並⑽搭（mix_n_mateh)方鱗^，其單位 時間產出量可達-定轉。以製程巾狐而言，應在設置電晶體 及鶴質接點之料層後執行—鮮步驟’然後再形成多層銅質互 49 201214515 連體，以便在通孔至通孔間距較大之矽通孔内形成直徑3至5微 米之互連結構。至於後鑽孔製程之實施方式係先將晶圓打薄再 將晶圓暫畴合於紐上，織從晶圓背面以爛方式形成石夕通 孔，直到蝕刻至阻擋層為止；此種矽通孔之直徑介於8與1〇微 米之間。 用於行動裝置之第三代雙倍資料率同步動態隨機存取記憶 體CDDR3 DRAM)必須縮小尺寸並降低耗能。就記憶體Ic而言， 10至50微米厚之矽材可設置高寬比（AR)為5:1至1〇:丨之通 孔，並以電鍍方式在通孔内形成銅質互連體；換言之，通孔直徑 為2至5微米。此直徑範圍大致符合可交由IDM及代工廠製作之 ▲夕通孔之直徑。 若欲透過被動中介層形成矽通孔之圖案，可由封測代工廠 (〇SAT)代勞。此種中介層之最終矽材目標厚度可為100至140 微米。中介層之厚度若減至100微米以下，硬質矽晶圓將變為撓 性矽箔。就通孔直徑而言，若高寬比為5:1，則矽通孔直徑之成 像目標可能在20至30微米左右。一矽質中介層包含由被覆銅線 所組成之重分布層（RDL)，其中被覆銅線之線寬與間距分別接近 對應石夕通孔之直徑與間距。 上述之線寬及直徑均在本案以405奈米曝光波長進行AOS無 光罩直接成像之能力範圍内。中介層可以多種方式運用，例如， σί透過中介層使原本過時之元件得以應用於難以重新設計之電 路板上。OSAT若欲與代工廠或IDM在中介層之商業應用上一較高 201214515 =，可提财質中介層之快速設計、製作，以及小量乃至大 置生產之職’並透過在中介層上重新布由狀方式，使複 ^之基板符合鮮大小；此外_其他細服務。在執行上述 4業時本案之A〇s無光罩直接成像技術可提供快速轉換，其靈 活度為W光罩式曝光工具（包括步進式緣及光罩對準系統） 所無法企及。 本案之A0S無光罩直接成像系統尚可在處理有變形之虞（例 如^與翹曲）之超·板物絲切之解魏。透過本文所 揭露之方法’本發明之廳無光罩直接成像系統可有效率地「拉 伸」光罩貞料賤合既有之基板賴’從而達成局部對準之目 的。習知光罩式微影技術則無此功能。 在另-方法中’本案之A〇S無光罩直接成像系統係用於形成 主動石夕質中介層上之魏孔圖案。為將三維IC整合元件之熱性 質^電氣性質最佳化，或有必要在研究或開發階段，或者在為同 一晶圓進行不同制目的之分織計時，針鮮通孔在主動晶粒 ^之叹置方式進行實驗設計⑽E)。本案之廳無光罩直接成像 系統可有效麵達成此-目的，故錢為此訂購任何光罩。 第29c圖係一二維積體電路之配置圖p如本範例所示，配置 圖中之各區塊（即A、B、C、D、E、F、G)分別代表該積體電路 之p卩分及其在一晶圓上之對應區域。延伸於區塊a與c之間、 區塊A與E之間及區塊c與G之間之線段分別代表該等區塊彼此 互通所需之路由線。熟習此項技藝者即可明瞭，在一具有數十億 51 201214515 個電晶體之積體電路中，區塊間通訊信號之路由十分複雜，其設 計難度甚高，所涉及之問題包括電阻電容延遲效應、串音干擾、 耗能及形狀因數等，在在均對積體電路之成本有直接影響。 本發明所揭露之系統及方法可解決第29c圖中系統單晶片之 設計問題，特別是用於晶粒至晶粒、晶粒至晶圓以及晶圓至晶圓 之一維接合，俾以更有效之方式製造三維積體電路。如第2犯圖 所示’積體電路可以三維;5*式排列ϋ大幅縮短各區塊間通訊 #號之路由長度。在此例中，區塊Α與C係位於積體電路之第一 層，而區塊8、〇、£、卩、0則位於積體電路之第二層。凡熟習此 項技藝之人均可明瞭，該積體電_之層數亦可多於兩層，以 達該積體電路之特定設計及成本目的。延伸於區塊A與E之間、 區塊八與13之間、區塊八與11'之間、區塊C與B之間、區塊c與 F之間’及區塊C與G之間之垂直線代表圖示積體電路中不同層 區塊間之通訊信號路由。由於此等路由線係以三維方式排列，其 長度已大幅縮短。在其他實施例中，可將類比電路與數位電路分 設於三維積體電路之不同層内。在另些實施辦，亦可將電路之 電源及接地平面分設於三維積體電路之不同層。 右以習知方法製造三維積體電路，積體電路之每一層均須使 用光罩’但在設計過程中往往必須多次迭代方可同時滿足功 能、效能及絲等衫蚊輯鮮。射之，錢計及驗證過 程中，積體電路各層所職之鮮#可能f要修改，因而增加積 體電路之開發成本賴發_。但若仙本㈣之祕寫入系 52 201214515 統，各層電路設計_之形成便不須借助光罩。此外，若採用本 發明成像寫人系統之多晶圓直接成像法，則積體電路中之複數層 將可平行製造，進而減少積體電路之開發成本並驗開發時間。 根據本發明之實_，核之成職人錢可祕料孔之 「先鑽孔」製程，以利三維積體電路晶片之接合。本案之無光罩 方法可取代使用光罩之習知填充步驟，此填充步獅為前段製 程（祖）前之加工工序（工序υ中之第二步驟，或為前段製 程後之加工工序（工序2)中之第三步驟。同樣地，本案之成像 寫入系統可用_通孔之「後鑽孔」製程，以利三維積體電路晶 片之接合。本案之無光罩方法可取代—使用光罩之習知填充步 驟，此填充步驟縣後段製程⑽〇L)前之加工工序（工序幻 中之第三步驟，或為後段製程後之加工工序（I序4)中之第五 步驟。 請注意’由於石夕通孔之通孔光罩圖案大多採用尺度不同於其 他光罩_之_尺寸，本餘光罩方法之靈活度恰可發揮極^ 之助益；因為若採用習知方法，麻最先進之曝紅具製作通孔 =罩圖案之經濟效益甚低，她之下，以最先進之曝光工具在前 段製程中形絲罩層職合贿效益。—如前述，本案成像寫入 系、、先可在成像過程中進行縮放比例修正、視點間距修正及轉動因 子修正’故可降低產品開發成本並縮短產品開發時程。 第30圖繪示本發明實施射—種多關之直接成像法。在 第30圖所示範例中係以—3χ6 Μ _為兩枚直徑公厘之 53 201214515 晶圓平行成像’其中第一晶圓3002可由第一組3χ3 SLM陣列成 像’第-晶圓3GG4可由第二組3x3 SLM陣列成像。透過此—方 法，各晶圓可包含一三維積體電路之不同設計圖案或不同層。此 外各SLM可為不同類型之通孔成像。再者，各SLM可用於執行 不同之〜像接合運异、縮放比例修正、視點間轉正及轉動因 修正。 根據本發明之實關’本案之SLM陣列可平域理複數枚晶 圓。例如，-3x3 SLM陣列可為九牧2忖晶圓成像而不須進行影 像之接合，其中各牧2叶晶圓係由一對應之slm錢成像，且本 案之成像寫人系統可分別控制各SLM以使九枚晶圓平行曝光。類 U於第3G圖之例’各SLM亦可執行不同之影像接合運算、縮 放比例修正、視點間距修正及轉動因子修正。在另一方法中，可 细3x3SLMP車列為九塊2_pCB成像，其中各pcB係由一對 應之SLM直接成像’且本案之成像寫入系統可分別控制各則以 使九塊PCB平行曝光。凡熟習此項技藝者即可瞭解，所述sij陣 =可有所調整以因應不同之製造需求，例如，可使用一 4χ6、㈣ 或12x12 SLM陣列為複數個以對應方式排列之2付晶圓或μ平 行成像。 在第30圖所示範例中，該鄕#光罩直接成像系統之排列 式可為複數枚綱公厘晶圓或矩形中介層基板（可·主動或 動發通孔巾介層）曝光。魅射介層衫，晶®之裝載方式 可叹计為與光罩式曝光系統相容。就矩形中介層基板而言，由於 54 201214515 其騎度與對準精確度之要求較低，除可以機器自動裝載外，尚 可乂手動方式裝裁。此種A〇s曝光系統可將多於一枚晶圓或基板 裝載曝光平台上以便同時掃描曝光，端視所需之單位時間 產出量而定。第3〇圖所示之範例係為兩枚晶圓平行曝光。 在明圓裝载過&巾，須先辨別晶圓之方位，然後再將晶圓裝 載於指枝置。各SLM可針對其所對應之曝光區域獨立執行「區 域對準」之功能。—旦計算出各區域之欠對準修正因子，即可將 其分別應用於各SLM所對應之光罩資料。請注意，若使用本案之 方法便不騎對各晶圓執行精密之麟準作業，？、要各對準目標 係在對應之解攝韻之視野内，或在若干平方公厘之區域内即 了」而&於各SLM成像單元之光罩資料可單獨接受欠對準修 正，後續仍可進行對準修正。透過上述功能，本案之娜無光罩 直接成像系統便可為複數牧晶圓曝光。在為複數枚晶圓進行郷 曝光之過程中’所有基板均位於同一曝光平台上，因此，鄕可 依方位及距離進行實體掃描。由於在曝光前即可將包含修正因子 之光罩資料分別施用於各SLM ’所得之晶圓圖案與透過單—實體 光罩形成者並無二致。第28b圖即為本方法之圖示。如第她圖 所示，吾人可在同-晶圓内’針對各SLM成像單元所對應之光罩 資料分別進行區域性之對準修正。此外，兩不同晶圓可能產生不 同之爾準誤差，例如第—晶圓之預對準誤差為⑹，第 -曰曰圓之預對準誤差為d，ey2) ’兩誤差可分別接受修正，然 後施用於光罩㈣以修正光罩聽。請注意，吾人亦可運用類似 55 201214515 之方法，使AOS為矩形基板曝光’並視需要控制及施用修正因子。 各SLM成像單元所對應之光罩資料亦可分別接受區域性之對準修 正。 尚冗度LED (ΗΒ-LED)市場之蓬勃發展乃受惠於各種顯示器 之背光應用，包括手持式裝置、電視、電腦監視器、廣告看板等。 為降低LED晶片之製造成本’方法之一係使用較大之晶圓，例如 從2吋晶圓改為4至6吋之晶圓。但高亮度led之磊晶晶圓製程 不同於以矽為基礎之IC製程’前者係以藍寶石或碳化矽為材料， 然後以金屬有機物化學氣相沉積法（M〇CVD)沉積一氮化鎵 (GaN)薄膜。氮化鎵係一堅硬、具有機械穩定性、高熱容量及高 導熱性之寬能隙半導體材料。氮化鎵之晶格常數與藍寶石或碳化 矽均不匹配。沉積於基板上之氮化鎵薄膜雖具有抗裂性，但卻使 晶圓嚴重翹曲及彎曲，且基板尺寸愈大，晶圓翹曲之問題愈嚴 重。例如，2吋藍寶石晶圓上之氮化鎵薄膜可使晶圓產生20至 25微米之翹曲及彎曲，4吋藍寶石晶圓上之氮化鎵薄膜可使晶圓 產生100微米以上之翹曲及彎曲，至於6吋晶圓，其平度範圍往 往超過250微米。相較之下，6吋矽磊晶晶圓之平度範圍可能僅 若干微米。因此，在加大高亮度LED之晶圓時，上述問題實為一 大挑戰。 目前用以製造LED晶片之主流晶圓大小為2吋。若欲以具有 成本效益之方式，利用微影製程製造出直徑大於2吋之LED晶片 用晶圓，所用之微影工具不僅須具備必要之解析度，更須具有足 56 201214515 曝光此彡伽I具杨膜之My石晶圓在各 曝先範圍内之典型翹曲及彎 賴層間之對準度是否夠高亦二要===之:’ 接觸式對準系統並不適合製造大於=考里因素。因此，傳統之 之晶圓。 大於2吁且供高亮度LED晶月使用 如第：Γ示?據本發明實施例之一無光罩掃描曝光系統》 二：=系統之曝光範圍較小，故可根據基板織 二峨對於嚴重Vector value distance. For example, I 〇 D-x is the distance between the centers of both SLM 2702 and SLM 2704; likewise, the distance between the centers of both SLM 2702 and SLM 2706 is 'I 〇 D-y. In Figure 27b, the entire imaging region is divided into a plurality of sub-regions in a grid, such as sub-regions 2708, 2710, 2712, and 2714. Each sub-region corresponds to the imaging region of the -SLM. In this example, the viewpoint spacing between the two SLMs used to image the sub-regions 27〇8 and 271〇 is measured as IOD-x, and the viewpoint spacing between the two SLMs imaged for the sub-regions 271〇 and 2714 is measured. Is I〇D-y. Once the IOD of the corresponding ω in the system is measured, the system can use this message to calibrate and generate mask data to control the exposure of each SLM in the system. Through the application of I〇D, even if each SLM is not located in the center of the towel, the secret can still prepare the mask data to compensate for any alignment error of the SLM in the system. Figures 28a and 28b illustrate a method of measuring and correcting an alignment state of an imaging writing system in an embodiment of the present invention. In Figure 28a, part of the SLM is rotated, for example SLM 1 and SLM 3 are slightly turned to the right, SLM 5, 6, 8 are slightly turned to the left, and SIJ imaging units 7, 9 are turned slightly to the right (all The magnitude of the rotation is exaggerated in the figure). These rotation errors can be determined and determined by the conventional (10) setting. In this example, the rotation correction factor is measured as 0 SLM. Once the 0SLM of each SLM in the system is measured, the system can use this information to calibrate and generate mask data to control the exposure of each SLM in the system. Through the application of the rotation correction factor, even if the orientation of each SLM relative to its imaging area is not completely accurate, the system can use the rotation correction factor to prepare the reticle data, thereby compensating for any error in the orientation of the SLM. 5, SLM #7 2803 The rotation correction factor of the imaging zone is measured as 45 201214515 When preparing the reticle data, the system will incorporate these rotation correction factors and produce aligned reticle data 2804. Figure 28b illustrates a pattern recognition isomorphic alignment method in an embodiment of the present invention. In this exemplary method, a plurality of predetermined patterns may be used as landmarks, and an image of the alignment target is captured based on the pattern recognition. For example, a plus sign (+) 2805 can be used along the edge of the imaging zone as the boundary identification. In addition, the existing design patterns (i.e., E and F in the figure) 2807 may indicate the corners of the image area between adjacent SLMs. In accordance with an embodiment of the present invention, the SLM can simultaneously find an alignment target. Once the alignment target is used, the system can determine a set of correction factors, such as offset, rotation correction, and scaling factor. If there are enough additional alignment marks, the correction for nonlinear distortion (such as axis bending or keystone distortion) can be calculated. The system can generate reticle data and use the above-described correction i to make the desired ugly fiber smear the actual measurement position. Over the past four decades, the design dimensions of complementary metal-oxide-semiconductor (CMOS) have been shrinking under Moore's Law, allowing IC component manufacturers to be able to meet in the market. The change is to add more and more versatile or transistor, while increasing the operating frequency of the component and reducing the overall wafer cost. But the economic benefits have finally reached the limit. As the technical difficulty of reducing the size of CM〇s has become more and more difficult, if the next generation of components smaller than 2 nanometers is to be manufactured, the capital investment required is not affordable. One of the new lithography exposure tools may be the cost of upgrading the industry. In order to improve the effectiveness and the scale of the axis, such as the lower cost, the goal of the goal, or to implement the concept of “2012 20121515 into the law of transcendence”, the industry has begun to focus on the integration of the system ten years ago instead of blindly Increase the transistor density. The three-dimensional packaging technology that has recently been implemented through the interconnection of the Shih Thong (TSV) has provided a way to reduce the size of Moore's Law. The three-dimensional sealing technique makes the heterogeneous integration feasible, and (4) enables us to be in the air_small body (4), logic, memory and dirty sensors and other components. The three-dimensional packaging technology is different from the single-chip (10), and is different from the concept of "beyond Moore's Law"; the system two-chip system continuously increases the number of transistors in the two-dimensional wafer area, and the concept of "beyond Moore's Law" The design size must be reduced to the extreme. The capital investment threshold for 3D packaging technology is low, and the economic benefits are attractive for manufacturers of next-generation consumer devices such as smart mobile devices. In fact, the above devices have long been one of the main driving forces of 3D packaging technology. Driven by strong market demand, despite the recession, the industry is rapidly developing the various tools & processes, processes and technologies required for integrated packaging in 3D systems. There are two kinds of three-dimensional packaging technology, the kind of which is called "three_(Si) integration", and the ones of the "1" combination" are based on Shi Xitong, but each has to make it difficult. The three (four) integration technology, also known as wafer bonding, can provide better electrical performance and low output per unit time. 4 low 'product height and weight are also densely produced 1 2 whole head ^ can (4) have added a number of butterfly _ (10) s image sensor also, degree. The purpose of the slave is to give the relevant application a three-dimensional correction technique. Memory and technology, in order to reduce the product footprint, meet the strict requirements of increasing memory density in 201214515. Figs. 29a to 29d illustrate a three-dimensional integrated circuit maskless parallel manufacturing method in the embodiment of the present invention. Figure 29a shows three ways to form a through-hole, namely via-first, via-middle and via-last; as the name implies, the three represent 矽The through hole is formed before the manufacturing of 1C, during the manufacturing process, and after the completion of the manufacturing. In the example of Figure 29a, the two types of broken through holes are shown in cross-section. Regardless of the type of through-hole (dark gray), the through-hole pattern is first formed by lithography, and then a deep trench is etched on the germanium substrate, and a conductive metal such as copper is filled in the trench. . Then, the back surface of the substrate is polished to gradually thin the substrate, so that the pupil is exposed on the back surface of the substrate. In this way, the exposed vias can be directly connected to another wafer with a matching via design. The design rules for the through hole are determined by "diameter/pitch" and "aspect ratio" (ie, the ratio of depth to diameter). In one example, the diameter/pitch ratio can be 50/250 microns and the aspect ratio is 5:1. In another example, the diameter/pitch ratio can be reduced to 10/100 micron with an aspect ratio of 10:1; or a diameter/pitch ratio of 5/5 〇 micron with an aspect ratio of 16:1; or diameter/pitch The ratio is 3/5 〇 micron with an aspect ratio of 16:1; or the direct control/pitch ratio is 1/2 G micron' with an aspect ratio of 2 ()]. In terms of pattern lithography and etching techniques, the above diameter/pitch ratio is a reasonable range, but the deep trench coating technique is still mixed. In order to provide the red order of the silk, it is necessary to improve the existing development process, such as improving the electrical reliability of the through-hole forming technology, improving the financial performance of the thin wafers, and improving the thermal energy. Rate, and how to improve the test method of stacked chips. 48 201214515 Method - The material hole transfer job, _, grain yield may be affected. For example, if the wafer with many good grains is finished, the hole is scrapped, _ The effect of the grain (4) is very large. Another method is directly bonded to the other wafer, but the other wafer may be designed by another industry, and may not be made by a compatible semi-lead. The process is manufactured in (8) and is tested in order to interconnect with other wafers. This method is used to make a hole-to-bed crane layer, and attach the ic wafer to the interposer, and then work. The interposer can be tree or The substrate material made of glass has a shape/size similar to that of a chip or a rectangular glass substrate. The role of the interposer is 1C which has a large number of output eight-inch and high-density routing lines (from the package to the PCB). The interposer does not have an active component, and can be separately manufactured by a foundry or an external package. Figure 29b is a cross-sectional view of an interposer embodiment, in which a specific application integrated circuit (ASIC) logic chip and a dynamic random access memory are used. Bulk (DRAM) wafer stack The stacking system (10) ☆ is set to 'and engages the 阙 _ passive towel layer. Another type of 矽 through hole can be used between the memory chips of the 诵 stack. Right to bend the active towel layer, that is, The pattern of the through-holes of the cake is formed on the 1C wafer. The SLM array (Array 〇f SLMs, hereinafter referred to as AOS) can be used without the reticle direct imaging tool and the integrated component manufacturer (10). Red with '10' (mix_n_mateh) square scale ^, its unit time output can reach - fixed rotation. For the process towel fox, should be performed after setting the layer of the transistor and the crane joint - fresh steps 'There is then a multi-layered copper interconductor 49 201214515 conjoined to form an interconnect structure with a diameter of 3 to 5 microns in the through-holes with a large via-to-via spacing. The implementation of the post-drilling process is first After the wafer is thinned, the wafer is temporarily bonded to the button, and the woven fabric is formed in a rotten manner from the back surface of the wafer until it is etched to the barrier layer; the diameter of the through hole is between 8 and 1 micron. The third generation double data rate synchronous dynamic random access memory for mobile devices Body CDDR3 DRAM) must be downsized and reduced in energy consumption. For memory Ic, a 10 to 50 micron thick coffin can be set with an aspect ratio (AR) of 5:1 to 1 〇: through hole, and The plating method forms a copper interconnect in the via hole; in other words, the via hole has a diameter of 2 to 5 μm. This diameter range is substantially in accordance with the diameter of the ▲ 通 through hole that can be made by IDM and the foundry. The layer forms a pattern of through-holes, which can be replaced by a packaging test factory (〇SAT). The final thickness of the intermediate layer can be 100 to 140 microns. If the thickness of the interposer is reduced to less than 100 microns, hard twins The circle will become a flexible enamel foil. As far as the through hole diameter is concerned, if the aspect ratio is 5:1, the imaging target of the 矽 through hole diameter may be about 20 to 30 microns. An enamel interposer comprises a redistribution layer (RDL) consisting of coated copper wires, wherein the line width and the pitch of the coated copper wires are respectively close to the diameter and the pitch of the corresponding shitong through holes. The above line width and diameter are all within the scope of the AOS maskless direct imaging capability at 405 nm exposure wavelength. The interposer can be used in a variety of ways. For example, σί allows the obsolete components to be applied to boards that are difficult to redesign through the interposer. If OSAT wants to be higher with the commercial application of the foundry or IDM in the intermediation layer, 201214515 =, the rapid design, production, and small-scale production of the intermediation layer can be promoted' and re-established through the intermediation layer. The cloth is made in a manner that makes the substrate of the complex meet the fresh size; in addition, _ other fine services. In the implementation of the above four industries, the A〇s reticle direct imaging technology of this case can provide fast conversion, and its flexibility is beyond the reach of W-mask exposure tools (including stepped edge and reticle alignment systems). In this case, the A0S reticle-free direct imaging system can still deal with the deformation of the super-plate material after deformation (such as ^ and warpage). Through the method disclosed herein, the hallless photographic direct imaging system of the present invention can efficiently "stretch" the reticle material to match the existing substrate to achieve local alignment. The conventional reticle lithography technology does not have this function. In another method, the A〇S reticle direct imaging system of the present invention is used to form a Weikong pattern on the active stone layer. In order to optimize the thermal properties of the three-dimensional IC integrated components, or it is necessary to conduct timing in the research or development stage, or in the same wafer for different purposes, the needle through hole in the active die ^ Experiment with the design of the sigh (10) E). In this case, the glare-free direct imaging system can effectively achieve this purpose, so you can order any reticle for this purpose. Figure 29c is a configuration diagram of a two-dimensional integrated circuit. As shown in this example, each block in the configuration diagram (ie, A, B, C, D, E, F, G) represents the integrated circuit. p卩 and its corresponding area on a wafer. The line segments extending between blocks a and c, between blocks A and E, and between blocks c and G represent the routing lines required for the blocks to communicate with each other, respectively. Those skilled in the art will understand that in an integrated circuit with billions of 51 201214515 transistors, the routing of communication signals between blocks is very complicated, and the design is very difficult. The problems involved include resistance-capacitance delay. Effects, crosstalk, energy consumption, and form factor all have a direct impact on the cost of the integrated circuit. The system and method disclosed in the present invention can solve the design problem of the system single chip in the figure 29c, especially for the die-to-die, die-to-wafer, and wafer-to-wafer one-dimensional bonding. An efficient way to manufacture a three-dimensional integrated circuit. As shown in the second figure, the integrated circuit can be three-dimensional; the 5* type arrangement greatly shortens the routing length of the ## communication between blocks. In this example, block Α and C are located on the first layer of the integrated circuit, while blocks 8, 〇, £, 卩, and 0 are located on the second layer of the integrated circuit. Anyone who is familiar with this technique can understand that the number of layers of the integrated body can be more than two layers to achieve the specific design and cost of the integrated circuit. Extending between blocks A and E, between blocks 8 and 13, between blocks 8 and 11', between blocks C and B, between blocks c and F' and blocks C and G The vertical line between the two represents the communication signal routing between different layer blocks in the integrated circuit. Since these routing lines are arranged in three dimensions, their length has been greatly reduced. In other embodiments, the analog circuit and the digital circuit can be separated into different layers of the three-dimensional integrated circuit. In other implementations, the power and ground planes of the circuit can also be divided into different layers of the three-dimensional integrated circuit. The three-dimensional integrated circuit is fabricated by a conventional method. Each layer of the integrated circuit must use a photomask. However, it is often necessary to perform multiple iterations in the design process to simultaneously satisfy functions, performance, and silk. In the process of shooting, money calculation and verification, the various layers of the integrated circuit are likely to be modified, thus increasing the development cost of the integrated circuit. However, if the secret of Sinben (4) is written in the system of 2012 20121515, the formation of each layer of circuit design does not require the use of a mask. In addition, if the multi-wafer direct imaging method of the imaging writer system of the present invention is employed, the plurality of layers in the integrated circuit can be manufactured in parallel, thereby reducing the development cost of the integrated circuit and verifying the development time. According to the invention of the present invention, the core of the clerk can use the "drilling first" process of the secret hole to facilitate the joining of the three-dimensional integrated circuit chip. The maskless method of the present invention can replace the conventional filling step of using a reticle, which is a processing step before the front stage process (grandfather) (the second step in the process ,, or the processing process after the anterior stage process (process 2) The third step. Similarly, the imaging writing system of the present invention can use the "post-drilling" process of the through-hole to facilitate the bonding of the three-dimensional integrated circuit chip. The maskless method of the present case can replace - use light The conventional filling step of the cover, which is the fifth step in the processing step before the process (10) 〇L) of the step (the third step in the process illusion, or the fifth step in the processing step after the subsequent process (I sequence 4). Note that because the through-hole mask pattern of Shixi through-hole is mostly different in size from other masks, the flexibility of the mask method can be used as a benefit; The most advanced exposure of the hemp red hole to make the through hole = the economic benefits of the cover pattern is very low, under her, with the most advanced exposure tools in the front-end process in the shape of the wire layer for bribery benefits. - As mentioned above, the image is written System, first in the imaging process The scaling correction, the viewpoint spacing correction, and the rotation factor correction are performed to reduce the product development cost and shorten the product development schedule. Fig. 30 is a diagram showing the direct imaging method of the embodiment of the present invention. In the example, -3χ6 Μ _ is the diameter of two 53 201214515 wafer parallel imaging 'where the first wafer 3002 can be imaged by the first set of 3χ3 SLM arrays' the first wafer 3GG4 can be a second set of 3x3 SLM arrays Imaging. Through this method, each wafer may comprise different design patterns or different layers of a three-dimensional integrated circuit. In addition, each SLM may image different types of through holes. Furthermore, each SLM can be used to perform different image bonding. The difference between the algorithm, the scaling correction, the inter-viewpoint rotation and the rotation correction. According to the invention, the SLM array of the present invention can planarize a plurality of wafers. For example, the -3x3 SLM array can image the 牧 牧 2 忖 wafer. There is no need to join the images, and each of the two leaf wafers is imaged by a corresponding slm money, and the imaging writer system of the present invention can control each SLM to make the nine wafers are exposed in parallel. Example 'SLM can also perform different image joining operations, scaling correction, viewpoint spacing correction and rotation factor correction. In another method, the fine 3x3 SLMP car is nine pieces of 2_pCB imaging, in which each pcB is composed of a corresponding one. SLM direct imaging' and the imaging writing system of the present invention can separately control each of them to make nine PCBs are exposed in parallel. It will be understood by those skilled in the art that the sij array can be adjusted to meet different manufacturing requirements. For example, a 4χ6, (4), or 12x12 SLM array can be used for a plurality of two wafers or μ parallel imaging arranged in a corresponding manner. In the example shown in FIG. 30, the arrangement of the 光# reticle direct imaging system can be Exposure for a plurality of metric wafers or rectangular interposer substrates (active or moving through-via layers). The glare-layered shirt and the loading method of Crystal® are exaggerated to be compatible with the reticle exposure system. In the case of a rectangular interposer substrate, since the requirements for riding accuracy and alignment accuracy are low in the 2012 20121515, it can be manually loaded in addition to the automatic loading of the machine. Such an A〇s exposure system can load more than one wafer or substrate onto an exposure platform for simultaneous scanning exposure, depending on the amount of output per unit time required. The example shown in Figure 3 is a parallel exposure of two wafers. To load the & towel in a clear circle, the wafer must be identified first, and then the wafer is placed on the finger. Each SLM can independently perform the function of "area alignment" for its corresponding exposure area. Once the under-correction correction factor for each region is calculated, it can be applied to the reticle data corresponding to each SLM. Please note that if you use the method of this case, you will not be able to perform precise operations on each wafer. The target data is to be in the field of view of the corresponding solution, or within a few square millimeters. "And the mask data of each SLM imaging unit can be individually subjected to under-alignment correction, followed by Alignment correction is still possible. Through the above functions, the caseless film direct imaging system of this case can expose multiple wafers. During the 郷 exposure of multiple wafers, all substrates are on the same exposure platform, so 实体 can be physically scanned by orientation and distance. Since the mask pattern containing the correction factor can be applied to each SLM' before the exposure, the wafer pattern obtained is the same as that of the single-solid mask. Figure 28b is an illustration of the method. As shown in the figure above, we can perform regional alignment correction for the reticle data corresponding to each SLM imaging unit in the same-wafer. In addition, two different wafers may produce different quasi-errors, for example, the pre-alignment error of the first wafer is (6), and the pre-alignment error of the first-turn circle is d, ey2) 'the two errors can be corrected separately, It is then applied to the reticle (4) to correct the reticle. Please note that we can also use a method similar to 55 201214515 to expose AOS to a rectangular substrate and control and apply correction factors as needed. The reticle data corresponding to each SLM imaging unit can also be subjected to regional alignment correction. The booming LED (ΗΒ-LED) market is booming thanks to backlighting applications for a variety of displays, including handheld devices, televisions, computer monitors, and advertising billboards. One way to reduce the cost of manufacturing LED chips is to use larger wafers, such as wafers from 2 to 6 to 6 to 6 wafers. However, the high-brightness LED epitaxial wafer process is different from the germanium-based IC process. The former is made of sapphire or tantalum carbide, and then deposited by metal organic chemical vapor deposition (M〇CVD). GaN) film. Gallium nitride is a hardband semiconductor material that is hard, mechanically stable, has high heat capacity, and has high thermal conductivity. The lattice constant of gallium nitride does not match either sapphire or tantalum carbide. Although the gallium nitride film deposited on the substrate has crack resistance, the wafer is severely warped and bent, and the larger the substrate size, the more severe the problem of wafer warpage. For example, a gallium nitride film on a 2 吋 sapphire wafer can cause warpage and bending of the wafer by 20 to 25 microns, and a gallium nitride film on a 4 Å sapphire wafer can cause warpage of the wafer to be more than 100 microns. And bending, as for 6-inch wafers, the flatness range often exceeds 250 microns. In contrast, the flatness of a 6-inch epitaxial wafer may be only a few microns. Therefore, the above problems are a real challenge when increasing the wafer of high-brightness LEDs. The current mainstream wafer size for manufacturing LED chips is 2吋. If you want to use a lithography process to fabricate wafers for LED wafers larger than 2 inches in a cost-effective manner, the lithography tools used must not only have the necessary resolution, but also have a foot 56 201214515 exposure. Whether the typical warpage of the Yang film and the alignment between the bend layers in the respective exposure ranges are high enough is also the same as ===: The contact alignment system is not suitable for manufacturing greater than = factor. Therefore, the traditional wafer. More than 2 calls for high-brightness LED crystal moon use. For example: ??? According to one embodiment of the present invention, the maskless scanning exposure system" 2: = the system has a small exposure range, so it can be based on the substrate weaving

請^ ’嶋__晰峨,，以便分別 為同-千σ上讀錄豸gj断触H 罩掃描曝衫_互接合糊，俾為—大尺寸晶圓平彳= 右欲對同—平台上之複紐晶_分_ 所有晶圓安放於個別之粒，此時各晶_有_組特有之轉員= 差。裝載過程中—粗略之預對準步驟後，上述轉動誤差 可調整至預設之限值内。之後若欲以對準狀態進行無光罩曝光’ 尚須掃描各晶圓上之對準記號（如第28b圖所示），_ 際之圖案範圍。 ^ ^ 除了圖案轉動（如第28a圖所示）外，各晶圓也可能因為曰 格常數不匹配之狀況在各熱處理循環中愈加明顯而出_曲= 彎曲之，躺導致職餘曲。各倾解掃描曝光單 元（即SLM成像單元）可獨立求出光罩資料之圖案修正因子，並 57 201214515 將該等圖案修正因子分別應用於各SLM祕單元所對應之光罩資 料。 一如前述，一線性排列之SLM陣列（A0S)可在同一平台上 以平行方式同時執行無光罩掃描曝光。為達此目的，該灿陣列 中之各SLM具有相同之光罩資料，但各SLM之光罩資料分別包含 一組對應於待曝光晶圓之特有修正因子。在另一範例中，一包含 兩具SLM之SLM陣列可處理同一晶圓，其中晶圓映射及光罩資料 修正之步驟實質相同’不同之處僅在於此處係由兩具μ成像單 元為同一晶圓曝光。 本案之A0S絲罩掃描曝光系統優點甚多，其不僅能以更有 效率之方式隨基板表面追織、點，更可對各牧待曝光之晶圓分別 細以不同之光罩修正圖案。此外’由於該系統可同時為複數枚晶 圓平仃曝^ ’製造系統之單位時間產出量絲明時曝光之晶圓 數，且其間亦不致影響各晶圓光罩_之修正。請注意，在將晶 圓裝載於曝光平。之過知中，本案廳無光罩掃描曝光系統對預 對f誤差之4度頗大，此誤差可在數公厘之内，或在各則成 像單元中對準攝w機之I像擷取限制範圍内。最好搭配使用機器 亡之晶載及卸額構，但若有必要，亦可由_熟練之操作人 貝以手動方式裝載晶圓以執行無光罩掃描曝光。 在-方法中，本案之⑽陣列可為複數枚圖案化藍寶石基板 (SS)發光一極體（LED)平行成像。由於每具⑽可為一枚脱 LED晶圓曝光’單位時間之產出量甚高。舉例而言，若使用- 5x5 58 201214515 SLM陣列，且每枚PSS LED之曝光時間為·一分鐘，則每分鐘可 為25枚晶圓曝光，亦即每小時可為1500枚晶圓曝光。此等單位 時間產出量超過以習知曝光工具製造PSS LED時之水準。請注 意’上述PSSLED製程往往使晶圓承受高應力，進而導致基板大 幅翹曲；通常每牧晶圓之翹曲幅度為1〇〇微米左右。此外，每一 批次之晶圓可能具有不同之基板翹(曲特性，若使用習知曝光工具 則難以在製程中因應此種變化，其原因在於習知接近式對準系統 原本即不適合處理翹曲之基板，而習知步進系統則將額外增加光 罩相關之成本。為解決此一問題，本案之成像寫入系統可獨立控 制各SLM之焦點，藉以在各SLM所對應之局部區域產生最佳成像 效果。此種以調適焦點之手段解決基板翹曲問題之方法如第9圖 及第21圖所示。 第32a與32b圖繪示本發明實施例中直接在部分晶圓基板 成像之方法。第32a圖係由- 1X3 SLM陣列執行同形對準曝光 f此方法中，成像_可由各SLM分別曝光。請注意，此一處^ 部分晶圓之功能在製造神化鎵（GaAs)晶圓時尤其有用，因為! 化鎵晶圓财晶圓更容級裂。若使㈣知工制難以處理如 晶圓，其原因在於光罩可能無法搭配部分晶圓使用。即使光罩; 搭配部分晶®個’兩者也權目互解。但若使財案之糊 寫入系統’吾人在為部分晶圓成像時便可分別控 對縮放比例、及細子修正等項目進行婦。如此-來 部分晶11無須精確對準也可完成曝光。同樣地，第3_會示如 59 201214515 何利用- MSLM陣列對兩部分晶圓執行平行同形對準曝光，其 中各晶圓係分別由-對應之SLM曝光。請注意，在第娜圖所示 範例中，兩部分晶圓不須彼此對準，且兩部分晶圓可有各自之偏 位角，該等偏㈣可在曝細种由SLM於行關加以補償。第 32c與32d圖則繪示本發明實施例中為柯形狀之設計圖案進行 直接成像之方法。詳言之，第32c圖中之心形可挽性基板之設計 圖案通可由—lx4 SLM陣列以無光罩之方式直接成像，而第 32d圖中f曲可撓性基板之矩形設計圖案咖4則可由一加Μ 陣列以無光罩之方式直接成像m範例中，吾人可將各μ 程式化’俾針對龜曲、縮放比例、⑽及轉動因子修正等項目進 行補償。 ' 第33a與33b圖!會示本發明實施例中之無光軍製造法。詳言 之，第33a圖係-使用光罩之習知製造法，第咖圖則為一· 本發明成像寫入系統之無光罩製造法。在第咖圖中，習知製造 法於方塊纖+接蚊案之產品設計職，然後分別於方塊 3304、3306及3308令執行光罩廠預備作業、光單寫入及光罩之 檢查與修復。錢至3期之作魏稱光罩軸業。若在方 鬼3308中發現瑕庇，可針對瑕錢行修復’有時則須重覆方塊 _之光罩寫入作業’因而增加額外之成本（圖中以$表示）， 此新增成本包括所用材料之成本，以及在方塊3306中製備新光 罩所時間成本。在完成光罩廠作紐，光罩將於方塊3310 中接欠品管測試。倘於測試期間發現錯誤則須重製光罩，換言 201214515 之’必須返回方塊3306以製造新光單，然此舉將增加更多成本 (圖中以$$表示），新增之成本包括材料成本及重製林所耗費 之時間成本。方塊3312則為產品製造驗證。若於驗證期間發現 功此或效能上之問題’產品可能必須重新設計，亦即必須重覆上 述流程’並於方塊3302中重新提出定案之產品設計圖案。此一 情況所増加之成本更高（圖中以$$$表示），實際金額可達數百 萬美元。若產品順利通過方塊3312之製造驗證，即可進入方塊 3314之量產程序。 在第33b圖中，該無光罩製造法係於方塊33〇2中接收定案 之產品設計圖案。然後，根據本發明之實施例，本案之成像寫入 系統將接收此設計資料並加以處理，以便利用一 SLM陣列進行後 續之成像及平行曝光。在處理設計資料以供成像之過程中，本案 之成像寫入系統可針對各SLM執行對準狀態修正、縮放比例修 正、晶圓翹曲修正、視點間距修正及轉動因子修正。上述修正動 作係以基板上特定區域之參數為基礎，且各SLM係分別接受控制 以執行該等修正動作。 第33b圖之方塊3312與第33a圖中之對應方塊相同，均為 產品製造驗證。若驗證後發現功能或性能上之問題，產品可能必 須重新設計，亦即必須重覆上述流程，並於方塊33〇2中重新提 出定案之產品設計圖案。此時，由於並未使用實體光罩，且亦不 須執行光罩廠作業（方塊3304至3308)或光罩品管作業，重製 光罩之時程將較第33a圖所示之習知製造法為短，產品開發成本 201214515 亦較低（如方塊3312至方塊3302之虛線所示）。若順利完成方 塊3312之產品製造驗證，即可進入方塊3314之量產程序。 根據本發明之實_ ’本案之成像寫人系断執行積體電路 之自動光學檢查，其中SLM陣列可如第23a至23c圖所示操取基 板之影像。例如，感測器2310及2322可擷取一基板某一區域= -或多個影像，而絲細絲-接受檢查之賴電路之一部 分。所搁取之每個影像將接受分析以找出異常之圖案，例如不應 出現之瑕疵及外來微粒等。在-實施例中’本案之成像寫入系: 可執行下列三種檢查：1)找出基板與光罩資料庫間之差異；2) 找出與基板圖案相關之畸變；及3)找出基板上之外來微粒。相 較於習知檢查綠，財案之祕寫4崎行自動光學檢查之 優點甚多。首先’由於SLM陣列可以平行方式比對光罩資料庫， 系統之單位時間產出量極高。其次’本案之成像寫人系統可執行 影像接合’故可為大型設計_進行基板圖案與光料料庫之比 對檢查。再者，各SLM可獨立檢查基板之—特定區域，因此可以 更有效之方式因應該區域内之各種狀況，例如可進行對準狀態修 正、縮放比例修正、IOD修正、轉動因子修正及基板龜曲修正。 此種自動光學檢查技術適用於非常大型之基板，例如第十代及更 新世代之平板顯示器。 本發明之實施例不僅適用且有利於FPD及其光罩之微影製程 (亦即在賴基板上形成獨-無二之原尺寸_或其精密複製 62 201214515 品），亦適用且有利於積體電路、電腦產生之全像（⑽、pcB等 微尺度與中尺度之大型成像顯示應用。 本發明之實_亦適収有利贿解之鄕雜，例如可 將預定之光罩資糊案直接“基板’藉以省去鮮成本並免除 相關問題。本發明之實施例使曝光工具得以執行無光罩式曝光， 並使其單位_之處理量超_十代及以±基板所需之水準。更 重要者，本發明之設計可改善製程窗口，進而確保微影製程之良 率。 以上雖藉由不同之功能單元及處理本發明之實施 例，但所述魏_可於㈣之魏單元與處職㈣任何適當 之方式分配而不絲本發明之精神與範圍。舉例而言，由不 理器或控制器執行之功能可改由同一處理器或蝴器完成^ 此，本文在提及特定功能單元時，谢旨可提供所述舰之適當手 段，而非指特定之邏輯或實體結構或組織。 田 本發明可以任何適當形式實現，包括硬體、軟體、勒 之部分内容可視需要而落實為可由-或多個資 科處理讀/或數位峨處理錄行之電腦軟體。本發明任 施例中之元件’其實體、魏及_均可以任何 所述功能可輯-單元或複數個單元纽 單元之-部分，，本物為單—單元其他功能 分配至柯之較__。 以或戦·與功能 63 201214515 熟習此項技藝之人士應可明瞭，本文所揭露之實施例可以多 種方式修改及組合，但仍保留本發明之基本機構及方法。為便於 解說，前文係針對特定實施例加以說明。然而，以上說明並未窮 盡所有可能之實施方式，亦未將本發明限縮於本文所揭示之特定 〜、…、驾此項技藝之人士在參閱以上說明後，或可思及多種修 改及蠻化夕士4 ^ ^ 式。之所以選擇並描述特定實施例，乃為闊釋本 實際制，使熟習此項技藝之人士得依特定用賴 丁夕文Μ善用本發明及各種實施例。 64 201214515 【圖式簡單說明】 在一併參閱本發明多種實施例之詳細說明及附圖後，當可對 本發明之技術特徵及優點有更完整之暸解。附圖中： 第la至ie圖繪示多種用以製造積體電路、印刷電路板及平 板顯示器之習知曝光工具。 第2圖纷示一用以製造光罩之曝光工具習知架構。 第3圖緣示一根據本發明實施例之數位微鏡裝置（DMD)或 空間範例。 第4圖繪示一根據本發明實施例之DMD投影系統。 第5圖綠示一根據本發明實施例之柵狀光閥（GLV)裝置， 並同時顯7F其鏡面反射狀態魏雜態之範例。 第6圖缘示一根據本發明實施例之小型空間光調變器（SLM) 成像單元範例。 第7圖繪示一根據本發明實施例之SLM成像單元平行陣列範 例0 第8圖係第7圖所示SLM成像單元平行陣列之俯視圖。 _第9圖右侧繪示如何利用本發明實施例之陣列式成像系統進 行局。[5製程窗σ最佳化，^左側與之賴者則為—習知單一透鏡 投影系統。 第10圖繪示本發明實施例中一種將基板局部不平處最佳化 之方法。 第11圖繪示本發明實施例中光罩資料結構之一應用方式。 65 201214515 =12 ’示—娜本發明實施例之平行物加總曝光法。 餘度之方L騎林㈣實補+—種於成像以系統内形成冗 第14 _示—根據本發明實施例之楔形邊界融合法。 之方=。15 _示本發明實施例中—種將SIJ成像單元排成陣列 第_16 ®繪示本發明實施例中—種用以製造撓性顯示器之無 光罩，二維陣列式成像寫入系統範例。 …、 第17圖緣示一根據本發明實施例之SLM成像單元。 第丨8圖繪示本發明實施例中一種使用SLM成像單元線性陣 無光罩微影法。 第19圖繪示本發明實施例中一種使用SLM成像單元二維陣 式無光罩微影法。 第20圖繪示本發明實施例中一種利用無光罩微影法為多種 產品因光罩數據尺寸不同，在同一可撓性捲轉式基板成像之方法。 第21圖繪示本發明實施例中一種依照基板表面局部狀況定 位各SLM成像單元之方法。 第22圖繪示本發明實施例中一種偵測像素焦點之方法。 第23a至23c圖繪示本發明實施例中三種用於即時偵測SLM 成像單元焦點之裝置範例。 第24圖繪示本發明實施例中一適用像素加總曝光法之成像 圖案範例。 66 201214515Please ^ '嶋__ 峨 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , On the top of the new crystal _ points _ all wafers placed in individual particles, at this time each crystal _ has a unique transfer of the group = poor. During the loading process - after the rough pre-alignment step, the above-mentioned rotation error can be adjusted to the preset limit. Then, if you want to perform maskless exposure in the alignment state, you must scan the alignment marks on each wafer (as shown in Figure 28b), the pattern range of _. ^ ^ In addition to the pattern rotation (as shown in Figure 28a), each wafer may become more pronounced in each heat treatment cycle due to the mismatch of the grid constants. Each of the tilting scanning exposure units (i.e., the SLM imaging unit) can independently determine the pattern correction factor of the mask data, and apply the pattern correction factors to the mask data corresponding to each of the SLM secret units. As previously mentioned, a linear array of SLM arrays (AOS) can simultaneously perform a maskless scanning exposure in parallel on the same platform. To this end, each SLM in the Can array has the same reticle data, but the reticle data for each SLM contains a unique set of correction factors corresponding to the wafer to be exposed. In another example, an SLM array comprising two SLMs can process the same wafer, wherein the steps of wafer mapping and mask data correction are substantially the same 'the only difference is that the two μ imaging units are the same here. Wafer exposure. The A0S wire cover scanning exposure system of the present invention has many advantages, which can not only chase and sew the surface of the substrate in a more efficient manner, but also modify the pattern with different reticle for each wafer to be exposed. In addition, because the system can simultaneously produce the number of wafers exposed by the unit time of a plurality of crystals, the system does not affect the correction of each wafer mask. Note that the crystal is loaded on the exposure flat. In the past, the vestibule scanning exposure system of this court has a large amplitude of 4 degrees for the pre-f error, and the error can be within a few millimeters, or the image of the camera is aligned in each imaging unit. Take the limit. It is best to use the machine's dead crystal load and unloading structure, but if necessary, the wafer can be manually loaded by the skilled operator to perform a maskless scanning exposure. In the method, the (10) array of the present invention can be a parallel imaging of a plurality of patterned sapphire substrates (SS) light-emitting diodes (LEDs). Since each (10) can be exposed for one de-LED wafer, the throughput per unit time is very high. For example, if a - 5x5 58 201214515 SLM array is used and the exposure time per PSS LED is one minute, then 25 wafer exposures per minute can be achieved, ie 1500 wafers per hour. These units have a time output that exceeds the level at which the PSS LEDs are manufactured using conventional exposure tools. Please note that the above PSSLED process tends to subject the wafer to high stresses, which in turn causes large warpage of the substrate; typically the warp of each wafer is about 1 μm. In addition, each batch of wafers may have different substrate warpage characteristics. If a conventional exposure tool is used, it is difficult to respond to such changes in the process. The reason is that the conventional proximity alignment system is not suitable for processing the warp. The substrate of the song, and the conventional stepping system will additionally increase the cost associated with the mask. To solve this problem, the imaging writing system of the present invention can independently control the focus of each SLM, thereby generating a local area corresponding to each SLM. The best imaging effect. The method for solving the substrate warpage problem by adjusting the focus is as shown in Fig. 9 and Fig. 21. The 32a and 32b diagrams illustrate the direct imaging of a portion of the wafer substrate in the embodiment of the present invention. Method 32a is performed by a -1X3 SLM array to perform a homogenous alignment exposure. In this method, imaging can be separately exposed by each SLM. Please note that the function of this part of the wafer is to fabricate a GaAs wafer. This is especially useful because the gallium wafer wafers are more tolerant. If the (4) knowledge system is difficult to handle, such as wafers, the reason is that the mask may not be used with some wafers. Even the mask; Crystal® 'both are also mutually exclusive. But if the financial paste is written into the system', when we are imaging part of the wafer, we can control the scaling and fine-tuning items separately. The partial crystal 11 can be exposed without precise alignment. Similarly, the third _ is shown as 59 201214515. The MSLM array performs parallel isomorphic alignment exposure on the two portions of the wafer, wherein each wafer system is respectively corresponding to SLM exposure. Please note that in the example shown in the figure, the two parts of the wafer do not have to be aligned with each other, and the two parts of the wafers may have their own offset angles. The partial (4) can be exposed in the SLM. Compensating for the line. The 32c and 32d drawings illustrate the method of directly imaging the design pattern of the ke shape in the embodiment of the present invention. In detail, the design pattern of the heart-shaped slidable substrate in the 32th figure is The -1x4 SLM array can be directly imaged without a reticle, and the rectangular design pattern of the f-flexible substrate in Fig. 32d can be directly imaged by a twisted array without a reticle. Stylize each μ '俾 for tortoise, scale (10) and the rotation factor correction and other items are compensated. 'Sections 33a and 33b! The light armor manufacturing method in the embodiment of the present invention is shown. In detail, the 33a figure is a conventional manufacturing method using a photomask, The coffee chart is a maskless manufacturing method of the image writing system of the present invention. In the coffee chart, the conventional manufacturing method is applied to the product design of the box fiber + mosquito case, and then at blocks 3304, 3306 and 3308, respectively. To carry out the preparation work of the mask factory, the writing of the light sheet and the inspection and repair of the mask. The money to the 3rd period Wei Wei called the mask shaft industry. If you find the shelter in Fang Ghost 3308, you can repair it for the money. Sometimes it is necessary to repeat the photomask write operation of the block _ thus adding additional cost (indicated by $ in the figure), this new cost includes the cost of the material used, and the time cost of preparing the new reticle in block 3306. Upon completion of the reticle factory, the reticle will be tested for quality control in block 3310. If an error is found during the test, the mask must be reworked. In other words, 201214515 'must return to block 3306 to make a new light sheet, but this will add more cost (indicated by $$), and the added cost includes material cost. And the time cost of reforestation. Block 3312 is for product manufacturing verification. If a problem with performance or performance is found during verification, the product may have to be redesigned, i.e., the process must be repeated, and the finalized product design pattern is resubmitted in block 3302. The cost of this situation is higher (indicated by $$), and the actual amount can reach millions of dollars. If the product successfully passes the manufacturing verification of block 3312, the mass production program of block 3314 can be entered. In Figure 33b, the maskless manufacturing process receives the finalized product design pattern in block 33〇2. Then, in accordance with an embodiment of the present invention, the imaging writing system of the present invention will receive and process the design data for subsequent imaging and parallel exposure using an SLM array. In the process of processing design data for imaging, the imaging writing system of the present invention can perform alignment state correction, scaling correction, wafer warpage correction, viewpoint spacing correction, and rotation factor correction for each SLM. The correction operation is based on parameters of a specific area on the substrate, and each SLM system receives control to perform the correction operations. Block 3312 of Figure 33b is identical to the corresponding block in Figure 33a and is a product manufacturing verification. If the function or performance is found after verification, the product may have to be redesigned, that is, the above process must be repeated, and the finalized product design pattern is re-submitted in Box 33〇2. At this time, since the physical mask is not used, and the mask factory operation (blocks 3304 to 3308) or the reticle quality control operation is not required, the time course of the re-shaping mask will be better than that shown in Fig. 33a. The manufacturing method is short and the product development cost 201214515 is also low (as indicated by the dashed line in blocks 3312 to 3302). If the product manufacturing verification of block 3312 is successfully completed, the mass production procedure of block 3314 can be entered. According to the present invention, the image writer of the present invention performs an automatic optical inspection of the integrated circuit, wherein the SLM array can take an image of the substrate as shown in Figs. 23a to 23c. For example, the sensors 2310 and 2322 can capture a region of a substrate = - or multiple images, and the filaments - accept a portion of the circuit. Each image that is taken will be analyzed to find patterns of anomalies, such as flaws and foreign particles that should not appear. In the embodiment, the image writing system of the present invention can perform the following three tests: 1) finding the difference between the substrate and the mask database; 2) finding the distortion associated with the substrate pattern; and 3) finding the substrate On the outside particles. Compared with the conventional inspection of green, the secret of the financial case is very good. First of all, because the SLM array can align the mask database in parallel, the system's throughput per unit time is extremely high. Secondly, the image writing system of the present invention can perform image bonding, so that the large-scale design can be compared with the substrate pattern and the optical material library. Furthermore, each SLM can independently inspect the specific area of the substrate, so that it can be more effective in response to various conditions in the area, such as alignment state correction, scaling correction, IOD correction, rotation factor correction, and substrate tort Corrected. This automated optical inspection technology is suitable for very large substrates such as the tenth and newer generation flat panel displays. The embodiments of the present invention are not only applicable but also beneficial to the lithography process of the FPD and its reticle (that is, forming a unique size on the substrate) or its precision reproduction 62 201214515, which is also applicable and beneficial to the product. Body circuit, computer-generated hologram ((10), pcB and other micro-scale and mesoscale large-scale imaging display applications. The invention _ is also suitable for bribery, such as the book can be directly sealed The "substrate" is used to eliminate the cost and eliminate the problems. Embodiments of the present invention enable the exposure tool to perform a maskless exposure and have a throughput of more than ten generations and a level required by the substrate. More importantly, the design of the present invention can improve the process window, thereby ensuring the yield of the lithography process. Although the above embodiments of the present invention are performed by different functional units, the Wei _ can be used in (iv) Service (4) Any appropriate way to distribute the spirit and scope of the invention. For example, the functions performed by the processor or controller may be performed by the same processor or butterfly. Functional unit The purpose of the ship may be to provide the appropriate means of the ship, and not to a specific logical or physical structure or organization. The invention may be implemented in any suitable form, including hardware, software, and parts of the content that may be implemented as needed - Or a plurality of software programs for reading/receiving the recorded computer software. The elements of any embodiment of the present invention may be any of the functions, the elements, or the plurality of unit units. - Partially, the object is a single-unit, and other functions are assigned to the __. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The present invention has been described with respect to the specific embodiments. ~,..., those who drive this skill can refer to the above instructions, or think about a variety of modifications and sorrows 4 ^ ^ style. The reason for choosing and describing the specific For example, it is a simplification of the actual system, so that those skilled in the art can make use of the invention and various embodiments according to the specific use of the singer. 64 201214515 [Simple description of the drawings] A more complete understanding of the technical features and advantages of the present invention will be obtained from the detailed description of the embodiments and the accompanying drawings in which: FIG. A conventional exposure tool. Figure 2 illustrates a conventional architecture of an exposure tool for fabricating a reticle. Figure 3 illustrates a digital micromirror device (DMD) or spatial example in accordance with an embodiment of the present invention. A DMD projection system according to an embodiment of the present invention is shown. Fig. 5 is a diagram showing an example of a grating light valve (GLV) device according to an embodiment of the present invention, and simultaneously exhibiting a specular reflection state of the hybrid state. Figure 6 illustrates an example of a small spatial light modulator (SLM) imaging unit in accordance with an embodiment of the present invention. Figure 7 is a plan view showing a parallel array of SLM imaging units shown in Figure 7 of the SLM imaging unit parallel array example 0 according to an embodiment of the present invention. The right side of Figure 9 illustrates how the array imaging system of the embodiment of the present invention can be used. [5 process window σ optimization, ^ left side and the latter are - a known single lens projection system. Figure 10 is a diagram showing a method for optimizing local unevenness of a substrate in an embodiment of the present invention. FIG. 11 is a diagram showing an application manner of a reticle data structure in an embodiment of the present invention. 65 201214515 = 12 ′′—A parallel addition total exposure method according to an embodiment of the invention. The margin of the square L riding forest (four) real complement + - planting into the system to form redundancy in the system - shown - wedge boundary fusion method according to an embodiment of the present invention. The square =. In the embodiment of the present invention, the SIJ imaging unit is arranged in an array. The 16th embodiment of the present invention is an example of a two-dimensional array imaging writing system for manufacturing a flexible display. . ..., Figure 17 shows an SLM imaging unit in accordance with an embodiment of the present invention. Figure 8 is a diagram showing a linear array reticle lithography method using an SLM imaging unit in an embodiment of the present invention. Figure 19 is a diagram showing a two-dimensional array maskless lithography method using an SLM imaging unit in an embodiment of the present invention. Figure 20 is a diagram showing a method for imaging a same flexible reelable substrate by using a maskless lithography method for a plurality of products due to different data sizes of the reticle in the embodiment of the present invention. Figure 21 is a diagram showing a method of locating each SLM imaging unit according to the local condition of the surface of the substrate in the embodiment of the present invention. FIG. 22 illustrates a method for detecting pixel focus in an embodiment of the present invention. 23a to 23c illustrate three examples of devices for instantly detecting the focus of an SLM imaging unit in an embodiment of the present invention. Fig. 24 is a view showing an example of an imaging pattern suitable for a pixel total exposure method in an embodiment of the present invention. 66 201214515

第25圖繪示本發明實施例中一種透過像素加總曝光法改呈 焦深（D0F)之方法。 Q 第26a與26b圖繪示本發明實施例中利用重疊區域接合相鄰 成像區之方法。 第27a與27b圖繪示本發明實施例中量測及利用相鄰Μ成 像單元中心間之視點間距之方法。 第28a與28b _示本發明實施例中成像寫入系統量測及修 正對準狀態之方法。 第28c與28d圖缘示本發明實施例中元件瑕疲判定及利用對 準關連性確定瑕疵所在位置之方法。 第29a至29d圖緣示本發明實施例中之三維積體電路益光罩 平行製造法。 第30圖繪示本發明實施例中之一或多個晶圓直接成像法。 第31 _示根據本發明實施例之—無光轉描曝光系統。 第32a與32b圖綠示本發明實施例中利用部分晶圓之益 平行製造法。 ” 第32c與32d崎示本發明實施例中為不同形狀可挽性基板 之設計圖案直接成像之方法。 第33a與33b圖!會示本發明實施例中之無光罩製造法。 在本說明書巾，相同之元件均使肋同標號。 67 201214515 【主要元件符號說明】 卜3、 5、6、7、8、9 SLM 102 反射鏡（先前技術） 104 光罩（先前技術） 106 投影透鏡（先前技術） 108 FPD基板（先前技術） 110 光源（先前技術） 112 第一投影透鏡（先前技術） 114 光罩（先前技術） 116 第二投影透鏡（先前技術） 118 晶圓（先前技術） 120 晶圓平台（先前技術） 122 光罩投影成像區（先前技術) 130 光罩（先前技術） 131 投影透鏡（先前技術） 132 基板晶圓（先前技術） 202 照明光（先前技術） 204 分光鏡（先前技術） 206 空間光調變器（先前技術） 208 傅利葉透鏡（先前技術） 210 傅利葉濾光鏡（先前技術） 212 縮小透鏡（先前技術） 68 201214515 214 光罩資料（先前技術） 216 空白光罩基板（先前技術） 302、304 數位微鏡裝置（DMD)或空間光調變器晶片（SLM) 306 傾斜之微鏡 308 維持原本位置不變之微鏡 402 啟動狀態 404 持平狀態 406 關閉狀態 408 光源 410 投影透鏡 502 共面之柵狀光閥（GLV)帶狀元件 504 交替折曲之柵狀光閥（GLV)帶狀元件 602 空間光調變器 604 微鏡 606 照明光源 608 對準光源 610 投影透鏡 702、704、706、708 SLM成像單元平行陣列 802 SLM成像單元 902 單一透鏡投影系統（先前技術） 904 折衷焦平面（先前技術） 906 基板表面之實際剖面形狀（先前技術） 69 201214515 908 單一透鏡為圖案成像時之最佳焦點設定範圍（先前技術） 910 各成像透鏡所對應之基板表面剖面形狀最大變化範圍（先 前技術） 912 成像單元 914 焦點 916 焦深設定範圍 1002 基板表面形狀不平之區域 1102 光罩資料實例 1104 扁平化光罩資料 1106 分區光罩資料圖案 1108 光罩圖案重疊部分 1201至1208 部份SLM成像方塊 1402 不匹配邊界 1404 邊界末端 1406 成像單元寫入區域 1502 SLM成像單元 1600 二維陣列式無光罩成像寫入系統 1602 SLM成像單元 1702 藍光及紅光二極體雷射 1704 孔口 1706 透鏡 1708 球面鏡 201214515 1710 數位微鏡裝置（DMD)或空間光調變器晶片（SLM) 1712 印刷電路板 1714 光束收集裝置 1716 分光鏡 1718 CCD攝影機 1720 透鏡總成 1722 紅光雷射二極體 1723、1724、1725、1726 藍光雷射二極體 1802 SLM成像單元 1804 可撓性捲軸式基板 1902 SLM成像單元二維陣列 1904 可撓性捲軸式基板 2002 SLM成像單元二維陣列 2006、2008、2010、2012、2014 不同「光罩數據」設計圖案 2102 SLM成像單元線性陣列 2104 基板表面 2202、2204 明暗像素 2206、2208 準焦狀態之明暗像素 2210 失焦狀態之明暗像素 2302 成像光源 2304 分光鏡 2306 物鏡 71 201214515 2308 外殼 2310 第一攝影感測器 2312 第一馬達 2314 第一折射盤 2316 第一光程差調變器 2317 圓形光學裝置 2318 扇形部分 2322 第二攝影感測器 2326 第二光程差調變器 2330 第三光程差調變器 2502 不同焦點設定 2504 最終焦深 2602 成像區 2604 空間光調變器 2606 成像區 2608 空間光調變器 2610 重疊區域 2612 理論邊界 2614、2616 使用者自訂邊界 2622 成像區 2624 空間光調變器 2626 成像區 72 201214515 2628 空間光調變器 2630 重疊區域 2632 理論邊界 2634、2636 使用者自訂邊界 2638、2639 折線 2702、2704、2706 SLM 之中心點 2708、2710、2712、2714 各 SLM 成像區 2802 SLM #7直接成像區 2803 SLM #7 2804 光罩資料 2805 「+」邊界之識別符號 2806所量測之圖案 2807 相鄰SLM間成像區之角落 2808 所需之圖案 2810 瑕疵 2812 平行矩形 2820 小型深色區域 3002 第一晶圓 3004 第二晶圓 3202 心形可撓性基板之設計圖案 3204 彎曲可撓性基板之矩形設計圖案 A、B、C、D、E、F、G 積體電路内之各部設計功能區塊 73Figure 25 is a diagram showing a method of changing the depth of focus (D0F) by the pixel total exposure method in the embodiment of the present invention. Q Figures 26a and 26b illustrate a method of joining adjacent imaging regions using overlapping regions in an embodiment of the present invention. Figures 27a and 27b illustrate a method of measuring and utilizing the viewpoint spacing between adjacent centers of imaging units in accordance with an embodiment of the present invention. The 28a and 28b show a method of measuring and correcting the alignment state of the image writing system in the embodiment of the present invention. Figures 28c and 28d illustrate the method of determining the component fatigue in the embodiment of the present invention and determining the location of the defect using the alignment property. Figs. 29a to 29d illustrate the parallel manufacturing method of the three-dimensional integrated circuit benefit hood in the embodiment of the present invention. Figure 30 illustrates one or more wafer direct imaging methods in an embodiment of the invention. A 31st-showless light transmissive exposure system in accordance with an embodiment of the present invention. The 32a and 32b diagrams illustrate the parallel manufacturing method of utilizing a portion of the wafer in the embodiment of the present invention. 32c and 32d show a method for directly imaging a design pattern of a different shape of a slidable substrate in the embodiment of the present invention. Figs. 33a and 33b show a method of manufacturing a mask without a mask in the embodiment of the present invention. Towels, the same components are given the same ribs. 67 201214515 [Description of main component symbols] Bu 3, 5, 6, 7, 8, 9 SLM 102 Mirror (Prior Art) 104 Photomask (Prior Art) 106 Projection Lens ( Prior Art) 108 FPD Substrate (Prior Art) 110 Light Source (Prior Art) 112 First Projection Lens (Prior Art) 114 Photomask (Prior Art) 116 Second Projection Lens (Prior Art) 118 Wafer (Prior Art) 120 Crystal Circular Platform (Prior Art) 122 Shutter Projection Imaging Area (Prior Art) 130 Photomask (Prior Art) 131 Projection Lens (Prior Art) 132 Substrate Wafer (Prior Art) 202 Illumination Light (Prior Art) 204 Beamsplitter (Previous Technology) 206 Spatial Light Modulator (Prior Art) 208 Fourier Lens (Prior Art) 210 Fourier Filter (Prior Art) 212 Shrink Lens (Prior Art) 68 201214515 214 Mask Data (Prior Art) 216 Blank Mask Substrate (Prior Art) 302, 304 Digital Micromirror Device (DMD) or Spatial Light Modulator Chip (SLM) 306 Tilted Micromirror 308 Maintaining the original position unchanged micromirror 402 activation state 404 flat state 406 off state 408 light source 410 projection lens 502 coplanar grating light valve (GLV) strip element 504 alternately curved grating light valve (GLV) ribbon Element 602 Spatial Light Modulator 604 Micromirror 606 Illumination Light Source 608 Alignment Light Source 610 Projection Lens 702, 704, 706, 708 SLM Imaging Unit Parallel Array 802 SLM Imaging Unit 902 Single Lens Projection System (Prior Art) 904 Compromise Focal Plane ( Prior Art) 906 Actual Sectional Shape of Substrate Surface (Prior Art) 69 201214515 908 Best Focus Setting Range for Single Lens for Pattern Imaging (Prior Art) 910 Maximum Variation Range of Substrate Surface Profile Shape for Each Imaging Lens (Prior Art 912 imaging unit 914 focus 916 depth of focus setting range 1002 substrate surface shape uneven area 1102 light Data Example 1104 Flattening Mask Data 1106 Partition Mask Data Pattern 1108 Mask Pattern Overlays 1201 to 1208 Partial SLM Imaging Blocks 1402 Mismatch Boundary 1404 Boundary End 1406 Imaging Unit Write Area 1502 SLM Imaging Unit 1600 Two-Dimensional Array Maskless Imaging System 1602 SLM Imaging Unit 1702 Blu-ray and Red LED Laser 1704 Hole 1706 Lens 1708 Spherical Mirror 201214515 1710 Digital Micromirror Device (DMD) or Spatial Light Modulator Chip (SLM) 1712 Printed Circuit Plate 1714 Beam Collector 1716 Beamsplitter 1718 CCD Camera 1720 Lens Assembly 1722 Red Laser Dipoles 1723, 1724, 1725, 1726 Blue Laser Diodes 1802 SLM Imaging Unit 1804 Flexible Rolled Substrate 1902 SLM Imaging Unit 2D Array 1904 Flexible Rolled Substrate 2002 SLM Imaging Unit 2D Array 2006, 2008, 2010, 2012, 2014 Different "Mask Data" Design Patterns 2102 SLM Imaging Unit Linear Array 2104 Substrate Surfaces 2202, 2204 Bright and Dark Pixels 2206 , 2208 light and dark pixels of the quasi-focus state 2210 light and dark pixels of the out-of-focus state 2302 imaging light source 2304 Beam splitter 2306 Objective lens 71 201214515 2308 Housing 2310 First photographic sensor 2312 First motor 2314 First refracting disk 2316 First optical path difference modulator 2317 Circular optical device 2318 Sector portion 2322 Second photographic sensor 2326 Second optical path difference modulator 2330 third optical path difference modulator 2502 different focus setting 2504 final depth of focus 2602 imaging area 2604 spatial light modulator 2606 imaging area 2608 spatial light modulator 2610 overlapping area 2612 theoretical boundary 2614 2616 User-defined boundary 2622 Imaging area 2624 Spatial light modulator 2626 Imaging area 72 201214515 2628 Spatial light modulator 2630 Overlapping area 2632 Theoretical boundary 2634, 2636 User-defined boundary 2638, 2639 Polyline 2702, 2704, 2706 SLM center points 2708, 2710, 2712, 2714 SLM imaging area 2802 SLM #7 direct imaging area 2803 SLM #7 2804 Mask data 2805 "+" boundary identification symbol 2806 measured pattern 2807 adjacent SLM imaging Corner of the Zone 2808 Required Pattern 2810 瑕疵 2812 Parallel Rectangular 2820 Small Dark Zone 3002 First Wafer 3004 Second Wafer 3202 Heart Shape Design of functional block 73 within each part of the rectangle 3204 the bent flexible substrate of the flexible substrate designs designs A, B, C, D, E, F, G integrated circuit

Claims (1)

201214515 七、申請專利範圍： -種製造-三_體電路之方法，包含下列步驟： 提供-成像寫人系統，其中該成像寫人祕包 ==⑽）成像單元，該等SLM成像單元係觸成—或= ―或多接I光罩資料，射該光料料係供寫人該三維積體電路之 =里該光罩資料，俾形成複數個對應於該三維積 一或多層之分區光罩資料圖案； r 圖案指ΓΓ多辦侧綱元峨理梅區光罩資料 控制該等SLM成像單元，俾將該等分 入該三維積體電路之該—或多層。 胃侧案千仃寫 2.如申請專利範圍第！項之 slm成像單元之步驟包含： m或多個所述 根據該等SLM成像單元，對該等分區光罩 比例修正，其_各該分 、_進仃減 的修正。 尤罩貝科圖案均具有一對應之縮放比例 3·如申請專利範圍第i項 Μ成像單元之步驟尚包含： 、中“一或多個所述 74 201214515 a根據該等SLM成料元，雜等分區光罩資料®案進行對準 狀射各该分區光軍資料圖案均具有一對應之對準狀態 的修正。 〜 士申°月專利範圍第^項之方法，其中指派—或多個所述 SLM成像單元之步驟尚包含： 根據该等SLM成像單元，職等分區光料料随進行視點 門巨GJE射各该分區光單資料圖案均具有一對應之視點間距 的修正。 5. 如申請專利範圍第1項之方法，其中指派-或多個所述 SLM成像單元之步驟尚包含： 根據該等SLM成像單元，對該等分區光罩㈣圖案進行轉動 因子GJL &中各該分區光罩資料圖案均具有一對應之轉動因子 的修正。 6. 如U利範圍第1項之方法，其中指派—或多個所述 SLM成像單元之步驟尚包含： "根據該等SLM成像單元，對該等分區光罩㈣圖案進行基板 交祕正，其巾各該分區鮮資料随均具有—對應之基板變形 的修正。 7. 如申晴專利範圍第1項之方法，其中控制該等SLM成像 單元之步驟包含： 針對mu成像單元，使—對應之所述分區光罩資料圖案 獨立於該成像寫入系統中其他所述SLM成像單元而曝光。 75 201214515 8. —種製造一三維積體電路之系統，包含·· /複數個空間光調變器⑽）成像單元，該等syi成像單元 係排列成一或多個平行陣列；及 -用以控制該等SLM成像單元之控制器，其包含： 第-邏輯，㈣触光料料，射該光料料係供寫 入該二維積體電路之一或多層； 第二邏輯’用以處理該光罩資料，形成複數個對應於該 二維積體電路中該—衫層之分區光罩資料圖案； 第三邏輯，用以指派一或多個所述SLM成像單元負責處 理各該分區光罩資料圖案；以及 、 罩資控制該等SLM成像單元，將該等分區光 罩貝侧案千仃寫入該三維積體電路之該一或多層。 9‘如申請專利範圍第8項之系統， 個所述SLM成像單元之第三邏輯包含： 或夕 第五邏輯，其可根據該等Μ成像軍元，對該 料圖案進纖嘯正，射各該峨 = 對應之縮放正。 ®购具有- 10.如申請專利範圍第8項之系統，其 個所述SLM成像單元之第三邏輯尚包含： 或夕 第六邏輯，其可根據該等SLM成像單元，對 ==:=，各該分_資_: 76 201214515 11. 如中請專利範圍第8項之系統，复中 個所述SLM成像單元之第三邏輯尚包含： ^ u指派一或多 第七邏輯，其可根據該等SLM成像單元，對 料圖案進行視點間距修正，其中各該分區光^刀區光罩資 對應之視點間距的修正。 案均具有一 12. 如申請專利範圍第8項之系統，㈠ 個所述SLM成像單元之第三邏輯尚包含：Λ M指派-或多 第八邏輯，其可根據該等SLM成像單元 料圖案進行轉動因子修正，其中各 區光罩資 對應之轉_子的修正。 〜£衫讀_均具有一 13. 如申請專利範圍第8項之系統，其中 個所述SLM成像單元之第三邏輯尚包含： ^‘派一或多 第九邏輯，其可根據該等SLM成像單元，對 料圖案進行基板變形修正，其中各該分區光罩資料圖^光罩資 對應之基板變形的修正。 圖案均具有一 14. 如申請專利範圍第8項之系統， 成像單元之第四邏輯包含： …用W控制該等SLM 第十邏輯，其可針對各該SLM 區光罩資料_而可各觸減光’使—對應之所述分 入系統中其㈣叫=^之不必咖於該成像寫 15. -種利用部分晶圓之製造方法，包㈣步 77 201214515 提供一成像寫入系統， 光調變器（SLM)成像單元， 平行陣列； 其中該成像寫入系統包含複數個空間 該等SLM成像單元係排列成—或多個 提供-或多個待加工製造之部分晶圓 寫入該一或多個部分 曰曰 接收光罩資料，其巾該光罩資料係供 圓之基板； #罝次μ Λ鮮胃料以軸複數個分區光罩資料圖案，該等分區 先草貝咖案係對應於該—或多個部分晶圓之所述基板； 指派-或多個所述SLM成像單元負責處理各該分區光罩資料 圖案’其中所派包含至少執行下列射之—：縮放比例修正、 對準狀態修正、視闕贿正、轉_子紅與基板變形修正； 以及 控制該等SLM成像單元，俾將該等分區料資料圖案平行寫 入該一或多個部分晶圓之所述基板。 ··“ 16.-種在-印刷電路板⑽）上平行製造複數個設計圖 案之方法，包含下列步驟： 提供-成像寫人系統，其中該成像寫人系統包含複數個空間 光調變器（SLM)成像單元，該等SLM成像單元係排列成 平行陣列； 提供一印刷電路板，其中該印刷電路板已劃分為複數區域， 各該區域包含一待製造之設計圖案； 78 201214515 接收光罩資料，其中該光罩資料用來寫入該印刷電路板之該 複數區域，· 處理該光罩資料，形成複數個對應於該印刷電路板該複數區 域之分區光罩資料圖案； 指派-或多個所述SLM成像單元負責處理各該分區光 以及 =狀 tir指派包含至少執行下列其中之-:縮放比例修正、 =、鋼雜正、咖恤喻變形修正； 資料圖案平行寫 控制該等SLM絲單元，俾將該等分區光罩 入該印刷電路板之該複數區域。201214515 VII. Patent application scope: - A method for manufacturing a three-body circuit, comprising the following steps: providing an image-writing system, wherein the imaging writer (=10) imaging unit, the SLM imaging unit is in contact Into or - or - or more than the I mask data, the light material is used to write the reticle data of the three-dimensional integrated circuit, and a plurality of partition lights corresponding to the one or more layers of the three-dimensional product are formed. The cover data pattern; the r pattern refers to the multi-segment element 峨 梅 梅 区 光 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制The stomach side case is written in thousands of miles. The step of the slm imaging unit comprises: m or a plurality of said corrections according to the SLM imaging units, and the correction of the divisional masks. The U.S. Beans pattern has a corresponding scaling ratio. 3. The steps of the imaging unit of the i-th aspect of the patent application range include: , "One or more of the 74 201214515 a according to the SLM constituent elements, miscellaneous The zonal reticle data case is aligned and each of the zonal ray data patterns has a corresponding alignment correction. ~ The method of the syllabus of the patent scope, where the assignment - or multiple The steps of the SLM imaging unit further include: according to the SLM imaging unit, the graded light material of the graded area has a corresponding correction of the viewpoint spacing according to the macroscopic GJE of the viewpoint gate. The method of claim 1, wherein the step of assigning - or the plurality of the SLM imaging units further comprises: performing, according to the SLM imaging units, the partitioning mask (four) pattern by the rotation factor GJL & The mask data pattern has a corresponding correction of the rotation factor. 6. The method of claim 1, wherein the step of assigning - or the plurality of SLM imaging units comprises: " according to the SLM For the image unit, the masks of the partition masks are subjected to the correctness of the substrate, and the fresh materials of the respective masks have the corresponding correction of the deformation of the substrate. 7. The method according to the first item of the Shenqing patent scope, wherein the control The steps of the SLM imaging unit include: for the mu imaging unit, causing the corresponding partitioned mask data pattern to be exposed independently of other of the SLM imaging units in the imaging writing system. 75 201214515 8. a three-dimensional integrated circuit system comprising: / / a plurality of spatial light modulators (10)) imaging units arranged in one or more parallel arrays; and - a controller for controlling the SLM imaging units The method includes: a first logic, (4) a light-sensitive material, the light material is used to write one or more layers of the two-dimensional integrated circuit; the second logic is used to process the light mask data to form a plurality of corresponding a partition mask data pattern of the shirt layer in the two-dimensional integrated circuit; a third logic for assigning one or more of the SLM imaging units to process each of the partition mask data patterns; and Controlling the SLM imaging units, writing the partition masks to the one or more layers of the three-dimensional integrated circuit. 9', as in the system of claim 8, the SLM imaging unit The third logic includes: or the fifth logic, which can image the military element according to the Μ, and the symmetry of the material pattern is shot, and the corresponding 峨 = corresponding scaling is positive. The system of the eighth aspect, wherein the third logic of the SLM imaging unit further comprises: or a sixth logic, according to the SLM imaging unit, for ==:=, each of the points _: _ 76 201214515 11. The system of claim 8, wherein the third logic of the SLM imaging unit further comprises: ^ u assigning one or more seventh logics, which can be based on the SLM imaging units The pattern performs a correction of the viewpoint spacing, wherein the correction of the viewpoint spacing corresponding to the photomask of each of the partitions is performed. The case has a system of 12. In the system of claim 8, the third logic of the SLM imaging unit further comprises: Λ M assignment - or multiple eighth logic, which can be based on the SLM imaging unit pattern The rotation factor correction is performed, wherein the correction of the rotation _ sub-corresponding to each zone photomask is performed. Each of the SLM imaging units has a third logic that still includes: ^ 'Send one or more ninth logic, which can be based on the SLMs. The imaging unit performs a substrate deformation correction on the material pattern, wherein each of the partition mask data sheets is corrected for the deformation of the substrate corresponding to the mask. The pattern has a system of 14. In the system of claim 8, the fourth logic of the imaging unit comprises: ... controlling the SLM tenth logic with W, which can be touched for each SLM area mask data The dimming 'make- corresponding to the sub-system into the system, (4) called = ^ does not have to be written in the image writing 15. - a method of using part of the wafer manufacturing method, package (four) step 77 201214515 provides an imaging writing system, light a modulator (SLM) imaging unit, a parallel array; wherein the imaging writing system comprises a plurality of spaces, the SLM imaging unit is arranged in a plurality or a plurality of wafers to be processed or a plurality of wafers to be processed are written to the one Or a plurality of parts 曰曰 receiving the reticle data, and the reticle data is for the substrate of the circle; #罝次μ ΛFresh stomach material is a plurality of partition reticle data patterns of the axis, and the partitions are first Corresponding to the substrate of the one or more partial wafers; assigning - or the plurality of the SLM imaging units are responsible for processing each of the partitioned mask data patterns 'where the included ones perform at least the following shots:: scaling correction, Alignment state repair , Depending Que bribery n, and the substrate rotation _ red sub-distortion correction; and controlling the plurality of SLM imaging units, to serve the expected data pattern of partitioned into parallel write the one or more of the portions of the wafer substrate. A method of making a plurality of design patterns in parallel on a printed circuit board (10), comprising the steps of: providing an image writing system, wherein the imaging writer system comprises a plurality of spatial light modulators ( An SLM) imaging unit, the SLM imaging units are arranged in a parallel array; a printed circuit board is provided, wherein the printed circuit board has been divided into a plurality of regions, each of which includes a design pattern to be manufactured; 78 201214515 receiving mask data The mask data is used to write the plurality of regions of the printed circuit board, and the mask data is processed to form a plurality of partition mask data patterns corresponding to the plurality of regions of the printed circuit board; The SLM imaging unit is responsible for processing each of the partitioned light and the =tir assignment includes at least one of: - scaling correction, =, steel miscellaneous, and sculpt deformation correction; data pattern parallel writing controls the SLM wire units And lining the partitions into the plurality of regions of the printed circuit board.