201211999 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種在液晶顯示器中降低電磁干擾(electromagnetic interference，EMI)的技術，尤其是，涉及一種用於降低EMI之液晶顯示器的 源極驅動器，其藉由允許用於驅動液晶顯示面板的資料信號從源極驅動器分 散並輸出。 【先前技術】 通常，液晶顯示器包含：液晶顯示面板，其中複數個閘極線與複數個資 料線在方向上相互垂直排列，以具有一矩陣形式的像素區域；驅動電路單 元，用於提供驅動信號以及資料信號於該液晶顯示面板；以及背光單元，用 於提供光源至該液晶顯示面板。 該驅動電路單元包含源極驅動器，用於提供資料信號於該液晶顯示面板 内的各個資料線；閘極驅動器，用於施加閘極驅動脈衝於該液晶顯示面板内 的各個閘極線；時序控制器，用於接收自該液晶顯示面板的驅動系統所輸入 之諸如顯示資料、垂直與水平同步信號以及時鐘信號等控制信號，以輸出具 有適合於該源極驅動器與該資料驅動器之時序的所接收的控制信號以產生 影像。 第1圖為習知源極驅動器的方塊圖。如此圖所示，該源極驅動器包含位 移暫存器單元110、鎖存單元120、數位類比（digital_t〇_anal〇g，D/A)轉換 器130以及輸出緩衝器14〇。 、 位移暫存器110使用時鐘信號CLK依序地位移取樣啟動信號ss ^ 鎖存單7L 120使用自位移暫存器11〇輸出的取樣啟動信號ss依序地鎖 存從時序控制器（未顯示）提供之每個通道的RGB影像資料（下文 為“資料”）DATA。 D/A轉換器no將鎖存單元12G所鎖存的數位㈣轉換為類比資料作 號。該類比資料信號依據極性信?虎助具有與公共電壓V相關的正值^ 負值0 〆 輸出緩衝胃140放大D/A轉換器130所轉換的該類比資料信號，並輪出 201211999 所放大的類比資料信號至液晶顯示面板的資料線D1至Dn。 鎖存單元120依序地鎖存每個通道的資料，並且同時輸出該資料。因此， 所有通道的資料電壓同時地從該輸出緩衝器14〇載入至各自的資料線D1至 Dn ° 如上所述，在習知液晶顯示器的源極驅動器中，所有通道的資料皆同時 輸出，因此，功率集中化。所以，由於功率集中化，嚴重地產生電磁干擾 (electromagnetic interference，EMI)。 【發明内容】 因此，本發明所要解決的是在現有技術中出現的問題，以及本發明的 一目的在於提供用於降低EMI的液晶顯示器的源極驅動器，其中當該源極驅 動器的鎖存器鎖存各通道的資料並輸出該所鎖存的資料時，各通道的資料同 時以預定的時差分散並輸出。 本發明的另-·目的在在於提供用於降低EMI的液晶顯示器的源極驅動 器，其中使用RC延遲器或HV反相器作為延遲元件，用於允許各通道的資 料同時以預定的時差分散並輸出。 本發明的又一目的在於提供用於降低EMI的液晶顯示器的源極驅動 器，其中當該源極驅動器的輸出緩衝器輸出資料信號時，該資料信號以一時 差依序地延遲的方式分散並輸出。 可了解到，本發明所解決的技術問題不限於上述技術問題，以及未提及 其他技術問題從以下說明書中對熟習該項技藝者將是顯而易見的。 為了達到上述目的，根據本發明的一方面，提供一種用於降低EMI的液 晶顯示器的源極驅動器，該源極驅動器包括：一第一鎖存單元，被配置以依 序地鎖存用於驅動液晶顯示面板之各通道的資料輸入驅動信號輸出單 广，被配置以輸出輸入驅動信號；複數個延遲器，被串聯連接而依序地延遲 該等輸入驅動信號；一第二鎖存單元，被配置以使用透過該等延遲器所依序 地延遲並且輸出的該等輸入驅動信號，依序地鎖存由該第一鎖存單元以一時 門差所鎖存之各通道的資料；以及一數位類比，d/a)轉換 器’被配置以將從該第二鎖存單元輸出之各通道的資料轉換為類比信號，並 輸出該所轉換的類比信號至一輸出緩衝器。 201211999 依據本發明另一方面，提供有一種用於降低EMI的液晶顯示器的源極驅 動器，S玄源極驅動器包括：一第一鎖存單元，被配置以依序地鎖存用於驅動 液晶顯示面板之各通道的資料；一輸入驅動信號輸出單元，被配置以輸出輸 入驅動彳S號，以使得由該第一鎖存單元所鎖存的資料在每一位元都被鎖存； 一第二鎖存單元，被配置以使用從該輸入驅動信號輸出單元輸出的該等輸入 驅動信號，依序地鎖存各通道的資料，該資料是藉由該第一鎖存單元以每一 位元一時間差的方式鎖存；以及一 D/A轉換器，被配置以將從該第二鎖存單 元輸出之各通道的資料轉換為類比信號，並輸出該所轉換的類比信號至一輸 出緩衝器。 1 依據本發明又一方面’提供一種用於降低EMI的液晶顯示器的源極驅動 器’該源極驅動器包括：一第一鎖料元，被配置以依序地鎖存用於驅動液 晶顯示面板之各通道的資料；一輸入驅動信號輸出單元，被配置以輸出輸入 驅動信號；複數個延遲ϋ，被配置以接收各自的該等輸人驅動信號，並藉由 一延遲量依序地延遲該等所接收的輸入驅動信號；一第二鎖存單元，被配置 以使用透職等延遲騎依雜延遲錄丨的該频人鶴舰，依序地鎖 存各通道的資料，該資料是藉由該第_赫單元_躲該延遲量的一時間 ，鎖存；以及-D/A轉換^ ’被配置靖從該第二鎖存單元輸出之各通道的 資料轉換為類比信號，並輸出該所轉換的類比信號至— …依據本發明又-方面，提供於降低聽的液==源極驅動 益’ 6玄源極驅動器包括：一資料輸出控制單元，被配置以當一資料作號由一 液晶顯示面板的各师料通道輸㈣，輸出—關控繼號驗以二所\ ^出_’第-延遲單元及第二延遲單元，被配置以—預定時間依序地延遲從 ^資料輸出控制單元輸出的該開關控制舰，並輸出該所延遲的開關控制信 I，-具有複數個多工㈣第-輸出緩衝單元置，被配置以使用由該第一延 ，皁该序地延遲並輸出的該_控制紐，選槪—放大器輸出的類比偉 ^ f出該所選擇的類比信號至—相應通道；以及_具有複數個多工器的 輸出_衫’被配置以使用由該第二延遲私依序地延遲 道選擇從一放大器輸出的類比信號，並輸出該所選擇‘ 201211999 4 【實施方式】 現將引用所關式以詳細說明本發明的具體實施例。盡可能地，所附圖 式中涉及的相同或類似的元件將採用相同的附圖標記。 第2圖為依據本發明的實施例，用於降低贿❸純顯示器的源極驅動 态的方塊圖。如此圖所示，該源極驅動器包含位移暫 巧元2胤、第二鎖存單元施、輸人驅動信號輸出二现、論第轉換 器240以及輸出緩衝器250。 位移暫存器單元21〇使用時鐘信號CLK依序地轉換取樣啟動信號ss。 第-鎖存單元22〇A使用從位移暫存器單元21〇輸出的該取樣啟動信號 依序地鎖存由時序控制器（未顯示）提供之各通道的資料data。 ▲鎖存第鎖存單元22〇B所鎖存之各通道的資料時，第三鎖存單元 220B。不同時鎖存該資料，但使用從輸入驅動信號輸出單元挪輸出的輸入驅 動^號DRV以一預定時差鎖存該資料DATA。 第3 _顯示提供來自輸入驅動信號輸出單元23〇的輸入驅動信號drv 鎖存單①2208的波糊。換言之，在將源極輸出致能信號S0E啟動 為=第3圖的（a)所示的“高”的狀態，輸入驅動信號輸出單元23〇以如第 -(e)所不的—預㈣差’依序地提供輸人驅動信號drv。第 :2=70 22GB鎖存對應於該所提供的輸入驅動信號drv的資料，並輸出 该所鎖存的資料至D/A轉換器240。 眘轉換器240將由第二鎖存單元22〇B所鎖存的數位資料轉換為類比 1觸比捕錢依雜性魏PL<D具有與公共餅VeGm相關的 正值或負值。 物ί ί緩衝$ 25G放大由D/A轉換器24G所轉換的類比資料信號，並輸出 S在#類比資料信號至液晶顯示面板的資料線D1 至Dn。 I文巾’將參關式’詳細描述其巾分散並輸出資料信號的實施例。 枓參閱第4圖，將描述其中使用複數個串聯的延遲器分散並輸出資 枓k旒的第一實施例。 SR 5上所述位移暫存器單元210的位移暫存器SR-L11至SR-Llm以及 ~筮—至SR~Rlm使用時鐘信號0^ ’依序地位移取樣啟動信號SS。 鎖存單元220A的鎖存器LA_L11至LAJLlm以及LA_R11至 201211999 ‘ LA_Rlm使用從位移暫存器單元210輸出的取樣啟動信號SS，依序地鎖存資 料 DATA1 以及 DATA2。 透過延遲器DJL11至D_Llm以及D_R11至D_Rlm，從輸入驅動信號 輸出單元230輸出的輸入驅動信號DRV依序地被延遲。 在通道的資料都被第一鎖存器單元220A的鎖存器LA_L11至LA_Llm 以及LA_R11至LA_Rlm鎖存後，第二鎖存單元220B的各個鎖存器LA_L21 至LA一L2m或LA_R21至LA_R2m鎖存相對應通道的資料。在此情況中， 該等鎖存器LA_L21至LA—L2m以及LA_R21至LA_R2m的每一個使用透 過由各個延遲器D_L11至D_Llm以及D_R11至D_Rlm所延遲並輸出之相 對應的輸入驅動信號DRV，以一預定時差依序地鎖存該相對應通道的資料。 例如，配置於輸入驅動信號輸出單元230左側的第一鎖存器LA_L21， 使用從輸入驅動信號輸出單元230輸出並被延遲器DJL11延遲一次.的輸入驅 動信號DRV，鎖存被第一鎖存單元220A的鎖存器LAJL11鎖存的資料。 第m鎖存器LA_L2m’使用從輸入驅動信號輸出單元230輸出並依序地 透過m個延遲器D—L11至D_Llm而延遲m次的輸入驅動信號DRV，鎖存 由第一鎖存單元220A的鎖存器LA_Llm所鎖存的資料。 因此，從第二鎖存單元220B的各個鎖存器LA_L21 至LA_L2m以及 LA—R21至LA_R2m輸出至d/Α轉換器240的各該通道的資料，可以與累積 延遲量相應的時差分散並輸出。 所述延遲器D L11至D Llm以及D R11至D Rlm可以多種方式實施。 第7圖中’延遲ft的實施例係使用由電阻與電容組成之Rc元件ri與⑽、 R2與M2 ’以及反相器n與12來實施。在此，各該金屬氧化物半導體⑽tal (^(^^—(^，(^電晶體⑽與心藉由將閉極連接至輸入終端、 將沒極連接至源極、然後將該沒極與源極之間的接觸點連接至接地端而作為 電容器使用。因此’可崎由增減RC元件R1與·、R2與M2以及反相 器II與12至所需的數量來得到所需的延遲量。 同時’將參閱第5圖描述對於各個通道的資料以每位元分開然後鎖存的 方式來分散與輸出資料的第二實施例。 如上所述’位移暫存器單元21〇的位移暫存器sun至SR_Llm以及 SR—R11至SR Rlm使㈣鐘信號CLK ’依序地位移取樣啟動信號％。 201211999 如上所述’第一鎖存單元220A的鎖存器LA_L11至LA_Llm以及 LA_R11至LA_Rlm使用從位移暫存器單元21〇輸出的取樣啟動信號SS，依 序地鎖存資料DATA1以及DATA2。 輸入驅動信號輸出單元230輸出輸入驅動信號DRV，從而致使第二鎖存 單元220B在每預定的位元鎖存由第一鎖存單元220A所鎖存的資料，並且從 輸入驅動信號輸出單元230輸出的該輸入驅動信號DRV，透過延遲器D_L1 j 以及D—R11分別地被延遲，然後依序地供應至第二鎖存單元22〇b的各個鎖 存器LA—L21至LA一L2m以及LA_R21至LA_R2m的每個位元。因此，是將 各通道的資料以每一位元或每個預定位元數依序地輸出的方式來將資料分 散並輸出。 例如，從輸入驅動信號輸出單元230輸出的該輸入驅動信號DRV透過 各自的延遲器D L11以及D_R11而延遲，然後被提供至第二鎖存單元22〇b 的各個鎖存器LA一L21至LA_L2m以及LA_R21至LA_R2m的第一位元，從 而將各個通道之資料的該第一位元輸出。然後，該輸入驅動信號DRV透過 各自的延遲器D—L11以及D—R11而延遲，然後被提供至各個鎖存器LA L21 至LA_L2m以及LA_R21至LA-R2m的第二位元，從而將各通道之資料的 該第二位元輸出。各通道之資料的最後一位元藉由提供輸入驅動信號DRV 至各該鎖存器LA—L21至LA—L2m以及LA—R21至LA_R2m的最後一位元而 輸出’然後再次輸出各通道之資料的第一位元。 儘管，在這個實施例中描述了資料從各個鎖存器LA__L21至LA_L2m以 及LA_R21至LA_R2m的每一位元輸出’但本發明不限於此。換言之，該 資料可以依據時間需求在每預定的位元數分散並輸出。 因此’從第二鎖存單元220B的各個鎖存器LAJL21至LA—L2m以及 LA R21至LA_R2m輸出至該d/Α轉換器240的各個通道的資料，可以被 分散並輸出。 同時，第二實施例將參閱第6圖來描述，其中資料按照同時地輸出輸入 驅動信號DRV’但透過具有不同延遲量的延遲器而分別地提供於通道的鎖存 器的方式來分散並輸出。 如上所述’位移暫存器單元210的位移暫存器SR_L11至Llm以及 SR一R11至SR_Rlm使用時鐘信號CLK，依序地位移元取樣啟動信號ss❶ 201211999 如上所述，第一鎖存單元220A的鎖存器LA_L11至LA_Llm以及 LA一R11至LA_Rlm使用從位移暫存器單元210輸出的取樣啟動信號ss，依 序地鎖存資料DATA1以及DATA2。 從輸入驅動信號輸出單元230輸出的輸入驅動信號DRV，透過具有不同 延遲量的各個延遲器D—L11至D Llm以及D_R11至D_Rlm而延遲，然後 依序地七供至該第一鎖存單元220B的各自的鎖存器la__L21至LA L2m以 及LA—R21至LA—R2m。因此，第二鎖存單元220B的鎖存器LA L21至 LA_L2m以及LA—R21至LA—R2m，以與該延遲器DJL11至D_Llm以及 D_R11至D—Rim的各個延遲量相對應的一時差來鎖存各通道的資料。 以延遲器D L11或D一R11作為最小延遲量且該延遲器D_Llm4D Rlm 作為最大延遲量的逐步增加形式來作為一實施例描述。 在此情況中’在鎖存器LA_L21至LA_L2m或LA—R21至LA_R2m中的 LA L21或LA_R21首先鎖存相對應通道的資料，接著下個鎖存器 或LA_R22，以對應於延遲器DJL12與D_R12之間的延遲量差作為一_時差 來鎖存相對應通道的資料。然後，該下個鎖存器LA—L23或LA-R23，以對 應於延遲H D_L13與D—R13之間的延遲量差作為—時差，而鎖存相對應通 道的資料i此’該鎖存器LA—L2m力LA—R2m最後鎖存最後—個通道的 資料。 因此，各該通道的資料可以從第二鎖存單22〇B的各個鎖存器la_l21 至LA_L2m以及LA_R21至LA_R2m以對應於延遲器D_lii與D—R11之間 的延遲量差的一時差分散並輸出至D/A轉換器24〇。 ，同時，第四實施例將參閱第8圖至第1G圖來描述，其中資料按照從輸 出緩衝器輸ίϋ的資料信n默時差而依序地親的方絲分散與輸出。 第8圖為本發明第四實施例的方塊圖。如此圖所示，源極驅動器包含資 巧出控制單元810、第-延遲單元、第二延遲單元_、第—輸出緩衝 器單元840、以及第二輸出緩衝器單元85〇。 資料輸出控制單元810輪出開關控制信號，用於分別控制提供在第一輸 出緩衝器單元840以及第二輸出緩衝器單元85〇的多工器。 :.第-延遲單元820藉由-單元延遲時間（第1〇圖中的‘f )依序地延遲從 資料輸出控制單元810輸出的各個開關控制信號，並且由第一延遲單元82〇 201211999 工 料 各個開關控制信號輸出至第—輪出緩衝器單元84G之相對應的多 類似地，第二延遲單元830以一單位延遲時間依序地延遲從資竹 制早—出的各個開關控制信號，並且由第二延遲單元83〇所延 職。m開關控制信號輸出至第二輸出緩衝器單元⑽之相對應的多工器 、s、首2實施财’如上所述，觸㈣輸出的嫌齡臟在與令央 通道對應之兩個外部（左與右）通道方向上依序地輸出。 元目的如上所述，第一延遲單元820延遲從資料輸出控制單 接供仏i㈠明難制信號，並且依序地輸出該延遲的開驗制信號至 個（例如’左）第一輸出緩衝器單元_的複數個多工器MUX。 於茫二1夕第。延遲單疋820依序地輸出從位於甲間的多工器刪^到位 於最左側的夕工器MUX的各個開關控制信號。 出的所述’第二延遲單元830延遲從資料輸出控制單元810輸 他（制如ifί號，並且依序地輪出該延遲的開關控制信號至提供給其 犧從位於她㈣職到位於最右側的多ί 益MUX的各個開關控制信號。 提供至第—輸鱗衝11單元84G的各個多卫器Μυχ，使用如上 ===麵觸，麵—器腑_類比資料 ，唬並輸出该等所選擇的類比資料信號至相對應通道OUTPUT。择果，盘 。亥等開關控制信號―樣’各通道的資料信號被延遲並輸出。 的如圖的⑻所示之未延遲的開關控制信號以及如第10圖 的⑷所不之較未延遲的開關控制信號進一步以時間 = ，門=至位於提供給第一輸出緩衝器單元840之 开工“ ^的多工器MUX。因此，位於中間的該多工器聰不延遲該 调但甘輸出該類比·信號至第一通道。然後，該多工器MUX藉由時門‘/ 類比資料信號，並輸出該延遲類比㈣信號至第二通道。隨後，各 ^夕工Is MUX依序地藉由該時間‘t，延遲該類 ，的類比資料信號至相對應的通道，以便於隨著位道 夕工器MUX ’輸出該進一步被延遲的類比資料信號。 〇 ，〇 201211999 第10圖的(a)為源極輸出啟動信號s〇E的波形圖。第1〇圖的(的至為 顯示被時間二延遲'並如上述透過多工器龐輸出之各通道的資料信號的 波形圖。換S之’第10縣完魏補雜輸級動信號S(DE^該時間‘t， 延遲並輸出的波形圖。 為此’第-延遲單元820具有複數個延遲器。該延遲器使用第7圖所示 的延遲器或常規延遲器可輕易地實現。 與第-延遲單元820以及第-輸出緩衝器單元84〇 一樣，第二延遲單元 830以及第二輸出緩衝器單元85〇執行與中間通道相對的右通道的操作，並 因此’該等通道的資料信號藉由料Fb1 ‘t，依序地延遲並如上述輸出。 同時’一第9圖解釋本發明的又—實施例。第9圖的實施例與第8圖的不 同在於.資料仏號藉由時間‘t’，從最外通道到巾間通道依序地延遲。 、換言之’在第8圖的實施例中，第一延遲單元82〇及第二延遲單元83〇 被配置在該等通道的中央部分，以及該等資料信號藉由時間‘t，，從該中間通 道到該最左或最右通道依序地延賴後輸出。另—方面，在第9圖的實施例 中，第-延遲單A 920及第二延遲單元93〇分別配置在該等通道的左側及右 側以及《亥等資料號藉由時間‘t，，從該最左或最右通道到該中間通道依序 地延遲然後輸出。 從以上·可知，本發明提供於降低膽的液晶顯示器的源極驅 ’其巾’當赫H鎖存各通道的=祕並輸出雜鎖存的諸，各通道的 資料使用輸人驅動紐，依序地以-預定時差或在每__位元分散並輸出 以更大限度地降低EMI。 本發明又提供一種用於降低腦的液晶顯#器的源極驅動器，其中，各 通道的資料轉從輸級衝ϋ輸出的諸賤，以―預定時差輯然後輸出 的形式分散並輸出，並因此’高賴的神被分散，從崎低贿。 以上所述僅為用於解釋本發明之較佳實施例，並非企圖據以對本發明做 =何形式上之限制，是以’凡有在補之創作精神下所作有關本發明之任 t飾或變更，皆仍應包括在本發明意圖保護之範疇。 【圖式簡單說明】 所附圖式其令提供關於本發明實施例的進一步理解並且結合與構成本 201211999 說明書的一部份，說明本發明的實施例並且描述一同提供對於本發明實施例 之原則的解釋。 圖式中： 第1圖為習知液晶顯示器的方塊圖； 第2圖為依據本發明的實施例，用於降低EM[的液晶顯示器的源極驅動 器的方塊圖； 第3圖的(a)是源輸出啟動信號的波形圖； 第3圖的(b)至(e)是在依序地延遲的同時，提供驅動信號於第二鎖存單元 的波形圖； 第4圖至第6圖為依據本發明的實施例，用於降低emi的該源極驅動器 的局部細節的方塊圖； ° 第7圖為顯示提供於本發明虹延遲器的實施例的電路圖； 第8圖為依據本發明的另一實施例’用於降低題的液 驅動器的方塊圖； 第9 ®為依據本發明的又—實施例，用於降低圓職晶顯示器的源 驅動器的方塊圖； 第1〇圖的(a)為源輸出啟動信號的波形圖；以及 ^ 10圖的(b)至⑷為在以時間“t”依序地延遲的同時， 出資 唬的波形圖。 【主要元件符號說明】 110 位移暫存器單元 120 鎖存單元 130 數位類比轉換器 140 輸出緩衝器 210 位移暫存器單元 220A第一鎖存單元 220B第二鎖存單元 230 輸入驅動信號輸出單元 240 D/A轉換器 12 201211999 250 輸出緩衝器 810 資料輸出控制單元 820 第一延遲單元 830 第二延遲單元 840 第一輸出緩衝器單元 850 第二輸出緩衝器單元 910 資料輸出控制單元 920 第一延遲單元 930 第二延遲單元 940 第一輸出緩衝器單元 950 第二輸出緩衝器單元 AMP 放大器 CLK 時鐘信號 Dl-Dn資料線 D_Lll〜D_Llm、D_Rll〜D_Rlm 延遲器 DRV 輸入驅動信號 II、12 反相器 LA_L11 〜LA_Llm、LA_Rll 〜LA_Rlm 鎖存器 M1、M2 MOS電晶體 MUX 多工器201211999 VI. Description of the Invention: [Technical Field] The present invention relates to a technique for reducing electromagnetic interference (EMI) in a liquid crystal display, and more particularly to a source driver for a liquid crystal display for reducing EMI, It is dispersed and output from the source driver by allowing a data signal for driving the liquid crystal display panel. [Prior Art] Generally, a liquid crystal display includes: a liquid crystal display panel, wherein a plurality of gate lines and a plurality of data lines are vertically arranged in a direction to each other to have a pixel area in a matrix form; and a driving circuit unit for providing a driving signal And a data signal to the liquid crystal display panel; and a backlight unit for providing a light source to the liquid crystal display panel. The driving circuit unit includes a source driver for providing data signals to respective data lines in the liquid crystal display panel, and a gate driver for applying gate driving pulses to respective gate lines in the liquid crystal display panel; timing control And a control signal input from a driving system of the liquid crystal display panel, such as display data, vertical and horizontal synchronization signals, and a clock signal, to output a received signal having a timing suitable for the source driver and the data driver Control signal to produce an image. Figure 1 is a block diagram of a conventional source driver. As shown in the figure, the source driver includes a shift register unit 110, a latch unit 120, a digital analogy (digital_t〇_anal〇g, D/A) converter 130, and an output buffer 14A. The shift register 110 sequentially shifts the sampling enable signal ss using the clock signal CLK. The latch single 7L 120 sequentially latches the sampling start signal ss from the shift register 11 从 from the timing controller (not shown). RGB image data (hereinafter referred to as "data") DATA for each channel provided. The D/A converter no converts the digit (4) latched by the latch unit 12G into an analog data number. The analog data signal is based on the polarity signal, and the positive value associated with the common voltage V is negative. 0 〆 The output buffer stomach 140 amplifies the analog data signal converted by the D/A converter 130, and is rotated by 201211999. The analog data signal is sent to the data lines D1 to Dn of the liquid crystal display panel. The latch unit 120 sequentially latches the data of each channel and simultaneously outputs the data. Therefore, the data voltages of all the channels are simultaneously loaded from the output buffer 14 至 to the respective data lines D1 to Dn ° as described above. In the source driver of the conventional liquid crystal display, the data of all the channels are simultaneously output. Therefore, power is concentrated. Therefore, due to power concentration, electromagnetic interference (EMI) is severely generated. SUMMARY OF THE INVENTION Accordingly, the present invention is to solve the problems occurring in the prior art, and an object of the present invention is to provide a source driver for a liquid crystal display for reducing EMI, wherein a latch of the source driver When the data of each channel is latched and the latched data is output, the data of each channel is simultaneously dispersed and output with a predetermined time difference. Another object of the present invention is to provide a source driver for a liquid crystal display for reducing EMI, in which an RC retarder or a HV inverter is used as a delay element for allowing data of each channel to be simultaneously dispersed by a predetermined time difference and Output. It is still another object of the present invention to provide a source driver for a liquid crystal display for reducing EMI, wherein when the output buffer of the source driver outputs a data signal, the data signal is dispersed and outputted in a manner of delay in a time difference . It is to be understood that the technical problems solved by the present invention are not limited to the above-mentioned technical problems, and other technical problems are not mentioned from the following description, which will be apparent to those skilled in the art. In order to achieve the above object, according to an aspect of the present invention, a source driver for a liquid crystal display for reducing EMI is provided, the source driver comprising: a first latch unit configured to sequentially latch for driving The data input drive signal output of each channel of the liquid crystal display panel is configured to output an input drive signal; a plurality of delay devices are connected in series to sequentially delay the input drive signals; a second latch unit is Configuring to sequentially latch data of each channel latched by the first latch unit with a one-time gate difference using the input drive signals sequentially delayed and outputted by the delays; and a digit The analog, d/a) converter is configured to convert data of each channel output from the second latch unit into an analog signal and output the converted analog signal to an output buffer. 201211999 According to another aspect of the present invention, a source driver for a liquid crystal display for reducing EMI is provided. The S-series source driver includes: a first latch unit configured to sequentially latch for driving a liquid crystal display Data of each channel of the panel; an input drive signal output unit configured to output an input drive 彳S number such that data latched by the first latch unit is latched at each bit; a second latch unit configured to sequentially latch data of each channel by using the input driving signals outputted from the input driving signal output unit, wherein the data is by each bit of the first latch unit a time difference manner latching; and a D/A converter configured to convert data of each channel output from the second latch unit into an analog signal, and output the converted analog signal to an output buffer . 1 according to still another aspect of the present invention, a source driver for a liquid crystal display for reducing EMI is provided. The source driver includes: a first lock cell configured to sequentially latch for driving the liquid crystal display panel Data for each channel; an input drive signal output unit configured to output an input drive signal; a plurality of delays ϋ configured to receive respective ones of the input drive signals, and sequentially delaying the delays by a delay amount The received input driving signal; a second latching unit configured to use the delaying rider to delay the recording of the frequency manned ship, sequentially latching the data of each channel, the data is by The _ _ unit _ hides the delay amount for a time, latches; and the -D/A conversion ^ ' is configured to convert the data of each channel output from the second latch unit into an analog signal, and outputs the Converting the analog signal to - according to the present invention - the aspect is provided for reducing the listening liquid == source driving benefit '6 Xuanyuan driver includes: a data output control unit configured to be used as a data number LCD display Each division channel of the display panel is input (4), and the output-off control is successively verified by the second unit, and the second delay unit and the second delay unit are configured to delay the slave data output control in a predetermined time. The switch outputs the switch to control the ship and outputs the delayed switch control signal I, having a plurality of multiplexed (four) first-output buffer units disposed to be used by the first delay, the soap is sequentially delayed and output The _ control button, the 槪-amplifier output analogy f f out the selected analog signal to the corresponding channel; and _ the output _shirt with a plurality of multiplexers is configured to use the second delay The analog signal is outputted from an amplifier in a privately delayed manner, and the selected one is outputted. [201211999 4 [Embodiment] Reference will now be made to detail the specific embodiments of the present invention. Wherever possible, the same or similar elements are referred to in the drawings. Figure 2 is a block diagram of a source drive state for reducing a bribe-only display in accordance with an embodiment of the present invention. As shown in the figure, the source driver includes a displacement temporary element 2, a second latch unit, an input driver signal output, a second converter 240, and an output buffer 250. The shift register unit 21 依 sequentially converts the sampling enable signal ss using the clock signal CLK. The first-latch unit 22A sequentially latches the data data of each channel supplied from the timing controller (not shown) using the sampling enable signal output from the shift register unit 21A. ▲ When latching the data of each channel latched by the latch unit 22B, the third latch unit 220B. The data is not latched at the same time, but the data DATA is latched by a predetermined time difference using the input drive DRV output from the input drive signal output unit. The 3rd_display provides a wave paste of the input drive signal drv latching the single 12208 from the input drive signal output unit 23A. In other words, when the source output enable signal S0E is activated to the state of "high" as shown in (a) of FIG. 3, the input drive signal output unit 23 is replaced by the first (e) - (four) The difference 'sequentially provides the input drive signal drv. The 2:70 22GB latches the data corresponding to the supplied input drive signal drv, and outputs the latched data to the D/A converter 240. The discretion converter 240 converts the digital data latched by the second latch unit 22A into an analog 1 touch-to-capture syndrome. The PL<D has a positive or negative value associated with the common pie VeGm. The object ί ί buffer $ 25G amplifies the analog data signal converted by the D/A converter 24G, and outputs the S analog data signal to the data lines D1 to Dn of the liquid crystal display panel. The "text towel" will be described in detail as an embodiment in which the towel is dispersed and the data signal is output. Referring to Fig. 4, a first embodiment in which a plurality of series-connected retarders are used to disperse and output the assets k 将 will be described. The shift registers SR-L11 to SR-Llm and ~筮- to SR~Rlm of the shift register unit 210 on SR 5 sequentially shift the sampling enable signal SS using the clock signal 0^'. The latches LA_L11 to LAJLlm and LA_R11 to 201211999 of the latch unit 220A ‘ LA_Rlm sequentially use the sample enable signal SS output from the shift register unit 210 to sequentially latch the data DATA1 and DATA2. The input drive signals DRV output from the input drive signal output unit 230 are sequentially delayed by the delays DJL11 to D_Llm and D_R11 to D_Rlm. After the data of the channel is latched by the latches LA_L11 to LA_Llm and LA_R11 to LA_Rlm of the first latch unit 220A, the respective latches LA_L21 to LA_L2m or LA_R21 to LA_R2m of the second latch unit 220B are latched. Corresponding channel data. In this case, each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m uses a corresponding input drive signal DRV that is delayed and outputted by the respective delays D_L11 to D_Llm and D_R11 to D_Rlm, The predetermined time difference sequentially latches the data of the corresponding channel. For example, the first latch LA_L21 disposed on the left side of the input driving signal output unit 230 is latched by the first latch unit using the input driving signal DRV output from the input driving signal output unit 230 and delayed by the delay DJL11 once. The latch of the 220A latch LAJL11. The mth latch LA_L2m' is latched by the first latch unit 220A using the input drive signal DRV outputted from the input drive signal output unit 230 and sequentially transmitted through the m delays D_L11 to D_Llm by m times. The data latched by the latch LA_Llm. Therefore, the data outputted from the respective latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B to the respective channels of the d/Α converter 240 can be dispersed and outputted with the time difference corresponding to the accumulated delay amount. The delays D L11 to D Llm and D R11 to D Rlm can be implemented in a variety of ways. The embodiment of 'delay ft' in Fig. 7 is implemented using Rc elements ri and (10), R2 and M2' composed of resistors and capacitors, and inverters n and 12. Here, each of the metal oxide semiconductors (10) tal (^(^^^(^) and the core are connected to the input terminal by the closed end, the immersion is connected to the source, and then the immersion is The contact point between the sources is connected to the ground and used as a capacitor. Therefore, the RC elements R1 and ·, R2 and M2, and the inverters II and 12 are increased or decreased to the required number to obtain the required delay. Meanwhile, a second embodiment in which the data of each channel is separated and then latched in a manner of being separated and then latched is described with reference to FIG. 5. As described above, the displacement of the displacement register unit 21〇 is temporarily suspended. The registers sun to SR_Llm and SR_R11 to SR Rlm cause the (four) clock signal CLK' to sequentially shift the sampling enable signal %. 201211999 As described above, the latches LA_L11 to LA_Llm and LA_R11 to LA_Rlm of the first latch unit 220A are used. The sample enable signal SS outputted from the shift register unit 21, sequentially latches the data DATA1 and DATA2. The input drive signal output unit 230 outputs the input drive signal DRV, thereby causing the second latch unit 220B to be at every predetermined position. Meta latch by first The data latched by the memory unit 220A and the input drive signal DRV output from the input drive signal output unit 230 are respectively delayed by the delays D_L1 j and D_R11, and then sequentially supplied to the second latch unit. Each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m of 22〇b. Therefore, the data of each channel is sequentially outputted in the order of each bit or each predetermined number of bits. The data is dispersed and output. For example, the input drive signal DRV output from the input drive signal output unit 230 is delayed by the respective delays D L11 and D_R11, and then supplied to each of the second latch units 22〇b. Latch LA_L21 to LA_L2m and first bits of LA_R21 to LA_R2m, thereby outputting the first bit of the data of each channel. Then, the input driving signal DRV is transmitted through respective delays D_L11 and D- R11 is delayed, and then supplied to the respective latches LA L21 to LA_L2m and the second bits of LA_R21 to LA-R2m, thereby outputting the second bit of the data of each channel. The last bit of the data of each channel yuan The first bit of the data of each channel is outputted by supplying the input drive signal DRV to the last bit of each of the latches LA_L21 to LA_L2m and LA_R21 to LA_R2m. The data is described in the embodiment from the respective latches LA__L21 to LA_L2m and each bit output of LA_R21 to LA_R2m', but the present invention is not limited thereto. In other words, the data can be dispersed and output every predetermined number of bits according to time requirements. . Therefore, the data outputted from the respective latches LAJL21 to LA_L2m and LA R21 to LA_R2m of the second latch unit 220B to the respective channels of the d/Α converter 240 can be dispersed and output. Meanwhile, the second embodiment will be described with reference to FIG. 6, in which data is dispersed and output in such a manner that the input drive signal DRV' is simultaneously output but is separately supplied to the latch of the channel through delays having different delay amounts. . As described above, the shift registers SR_L11 to Llm and SR_R11 to SR_Rlm of the shift register unit 210 sequentially use the clock signal CLK to sequentially shift the element sampling enable signal ss❶ 201211999, as described above, the first latch unit 220A The latches LA_L11 to LA_Llm and LA_R11 to LA_Rlm sequentially latch the data DATA1 and DATA2 using the sampling enable signal ss output from the shift register unit 210. The input drive signal DRV output from the input drive signal output unit 230 is delayed by the respective delays D_L11 to D Llm and D_R11 to D_Rlm having different delay amounts, and then sequentially supplied to the first latch unit 220B. The respective latches la__L21 to LA L2m and LA_R21 to LA_R2m. Therefore, the latches LA L21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 220B are locked with a time difference corresponding to the respective delay amounts of the delays DJL11 to D_Llm and D_R11 to D_Rim. Save the data of each channel. The retarder D L11 or D_R11 is taken as the minimum delay amount and the delay D_Llm4D Rlm is described as an incremental form of the maximum delay amount as an embodiment. In this case, 'LA L21 or LA_R21 in the latches LA_L21 to LA_L2m or LA_R21 to LA_R2m first latch the data of the corresponding channel, then the next latch or LA_R22 to correspond to the delays DJL12 and D_R12 The delay difference between the two is used as a time difference to latch the data of the corresponding channel. Then, the next latch LA_L23 or LA-R23, as the delay difference corresponding to the delay between H D_L13 and D-R13, is used as the time difference, and the data of the corresponding channel is latched. The LA-L2m force LA-R2m finally latches the data of the last channel. Therefore, the data of each channel can be dispersed and output from the respective latches la_l21 to LA_L2m and LA_R21 to LA_R2m of the second latch unit 22B with a time difference corresponding to the delay amount difference between the delays D_lii and D_R11. To the D/A converter 24〇. Meanwhile, the fourth embodiment will be described with reference to Figs. 8 to 1G, in which the data is sequentially dispersed and output in accordance with the time difference of the data signal n from the output buffer. Figure 8 is a block diagram showing a fourth embodiment of the present invention. As shown in this figure, the source driver includes an instruction output control unit 810, a first delay unit, a second delay unit_, a first output buffer unit 840, and a second output buffer unit 85A. The data output control unit 810 rotates the switch control signals for controlling the multiplexers provided in the first output buffer unit 840 and the second output buffer unit 85, respectively. The first-delay unit 820 sequentially delays the respective switch control signals output from the material output control unit 810 by the -unit delay time ('f in the first diagram), and is processed by the first delay unit 82〇201211999 Similarly, the respective delays of the respective switch control signals outputted to the first-out-out buffer unit 84G are similarly delayed, and the second delay unit 830 sequentially delays the respective switch control signals from the bamboo system in a unit delay time, and It is extended by the second delay unit 83. The m switch control signal is output to the corresponding multiplexer of the second output buffer unit (10), and the first two implementations are as described above, and the suspicion of the output of the touch (four) is on the outside of the two corresponding to the command channel ( Left and right) are sequentially output in the channel direction. The purpose of the element is as described above, the first delay unit 820 delays the supply of the data from the data output control unit, and sequentially outputs the delayed detection signal to a (for example, 'left' first output buffer). Multiple multiplexer MUXs of unit_. Yu Yi 2nd eve. The delay unit 820 sequentially outputs the respective switch control signals from the multiplexer located between the multiplexers to the leftmost multiplexer MUX. The 'second delay unit 830' delays the loss from the data output control unit 810 (made as the if ί, and sequentially rotates the delayed switch control signal to provide for the sacrifice to be located at her (four) position to the most On the right side, the various switch control signals of the MUX are provided. Each of the multi-guards provided to the 84G of the first-level scale punching unit is used, using the above === face touch, face-to-face 腑 analog data, and outputting the same The selected analog data signal is connected to the corresponding channel OUTPUT. The selection, the switch control signal, etc., the data signal of each channel is delayed and output. The undelayed switch control signal shown in (8) of the figure As compared with (4) of FIG. 10, the undelayed switch control signal is further in time =, gate = to the multiplexer MUX located at the start of the first output buffer unit 840. Therefore, the middle is located The multiplexer does not delay the adjustment but outputs the analog signal to the first channel. Then, the multiplexer MUX outputs the delay analog (4) signal to the second channel by using the time gate '/ analog data signal. Each The Is MUX sequentially delays the analog data signal of the class to the corresponding channel by the time 't, so as to output the further delayed analog data signal with the tracker MUX'. 201211999 (a) of Fig. 10 is a waveform diagram of the source output enable signal s〇E. The data of each channel of the first graph (showing that the time is delayed by two) and output through the multiplexer as described above. Waveform diagram of the signal. For the '10th county, the Wei complements the transmission level signal S (DE^ the time 't, the waveform diagram of the delay and output. For this purpose, the delay-unit 820 has a plurality of delays. The delay is easily implemented using a delay or a conventional delay as shown in Fig. 7. Like the first delay unit 820 and the first output buffer unit 84, the second delay unit 830 and the second output buffer The unit 85 〇 performs the operation of the right channel opposite to the intermediate channel, and thus the data signals of the channels are sequentially delayed by the material Fb1 't and output as described above. Meanwhile, a ninth diagram explains the present invention. - Embodiments. The embodiment of Figure 9 and the Figure 8 In the same manner, the data nickname is sequentially delayed from the outermost channel to the towel channel by time 't'. In other words, in the embodiment of Fig. 8, the first delay unit 82 and the second delay unit 83 〇 is configured in the central portion of the channels, and the data signals are sequentially outputted from the intermediate channel to the leftmost or rightmost channel by time 't. On the other hand, in the ninth In the embodiment of the figure, the first delay plane A 920 and the second delay unit 93 〇 are respectively disposed on the left side and the right side of the channels, and the "the data number of the sea is by the time 't, from the leftmost or rightmost channel. The intermediate channel is sequentially delayed and then output. From the above, it can be seen that the present invention provides a source drive for reducing the biliary liquid crystal display, and when the H-latch latches each channel and outputs a mis-locked The data of each channel uses the input driver button, which is sequentially dispersed with a predetermined time difference or at every __ bit to output EMI to reduce EMI to a greater extent. The invention further provides a source driver for reducing the liquid crystal display of the brain, wherein the data of each channel is transferred from the output of the transmission level, and is dispersed and outputted in the form of a predetermined time difference and then output, and Therefore, the god of Gao Lai was dispersed and bribed from Qi. The above description is only for the purpose of explaining the preferred embodiments of the present invention, and is not intended to be a limitation of the present invention. Changes are still to be included in the scope of the invention as intended. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings are intended to provide a further understanding of the embodiments of the invention explanation of. In the drawings: FIG. 1 is a block diagram of a conventional liquid crystal display; FIG. 2 is a block diagram of a source driver for reducing a liquid crystal display according to an embodiment of the present invention; (a) of FIG. Is a waveform diagram of the source output enable signal; (b) to (e) of FIG. 3 are waveform diagrams for providing a drive signal to the second latch unit while sequentially delaying; FIGS. 4 to 6 are A block diagram of a partial detail of the source driver for reducing emi in accordance with an embodiment of the present invention; FIG. 7 is a circuit diagram showing an embodiment of the rainbow retarder provided in the present invention; FIG. 8 is a circuit diagram showing an embodiment of the rainbow retarder according to the present invention; Another embodiment 'block diagram of a liquid driver for reducing the problem; ninth> is a block diagram of a source driver for reducing a circular crystal display according to still another embodiment of the present invention; A waveform diagram of the start signal for the source output; and (b) to (4) of the graph 10 are waveform diagrams of the capital contribution while sequentially delaying at time "t". [Main component symbol description] 110 Displacement register unit 120 Latch unit 130 Digital analog converter 140 Output buffer 210 Displacement register unit 220A First latch unit 220B Second latch unit 230 Input drive signal output unit 240 D/A converter 12 201211999 250 output buffer 810 data output control unit 820 first delay unit 830 second delay unit 840 first output buffer unit 850 second output buffer unit 910 data output control unit 920 first delay unit 930 second delay unit 940 first output buffer unit 950 second output buffer unit AMP amplifier CLK clock signal Dl-Dn data line D_Lll~D_Llm, D_Rll~D_Rlm delay device DRV input drive signal II, 12 inverter LA_L11 ~ LA_Llm, LA_Rll ~LA_Rlm Latch M1, M2 MOS transistor MUX multiplexer
Rl、R2電阻 SS 取樣啟動信號 SOE 源極輸出啟動信號 SR_L11 〜SR_Llm、SR_R11 〜SR_Rlm 位移暫存器 13Rl, R2 resistor SS sampling start signal SOE source output enable signal SR_L11 ~ SR_Llm, SR_R11 ~ SR_Rlm Displacement register 13