201206174 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種驅動裝置，特別是指一種能自動 偵測格式並依據格式自動切換濾波器的視訊濾波器驅動裝 置。 【先前技術】 隨著時代追求高畫質的腳步，高品質的原影原音重現 是人類對於視聽感官的終極需求，故視訊處理技術已由以 往的類比（analog)技術發展到目前的數位（digital)技術。並且 ，在視訊信號格式方面，也由標準畫質（Standard-Definition， 簡稱SD)發展到高畫質（High Definition，簡稱HD)，其中標 準畫質（SD)的視訊信號格式包含有複合（Composite)信號、S-Video(Y/C)信號等，而高畫質（HD)的視訊信號格式包含有 DVI以及HDMI等。不過，目前大眾所使用的電視機（TV) 與播放器（Player)不一定能支援高晝質的視訊信號格式，所 以現有的電視機或是播放器（player)在設計上就必需考量到 如何處理各式的視訊信號格式及向下兼容的彈性。 參閱圖1，針對電視與播放器的主要晶片（Main chip) 1 而言，爲了滿足各式的視訊信號格式，就必需同時支援各 種晝質解析度的格式才能確保實際應用於產品的彈性及相 容性。目前普遍的視訊信號格式包括SD視訊信號的 CVBS+S-Video(Y/C)以及HD視訊信號格式的R/G/B或 Y/Pb/Pr，而在主要晶片（Main chip)l内部的視訊解碼器 (video decoder)ll是以數位資料的形態經過數位類比轉換器 201206174 (DAC) 12合成類比的視訊信號輸出，所以在視訊信號輸出 方面，為了可以輸出目前普遍使用的視訊信號格式，主要 晶片（Main chip)l的視訊解碼器11需同時搭配六組數位類 比轉換器（DAC)12，並且外部的視訊濾波器驅動裝置（Video Filter Driver)2則必需具有六個分別連接各個數位類比轉換 器12的視訊信號濾波單元，而且，由於SD視訊信號格式 與HD視訊信號所需的視訊信號濾波單元不同’所以視訊信 號濾波單元分為接受CVBS、Y、C輸入的SD視訊信號濾 波單元21，以及接受R/G/B或Y/Pb/Pr輸入的HD視訊信 號濾波單元22。 進一步說明，參閱圖2，SD視訊信號濾波單元21具有 一直流箝位電路（DC Clamping)211、一類比頻寬（analog bandwidth)為9MHz的低通濾波器（lpf)212及一 6dB的增益 模組213。而參閱圖3，HD視訊信號濾波單元22具有一直 流箝位電路（DC Clamping)221、一類比頻寬（anai〇g bandwidth)為36MHz的低通濾波器（lpf)222及一 6dB的增 益模組223。相較之下，SD視訊信號濾波單元21與HD視 汛仏號濾波單凡22的差異，僅在於兩者的低通濾波器的頻 率截止點不同（即頻寬不同），但也因此差異造成電視與播放 器的成本增加與空間上的浪費。舉例來說，若輸出的視訊 信號為CVBS+S-Video(Y/C)，實際上同一時間只利用到三 個數位類比轉換器12與三個SD視訊信號渡波單元21。反 之右輸出的視訊信號為R/G/B，實際上同一時間也是只利 用到三個數位類比轉換器12與三個HD視訊信號遽波單元 201206174 一 ^代表著不管輸出的視訊信號格式為SD或HD都會有 比轉換器12與三個視訊信號遽波單元未被使用 到。 )丄有4α於此，若能將SD視訊信號遽波單元h與肋視 ，號應波單兀22加以整合，將可有效地降地電視與播放 器之主要晶片與視訊濾波器驅動裝置的成本與空間，故為 本案欲解決的方向。 【發明内容】 因此’本發明之目的，即在提供一種自動選擇濾波器 的視訊濾波器驅動裝置。 於是，本發明視訊濾波器驅動裝置，可接收一第一視 訊2號，並包含一信號格式判斷單元及一第一視訊信號濾 波早π。信號格式判斷單元接收該第一視訊信號，並包括 一同步信號分離模組及一頻率偵測模組。同步信號分離模 組由該第一視訊信號中分離出一同步信號成分；頻率偵測 模組耦接該同步信號分離模組並接收該同步信號成分，該 頻率偵測模組用以偵測出該同步信號成分的頻率為一第一 頻率或是一第二頻率，並發出一控制信號。第一視訊信號 濾波單元包括一濾波器組及—切換開關。濾波器組具有一 第一濾波器及一第二濾波器；切換開關耦接該頻率偵測模 組與該濾波器組，並且接收該第一視訊信號與該控制信號 ’該切換開關依據該控制信號控制該第一視訊信號輸入該 第一滤波器或該第二濾' 波器其中之一，使對該第一視訊信 號進行滤波。 201206174 較佳地’該同步信號成分為水平同步信號。 較佳地，該信號格式判斷單元還包括一用以分離出該 視讯信號中之亮度信號且耦接該同步信號分離模組的亮度 色度分離模組，並且該第一視訊信號通過該同步信號分離 模組前’會先通過該亮度色度分離模組。 較佳地’當該頻率偵測模組偵測出該同步信號成分的 頻率為該第一頻率時’該控制信號為低電位的信號，並且 該切換開關控制該第一視訊信號輸入該第一濾波器進行濾 波；當該頻率偵測模組偵測出該同步信號成分的頻率為該 第二頻率時’該控制信號為高電位的信號，並且該切換開 關控制該第一視訊信號輸入該第二濾波器進行濾波。 較佳地，該視訊濾波器驅動裝置還包含一用以處理一 第二視訊信號的第二視訊信號濾波單元，該第二視訊信號 攄波單元包括該濾波器組及該切換開關，該切換開關耦接 該頻率偵測模組與該濾波器組，並且接收該第二視訊信號 與該控制信號’該切換開關依據該控制信號控制該第二視 訊信號輸入該第一濾波器或該第二濾波器其中之一，使對 該第二視訊信號進行濾波。另外，該視訊濾波器驅動裝置 還包含一用以處理一第三視訊信號的第三視訊信號濾波單 元’該第三視訊信號濾波單元包括該濾波器組及該切換開 關’該切換開關耦接該頻率偵測模組與該濾波器組，並且 接收該第三視訊信號與該控制信號’該切換開關依據該控 制信號控制該第三視訊信號輸入該第一濾波器與該第二濾 波器其中之一，使對該第三視訊信號進行濾波。 201206174 再者，該第一視訊信號濾波單元、該第二視訊信號據 波單元與該第三視訊信號信號濾波單元分別還包括—耦接 該濾波器組且用以提高濾波後的視訊信號之強度的增益模 組。並且，該第一視訊信號濾波單元、該第二視訊信號渡 波單元與該第三視訊信號信號濾波單元分別還包括一直流 箝位電路，以將信號箝位在一直流位準作為後端線路的信 號截取參考電壓。 較佳地，該第一頻率為標準畫質視訊信號中的水平同 步信號的頻率，該第二頻率為高畫質視訊信號中的水平同 步信號的頻率。 另外，本發明之另一目的，在於提供一種具有上述視 訊濾波器驅動裝置且節省成本與空間的視訊處理器。 本發明之功效在於’藉由信號格式判斷單元判斷出第 一視讯信號的視訊信號格式，並且，第一視訊信號濾波單 兀、第二視訊信號濾波單與第三視訊信號濾波單元依據頻 率偵測模組所發出的控制信號切換使用不同的濾波器，藉 此將不同頻寬的第一濾波器與第二濾波器整合於同一個視 訊信號濾波單元内，再者，主要晶片相對應地僅需設置三 個數位類比轉換器，相較於習知確實節省了視訊處理器的 成本與空間。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 201206174 參閱圖4，為本發明視訊處理器的較佳實施例。視訊處 理器（Video Processor)適合用於電視機（τν)或播放器（piayer) ，並具有一主要晶片（Main chip)4及一視訊濾波器驅動裝置 (Video Filter Driver)5，視訊濾波器驅動裝置5用以與主要 晶片4搭配作用。主要晶片4具有一視訊解碼器（vide〇 decoderHl以及連接視訊解碼器41的一第一數位類比轉換 器（DAC)421、一第二數位類比轉換器（DAC)422及一第三數 位類比轉換器（DAC)423 ^視訊解碼器41是以數位資料的形 態處理視訊信號，而所述的數位類比轉換器42丨、422、 用以將視訊解碼器41輸出的數位資料轉換成類比視訊信號 (analog video Signal)。並且，由圖4可得知所述的數位類比 轉換器421、422、423輸出的視訊信號格式可為一組標準 畫質（簡稱SD)視訊信號的CVBS、Y及C，或是一組高書質 (簡稱HD)視訊信號的Y、pb、Pr，或是一組SD/HD視訊作 號的G、B、R。爲了以下說明，定義第一數位類比轉換器 421所輸出的信號為第一視訊信號S1，如cVB S或γ戋g ;定義第二數位類比轉換器422所輸出的信號為第二視訊 信號S2,如Y或Pb或B;定義第三數位類比轉換器々η所 輸出的信號為第三視訊信號S3，如C或ΡΓ或R。 繼續參閱圖4，視訊濾波器驅動裝置5包含—信號格式 判斷單元、一連接第一數位類比轉換器421的第一視1 號渡波單元51、一連接第二數位類比轉換器422的第_ 視訊信號濾波單元52，以及一連接第三數位類比轉換器 423的第二视訊信號濾波單元53 ’其中，第一視訊信號、慮 201206174 波單元51接收第一視訊信E S1 ’第二視訊信號濾波單元 52接收第二視訊信冑S2,第三視訊信號渡波單元53接收 第三視訊信號S3，並且上述的視訊信號濾波單元51〜53的 構造相同，僅在於接收的視訊信號不同。再者，每一視訊 #號濾波單το 51〜53外部連接一電阻9以供與後端線路做 阻抗匹配。 在此先行說明本實施例的特點在於，利用SD視訊信號 與HD視訊信號中的同步信號之水平同步信號（H〇riz〇ntai sync signal)的頻率不同來選擇視訊信號的濾波器頻寬。進 一步說明，SD視訊信號中的同步信號之水平同步信號的頻 率為15KHz ’而HD視訊信號中的同步信號之水平同步信號 的頻率為45KHz ’因此，本實施例利用SD視訊信號與 視訊信號兩者的水平同步信號的頻率不同來判斷視訊信號 格式為SD或HD，並藉此選擇適合的濾波器，詳細說明如 下。 參閱圖5，視訊濾波器驅動裝置5的信號格式判斷單元 50包括依序設置的一接收第一視訊信號S1的亮度色度分離 (Y/C separation)模組501、一耦接亮度色度分離模組5〇1的 同步信號分離（Sync signal separation)模組502、一搞接同步 #號分綠模組502的頻率偵測（Frequency detection)模組503 及一麵接頻率彳貞測模組503的位準移位（Level shift)模組504 ，並且上述的各模組係以電路（circuit)來實現。另外，需說 明的疋’由於第一視訊號S1 (CVBS或Y或G)中包含有同 步信號’故藉一緩衝器（圖未示）將第一數位類比轉換器421 201206174 ^輸出的第；f見δί1信號S1分為兩路分別輸入信號格式判斷 單兀50與第一视訊信號濾波單元51。 儿度色度刀離模組5〇1接收第一視訊信號且用以分 離出第視騎號S1(如CVBS.)中之亮度信號⑺，但也會 因^信號的不同而不作用’舉例來說，若輸入的第一視 ^ °號S1 * Y或G ’則亮度色度分離模組501不作用。接 著同乂 L號分離模組5〇2用以將第一視訊信號si中的同201206174 VI. Description of the Invention: [Technical Field] The present invention relates to a driving device, and more particularly to a video filter driving device capable of automatically detecting a format and automatically switching a filter according to a format. [Prior Art] With the pursuit of high image quality in the era, high-quality original sound reproduction is the ultimate demand of human visual sense, so the video processing technology has been developed from the previous analog technology to the current digital ( Digital) technology. Moreover, in terms of video signal format, it is also developed from Standard-Definition (SD) to High Definition (HD), in which the standard image quality (SD) video signal format contains composite (Composite). ) Signals, S-Video (Y/C) signals, etc., and high-definition (HD) video signal formats include DVI and HDMI. However, the TVs and players currently used by the public do not necessarily support high-quality video signal formats, so existing TVs or players must be designed. Handle various video signal formats and backward compatibility. Referring to FIG. 1, for the main chip 1 of the television and the player, in order to satisfy various video signal formats, it is necessary to simultaneously support various formats of enamel resolution to ensure the elasticity and phase of the actual application. Capacitance. The current common video signal formats include CVBS+S-Video (Y/C) for SD video signals and R/G/B or Y/Pb/Pr for HD video signal formats, and are internal to the main chip. The video decoder ll is a video signal output synthesized by the digital analog converter 201206174 (DAC) 12 in the form of digital data. Therefore, in terms of video signal output, in order to output the currently widely used video signal format, mainly The video decoder 11 of the main chip 1 needs to be equipped with six sets of digital analog converters (DACs) 12 at the same time, and the external video filter driver (Video Filter Driver) 2 must have six separate analog analog conversions. The video signal filtering unit of the device 12, and because the SD video signal format is different from the video signal filtering unit required for the HD video signal, the video signal filtering unit is divided into the SD video signal filtering unit 21 that accepts the CVBS, Y, and C inputs. And an HD video signal filtering unit 22 that accepts R/G/B or Y/Pb/Pr input. Further, referring to FIG. 2, the SD video signal filtering unit 21 has a DC Clamping 211, a low-pass filter (lpf) 212 with an analog bandwidth of 9 MHz, and a 6 dB gain mode. Group 213. Referring to FIG. 3, the HD video signal filtering unit 22 has a DC Clamping 221, a low-pass filter (lpf) 222 having an analog bandwidth of 36 MHz, and a 6 dB gain mode. Group 223. In contrast, the difference between the SD video signal filtering unit 21 and the HD video signal filtering unit 22 is only that the frequency cutoff points of the low pass filters of the two are different (that is, the bandwidth is different), but the difference is also caused. The cost of TV and player increases and the space is wasted. For example, if the output video signal is CVBS+S-Video(Y/C), only three digital analog converters 12 and three SD video signal wave unit 21 are actually used at the same time. On the contrary, the video signal outputted by the right is R/G/B. In fact, only three digital analog converters 12 and three HD video signal chopping units 201206174 are used at the same time. The video signal format of the output is SD. Or HD will have no more than the converter 12 and the three video signal chopping units are not used. There is a 4α here, if the SD video signal chopping unit h and the rib view, the number should be waved and integrated 22, it will effectively lower the main chip and video filter driver of the TV and player. Cost and space, so the direction to be resolved in this case. SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a video filter driving apparatus that automatically selects a filter. Therefore, the video filter driving device of the present invention can receive a first video number 2 and includes a signal format determining unit and a first video signal filter π. The signal format determining unit receives the first video signal, and includes a synchronization signal separation module and a frequency detection module. The synchronization signal separation module separates a synchronization signal component from the first video signal; the frequency detection module is coupled to the synchronization signal separation module and receives the synchronization signal component, and the frequency detection module is configured to detect The frequency of the synchronization signal component is a first frequency or a second frequency, and a control signal is issued. The first video signal filtering unit includes a filter bank and a switch. The filter bank has a first filter and a second filter; the switch is coupled to the frequency detection module and the filter bank, and receives the first video signal and the control signal. The switch is controlled according to the control The signal controls the first video signal to be input to one of the first filter or the second filter to filter the first video signal. 201206174 Preferably the sync signal component is a horizontal sync signal. Preferably, the signal format determining unit further includes a luminance chrominance separation module configured to separate the luminance signal in the video signal and coupled to the synchronization signal separation module, and the first video signal passes the synchronization. Before the signal separation module, the luminance chrominance separation module will pass first. Preferably, when the frequency detecting module detects that the frequency of the synchronization signal component is the first frequency, the control signal is a low potential signal, and the switching switch controls the first video signal input to the first The filter performs filtering; when the frequency detecting module detects that the frequency of the synchronization signal component is the second frequency, the control signal is a high potential signal, and the switching switch controls the first video signal input to the first The second filter performs filtering. Preferably, the video filter driving device further includes a second video signal filtering unit for processing a second video signal, the second video signal chopping unit includes the filter group and the switch, the switch Coupling the frequency detecting module and the filter bank, and receiving the second video signal and the control signal. The switching switch controls the second video signal to input the first filter or the second filter according to the control signal. One of the devices causes the second video signal to be filtered. In addition, the video filter driving device further includes a third video signal filtering unit for processing a third video signal. The third video signal filtering unit includes the filter group and the switch. The switch is coupled to the switch. a frequency detecting module and the filter group, and receiving the third video signal and the control signal. The switching switch controls the third video signal to input the first filter and the second filter according to the control signal. First, filtering the third video signal. 201206174 The first video signal filtering unit, the second video signal data unit, and the third video signal filtering unit respectively comprise: coupling the filter group to improve the intensity of the filtered video signal Gain module. And the first video signal filtering unit, the second video signal filtering unit and the third video signal filtering unit respectively comprise a DC clamp circuit for clamping the signal to a DC level as a back-end line. The signal intercepts the reference voltage. Preferably, the first frequency is the frequency of the horizontal synchronization signal in the standard picture quality video signal, and the second frequency is the frequency of the horizontal synchronization signal in the high picture quality video signal. Further, another object of the present invention is to provide a video processor having the above-described video filter driving device and which is cost-effective and space-saving. The effect of the present invention is that the video signal format of the first video signal is determined by the signal format determining unit, and the first video signal filtering unit, the second video signal filtering unit and the third video signal filtering unit are based on the frequency detection. The control signals sent by the test module are switched using different filters, so that the first filter and the second filter of different bandwidths are integrated into the same video signal filtering unit, and the main wafers are correspondingly only Three digital analog converters need to be set up, which saves the cost and space of the video processor compared to the conventional one. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. 201206174 Referring to Figure 4, a preferred embodiment of the video processor of the present invention is shown. The video processor is suitable for a television (τν) or a player (piayer), and has a main chip 4 and a video filter driver 5, and a video filter driver. The device 5 serves to cooperate with the main wafer 4. The main chip 4 has a video decoder (vide〇decoderH1 and a first digital analog converter (DAC) 421 connected to the video decoder 41, a second digital analog converter (DAC) 422 and a third digital analog converter. (DAC) 423 ^ The video decoder 41 processes the video signal in the form of digital data, and the digital analog converter 42 丨, 422 converts the digital data output by the video decoder 41 into an analog video signal (analog Video Signal). It can be seen from FIG. 4 that the video signal format output by the digital analog converters 421, 422, and 423 can be CVBS, Y, and C of a group of standard picture quality (SD) video signals, or Is a set of high-quality (HD) video signals Y, pb, Pr, or a set of SD / HD video number G, B, R. For the following description, define the output of the first digital analog converter 421 The signal is the first video signal S1, such as cVB S or γ戋g; the signal output by the second digital analog converter 422 is defined as the second video signal S2, such as Y or Pb or B; defining a third digital analog converter The signal output by 々η is the third video signal S3, For example, C or ΡΓ or R. Referring to FIG. 4, the video filter driving device 5 includes a signal format determining unit, a first view number 1 wave connecting unit 51 connected to the first digital analog converter 421, and a second digital analog class. a _ video signal filtering unit 52 of the converter 422, and a second video signal filtering unit 53 ′ connected to the third digital analog converter 423. The first video signal, the 201206174 wave unit 51 receives the first video message E. S1 'the second video signal filtering unit 52 receives the second video signal S2, the third video signal filtering unit 53 receives the third video signal S3, and the video signal filtering units 51 to 53 have the same configuration except for the received video. The signals are different. Furthermore, each video ## filter number το 51~53 is externally connected with a resistor 9 for impedance matching with the back end line. Herein, the present embodiment is characterized by using SD video signal and HD video. The frequency of the horizontal synchronization signal (H〇riz〇ntai sync signal) of the synchronization signal in the signal is different to select the filter bandwidth of the video signal. Further, the SD video signal is described. The frequency of the horizontal synchronizing signal of the synchronizing signal is 15 kHz' and the frequency of the horizontal synchronizing signal of the synchronizing signal in the HD video signal is 45 kHz. Therefore, in this embodiment, the frequency of the horizontal synchronizing signal of both the SD video signal and the video signal is utilized. Differently, the video signal format is determined to be SD or HD, and a suitable filter is selected by the following, which is described in detail below. Referring to FIG. 5, the signal format determining unit 50 of the video filter driving device 5 includes a first video receiving device. A chrominance chromaticity separation (Y/C separation) module 501 of the signal S1, a Sync signal separation module 502 coupled to the chrominance chrominance separation module 5〇1, and a synchronization synchronization ##分绿The frequency detection module 503 of the module 502 and the level shift module 504 connected to the frequency measurement module 503 are connected to each other by a circuit. to realise. In addition, it should be noted that the first digital signal S1 (CVBS or Y or G) includes a synchronization signal, so the first digital analog converter 421 201206174 ^ is outputted by a buffer (not shown); f see δί1 signal S1 is divided into two separate input signal format determination unit 50 and first video signal filtering unit 51. The color chromatographic knife receives the first video signal from the module 5〇1 and is used to separate the luminance signal (7) in the first riding number S1 (such as CVBS.), but may also not act due to the difference of the ^ signal. In other words, if the first visual number S1 * Y or G ' is input, the luminance chrominance separation module 501 does not function. The same as the L-separation module 5〇2 for the same in the first video signal si
步信號分離出-同步信號成分（若第一視訊信號si為CMS J輸入同步L號分離模組5〇2的信號為亮度信號），在本 實施例中，該同步信號成分為水平同步信號。此外，亦可· 在时信號分離模組5〇2内增設一電容，以使輸出的水平 同步^號變形，以便頻率傾測模組503更易於辨識出水平 同步信號的頻率。 頻率_模組503接收水平同步信號，並且偵測出該 水平同步信號的頻率為一 SD視訊信號格式的第一頻率 (15KHZ)，或是一 HD視訊信號格式的第二頻率（45KHZ)，並 發出-控制所述視訊信號濾波單元51〜53的控制信號CS。 在本實施例中，頻率摘測模組5〇3在谓測出該水平同步信鲁 冑的頻率為第一頻率時，使所發出的控制訊號為低電位： 頻率偵測模組503在债測出該水平同步信號的頻率為第二 頻率時’使所發出的控制訊號為高電位，藉此’控制信號 cs為高電位時’表示輸入的視訊信號格式為sd;控制信號 CS為低電位時’表示輸入的視訊信號格式為hd。而位準 移位模組504的功用容後再述。 10 201206174 接著先以視訊濾波器驅動裝置5的第一視訊信號濾波 單元51做說明，並繼續參閱圖5，第一視訊信號濾波單元 51包括一耦接第一數位類比轉換器421的直流箝位電路（DC Clamping)601、一耦接直流箝位電路601的切換開關 (Switcli)602、一耦接切換開關602的濾波器組603及一耦 接濾波器組603的增益（Gain up)模組604，並且上述的模組 係以電路（circuit)來實現。直流箝位電路601用以將信號箝 位在一直流位準作為後端線路的信號截取參考電壓。濾波 器組603具有一適於過濾SD視訊信號的第一濾波器61及 一適於過濾HD視訊信號的第二濾波器62，所述的濾波器 用以將通過的視訊信號（第一視訊信號S1)的雜訊去除，並 且’在本實施例中’第一濾波器為頻寬9MHz的低通濾波器 (LPF) ’第二濾波器為頻寬36MHz的低通濾波器（LpF)。切 換開關602接收來自信號格式判斷單元5〇的控制信號cs 以選擇切換至濾波器組603内適用的濾波器。在本實施例 中，切換開關602為一數位開關，於是，當控制信號cs為 低電位（即表示第一視訊信號S1為SD格式）時，切換開關 6〇2切換至適於SD視訊信號的第一濾波器61 ;當控制信號 cs為高電位（即表示第一視訊信號S1為HD格式）時，切換 開關602切換至適於HD視訊信號的第二濾波器62。進一 步說明的疋，該位準位移模組5〇4用以調整控制信號cs的 電位以使控制彳s號CS的高電位與低電位合乎切換開關 6〇2的切換標準。而且’經過滤波的第一視訊信號會通 、'曰益模、，且604以增加其信號強度約6db，以做為阻抗匹配 201206174 使用（如電視機輸入阻抗為75Qhm)，但並不以此為限。 參閲圖6,第二視訊信號滤波單元52與第一視訊信號 遽波單元51的差異在於，第二視訊信號濾波單元52的直 流箝位電路6〇1是接收第二視訊信號S2，其餘構造與功用 相同，故不多加贅述。參閱圖7,第三視訊信號遽波單元 ”與第-視訊信號濾波單元52的差異在於，第三視訊信號 渡波單元53的直流箝位電路6〇1是接收第三視訊信號μ， 其餘構造與功用相同，故不多加贅述。 整體來說’若主要晶片4輸出的第一視訊信號W、第 -視-flU S2、第二視訊信號S3的視訊信號格式為， 則信號格式判斷單元的頻㈣測模組5〇3偵測出第一視 訊信號S1中水平同步信號的頻率為第一頻率（ΐ5κ叫並 且使發出的㈣錢CS為低電位，於是，第—視訊信號滤 波單π 5卜第一視訊信號濾波單元52與第三視訊信號遽波 單元53的切換開關6〇2會依控制信號cs切換使用第一濾 波器61，以供SD視訊信號進行濾波。另一方面，若主要 的片4輸出的第一視汛信號S1、第二視訊信號、第三視 則5號S3的視訊信號格式為HD，則信號格式判斷單元5〇 的頻率偵測模組5 0 3偵測出第一視訊信號S i中水平同步信 號的頻率為第二頻率（45KHz)，並且使發出的控制信號cs 為高電位’於是’第―視訊信號渡波單元Η、第二視訊信 唬;慮波單兀52與第二視訊信號濾波單元53的切換開關6〇2 會依控制信號cs切換使用第二濾波器62，以供sd視訊信 號進行濾波。如此一來，本實施例的主要晶片4僅需要三 12 201206174 組數位類比轉換器，以及視訊濾波器驅動裝置5僅需要三 組視訊信號濾波單元，相較於習知確實節省了視訊處理器 的成本與空間。The step signal separates the sync signal component (if the first video signal si is a signal of the CMS J input sync L-separation module 5〇2 is a luminance signal), in the present embodiment, the sync signal component is a horizontal sync signal. In addition, a capacitor may be added in the signal separation module 5〇2 to deform the horizontal synchronization of the output, so that the frequency panning module 503 can more easily recognize the frequency of the horizontal synchronization signal. The frequency_module 503 receives the horizontal synchronization signal, and detects that the frequency of the horizontal synchronization signal is a first frequency (15KHZ) of an SD video signal format, or a second frequency (45KHZ) of an HD video signal format, and The control signal CS of the video signal filtering units 51 to 53 is issued-controlled. In this embodiment, the frequency sampling module 5〇3 causes the issued control signal to be low when the frequency of the horizontal synchronization signal is measured as the first frequency: the frequency detecting module 503 is in debt When the frequency of the horizontal synchronizing signal is measured as the second frequency, 'the control signal sent is high, and the 'control signal cs is high' indicates that the input video signal format is sd; the control signal CS is low. When 'represents the input video signal format is hd. The function of the level shifting module 504 will be described later. 10 201206174 The first video signal filtering unit 51 of the video filter driving device 5 is first described, and with reference to FIG. 5 , the first video signal filtering unit 51 includes a DC clamp coupled to the first digital analog converter 421 . A circuit (DC Clamping) 601, a switching switch (Switcli) 602 coupled to the DC clamp circuit 601, a filter bank 603 coupled to the switch 602, and a gain (Gain up) module coupled to the filter bank 603 604, and the above modules are implemented in a circuit. The DC clamp circuit 601 is used to clamp the signal to a DC level as a signal for the back-end line to intercept the reference voltage. The filter bank 603 has a first filter 61 adapted to filter the SD video signal and a second filter 62 adapted to filter the HD video signal, the filter for passing the video signal (the first video signal S1) The noise is removed, and 'in the present embodiment, the first filter is a low pass filter (LPF) having a bandwidth of 9 MHz. The second filter is a low pass filter (LpF) having a bandwidth of 36 MHz. The switch 602 receives the control signal cs from the signal format judging unit 5A to selectively switch to the applicable filter in the filter bank 603. In this embodiment, the switch 602 is a digital switch. When the control signal cs is low (that is, the first video signal S1 is in the SD format), the switch 6〇2 is switched to the SD video signal. The first filter 61; when the control signal cs is high (that is, the first video signal S1 is in the HD format), the switch 602 is switched to the second filter 62 suitable for the HD video signal. Further, the level shifting module 5〇4 is used to adjust the potential of the control signal cs so that the high potential and the low potential of the control 彳s number CS meet the switching standard of the switching switch 6〇2. And 'the filtered first video signal will pass, '曰益模, and 604 to increase its signal strength by about 6db, used as impedance matching 201206174 (such as TV input impedance is 75Qhm), but not Limited. Referring to FIG. 6, the second video signal filtering unit 52 is different from the first video signal chopping unit 51 in that the DC clamp circuit 6〇1 of the second video signal filtering unit 52 receives the second video signal S2, and the rest of the configuration is The same as the function, so do not add more details. Referring to FIG. 7, the third video signal chopping unit is different from the first video signal filtering unit 52 in that the DC clamp circuit 6〇1 of the third video signal fluctuating unit 53 receives the third video signal μ, and the rest of the configuration is The function is the same, so it is not mentioned in more detail. Overall, if the video signal format of the first video signal W, the first-view-flU S2, and the second video signal S3 outputted by the main chip 4 is, the frequency of the signal format determining unit (4) The measuring module 5〇3 detects that the frequency of the horizontal synchronizing signal in the first video signal S1 is the first frequency (ΐ5κ is called and the emitted (four) money CS is low, so the first video signal filtering single π 5 bu The video signal filtering unit 52 and the switching switch 6〇2 of the third video signal chopping unit 53 switch to use the first filter 61 for filtering the SD video signal according to the control signal cs. On the other hand, if the main slice 4, the output video signal of the first video signal S1, the second video signal, and the third video S3 is HD, and the frequency detection module 5 0 3 of the signal format determining unit 5 detects the first The level of the video signal S i is the same The frequency of the signal is the second frequency (45KHz), and the issued control signal cs is high potential 'thus' the first video signal wave unit Η, the second video signal 虑; the wave unit 兀 52 and the second video signal filtering unit The switching switch 6〇2 of 53 switches to use the second filter 62 for filtering the sd video signal according to the control signal cs. Thus, the main wafer 4 of the embodiment only needs three 12 201206174 group digital analog converters. And the video filter driving device 5 only needs three sets of video signal filtering units, which saves the cost and space of the video processor compared with the conventional ones.
附帶說明的是，參閱圖8，為顯示於電視或播放器之顯 不螢幕的—使用介面900。使用者可藉由使用介面900選擇 主要晶片4所輸出的視訊信號，以滿足所需的視覺感受。 舉例來說，若使用者欲觀看HD視訊信號格式的影像，則透 過遙控器在使用介面900上進行點選，使主要晶片4的 各數位類比轉換器421、422、423輸出γ、Pb、Pr或G、B 、R至視訊濾波器驅動裝置5的第一視訊信號濾波單元51 、第二視訊信號濾波單元52與第三視訊信號濾波單元53， 再藉由第一視訊信號濾波單元51、第二視訊信號濾波單元 52與第三視訊信號濾波單元53輸出Y、Pb、pr或g、B、 R至顯示螢幕’如此-來，制者便可觀看到所需的畫面品 質。 一 。V、上所述，本實施例的視訊濾波器驅動裝置5藉由信 '格式判斷單元50判斷出第一視訊信號Sl的視訊信 、 並且，第一視訊信號濾波單元51、第二視訊信號濾波 戶7^ 2與第二視訊信號濾波單元53依據頻率偵測模組5们 所發出的控制信號cs切換使用不同的濾波器，藉此將不同 1寬的第一濾波器61與第二濾波器62整合於同一個視訊 魂據波單元内，再者，主要晶# 4相對應地僅需設置三 位類比轉換器421、422、423，相較於習知確實節省了 、K處理器的成本與空間，故確實能達成本發明之目的。 13 201206174 惟以上所述者，僅為本發明之較佳實施例而已，泛指 針對應用不同視訊格式之水平同步㈣制而達到相對應 的濾波器自動調整，當不能以此限定本發明實施之範圍， 即大凡依本發明申請專利範圍及發明說明内容所作之簡單 的等效變化與修飾，皆仍屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一方塊圖，說明習知的主要晶片與視訊濾波器 驅動裝置； 圖2是一方塊圖，說明該視訊濾波器驅動裝置的SD視 訊信號濾波單元； 圖3是一方塊圖，說明該視訊濾波器驅動裝置的HD視 訊信號濾波單元； 圖4是一方塊圖，說明本發明視訊處理器的主要晶片 與視訊濾波器驅動裝置； 圖5是一方塊圖’說明該視訊濾波器驅動裝置的信號 格式判斷單元與第一視訊信號濾波單元； 圖6是一方塊圖，說明該視訊濾波器驅動裝置的第二 視訊信號濾波單元； 圖7 —方塊圖’是說明該視訊濾波器驅動裝置的第三 視訊信號滤波單元；及 圖8是一示意圖，說明電視或播放器的使用介面。 201206174 【主要元件符號說明】 4 ....... 主要日日片 53…… …·第三視訊信號濾波單元 41·····. •…視訊解碼器 601… •…直流箝位電路 421 ··· •…第一數位類比轉換器 602… …·切換開關 422 ··· …·第二數位類比轉換器 603… …·濾波器組 423 ···. .···第三數位類比轉換器 604… …·增益模組 5 ....... •…視訊濾波器驅動裝置 61…… •…第 渡波器 50…… …·信號格式判斷單元 62…… …·第二濾波器 501… •…亮度色度分離模組 900… —使用介面 502… •…同步信號分離模組 9 ....... •…電阻 503… •…頻率偵測模組 S1…… •…第一視訊信號 504… •…位準移位模組 S2…… •…第二視訊信號 51…… •…第一視訊信號濾波單元 S3·.··· •…第三視訊信號 52…… •…第二視訊信號濾波單元 CS ···· …·控制信號Incidentally, referring to Fig. 8, a display interface 900 is shown for display on a television or a player. The user can select the video signal output by the main chip 4 by using the interface 900 to meet the desired visual experience. For example, if the user wants to view the image in the HD video signal format, the user selects the interface 900 through the remote controller to output the gamma, Pb, and Pr signals of the digital analog converters 421, 422, and 423 of the main chip 4. Or G, B, R to the first video signal filtering unit 51, the second video signal filtering unit 52, and the third video signal filtering unit 53 of the video filter driving device 5, and then by the first video signal filtering unit 51, The two video signal filtering unit 52 and the third video signal filtering unit 53 output Y, Pb, pr or g, B, R to the display screen 'so that the system can view the desired picture quality. One . V, as described above, the video filter driving apparatus 5 of the present embodiment determines the video information of the first video signal S1 by the letter format determining unit 50, and the first video signal filtering unit 51 and the second video signal filtering. The user 7^2 and the second video signal filtering unit 53 switch between different filters according to the control signal cs sent by the frequency detecting module 5, thereby using the first filter 61 and the second filter of different widths 1 62 is integrated in the same video soul unit, and in addition, the main crystal # 4 correspondingly only needs to set up three analog converters 421, 422, 423, compared with the conventional savings, the cost of the K processor With the space, it is indeed possible to achieve the object of the present invention. 13 201206174 However, the above description is only a preferred embodiment of the present invention, and the general pointer adjusts the horizontal synchronization (4) of different video formats to achieve the corresponding automatic filter adjustment, and cannot limit the implementation of the present invention. The scope, that is, the simple equivalent changes and modifications made by the present invention in the scope of the invention and the description of the invention are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional main chip and video filter driving device; FIG. 2 is a block diagram showing an SD video signal filtering unit of the video filter driving device; A block diagram illustrating the HD video signal filtering unit of the video filter driving device; FIG. 4 is a block diagram showing the main chip and video filter driving device of the video processor of the present invention; FIG. 5 is a block diagram illustrating a signal format judging unit of the video filter driving device and a first video signal filtering unit; FIG. 6 is a block diagram illustrating a second video signal filtering unit of the video filter driving device; FIG. 7 is a block diagram illustrating the video A third video signal filtering unit of the filter driving device; and FIG. 8 is a schematic diagram illustrating a user interface of the television or the player. 201206174 [Explanation of main component symbols] 4 ....... Main day and day film 53...... .... Third video signal filtering unit 41·····.....Video decoder 601... •...DC clamp circuit 421 ··· •...first digital analog converter 602...·switching switch 422 ·····the second digital analog converter 603...·filter bank 423 ···..····the third digit analogy Converter 604 ... ... gain module 5 . . . ... video filter drive device 61 ... ... ... waver 50 ... ... signal format determination unit 62 ... ... ... second filter 501...•...Brightness chroma separation module 900...——Using interface 502... •...Synchronization signal separation module 9 ....... •...Resistance 503... •...Frequency detection module S1... •... A video signal 504... •... level shift module S2... •...second video signal 51...•...first video signal filtering unit S3·.........third video signal 52... Second video signal filtering unit CS ······ control signal
1515