TW201203492A - Die package and related die package structure manufacturing method - Google Patents

Die package and related die package structure manufacturing method Download PDF

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Publication number
TW201203492A
TW201203492A TW099145752A TW99145752A TW201203492A TW 201203492 A TW201203492 A TW 201203492A TW 099145752 A TW099145752 A TW 099145752A TW 99145752 A TW99145752 A TW 99145752A TW 201203492 A TW201203492 A TW 201203492A
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Taiwan
Prior art keywords
die
core material
material layer
layer
package structure
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TW099145752A
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English (en)
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TWI456727B (zh
Inventor
Jen-Chung Chen
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Nanya Technology Corp
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Description

201203492 六、發明說明： 【發明所屬之技術領域】 本發明有關於晶粒封裝結構以及相關的晶粒封裝結構製造方 法’特別有關於使用TSV(Through-SiliconVia，妙晶穿孔)的晶粒封 裝結構以及相關的晶粒封裝結構製造方法。 【先前技術】 現今的DRAM結構常需要高密度或高速度的結構。為了滿足高 密度結構的需求，發展出了 3D封裝結構。與傳統的2D封裝結構比 車义起來，使用3D封裝技術的晶片具有較短的導電路徑以及垂直的 導電結構。使得使用3D封裝技術的晶片與傳統2D封裝結構比較起 來具有較短的傳導路徑以及較少的訊號延遲時間。此外，可以藉由 3D封裝結構增加晶片表現。而且，晶片功率消耗寄生電容以及電 感亦會隨之減少。 TSV技術係為一種3D封裝技術。然而，現今的Tsv技術仍然 不穩定且具有高成本，使得齡的3D雖技術難以跟傳統封裝技 競爭。 义 【發明内容】 因此，本發明之一目的為提供一種較簡潔的3D封裝結構。 本發明之一實施例揭露了一種晶粒封裴結構，包含：_ . 日日 ;立’-第二晶粒；一核心材料層，位於該第—晶粒和該第二晶粒之 201203492 間，至少一通孔，通過該第一晶粒、該第二晶粒以及該核心材料層； 一金屬材料，填入該通孔中，使得該第一晶粒、該第二晶粒以及該 核心材料層可以彼此電性連接；至少一訊號傳收單元，接觸該金屬 材料，以及-介電層，包圍該第一晶粒，包含暴露該訊號傳收單元 的至少一開口。 本發明之另-實施例揭露了 __種晶粒封裝結構製造方法，包含： ⑻形成具有通孔的-私材料層，該通孔巾具有金屬，其中該金屬 具有-突出部份，該突出部份突出雜心材料層；⑼在該核心材料 層的-第-側提供-第-晶粒，其中該第—晶粒具有通孔，且該第 -晶粒的該通孔電性連接至該第—晶粒之—第—側上的核心材料層 之該通孔；⑹於該第-晶粒上提供至少—峨傳收單元，其中軌 號傳收單元位於該第-晶粒的—第二側上，其中該第—晶粒的該第 二側相對於該第-晶粒的該第—側；⑹在該第—晶粒和該核心材料 層上形成-介電層’其中該介電層包含暴露該訊號傳收單元的至少 一開口；以及⑻於該核心材料層的一第二側上形成一第二晶粒，宜 中該核心材料層_第二謝目對於祕吨料層賴第-側。八 根據前述之實_，可叫奴錢錄電路， 整的3D封裝結構。 竹間早但兀 【實施方式】 #及^續物#專侧#蝴了編彙來指稱特 疋的讀。端倾巾具麵常知識者射 ， 會用不同的名詞來稱呼同+ ’綴〜商可敍 201203492 圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上· 的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提 及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。 第1圖输示了根據本發明之一實施例的晶粒封裝結構1〇〇的剖面 圖。如第1圖所示’晶粒封裝結構1〇〇包含一第一晶粒ι〇ι，一核 心材料層103、-第二晶粒105、通孔1〇7、1〇9、金屬材料11〇、介 電層11卜觸通凸塊_^，）112、114、填充材料113、115以 及連接墊117〜127。核心材料層1〇3 (可為聚合物材料例如ρι等）， 被提供於第-晶粒1〇1和第二晶粒1〇5之間。此外，填充材料⑴ _ 位於核心材料層103和第二晶粒1〇5之間，且填充材料ιΐ5位於第 -晶粒ιοί和核心材料層103之間。通孔1〇7、1〇9穿過第一晶粒 101、第二晶粒105以及核心材料層103。金屬材料11〇填入通孔1〇7 和109中，使得第一晶粒101、第二晶粒1〇5以及核心材料層ι〇3 可以彼此電性連接。觸通凸塊112、114接觸金屬材料則，使得黏 接(bonding)在連接墊117〜127上的錫球可透過觸通凸塊ιΐ2、ιΐ4和 金屬110。也就是說，觸通凸塊⑴心可作為訊號傳收單元使用。籲 介電層111包圍第一晶粒10卜並包含了暴露觸通凸塊112、114的 開口 129、13 卜 在實施例中，第一晶粒⑼4系為一主機裝置(脱咖， 且第二晶粒105係為—僕裝置(slave device)。此外，晶粒封裝結構 100可更包含除了第-晶粒1〇1和第二晶粒1〇5之外的晶粒。如第2 圖所示’晶粒封裝結構100更包含了一第三晶粒1〇5，其亦作為僕 裝置使用。姐意的是，晶粒封裝結構剛可包含更多的晶粒，但 6 201203492 於此不再贅述。在此例中，填充材料203可被提供於第二晶粒1〇5 和第三晶粒201之間。此種結構可被使用於多種電子裝置中(例如， 一 DRAM) 〇 第3-10圖繪示了根據本發明之一實施例的晶粒封裝結構製造方 法。請留意第3-10圖甲的步驟僅用以舉例，並非用以限定本發明。 如第3(a)圖所示，提供了一核心材料層3〇1(例如聚合物材料ρι)。 在第3(b)圖中，通孔303和305形成於核心材料層;3〇1中。然後， 在第4(a)圖中，如銅之類的金屬材料斯可被提供於核心材料層則 上(例如，透過塗佈處理）。在第4(b)圖中，光阻層4〇1被提供在金 屬材料307的某些部份上1著會透過顯影或侧移除其他部份的 金屬材料307，使得金屬材料307突出於核心材料層3〇1的表面， 如第5⑻圖所示。然後，光阻層5〇1被提供於核心材料層3〇ι上。 在第6⑻圖中，第一晶粒6〇1被提供在一表面上，此表面相對於 光阻層被提供的表面。第-晶粒⑽包含了通孔6()2和6()4 (例如， TSV、’’。構）核〜材料層301的通孔和第一晶粒6⑴可以透過熱壓接 法(The麵lc卿職i〇n)、超音波壓接法⑽^侧㈣或 溶接等形式而連結在-起。此外’填紐料⑽可被提供於核心材 料層301以及第一晶粒6〇1之間，使得第一晶粒6⑴可緊密的連接 至核心材料層3()1，且蒸氣可被防止進入核心材料層3〇ι和第一晶 粒601間的間隙。 在第7(a)圖中，提供了觸通凸塊期、7〇3(作為訊號傳收單元使 用）’被提供以接觸第一晶粒6〇1的通孔6〇2、6〇4。透過此類觸通 凸塊彻、703 ’可以省略長成金屬種和薄膜的製程，使得介電材料 201203492 魏可峨⑽成。在第糊巾，可使用一顯影 S來對準觸通凸塊7〇卜7〇3的位置，使得光阻材料7〇5、抓可 被提供在觸通凸塊期、703上。然後，介電材料_可為W膠或 B P皆環氧樹脂）’可透過—印刷過程被提供(未限制於此）。在第卿 圖中，光阻材料705、707被移除，以形成曝露觸通凸塊7m、703 的開口。 在第9(a)圖中，提供了錫球的連接墊9_u。在第9⑼圖中提 供了第二晶粒913。此外’類似於第一晶粒6〇卜填充材料915可被 提供於第二晶粒913和核心材料層301之間。在第1〇(a)圖中，錫球 1001〜1011被提供於連接墊901〜911 ±，且可施行一油墨製程⑽ process)以形成第i〇(b)圖的結構。然後可施行一凸塊底金屬層 (Under5wmpMetallurgy，UBMj製程至第二晶粒913的一主動表面。 如前所述，可提供多個晶粒以形成第2圖的結構，並可藉由此方法 形成較高容量的DRAM。 根據前述實施例’可快速形成連接墊電路並形成簡潔但完整的 3D封裝置結構。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所 做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第i圖和第2圖繪示了根據本發明之一實施例的晶粒封裂結構的 剖面圖。 第3_1〇圖繪示了根據本發明之一實施例的晶粒封袭結構製造方 201203492 法。 【主要元件符號說明】 100晶粒封裝結構 101、601第一晶粒 103、301核心材料層 105、913第二晶粒 107、109、303、305、602、604 通孔 ® 110、307金屬材料 111介電層 112、 114、701、703 觸通凸塊 113、 115、603填充材料 117-127、907-911 連接墊 201第三晶粒 401、501光阻層 • 705、707光阻材料 801介電材料 915填充材料 1001〜1011錫球

Claims (1)

  1. 201203492 七、申請專利範圍： 1. 一種晶粒封裝結構，包含： 一第一晶粒； 一第二晶粒； 一核心材料層’位於該第-晶粒和該第二晶粒之間； 至少一通孔，穿過該第一晶粒、 s U及_心、材料層； 一金屬材枓’填入該通孔中，佶 .,.la 吏于。玄第一明粒、該第二晶粒以及該 核心材料層可以彼此電性連接； 至少-訊號傳收單元，接戦金屬材料；以及 "口電層’包_第—晶粒’包含暴露該喊傳收單元的至少一開 利範圍第1項的晶粒缝結構，其中該第一晶粒係為一 主機裝置，且該第二晶粒係為一僕敦置。 專2第1項的晶粒封裝結構，更包含-第三晶粒，具 夕孔’使付該第二晶㈣f性連接至該第二晶粒。 4. ^綱_第i項的_裝結構，更包含填充材料 充材料位於該第—晶粒以及該核、 ' 心材料之間。 彳㈠树，似轉二脉和該核 5•如申請專侧第丨_陶_，嫩蝴開口旁的 201203492 連接墊。 申月專利範圍第i項的晶粒封裝結構，其中該核心材料層包含 聚合物材料。 7· -種晶粒封裝結構製造方法，包含： Ί、有通孔的—核心材料層，該通孔中具有金屬，其中該金 屬具有一突出部份，該突出部份突出該核心材料層； ⑼在該核心材料層的—第—側提供—第—晶粒，其中該第一晶粒 具有通孔’且該第-晶粒的該通孔電性連接至該第一晶粒之一第 一側上的核心材料層之該通孔； (0於該第-晶粒上提供至少—訊號傳收單元，其中該訊號傳收單 讀於該第-晶粒的-第二側上，其中該第—晶粒的該第二側相 對於遠第一晶粒的該第一側； ⑷在該第-晶粒和該核心材料層上形成一介電層，其中該介電 包含暴露該訊號傳收單元的至少一開口；以及 ⑹於該核心材料層的-第二側上形成一第二晶粒，其中該核心 料層的該第二側相對於該核^材料層的該第一側。 8.如申請專利額第7項的晶粒封裝結構製造方法，更包 第二晶粒，該第三晶粒具有至少—通孔 ” 連接至該第二晶粒。 使传辟二晶粒可電性 201203492 9. 如申請專利範圍第7項的晶粒封裝結構製造方法，更包含提供填 充材料，該填充材料位於該第一晶粒以及該核心材料之間，以及 §亥第一晶粒和該核心材料之間。 10. 如申請專利範圍第7項的晶粒封裝結構製造方法，其中該步驟 ⑻包含： 於該核心材料層中形成該通孔； 於該核心材料層的-表面上以及該通孔中錢上金屬；以及 於該金屬上提供-光阻層並触科該金屬的其他部份以形成該突出部 份0 U.如申請專利範圍第7項的晶粒封裝結構製造方法，更包含： 在提供-/二晶粒於該核心材料層之―第二側上之前，於核心材料 層之s玄第一侧上提供一光阻層。 12如申=專利範圍第7項的晶粒封裝結構製造方法，其中該娜# (e)包含： 於該sfl號傳收單元上提供一光阻層； 提供該介電層；以及 移除該§fl號傳收單元上的該光阻層。 八、圖式： 12
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