201143262 六、發明說明： m 【發明所屬之技術領域】 本發明是有關於一種功率因數調整電路，特別是有 關於一種無橋交錯式功率因數調整電路。 【先前技術】 目前，市場上大部分的交直流電源控制裝置，如變頻 •控制窗型冷氣、中央空調系統之各種變頻驅動器或交流感 應馬達之速度控制，主要可分為三大控制方式，分別為極 數控制、功率控制及頻率控制，最前者極數控制的變極數 接線十分複雜，次者功率控制則需穩定負載方可使用，而 變頻率控制在現今的交直流電源控制產業裡具有其優勢， 尤為交流感應馬達之速度控制的最佳方法。 _變頻率控制將交流電轉變為直流電，再將它切換成不 同頻率的父流電以驅動馬達。因此，如何提供高效率、高 鲁功率因數、低連波電流及大容量的交流轉直流轉換器已成 為一個研究與應用上日趨重要的課題。 現今已被提出來的電路模組有： (1) 功因調整電路，其優點在於提高功率因數。 (2) 無橋式整流功因調整電路，其優點在於提高效率。 (3) 交錯式功因調整電路，其優點在於減少漣波電流。 惟效率、功率因數、漣波電流及成本均為現今市場應 用上極為重視的要‘點。因此，以f求來說，要同時具有如 201143262 上述幾點優點之理想的功率因數調整電路，已成市場應用 上刻不容緩的問題。 【發明内容】 有鑑於上述習知技術之問題，本發明之目的就是在 提供無橋交錯式功率因數調整電路，以解決目前現有電 路在效率、功率因數、漣波電流及成本不符合市場需求 的問題。 根據本發明之目的，提出一種無橋交錯式功率因數 =整電路，係包含電壓源、第一電流感應單元、第二電 2感應單元以及切換單元組。其中電壓源產生正弦波交 電壓汛唬。第一電流感應單元連接電壓源並接收正弦 波父流電壓訊號之正半週週期，且第一電流感應單元具 有第一輸出電壓及第二輸出電壓。第二電流感應單元連 接電壓源並接收該正弦波交流電壓訊號之負半週週期， 並第二電流感應單元具有第三輸出電壓及第四輸出電 壓:切換單元組係包含第一切換單元、第二切換單元、 =二切換早兀、第四切換單元、電容、負載電阻以及總 輸^電壓。其中第-切換單元、第二切換單元、第三切 ，單7C、第四切換單①、電容、負載電阻以及總輸出電 ^彼此並聯’且第一電流感應單元連接第-切換單元和 ^二切換單元’第二電流感應單it連接第三⑽單元和 四切換單元。此外’在電壓源之波形為正 間’當第—切換單元導通之階段，第—錢感應單= 201143262 运第-電流流進第二切換單元，並經由負載電 切換單元流回第二電流感應單元；當第—切換 ，階段’第-電流感應單元傳送第二電流流進第：：換 :::並經由負載電阻和第三切換單元流回' 應早兀。而在電壓源之波形為負半週週期期間，：4 切換單元導通之階段’第二電流感 ：： 流進第四切換單元，並經由負載電阻和第== 回第-電流感應單元；當第三切換單元截止之階严 j流感應單元傳送第四電流流進第三切換單/並經 由負載電阻和第-切換單元流回第—電流感應單元。、，· 體，ί中雷！：切換單元係包含第一二極體及第-電晶 切換單元係包含第…：:二：=之輸入端；第二 一一極體及第一電晶體，第二電晶體 極體之輸入端；第三切換單元係包含 晶體，第三電晶體之汲極串聯第三 二電第四切換單元係包含第四二極體及第 戚。i +笛_ a體之，及極串聯第四二極體之輸入 -極極體、第二二極體、第三二極體及第四 接在一起，並並聯電容、負載電阻及 端；且第一電晶體、第二電晶體、第 * 目電晶體之源極連接在―起，並並聯電 ♦、負载電阻及總輸出電魔 —+Γ-0： 之波形為正半週週期：：；負電k。此外，在電壓源 :入應單元傳送第-電流流經第二二極體之 ' 、兩鳊，並經由負载電阻和第四電晶體之源極 7 201143262 二電流感應單元；當第-電晶體截止之階 ί入應單元傳送第二電流流經第-二極體之 :=:=1並經由？载電阻和第三電晶體之源極 :電流感應單^。在電壓源之波形為負半 週週』期間’當第三電晶體觸發 感應單元傳送第：電f㈣ 姐4γ=電机机經第四二極體之輸入端與輸出 二ϊί載電阻和第二電晶體之源極和沒極流回第 電流感應早元；告笛；;：带a Μ 田第一 t日日體截止之階段，第二電流 第四電流流經第三二極體之輸入端與輸出 一带由ί載電阻和第—電晶體之源極和沒極流回第 一電流感應單元。 其中’無橋交錯式功率因數調整電路更包括一控制 電路連接於電1輸人源與切換單（组之間，控制電路分 ，連接第-電晶體、第二電晶體、第三電晶體及第四電 曰曰體之閘極’且控制電路分別傳送電壓訊號至第一電晶 體、第二電晶體、第三電晶體及第四電晶體之閘極；當 電壓訊號經過緩衝器至閘極時’則電晶體觸發導通，若 電壓訊號未經過緩衝II至閘極時，則電晶體截止。此外 控制電路Α @㉟路控制電路或閉迴路控制電路。 其t]開迴路控制電路接收電壓輸入源之輸入電壓 與切換單元組之輸入電流，進而使得輸入電流與輸入電 壓調整成同相位。而閉迴路控制電路接收電壓輸入源之 輸入電壓與切換單元組之總輸出電壓，進而使得總輸出 電壓能維持在—常壓，且切換單元組之負載電阻值之大 小並不會影響總輸出電壓維持在一常壓。 201143262 其中，第一電流感應單元包含第一電感以及第二電 ' 感；第二電流感應單元包含第三電感以及第四電感。且 、 第一電感連接第一二極體之輸入端，第二電感連接第二 二極體之輸入端，第三電感連接第三二極體之輸入端， 第四電感連接第四二極體之輸入端。此外，無橋交錯式 功率因數調整電路其交流電壓之頻率與搭配之兩組電流 感應單元之值成一反比。 承上所述’依本發明之無橋交錯式功率因數調整電 鲁路’其可具有一個或多個下述優點： (1) 功因調整其輸入端的功率因數趨近Ki。 (2) 無橋式整流電路效率提升至0.96以上。 (3 )交錯式功因調整電路之漣波電流減為一般之十 分之一。 (4)降低了整流器額外的需求成本。 (5 )輸出電壓更穩定’以應付更大電流的負載。 鲁 【實施方式】 以下將參照相關圖式，§兒明依本發明之無橋交錯式 力率因數調整電路之實施例，為使便於理解，下述實施 例中之相同元件係以相同之符號標示來說明。 數』ίΓ1圖’其係為本發明之無橋交錯式功率因 數調整電路之主電路圖。該圖中，包含一電壓源10 —電流感應單元η、第二電流感應單元12以及切換單 201143262 元組13、。其中電壓源1 〇產生正弦波交流電壓訊號。第 :電流感應單元11連接電壓源10並接收正弦波交流電 壓訊號之正半週週期，且第一電流感應單元11具有第一 輸出電壓V1及第二輸出電壓V2。第二電流感應單元12 連接電壓源1〇並接收該正弦波交流電壓訊號之負半週 週期，並第二電流感應單元12具有第三輸出電壓乂3及 第四輸出電壓V4。切換單元組13包含第一切換單元 1^31、第二切換單元132、第三切換單元133、第四切換 單兀134、電容C、負載電阻R以及總輸出電壓％。其 中第一切換單元13卜第二切換單元132、第三切換單元 133、 第四切換單元134、電容c、負載電阻r以及總輸 出電壓Vo彼此相互並聯在一起，且第一電流感應單元 11連接第一切換單元131和第二切換單元132，第二電 流感應單元12連接第三切換單元133和第四切換 134。 ' 承接上述，在電壓源1〇之波形為正半週週期的期間 時，當第一切換單元131導通的階段，第一電流感應單 元11會傳送第一電流流進第二切換單元132，並經由負 載電阻R和第四切換單元134流回第二電流感應單元 12，而當第一切換單元〗31截止的階段，第一電流感應 單元11傳送第二電流流進第一切換單元丨3〗，並經由負 載電阻R和第三切換單A 133流回第二電流感應單元 12。而在電壓源10之波形為負半週週期的期間，當第三 切換單元133導通的階段，第二電流感應單元12^送& 二電流流進第四切換單元134，並經由負载電阻R和第 201143262 二切換單元132流回第一電流感應單元11 ;當第三切換 早元133截止的階段’第二電Li·感應早元12傳送第四電 、 流流進第三切換單元133，並經由負載電阻r和第一切 換單元131流回第一電流感應單元11。 此外，第一切換單元131包含第一二極體D1及第 一電晶體Ml，第一電晶體Ml之沒極串聯第一二極體 D1之輸入端；第二切換單元132包含第二二極體D2及 第二電晶體M2’第二電晶體M2之汲極串聯第二二極體 φ D2之輸入端；第三切換單元133包含第三二極體D3及 第三電晶體M3,第三電晶體M3之汲極串聯第三二極體 D3之輸入端，第四切換早元134包含第四二極體D 4及 第四電晶體M4 ’第四電晶體M4之汲極串聯第四二極體 D4之輸入端。而這些第一二極體D1、第二二極體D2、 第三二極體D3及第四二極體D4之輸出端連接在一起， 並並聯電容C、負載電阻R及總輸出電壓Vo之正電端； 並且這些第一電晶體Ml、第二電晶體M2、第三電晶體 φ M3及第四電晶體M4之源極連接在一起，並並聯電容 C、負載電阻R及總輸出電壓Vo之負電端。 進一步詳述的是，在電壓源10之波形為正半週週期 期間，當第一電晶體Ml觸發導通之階段，第一電流成 應單元11傳送第一電流流經第二二極體D2之輸入端與 輸出端，並經由負載電阻R和第四電晶體M4之源極和 没極流回第二電流感應單元12 ;當第一電晶體mi截止 之階段，第一電流感應單元11傳送第二電流流經第一二 極體D1之輸入端與輸出端，並經由負載電阻R和第三 11 201143262 電晶體M3之源極和汲極流回第二電流感應單元12。而 在電壓源10之波形為負半週週期期間，當第三電晶體· M3觸發導通之階段，第二電流感應單元〗2傳送第三電 /爪流經第四一極體D4之輸入端與輸出端，並經由負載 電，R和第二電晶體M2之源極和汲極流回第一電流感 應單元11，當第三電晶體M3截止之階段，第-雷流威 應單元12傳送第四電流流經第三二極體D3:輸= 輸出端，並經由負載電阻R和第一電晶體D1之源極和 没極流回第一電流感應單元11。 請參閱第2圖及第4圖，無橋交錯式功率因數調整 電路更包括一控制電路連接於電壓輸入源1〇與切換單 疋組13之間，進一步說明，控制電路分別連接第一電晶 體Ml、第二電晶體M2、第三電晶體M3及第四電晶體 M4之閘極’且控制電路分別傳送電壓訊號至第一電晶體 1VH、第二電晶體M2、第三電晶體M3及第四電晶體 之閘極；當電壓訊號經過緩衝器至閘極時，則電晶體觸 發導通，若電壓訊號未經過緩衝器至閘極時，則電晶體 截止。此外，㈣j電路為一開迴路控制電m戈閉迴路_ 控制電路21。 承上所述，開迴路控制電路20接收電壓輸入源1〇 之輸入電壓Vin與切換單元組13之輸入電流，進而使得 輸入電流與輸入電壓vin調整成同相位。而閉迴路控制 電路21接收電壓輸入源1〇之輸入電壓與切換單元 組13之總輸出電壓v〇,進而使得總輸出電壓％能維持 在㊉壓，且切換單元組13之負載電阻R之值的大小 12 201143262 並不會影響總輸出電壓ν〇維持在一常壓。 、 一在本實施例中，第一電晶體Ml、第二電晶體M2、 第二電晶體M3以及第四電晶體M4皆為p型電晶體。 且第電流感應單兀11包含第一電感L1以及第二電感 L2 ’第二電流感應單元12包含第三電感u以及第四電 感L4，此四個電感皆為高頻偶合式電感。此外，第一電 感U連接第一二極體D1之輸入端，第二電感連接 第二二極體D2之輸入端’第三電感匕3連接第三二極體 ’ D3之輸入端，第四電感"連接第四二極體d4之輸入 端。 :，本實施例中，第一電流感應單元U及該第二電流 ，應單元12稱為一耦合式昇壓型功因調整電路，該切換 單元組13為一交錯式功因調整電路。 &順帶一提的是，無橋交錯式功率因數調整電路其交 /爪電壓之頻率與搭配之兩組電流感應單元丨卜12之值成 一反比。 知上所述’本發明之無橋交錯式功率因數調整電 路，結合了無橋式整流功因調整電路及交錯式功因調整 ，路之概念，藉由擷取其各自優點發展而成的一種具有 高功率因數與高效能之昇壓穩壓電路。其具有如下特點： (1) 功因調整其輸入端的功率因數趨近於1。 (2) 無橋式整流電路效率提升至〇 96以上。 (3 )交錯式功因調整電路之漣波電流減為一般之十 分之一。 13 201143262 (4)降低了整流器額外的需求成本。 ⑸輸出電壓更穩定’以應付更大電流的負载。 以上所述僅為舉例性，而非為限制性者。任何未脫 :本發明之精神與料，而對其進行之等效修改或變 更，均應包含於後附之申請專利範圍中。 【圖式簡單說明】 第1圖係'為本發明之無橋交錯式功率因數調整電路之 主電路圖； 第圖係為本發明之無橋交錯式功率因數調整電路之 主電路含開迴路控制電路圖； 圖係為本發明之無橋交錯式功率因數調整電路之 主電路含開迴路控制電路的模擬結果圖； 圖係為本發明之無橋交錯式功率因數調整電路 之主電路含閉迴路控制電路圖；以及 第 5 hi 、 係為本發明之無橋交錯式功率因數調整電路之 主電路含閉迴路控制電路的模擬結果圖。 【主要元件符號說明】 1G:電壓源； 11:第一電流感應單元； 2·第一電流感應單元； 201143262 13 :切換單元組； ' 20 :開迴路控制電路； ^ 21 :閉迴路控制電路； 131 :第一切換單元； 132 :第二切換單元； 133 :第三切換單元； 134 :第四切換單元； • Vin :輸入電壓； L1 :第一電感； L2 :第二電感； L3 :第三電感； L4 :第四電感； VI :第一輸出電壓； V2 :第二輸出電壓； ® V3 :第三輸出電壓； V4 :第四輸出電壓； D1 :第一二極體； D2 :第二二極體； D3 :第三二極體； D4 :第四二極體；201143262 VI. Description of the Invention: m [Technical Field of the Invention] The present invention relates to a power factor adjustment circuit, and more particularly to a bridgeless interleaved power factor adjustment circuit. [Prior Art] At present, most of the AC/DC power supply control devices on the market, such as inverter/control window type air-conditioning, various variable frequency drives of central air-conditioning systems or speed control of AC induction motors, can be divided into three major control modes. For the pole number control, power control and frequency control, the pole number connection of the former pole number control is very complicated, the second power control needs to be stable and the load can be used, and the variable frequency control has the current AC/DC power supply control industry. Its advantages are especially the best way to control the speed of an induction motor. The variable frequency control converts the alternating current into direct current, and then switches it to a parent current of different frequencies to drive the motor. Therefore, how to provide high efficiency, high power factor, low continuous current and large capacity AC to DC converter has become an increasingly important issue in research and application. The circuit modules that have been proposed today are: (1) Power factor adjustment circuit, which has the advantage of improving the power factor. (2) The bridgeless rectifier power factor adjustment circuit has the advantage of improving efficiency. (3) Interleaved power factor adjustment circuit, which has the advantage of reducing chopping current. However, efficiency, power factor, chopping current and cost are all important points in today's market applications. Therefore, in terms of f, the ideal power factor adjustment circuit with the above advantages of 201143262 has become an urgent problem in the market. SUMMARY OF THE INVENTION In view of the above problems of the prior art, the object of the present invention is to provide a bridgeless interleaved power factor adjustment circuit to solve the current current circuit in terms of efficiency, power factor, chopping current and cost are not in line with market demand. problem. In accordance with the purpose of the present invention, a bridgeless interleaved power factor = integrated circuit is provided that includes a voltage source, a first current sensing unit, a second electrical sensing unit, and a switching unit group. The voltage source generates a sinusoidal voltage 汛唬. The first current sensing unit is coupled to the voltage source and receives a positive half cycle period of the sine wave parent voltage signal, and the first current sensing unit has a first output voltage and a second output voltage. The second current sensing unit is connected to the voltage source and receives the negative half cycle period of the sine wave AC voltage signal, and the second current sensing unit has a third output voltage and a fourth output voltage: the switching unit group includes the first switching unit, Two switching units, = two switching early, fourth switching unit, capacitor, load resistance and total output voltage. The first switching unit, the second switching unit, the third switching unit, the single 7C, the fourth switching unit 1, the capacitor, the load resistor and the total output circuit are connected in parallel with each other and the first current sensing unit is connected to the first switching unit and the second switching unit The switching unit 'second current sensing single is connected to the third (10) unit and the fourth switching unit. In addition, 'the waveform of the voltage source is positive'. When the first-switching unit is turned on, the first-money sensing unit = 201143262--the current flows into the second switching unit, and flows back to the second current sensing via the load switching unit. Unit; when the first-switching, phase 'the current-current sensing unit transmits the second current into the first::change::: and flows back through the load resistor and the third switching unit' should be early. While the waveform of the voltage source is in the negative half cycle period, the phase of the switching unit is turned on. The second current sense: flows into the fourth switching unit, and passes through the load resistor and the == back to the first current sensing unit; The third switching unit cut-off step j flow sensing unit transmits the fourth current into the third switching unit / and flows back to the first current sensing unit via the load resistor and the first switching unit. ,,· Body, ί中雷! The switching unit includes a first diode and a first-metal switching unit including an input end of the first::: two:=; a second one and a first transistor, and an input of the second transistor The third switching unit includes a crystal, and the third transistor of the third transistor is connected in series with the third diode. The fourth switching unit includes a fourth diode and a third diode. i + flute _ a body, and the input of the fourth diode of the pole series - the pole body, the second diode, the third diode and the fourth are connected together, and the capacitor, the load resistor and the terminal are connected in parallel; The source of the first transistor, the second transistor, and the fourth transistor are connected to each other, and the parallel circuit ♦, the load resistance, and the total output electric magic—+Γ-0: the waveform is a positive half cycle period: ; negative k. In addition, in the voltage source: the input unit transmits a first current flowing through the second diode's ', two turns, and through the load resistor and the fourth transistor source 7 201143262 two current sensing unit; when the first transistor The cut-off step is to transmit the second current through the first-dipole: =:=1 and via? The load resistance and the source of the third transistor: current sensing single ^. During the negative half-cycle of the voltage source's period, when the third transistor triggers the sensing unit to transmit the first: electric f(4), the sister 4γ = the input of the motor through the fourth diode and the output of the second resistor, and the second resistor The source and the immersion of the transistor return to the current sense early element; whistle;;: with a Μ field the first t day of the body cut-off phase, the second current fourth current flows through the input of the third diode The terminal and the output are returned to the first current sensing unit by the source and the immersion of the Δ load resistor and the first transistor. The 'bridgeless interleaved power factor adjustment circuit further includes a control circuit connected to the electric 1 input source and the switching unit (between groups, the control circuit is divided, the first transistor, the second transistor, the third transistor and a gate of the fourth electrode body and the control circuit respectively transmits a voltage signal to the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor; when the voltage signal passes through the buffer to the gate At the time of 'the transistor triggers the conduction, if the voltage signal does not pass the buffer II to the gate, the transistor is turned off. In addition, the control circuit Α @35 way control circuit or closed loop control circuit. Its t] open loop control circuit receives voltage input The input voltage of the source and the input current of the switching unit group, so that the input current and the input voltage are adjusted in phase, and the closed loop control circuit receives the input voltage of the voltage input source and the total output voltage of the switching unit group, thereby making the total output voltage Can maintain at - atmospheric pressure, and the magnitude of the load resistance of the switching unit group does not affect the total output voltage maintained at a normal pressure. 201143262 Among them, the first The current sensing unit includes a first inductor and a second electrical sense; the second current sensing unit includes a third inductor and a fourth inductor, and the first inductor is connected to the input end of the first diode, and the second inductor is connected to the second inductor. At the input end of the polar body, the third inductor is connected to the input end of the third diode, and the fourth inductor is connected to the input end of the fourth diode. In addition, the frequency and matching of the AC voltage of the bridgeless interleaved power factor adjustment circuit The values of the two sets of current sensing units are inversely proportional to each other. The above-mentioned "bridgeless interleaved power factor adjustment electric circuit" according to the present invention may have one or more of the following advantages: (1) the power factor adjusts its input terminal The power factor approaches Ki. (2) The efficiency of the bridgeless rectifier circuit is increased to 0.96 or higher. (3) The chopping current of the interleaved power factor adjustment circuit is reduced by one tenth of the general. (4) The additional rectifier is reduced. Cost of demand (5) The output voltage is more stable 'to cope with the load of larger current. Lu [Embodiment] The following will refer to the related drawings, and the embodiment of the bridgeless interleaved force factor adjustment circuit according to the present invention For the sake of understanding, the same components in the following embodiments are denoted by the same reference numerals. The numeral is a main circuit diagram of the bridgeless interleaved power factor adjustment circuit of the present invention. A voltage source 10 - a current sensing unit η, a second current sensing unit 12, and a switching unit 201143262 tuple 13, wherein the voltage source 1 〇 generates a sine wave AC voltage signal. The current sensing unit 11 is connected to the voltage source 10 and receives the sine The positive current half cycle of the alternating current voltage signal, and the first current sensing unit 11 has a first output voltage V1 and a second output voltage V2. The second current sensing unit 12 is connected to the voltage source 1〇 and receives the sine wave AC voltage signal. The negative half cycle period, and the second current sensing unit 12 has a third output voltage 乂3 and a fourth output voltage V4. The switching unit group 13 includes a first switching unit 1^31, a second switching unit 132, a third switching unit 133, a fourth switching unit 134, a capacitor C, a load resistor R, and a total output voltage %. The first switching unit 13 , the second switching unit 132 , the third switching unit 133 , the fourth switching unit 134 , the capacitor c , the load resistor r , and the total output voltage Vo are mutually connected in parallel, and the first current sensing unit 11 is connected. The first switching unit 131 and the second switching unit 132, the second current sensing unit 12 is connected to the third switching unit 133 and the fourth switching 134. In the above, when the waveform of the voltage source 1〇 is a positive half cycle period, when the first switching unit 131 is turned on, the first current sensing unit 11 transmits the first current to the second switching unit 132, and Flowing back to the second current sensing unit 12 via the load resistor R and the fourth switching unit 134, and when the first switching unit 31 is turned off, the first current sensing unit 11 transmits the second current into the first switching unit 丨3 And flowing back to the second current sensing unit 12 via the load resistor R and the third switching unit A 133. While the waveform of the voltage source 10 is in a negative half cycle period, when the third switching unit 133 is turned on, the second current sensing unit 12 sends & two currents into the fourth switching unit 134, and via the load resistor R. And the 201143262 second switching unit 132 flows back to the first current sensing unit 11; when the third switching early element 133 is turned off, the second electric Li·sensing early element 12 transmits the fourth electric current, and the flow flows into the third switching unit 133. And flowing back to the first current sensing unit 11 via the load resistor r and the first switching unit 131. In addition, the first switching unit 131 includes a first diode D1 and a first transistor M1, the first transistor M1 is connected in series with the input end of the first diode D1; the second switching unit 132 includes a second diode The drain of the body D2 and the second transistor M2' of the second transistor M2 is connected in series with the input terminal of the second diode φ D2; the third switching unit 133 includes the third diode D3 and the third transistor M3, and the third The drain of the transistor M3 is connected in series with the input terminal of the third diode D3, and the fourth switching early element 134 includes the fourth diode D 4 and the fourth transistor M4. The fourth transistor M4 is connected in series with the fourth diode. The input of the pole D4. The output ends of the first diode D1, the second diode D2, the third diode D3 and the fourth diode D4 are connected together, and the capacitor C, the load resistor R and the total output voltage Vo are connected in parallel. a positive terminal; and the sources of the first transistor M1, the second transistor M2, the third transistor φ M3, and the fourth transistor M4 are connected together, and the capacitor C, the load resistor R, and the total output voltage Vo are connected in parallel The negative terminal. More specifically, during the positive half cycle period of the waveform of the voltage source 10, when the first transistor M1 triggers the conduction phase, the first current forming unit 11 transmits the first current through the second diode D2. The input end and the output end flow back to the second current sensing unit 12 via the source and the dynode of the load resistor R and the fourth transistor M4; when the first transistor mi is turned off, the first current sensing unit 11 transmits the first The two currents flow through the input end and the output end of the first diode D1, and flow back to the second current sensing unit 12 via the load resistor R and the source and drain of the third 11 201143262 transistor M3. While the waveform of the voltage source 10 is in a negative half cycle period, when the third transistor M3 triggers the conduction phase, the second current sensing unit transmits a third electric/claw through the input end of the fourth one of the fourth body D4. And the output terminal, and via the load, the source and the drain of the R and the second transistor M2 flow back to the first current sensing unit 11, and when the third transistor M3 is turned off, the first-throttle retributing unit 12 transmits The fourth current flows through the third diode D3: the output terminal, and flows back to the first current sensing unit 11 via the load resistor R and the source and the dynode of the first transistor D1. Referring to FIG. 2 and FIG. 4, the bridgeless interleaved power factor adjustment circuit further includes a control circuit connected between the voltage input source 1 and the switching unit group 13. Further, the control circuit is respectively connected to the first transistor. a gate of the M1, the second transistor M2, the third transistor M3, and the fourth transistor M4, and the control circuit respectively transmits the voltage signal to the first transistor 1VH, the second transistor M2, the third transistor M3, and the The gate of the four transistors; when the voltage signal passes through the buffer to the gate, the transistor triggers the conduction. If the voltage signal does not pass through the buffer to the gate, the transistor is turned off. In addition, the (four)j circuit is an open loop control electric m closed circuit _ control circuit 21. As described above, the open loop control circuit 20 receives the input voltage Vin of the voltage input source 1 and the input current of the switching unit group 13, thereby making the input current and the input voltage vin adjusted in phase. The closed loop control circuit 21 receives the input voltage of the voltage input source 1〇 and the total output voltage v〇 of the switching unit group 13, so that the total output voltage % can be maintained at ten voltages, and the value of the load resistance R of the switching unit group 13 The size of 12 201143262 does not affect the total output voltage ν 〇 maintained at a constant pressure. In this embodiment, the first transistor M1, the second transistor M2, the second transistor M3, and the fourth transistor M4 are all p-type transistors. The first current sensing unit 11 includes a first inductor L1 and a second inductor L2. The second current sensing unit 12 includes a third inductor u and a fourth inductor L4, all of which are high frequency coupled inductors. In addition, the first inductor U is connected to the input end of the first diode D1, and the second inductor is connected to the input end of the second diode D2. The third inductor 匕3 is connected to the input end of the third diode D3. The inductor " connects the input of the fourth diode d4. In the present embodiment, the first current sensing unit U and the second current receiving unit 12 are referred to as a coupled boost type power factor adjusting circuit, and the switching unit group 13 is an interleaved power factor adjusting circuit. Incidentally, the frequency of the AC/Paw voltage of the bridgeless interleaved power factor adjustment circuit is inversely proportional to the value of the two sets of current sensing units. Known as the above-mentioned bridgeless interleaved power factor adjustment circuit, combined with the bridgeless rectification power factor adjustment circuit and the interleaved power factor adjustment, the concept of the road, developed by taking advantage of their respective advantages Boost regulator circuit with high power factor and high efficiency. It has the following characteristics: (1) The power factor of the input is adjusted to be close to 1. (2) The efficiency of the bridgeless rectifier circuit is increased to 〇 96 or higher. (3) The chopping current of the interleaved power factor adjustment circuit is reduced to one tenth of the general. 13 201143262 (4) Reduce the additional cost of the rectifier. (5) The output voltage is more stable' to handle the load of higher current. The above is intended to be illustrative only and not limiting. Any changes or modifications of the spirit and composition of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main circuit diagram of a bridgeless interleaved power factor adjustment circuit of the present invention; FIG. 1 is a schematic diagram of an open circuit control circuit of a main circuit of a bridgeless interleaved power factor adjustment circuit of the present invention. The diagram is a simulation result diagram of the main circuit of the bridgeless interleaved power factor adjustment circuit of the present invention including an open loop control circuit; the diagram is a closed loop control circuit diagram of the main circuit of the bridgeless interleaved power factor adjustment circuit of the present invention And 5th hi, which is a simulation result diagram of the closed circuit control circuit of the main circuit of the bridgeless interleaved power factor adjustment circuit of the present invention. [Main component symbol description] 1G: voltage source; 11: first current sensing unit; 2. first current sensing unit; 201143262 13: switching unit group; '20: open loop control circuit; ^ 21: closed loop control circuit; 131: first switching unit; 132: second switching unit; 133: third switching unit; 134: fourth switching unit; • Vin: input voltage; L1: first inductance; L2: second inductance; L3: third Inductance; L4: fourth inductor; VI: first output voltage; V2: second output voltage; ® V3: third output voltage; V4: fourth output voltage; D1: first diode; Polar body; D3: third diode; D4: fourth diode;
Ml :第一電晶體； 15 201143262 M2 :第二電晶體； M3 :第三電晶體； M4 :第四電晶體； C :電容； R :負載電阻；以及 Vo :總輸出電壓。Ml: first transistor; 15 201143262 M2: second transistor; M3: third transistor; M4: fourth transistor; C: capacitance; R: load resistance; and Vo: total output voltage.