201143088 六、發明說明： 【發明所屬之技術領域】 本發明係關於^種短路型閘流體（thyristor )0 【先前技術】 PNPN閘流體中’已開示有將與其它部分相比接合崩潰 電壓較低的區域設置在接合部，從而降低切換為ON狀態 的崩潰電壓、即觸發電壓（breakover voltage)的短路型閘 流體（例如，參照專利文獻1至專利文獻4)。 圖4所示的以往的短路型閘流體中，當從端子τ〗向端 子T2施加偏壓時，接合部J2即被施加反方向電壓。因此 ，比接合部J2的接合崩潰電壓更低的高濃度雜質層p+十區 域將首先崩潰。其結果是電流集中流至此P++區域。如果 此電流增大，由於橫向的電阻，Pi區域正下面的N1區域 產生電壓下降。由於此電壓下降，接合部為正向偏壓， 在P++區域偏壓值達到最大。此偏壓一超過接合部^的擴 散電位’即會引起從P1區域注入電洞，將端子τι與端子 T2之間轉換為0N狀態。像這樣，在圖4所示的以往的短 路型閘流體中’切換為⑽狀態的觸發電壓係依據P++區域 和N1區域的接合崩潰電壓決定。 先前技術文獻 專利文獻 專利文獻1日本特許公開平〇3_625?1號公報 專利文獻2日轉許公開平队·35號公報 專利文獻3日本料公開平Q3_233973號公報 專利文獻4日本特許公開平〇5·190837號公報 4/29 201143088 但是，在圖4所示的以往的短路型閘流體中，切換 ON狀態的觸發電壓係基於P++區域及與之相接的m區域 的雜質濃度決定。ϋ此’在實現極低觸發電壓的短路型間 流體時，就需要改變Ρ++區域與N1區域的雜質濃度。然而 在改變N1區域的雜質濃度時，會給閘流體的保持電流的特 性造成影響。因此，通過改變N1區域的雜質濃度，在維持 保持電流特性的同時降低觸發電壓是很困難的。這樣，在 圖4所示的以往的短路型閘流體中，要在不給保持電流特 性造成影響的情況下，實現切換為〇N狀態的觸發 低壓化是非常困難的。 土、 因此’本發明的目的在於，提供一種在不給保持電流 特性造成影響的情況下，實現將切換為ON狀態的觸發電 Μ低壓化的短路型閘流體。 【發明内容】 為解決上述問題，本發明的短路型閘流體依序接合第丄 導電型的第1區域、第2導電型的第2區域、前述第1導 電型的第3區域、前述第2導電型的第4區域，並設有使 前述第1區域與前述第2區域短路的電極；其具有形成為 與前述第3區域相接、比前述第3區域的雜質濃度更高的 前述第1導電型的第5區域，以及形成為與前述第2區域 及前述第5區域相接、比前述第2區域的雜質濃度更高的 前述第2導電型的第6區域；其觸發電壓值係依據前述第5 區域的雜質濃度和前述第6區域的雜質濃度設定，保持電 流值係依據至少包含如述第2區域的雜質濃度的參數設定 〇 另外，本發明的特徵在於，在上述發明中，前述第5 5/29 201143088 區域或第6區域係形成在前述第 .、 從前述電極與前述第2區域的接二:= 區域和前述第垂:上述發明中’前述第5 導體基板絲面。— σ —直於與前述1：極相接的半 另外，本發明的特徵在於， 區域和前述第6區域的接合面平砂=日种1述第5 導體基板的表面。 #於與所述電極相接的半 另外’本發明的特徵在於，在上述發 區域和前述第6區域中任—奸“ W述弟5 相接的半導體基板的表面。Ml為暴路在與前述電極 發明效果 m2 n 的第3 區 域則述第2導電型的第4區域依序接合，並設 ^區域與前述第2區域短路的電極。另外，^ 體具有與前述第3區域相接形成、比前述第3區_ = 漢度更Γ%的前述第】導電型的第5區域，以及與前述第2 區域及前述第5區域相接形成 '比前述第2區域、曲 度更高的前述第2導電型的第6區域。 很 在這種短路型閘流體中，於第i區域與第4區域之間 施加偏壓時’由於第5區域的雜質濃度和第6區域的雜質 濃度較高’於第5區域和第6區域的接合面比第2區域 第3區域的接合面先出現崩潰。 因此，切換為短路型Μ流體之0N狀態的觸發電壓係 6/29 201143088 第6區域的接合崩潰電壓決定。此吏μ 接口朋m電壓係依據第5區域的雜 、疋此處’此 定，一保持電流特‘ 壓的參數是第5區域巴有了決定觸發電 的短路軸電流。藉此，本發明 實現觸=:=在不影響保持電流特性的情况下， 【實施方式】 對依據本發明第1實施形態的短路型 具體實施形態 第1實施形態 下面參照附圖 閘k體進行說明。 圖1疋表不第1實施形態的短路型閘流Μ 100的戴面 結構圖。 ，圖1中’短路型閘流體100具有Ρ區域（1、3、5) 、Ν 區域（2、4)、通道截斷環（channel stopper) (6〜9)、 電極（11、12)、絕緣層（21〜24)、p++區域（3卜％)、以 及 N++區域（41、42)。 P區域3是作為第1導電型的p型半導體區域，為構成 紐路型開流體削之主體層的半導體基板。此處，將圖^ 中半導體基板的上側面作為第丨表面F1，將半導體基板的 下側面作為第2表面F2。 N區域2是作為第2導電型的η型半導體區域。N區 7/29 201143088 域2形成在P區域1與P區域3之間，其一部分與第1表 面F1相接。 P區域1是p型半導體區域，成形為暴露在第1表面 F卜 N區域4是η型半導體區域。N區域4形成在P區域3 與Ρ區域5之間，其一部分與第2表面F2相接。 Ρ區域5是ρ型半導體區域，成形為暴露在第2表面 F2。 通道截斷環（6〜9)成形為第1表面F1或第2表面F2 與短路型閘流體100的側面相接，是比Ρ區域3的雜質濃 度更南的Ρ型半導體區域。通道截斷壞（6〜9)係抑制對短 路型閘流體100的機能來說，所不期望的漏電流（通道電 流）。 絕緣層21係設置為與第1表面F1相接，並面對第1 表面F1。絕緣層21成形為從通道截斷環6的一部分覆蓋至 Ρ區域1的一部分。絕緣層22係設置為與第1表面F1相接 ，並面對第1表面F1。絕緣層22成形為從通道截斷環7 的一部分覆蓋至Ν區域2的一部分。 另外，絕緣層23係設置為與第2表面F2相接，並面 對第2表面F2。絕緣層23成形為從通道戴斷環9的一部分 覆蓋至Ρ區域5的一部分。絕緣層24係設置為與第2表面 F2相接，並面對第2表面F2。絕緣層24成形為從通道截 斷環8的一部分覆蓋至Ν區域4的一部分。 電極11成形為沿著第1表面F1與沒有覆蓋絕緣層21 的Ρ區域1的一部分和沒有覆蓋絕緣層22的Ν區域2的一 部分相接。電極11的材質為金屬，例如紹。電極11係在 8/29 201143088 使P區域1和N區域2短路的同時，與P區域1及N區域 2 歐姆接觸（Ohmic contact)。 另外，電極12成形為沿著第2表面F2與沒有覆蓋絕 緣層23的P區域5的一部分和沒有覆蓋絕緣層24的N區 域4的一部分相接。電極12的材質為金屬，例如铭。電極 12使P區域5和N區域4短路，同時與P區域5及N區域 4歐姆接觸。 P++區域31係形成在與P區域3相接的絕緣層21下方 ，是比P區域3的雜質濃度更高的p型半導體區域。另外 ，P++區域31係成形為暴露在第1表面F1。 P++區域32係形成在與P區域3相接的絕緣層23上方 ，是比P區域3的雜質濃度更高的p型半導體區域。另外 ，P++區域32係成形為暴露在第2表面F2。 N++區域41係形成在與N區域2及P++區域31相接 的絕緣層21下方，是比N區域2的雜質濃度更高的η型半 導體區域。另外，Ν++區域41係成形為暴露在第1表面F1 〇 Ν++區域42係形成在與Ν區域4及Ρ++區域32相接 的絕緣層23上方，是比Ν區域4的雜質濃度更高的η型半 導體區域。另外，Ν++區域42係成形為暴露在第2表面F2 〇 Ρ++區域（31、32)及Ν++區域（41、42)是使用例如 離子注入法等成形為暴露在第1表面F1或第二表面F2。 另外，Ρ++區域31或Ν++區域41係配置在Ν區域2 和Ρ區域3的接合部J2的接合面内、距電極11和Ν區域2 的接觸面較遠的距離。理想的配置位置，是從電極11與Ν 9/29 201143088 區域2的接觸面起距離最遠的位置或該位置附近。又，p++ 區域31與N++區域41的接合部j5中，接合部J5的接合面 係垂直於與電極11相接的第1表面π。 另外’ P++區域32或N++區域42係配置在N區域4 和P區域3的接合部J3的接合面内、距電極I]和N區域 4的接觸面較遠的距離。理想的配置位置，是從電極12與 N區域4的接觸面起距離最遠的位置或該位置附近。又， P++區域32與N++區域42的接合部J6中，接合部J6的接 合面係垂直於與電極12相接的第2表面打。 另外，接合部J5及J6中，接合部J5及J6的接合面積 越大，閘流體就能更容易的切換為〇N狀態。因此，接合 部J5及J6 #形狀最好依據閘流體的式樣進行調整，將接合 部J5及J6的接合面積適當設定為較大。 短路型閘流體100係在連接於電極u的端子T1和連 接於電極12的端T2之間施加偏壓’在端子T1的端子電 壓而於端*fT2的軒電壓的第丨情況下，作為qN狀態的 PNPNP喊體動作。在該p情況下，短路制流體⑽ 係等同於以PNPN的順序接合p區域！ u i區域）1區 域2 (第2區域)、P區域3 (第3區域)、N區域*… 區域）的閘流體。此處’以P++區域3H乍為第5區域，以 N++區域41作為第6區域。 另外，短路型閘流體1〇〇係在端子T2與端子T1之 施加偏壓，於端子T2的端子電壓高於端子T1的端子電^ 的第2情況下，作為0N狀態的pNpNp閘流體動作二 第2情況下，短路型閘流體1〇〇等同於以pNp 5" 合P區域5 (第i區域）、N區域4 (第 /員序接 Λ j P區域3 10/29 201143088 (第3區域）、N區域2 (第4區域）的閘流體。此處，以 P++區域32作為第5區域，以N++區域42作為第6區域。 親，短路型閘流體⑽即是所謂的雙向性2端子結構的 閘流體。 接下來對本實施形態的動作進行說明。 首先，對在圖1所示的短路型閘流體1〇〇中，於端子 T1與端子T2之間施加偏壓的上述第丨情況的動作進行說 明。 在圖1中，上述第1情況是對接合部J2和接合部J5 分別施加反方向電壓（反向偏壓）。接合部J2是N區域2 (第2區域）與P區域3 (第3區域）的接合部，接合部 J5是N++區域41 (第ό區域）與p++區域31 (第5區域） 的接合部。Ν++區域41的雜質濃度係高於Ν區域2的雜質 濃度。另外，Ρ++區域31的雜質濃度係高於ρ區域3的雜 質濃度。因此’接合部J5的接合崩潰電壓比接合部J2的接 合崩潰電壓低。因此，接合部j5比接合部J2先崩潰。其結 果是’電流集中流至Ν++區域41與ρ++區域31接合的部 分。如果此電流增大’由於Ν區域2中橫向的電阻，即從 電極11與Ν區域2的接觸面、通過ρ區域1的下方、到達 Ν++區域41之區域的電阻，在ρ區域1下方的ν區域2則 產生電壓下降。由於該電壓下降，ρ區域1與Ν區域2的 接合部J1變為正向偏壓，偏壓值在ρ++區域31變為最大。 此偏壓一超過接合部的擴散電位，即會引起電洞從ρ區 ' 域1注入，將端子T1與T2之間切換為ON狀態。 另外’短路型閘流體100中，將把端子T1與端子T2 間切換為ON狀態的電壓稱為觸發電壓。上述第1情況的 11/29 201143088 觸發電壓係與接合部j5崩潰的電壓相等。接合部j5崩潰的 ，壓係依據P++區域31的雜質濃度和N++區域4]的雜質 >辰度設定。即’上述第1情況的觸發電壓係依據P++ 3】的雜質漢度和N++區域41㈣雜質遭度設定。另外 體的特性之-—表示為了維持端子T1與端子Τ2之間的^ 狀悲的電流值之保持電流值—係依據至少包含Ν區域 雜f濃度的參數設定。另外，在決定保持電流值的參數中 ’曲运包含P區域1的雜質濃度和擴散深度、p區域 Ϊ度和擴散深度、Ρί1域1的_形狀等。N區域2的雜^ k度是決定保持電流值的參數之一。 雜貝 接下來，對在圖1所示的短路型間流體⑽中，於# $Γ。與端子T2之間施加偏壓的上述第2情況的動作進^ 在圖1巾’上料2情妓錢合部Τ3和接 分別施加反方向電壓（反向偏壓）。接 ^ ，區域)與卿(第3區域)的接合;= 把是㈣區域42(第6區域）與p++區域32 (第 的接合部。N++區域42的雜質濃度高於n f另外，P++區域32的雜質濃度高於P區域3=5 ，接合部J6的接合•電觀接合 潰電壓低。因此，接合部死比接合部乃先=:月 ，電流集中流至N绳域42與p++區域 果疋 流增大’由於Ν區域4的橫向電;= 與Ν區域4的接觸面起、通過 Ρ從電極12 域42之區域的電阻，在^ ®下降。由於此電厘下降，P區域戈4產生電 ，、以（he域4的接合部 12/29 201143088 J4變為正向偏壓，偏壓值在p++區域31變為最大。此偏壓 一超過接合部J4的擴散電位，即會引起電洞從p區域5注 入’將端子T1與T2之間切換為ON狀態。 另外，短路型閘流體100中，上述第2情況的觸發電 壓係與接合部J6崩潰的電壓相等。接合部J6崩潰的電壓係 依據P++區域32的雜質濃度和N++區域42的雜質濃度設 =。即，上述第2情況的觸發電壓係依據p++區域32的雜 質，度和N++區域42的雜質濃度設定。另外，表示為了維 寺而子T1與端子丁2之間的on狀態的電流值之保持電流 $ h依據至少包含N區域4的雜質濃度的參數設定。另 濃戶在决定保持電流值的參數中，還包含P區域5的雜質 < λΓ和擴散深度、p區域3的雜質濃度和擴散深度、p區域 21的圖安并彡& μ 木开ν狀夸。Ν區域4的雜質濃度是決定保持電流值的 翏數之—。 如上所述，本實施形態的短路型閘流體100係以ΡΝΡΝ 依序接人ρ 型門准〇區域1、Ν區域2、Ρ區域3、Ν區域4 ’且短路 另夕體100具有使Ρ區域1和Ν區域2短路的電極11。 ，紐路型閘流體1〇〇係以ρΝρΝ依序接合ρ區域5、ν 4短 。區域3、N區域2，且具有使P區域5和N區域 質的^極12。短路型閘流體100具有比P區域3的雜 G =更高的P++區域31 (或32)、比N區域2的雜質濃 N++區域41、以及比N區域4的雜質濃度更高的 壓，因此’如果在電極11和電極12之間施加偏 或ί>++7區域31與N++區域41的接合部J5比接合部J2 ( 私4山區域32與1^'1'區域42的接合部允比接合部J3)先 '、刀換為短路型閘流體100之ON狀態的觸發電 13/29 201143088 壓係依據P++區域31與N++區域41的接合崩潰電壓（或 P++區域32與N++區域42的接合崩潰電壓）決定。 此接合崩潰電壓係依據P++區域31與N++區域41的 雜質濃度（或P++區域32與N++區域42的雜質濃产）決 定。因此，此接合崩潰電壓可以不取決於有關保持^流特 性的N區域2 (或4)的雜質濃度而決定。例如，在進行觸 發電壓的低壓化時’通過提高N++區域（41、42)的雜質 濃度’可以降低P++區域31與N++區域41的接合崩潰電 壓（或P++區域32與N++區域42的接合崩潰電壓）。由此 ’短路型閘流體100可以進行觸發電壓的低壓化。 另外’由於觸發電壓的設定變容易，例如可設定符合 各種LED ( Light Emitting Diode)的順方向電壓之觸發電壓 。因此，短路型閘流體100可適用作為在LED的開啟故障 時的電流旁路元件。 這樣，本實施形態的短路型閘流體1〇〇中，決定觸發 電壓的參數是P++區域31 (或32)的雜質濃度和N++區域 41 (或42)的雜質濃度。另外’決定保持電流的參數之一 疋N區域2 (或4)的雜質濃度。因此，可以對觸發電壓和 保持電流進行單獨控制。這樣，短路型閘流體100就可以 在不影響保持電流特性的情況下，實現觸發電壓的低壓化 〇 第2實施形態 下面參照附圖，對本發明的第2實施形態的短路型閘 流體進行說明。 圖2是表示第2實施形態的短路型閘流體100a的戴面 結構圖。 14/29 201143088 在圖2中，短路型間流體驗具有 )、N區域（2、4)、通道截斷環（6〜9)、電極 、5 絕緣層（21〜24)、P++區域（31a、瓜）、以及叫區、 :42a)。在圖2中’對於與圖丨相同的結構標記相同的 P++區域31a係形成在與p區域3相接的絕缘 方，是比P區域3的雜質濃度更高的p型”體^域 外，阳區域3la係形成在p區域i下方的接合部了2部八 P++區域32a係形成在與p區域3相接的絕緣層μ上 方，是比P區域3 濃度更高的p鮮導體區域。另 外’ P++區域32a係形成在P區域5上方的接合部b部分 〇 N++區域42a成形為與N區域2及p++區域3U相接， 是比N區域2的雜質濃度更高的n型半導體區域。另外， N++區域41a係形成在p++區域31a上方部分。 N++區域41a成形為與n區域4及P++區域32a相接， 是比N區域4的雜質濃度更高的η型半導體區域。另外， Ν++區域42a係形成在ρ++區域32a下方部分。 P++區域（31a、32a)、及 N++區域（41a、42a)係通 過例如擴散法等嵌入半導體基板的内部形成。 另外，P++區域31a或N++區域41a係配置在N區域2 和P區域3的接合部J2的接合面内、距電極11和N區域2 的接觸面較遠的距離。理想的配置位置，是從電極11與N 區域2的接觸面起距離最遠的位置或該位置附近。另外， 關於p++區域31a與N++區域41a的接合部J5a’接合部J5a 15/29 201143088 的接合面平行於與電極11相接的第1表面F1。 另外，P++區域32a或N++區域42a係配置在]si區域4 和P區域3的接合部j3的接合面内、距電極12和N區域 4的接觸面較遠的距離。理想的配置位置，是從電極12與 N區域4的接觸面起距離最遠的位置或該位置附近。另外 P +區域32與N++區域42的接合部J6a中，接合部J6a 的接合面係平行於與電極12相接的第2表面F2。 〇短路型閘流體10如係在端子T1和端子T2之間施加偏 壓，於端子T1的端子電壓高於端子T2的端子電壓的第工 情況下，作為ON狀態的PNPNP閘流體動作。在該第！情 況下，短路型閘流體1〇〇a等同於以pNPN的順序接合p區 域1 (第1區域）、N區域2 (第2區域）、p區域3 (第3 區域）、N區域4 (第4區域）的閘流體等價。此處，以p++ 區域31a作為第5區域，以N++區域4U作為第6區域。 另外，短路型閘流體100a係在端子T2與端子T1之間 施加偏壓’於端子T2的端子高於端子T1的端子電壓 的第2情況下，作為〇N狀態的pNpNp閘流體動作。在此 第2情況下，短路型閘流體1〇〇a等同於以pNpN的順序接 合P區域5 (第1區域）、N區域4 (第2區域）、p區域3 (第3區域）、N區域2 (第4區域）的閘流體。又，此處 ，以P++區域32a作為第5區域，以N++區域42a作為第6 區域。這樣，短路型閘流體100a即是所謂的雙向性2端子 結構的閘流體。 接下來對本實施形態的動作進行說明。 圖2所示的短路型閘流體1〇〇a與短路型閑流體相 比，除了將P++區域（3】、32)和N++區域（4卜〇替 16/29 201143088 換為 P++區域（31a、32a) *N++區域（41a、42a)以外， 其它動作相同。 在圖2中，N++區域4la的雜質濃度高於N區域2的 雜質濃度。另外，P++區域31&的雜質濃度高於p區域3的 雜質激度。因此，接合部祝的接合崩潰電壓低於接合部 J2的接合崩潰電壓。在上述的第丨情況，N++區域4ι&(第 ^域）與P++區域31a (第5區域）的接合部…比接合 部J2先崩潰。之後的動作與短路型閘流體1〇〇的動作相同 〇 另外，在短路型閘流體1〇〇a中，上述第丨情況的觸發 電壓與接合部〗5a崩潰的電壓相等。接合部；5a崩潰的電壓 係依據P++區域31a的雜質濃度和N++區域41a的雜質濃 度設定。即’該上述第卜清況的觸發電壓係依據p++區域 31a的雜質濃度和N++區域41&的雜質濃度設定。另外，表 不為了維持端子T1與端子T2之間的〇N狀態的電流值之 保持電流值’係依據至少包含N區域2雜質濃度的參數 設定。另外，決絲持電流值的參數中，還包括p區域i 的雜質濃度和擴散深度、P g域3的雜質濃度和擴散深度、 P區域1的圖案形狀等。N區域2的雜質濃度是決定保持電 流值的參數之一。 曲另外，N++區域42a的雜質濃度高區域4的雜質 浪度。P++區域32a的雜質濃度高於p區域3的雜質濃度。 因此，接合部J6a的接合崩潰電壓比接合部J3的接合崩潰 黾壓低。因此，在上述第2情況下，N++區域42a (第ό區 域）與Ρ++區域32a (第5區域）的接合部J6a，比接合部 J3先崩潰。隨後的動作與短路型閘流體1〇〇相同。 17/29 201143088 另外，在短路型閘流體l〇〇a中，在上述第2情況的觸 發電壓，與接合部J6a崩潰的電壓相等。接合部J6a崩潰的 電壓係依據P++區域32a的雜質濃度和N++區域42a的雜 質濃度設定。即，上述第2情況的觸發電壓係依據p++區 域32a的雜質濃度和N++區域42a的雜質濃度設定。另外 ，表不為了維持端子T2與端子T1之間的0N狀態的電流 值之保持電流值，係依據至少包含N區域4的雜質濃度的 參數設定。另外，在決定保持電流值的參數中，還包含p 區域5的雜質濃度和擴散深度、p區域3的雜質濃度和擴散 深度、P區域5的圖案形狀等。N區域4的雜質濃度是決定 保持電流值的參數之一。 如上所述’本實施形態的短路型閘流體1〇〇a，具有比 P區域3的雜質濃度更高的P++區域31a(或32a)、比N區 域2的雜質濃度更高的N++區域41a、以及比N區域4的 雜質濃度更鬲的N++區域42a。因此，如果在電極11和電 極12之間施加偏壓，P++區域31a與N++區域41a的接合 部J5a比接合部J2(或P++區域32a與N++區域42a的接合 部J6a比接合部J3)先發生崩潰。切換為短路型閘流體i〇〇a 之ON狀態的觸發電壓係依據P++區域31 a與N++區域41 a 的接合崩潰電壓（或P++區域32a與N++區域42a的接合 崩潰電壓）決定。 此接合崩潰電壓係依據P++區域31a與N++區域41a 的雜質濃度（或P++區域32a與N++區域42a的雜質濃度 )決定。因而，此接合崩溃電壓可以不取決於保持電流特 性相關之N區域2 (或4)的雜質濃度而決定。 這樣’本實施形態的短路型閘流體l〇〇a就可期待有與 18/29 201143088 第1實施形態的短路型閘流體100同等的效果。 第3實施形態 下面參照附圖，說明依據本發明第3實施形態短路型 閘流體。 圖3為顯示第3實施形態的短路型閘流體l〇〇b的截面 結構圖。 在圖3中，短路型閘流體i〇〇b具有P區域（la、lb、 3)、N區域（2a、2b、4)、通道截斷環（6〜9)、電極（1 ia 、12a)、絕緣層（22a、22b、25)、P++區域 31b、以及 N++ 區域（41b、42b)。此圖中，對於與圖1相同的結構標記相 同的符號。 P區域la、lb是p型半導體區域，成形為暴露在第1 表面F1。 N區域2a是η型半導體區域，成形在P區域la與p 區域3之間。另外，N區域2a的一部分與第1表面F1相 接。 N區域2b是η型半導體區域，成形在P區域lb與p 區域3之間。另外，N區域2b的一部分與第1表面F1相 接。 N區域4是η型半導體區域，成形為暴露在第2表面 F2。 絕緣層22a設置成與第1表面F1相接，並面對第1表 面F1。絕緣層22a以從通道截斷環7的一部分覆蓋至N區 域2a的一部分的方式成形。另外，絕緣層22b設置成與第 1表面F1相接，並面對第1表面F卜絕緣層22b以從通道 截斷環6的一部分覆蓋至N區域2b的一部分的方式成形。 19/29 201143088 相接，並面對第1 部分覆蓋至P區域 另外，絕緣層25 s史置為與第i表面 表面F1。絕緣層25以從p區域la的一 lb的一部分的方式成形。 電極11a成H著第丨表面π與沒減蓋絕緣層μ 的P區域⑴、⑻的—部分和沒有覆蓋絕緣層（22a、22b )的N區域（2a、2b)的一部分相接。電極iu的材質為 金屬，例如1呂。電極Ua係在使P區域Ua、lb)和N區 域（2a、2b)短路的同時，與p區域（ia、ib^N (2a、2b)歐姆接觸。 一 另外，電極123成形為沿著第2表面F2與N區域4和 通道麟環（8、9)趣1極仏叫質為金屬，例如 鋁。電極12a與N區域4歐姆接觸。 =+.區域31b (场成在與p區域3相接的絕緣層υ下 方疋比P區或3的4漠度更高的p型半導體區域。另 外’P++區域3lb係成形為暴露在第】表面打。 N++區域41b 成在與N區域2a及區域训相 接的絕緣詹25下方，是比N區域2a的雜f濃度更高的n 型半導體d域。另外’ Ν++區域41b係成形絲露在第i 表面F1。 N++區域42b係形成在與n區域2b及P++區域31b相 接的絕緣層25下方，是比n區域2b的雜質濃度更高的n 型半導體區域。另外，N++區域42b係成形為暴露在第1 表面F1。 P++區域31b及N++區域（41b、42b)是使用例如離子 注入法等，成形為暴露在第1表面F1。 另外，N++區域41b係配置在N區域2a和P區域3的 20/29 201143088 接合部J2a的接合面内、距電極以和n區域2a的接觸面 較遠的距離。理想的配置位置，是從電極lla與N區域2a 的接觸面起距離最遠的位置或該位置附近。另外，P++區域 31b與N++區域41b的接合部J7a中，接合部J7a的接合面 係垂直於與電極11a相接的第1表面F1。 另外’ N++區域42b係配置在n區域2b和P區域3的 接合部J2b的接合面内、距電極11&和N區域2b的接觸面 較遠的距離。理想的配置位置，是從電極14與N區域2b 的接觸面起距離最遠的位置或該位置附近。另外，p++區域 31b與N++區域42b的接合部j7b中，接合部j7b的接合面 係垂直於與電極11a相接的第1表面F1。 短路型閘流體l〇〇b係在連接於電極ua的端子τι和 連接於電極12a的端子T2之間施加偏壓，在端子T1的端 子電壓高於端子T2的端子電壓的第丨情況下，作為〇N狀 恶的PNPNP閘流體動作。在該第〗情況下，短路型閘流體 l〇〇b等同於以PNPN的順序接合p區域la(第i區域）、N 區域2a (第2區域）、P區域3 (第3區域）、N區域4 (第 4區域）及P區域lb (第1區域）、N區域2b (第2區域） 、P區域3 (第3區域）、N區域4 (第4區域）的閘流體。 此處’以P++區域31b作為第5區域，以N++區域（4ib、 42b)作為第6區域。 另外，在短路型閘流體l〇〇b於端子T2與端子T1之間 施加偏壓、端子T2的端子電壓高於端子τι的端子電壓的 第2情況下為反向偏壓，故不導電。 這樣的短路型閘流體100b即所謂的單向性2端子結構 的閘流體。 21/29 201143088 接下來對本實施形態的動作進行說明。 圖3所示的短路型閘流體l〇〇b，除下诚201143088 VI. Description of the Invention: [Technical Field] The present invention relates to a short-circuit type thyristor 0 [Prior Art] A PNPN gate fluid has been shown to have a lower breakdown voltage than other parts. The area is provided at the joint portion, thereby reducing the breakdown voltage that is switched to the ON state, that is, the short-circuit type thyristor (for example, refer to Patent Documents 1 to 4). In the conventional short-circuit type thyristor shown in Fig. 4, when a bias voltage is applied from the terminal τ to the terminal T2, the junction portion J2 is applied with a reverse voltage. Therefore, the high-concentration impurity layer p+10 region which is lower than the junction breakdown voltage of the junction portion J2 will first collapse. As a result, current concentrates to this P++ region. If this current increases, a voltage drop occurs in the N1 region just below the Pi region due to the lateral resistance. As the voltage drops, the junction is forward biased and the bias value is maximized in the P++ region. When the bias voltage exceeds the diffusion potential of the junction portion, the hole is injected from the P1 region, and the terminal τ1 and the terminal T2 are switched to the ON state. As described above, the trigger voltage that is switched to the (10) state in the conventional short-circuit type thyristor shown in Fig. 4 is determined based on the junction collapse voltage of the P++ region and the N1 region. CITATION LIST PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PRIOR ART Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. 35 No. 35 Patent Publication No. 3 Japanese Patent Publication No. H3_233973 In the conventional short-circuit type thyristor shown in FIG. 4, the trigger voltage for switching the ON state is determined based on the impurity concentration of the P++ region and the m region in contact therewith. In the case of a short-circuit type fluid that achieves a very low trigger voltage, it is necessary to change the impurity concentration of the Ρ++ region and the N1 region. However, when the impurity concentration in the N1 region is changed, the characteristics of the holding current of the thyristor are affected. Therefore, by changing the impurity concentration of the N1 region, it is difficult to reduce the trigger voltage while maintaining the holding current characteristics. As described above, in the conventional short-circuit type thyristor shown in Fig. 4, it is extremely difficult to achieve a low-voltage triggering switch to the 〇N state without affecting the holding current characteristics. Therefore, it is an object of the present invention to provide a short-circuit type thyristor that reduces the voltage of a trigger circuit that is switched to an ON state without affecting the holding current characteristics. In order to solve the above problems, the short-circuiting thyristor of the present invention sequentially joins the first region of the second conductivity type, the second region of the second conductivity type, the third region of the first conductivity type, and the second portion. The fourth region of the conductive type is provided with an electrode that short-circuits the first region and the second region, and has the first portion that is formed in contact with the third region and has a higher impurity concentration than the third region. a fifth region of the conductivity type, and a sixth region of the second conductivity type formed to be in contact with the second region and the fifth region and having a higher impurity concentration than the second region; and the trigger voltage value is based on The impurity concentration of the fifth region and the impurity concentration of the sixth region are set, and the holding current value is set according to a parameter including at least the impurity concentration of the second region. The present invention is characterized in that, in the above invention, The fifth or the fifth region is formed in the second and second regions of the electrode and the second region: the region and the sag: the fifth conductor substrate of the invention. - σ - a half which is in direct contact with the above-mentioned 1: pole. Further, the present invention is characterized in that the joint surface of the region and the sixth region is flat sand = the surface of the fifth conductor substrate. The invention of the present invention is characterized in that, in the above-mentioned hair-emitting region and the sixth region, the surface of the semiconductor substrate that is in contact with the electrode 5 is used. In the third region of the electrode effect m2 n described above, the fourth region of the second conductivity type is sequentially joined, and the electrode having the region short-circuited with the second region is provided. The body is formed to be in contact with the third region. a fifth region of the first conductivity type that is more than % of the third region _ = Han degrees, and a second region and the fifth region are formed to be in contact with the second region and the curvature. In the sixth region of the second conductivity type, in the short-circuit type thyristor, when a bias voltage is applied between the i-th region and the fourth region, the impurity concentration in the fifth region and the impurity concentration in the sixth region are higher. The joint surface of the high region 5 and the sixth region collapses first than the joint surface of the third region and the third region. Therefore, the trigger voltage of the 0N state of the short-circuit type helium fluid is switched to 6/29 201143088. The junction breakdown voltage is determined. This 吏μ interface is based on the 5th zone. The miscellaneous, 疋 here, this is a parameter that maintains the current characteristic voltage is that the fifth region has a short-circuit axis current that determines the triggering electric power. Thereby, the present invention realizes that the touch =:= does not affect the holding current characteristic. [Embodiment] The first embodiment of the short-circuit type embodiment according to the first embodiment of the present invention will be described below with reference to the gate body of the drawing. Fig. 1 shows the short-circuit type thyristor 100 of the first embodiment. The structure of the wearing surface. In Fig. 1, the short-circuit type thyristor 100 has a meandering region (1, 3, 5), a Ν region (2, 4), a channel stopper (6 to 9), and an electrode ( 11, 12), insulating layer (21 to 24), p++ region (3b%), and N++ region (41, 42). P region 3 is a p-type semiconductor region of the first conductivity type, and is a New Zealand type. The semiconductor substrate of the main layer of the fluid-cut layer is formed. Here, the upper surface of the semiconductor substrate is referred to as a second surface F1, and the lower surface of the semiconductor substrate is referred to as a second surface F2. The N region 2 is a second conductivity type. Η-type semiconductor region. N region 7/29 201143088 Domain 2 is formed in P region 1 and P region A portion of the first surface F1 is connected to the first surface F1. The P region 1 is a p-type semiconductor region, and is formed to be exposed on the first surface F. The N region 4 is an n-type semiconductor region. The N region 4 is formed in the P region 3 and A portion of the meandering region 5 is in contact with the second surface F2. The meandering region 5 is a p-type semiconductor region and is formed to be exposed on the second surface F2. The channel cut ring (6 to 9) is formed into the first surface F1 or the first surface. 2 The surface F2 is in contact with the side surface of the short-circuiting thyristor 100, and is a Ρ-type semiconductor region which is more south than the impurity concentration of the Ρ region 3. The channel cut-off is bad (6 to 9) suppressing the function of the short-circuit thyristor 100. Undesired leakage current (channel current). The insulating layer 21 is provided in contact with the first surface F1 and faces the first surface F1. The insulating layer 21 is shaped to cover a portion of the meandering region 6 from a portion of the channel intercepting ring 6. The insulating layer 22 is provided in contact with the first surface F1 and faces the first surface F1. The insulating layer 22 is shaped to cover a portion of the meandering region 2 from a portion of the channel interrupting ring 7. Further, the insulating layer 23 is provided in contact with the second surface F2 and faces the second surface F2. The insulating layer 23 is shaped to cover a portion of the meandering region 5 from a portion of the channel wear ring 9. The insulating layer 24 is disposed in contact with the second surface F2 and faces the second surface F2. The insulating layer 24 is shaped to cover a portion of the meandering region 4 from a portion of the channel shutoff ring 8. The electrode 11 is formed to be in contact with a portion of the meandering region 1 not covering the insulating layer 21 and a portion of the meandering region 2 not covering the insulating layer 22 along the first surface F1. The material of the electrode 11 is metal, for example. The electrode 11 is short-circuited with the P region 1 and the N region 2 at 8/29 201143088, and is in ohmic contact with the P region 1 and the N region 2. Further, the electrode 12 is formed to be in contact with a portion of the P region 5 not covering the insulating layer 23 and a portion of the N region 4 not covering the insulating layer 24 along the second surface F2. The material of the electrode 12 is metal, such as Ming. The electrode 12 shorts the P region 5 and the N region 4 while being in ohmic contact with the P region 5 and the N region 4. The P++ region 31 is formed under the insulating layer 21 that is in contact with the P region 3, and is a p-type semiconductor region having a higher impurity concentration than the P region 3. Further, the P++ region 31 is formed to be exposed on the first surface F1. The P++ region 32 is formed over the insulating layer 23 that is in contact with the P region 3, and is a p-type semiconductor region having a higher impurity concentration than the P region 3. Further, the P++ region 32 is shaped to be exposed on the second surface F2. The N++ region 41 is formed under the insulating layer 21 in contact with the N region 2 and the P++ region 31, and is an n-type semiconductor region having a higher impurity concentration than the N region 2. Further, the Ν++ region 41 is formed so as to be exposed on the first surface F1. The 〇Ν++ region 42 is formed over the insulating layer 23 which is in contact with the Ν region 4 and the Ρ++ region 32, and is an impurity of the Ν region 4 A higher concentration of n-type semiconductor regions. Further, the Ν++ region 42 is formed so as to be exposed on the second surface F2 〇Ρ ++ region (31, 32) and the Ν ++ region (41, 42) is formed by exposure to the first surface by, for example, ion implantation. F1 or second surface F2. Further, the Ρ++ region 31 or the Ν++ region 41 is disposed at a distance from the contact surface of the joint portion J2 of the Ν region 2 and the Ρ region 3, and a distance from the contact surface of the electrode 11 and the Ν region 2. The ideal arrangement position is the position farthest from the contact surface of the electrode 11 and the region 2 of the 430 9/29 201143088 or the vicinity of the position. Further, in the joint portion j5 of the p++ region 31 and the N++ region 41, the joint surface of the joint portion J5 is perpendicular to the first surface π which is in contact with the electrode 11. Further, the 'P++ region 32 or the N++ region 42 is disposed at a distance far from the contact surface of the electrode I] and the N region 4 in the joint surface of the joint portion J3 of the N region 4 and the P region 3. The ideal arrangement position is the position farthest from the contact surface of the electrode 12 and the N region 4 or the vicinity of the position. Further, in the joint portion J6 of the P++ region 32 and the N++ region 42, the joint surface of the joint portion J6 is perpendicular to the second surface that is in contact with the electrode 12. Further, in the joint portions J5 and J6, the larger the joint area of the joint portions J5 and J6, the easier the sluice fluid can be switched to the 〇N state. Therefore, it is preferable that the joint portions J5 and J6 # are adjusted in accordance with the pattern of the thyristor, and the joint areas of the joint portions J5 and J6 are appropriately set to be large. The short-circuit type thyristor 100 is a qN in which a bias voltage 'terminal voltage at the terminal T1 is applied between the terminal T1 connected to the electrode u and the terminal T2 connected to the electrode 12 at the terminal voltage of the terminal *fT2. The state of the PNPNP shouts action. In the case of p, the short circuit fluid (10) is equivalent to joining the p region in the order of PNPN! u i area) Gate fluid of Zone 1 (2nd zone), P Zone 3 (3rd zone), N zone*... zone). Here, the P++ region 3H乍 is the fifth region, and the N++ region 41 is the sixth region. Further, the short-circuit type thyristor 1 is applied with a bias voltage between the terminal T2 and the terminal T1, and when the terminal voltage of the terminal T2 is higher than the terminal voltage of the terminal T1, the pNpNp thyristor acts as the 0N state. In the second case, the short-circuit type thyristor 1〇〇 is equivalent to pNp 5" P region 5 (i-th region), N region 4 (the first member is connected to j P region 3 10/29 201143088 (third region) The thyristor of the N region 2 (the fourth region). Here, the P++ region 32 is the fifth region, and the N++ region 42 is the sixth region. The pro-short-type thyristor (10) is a so-called bidirectional 2-terminal. Next, the operation of the present embodiment will be described. First, in the case of the above-described second case in which the bias voltage is applied between the terminal T1 and the terminal T2 in the short-circuit type thyristor 1A shown in FIG. In the first case, in FIG. 1, the opposite direction voltage (reverse bias) is applied to the junction portion J2 and the junction portion J5. The junction portion J2 is the N region 2 (the second region) and the P region 3 The joint portion (the third region), the joint portion J5 is the N++ region 41 (the third region) and the p++ region 31 ( The junction area of the 区域++ region 41 is higher than the impurity concentration of the Ν region 2. Further, the impurity concentration of the Ρ++ region 31 is higher than the impurity concentration of the ρ region 3. Therefore, the junction J5 The joint collapse voltage is lower than the joint collapse voltage of the joint portion J2. Therefore, the joint portion j5 collapses earlier than the joint portion J2. As a result, the current concentrate flows to the portion where the Ν++ region 41 is joined to the ρ++ region 31. This current increases 'because of the lateral resistance in the Ν region 2, that is, the contact surface from the contact surface of the electrode 11 and the Ν region 2, the region below the ρ region 1, and the region reaching the Ν++ region 41, below the ρ region 1 A voltage drop occurs in the ν region 2. As the voltage drops, the junction J1 of the ρ region 1 and the Ν region 2 becomes forward biased, and the bias value becomes maximum at the ρ++ region 31. This bias exceeds the junction The diffusion potential of the part causes the hole to be injected from the ρ-region 'field 1 and switches the terminal T1 and T2 to the ON state. In the short-circuit type thyristor 100, the terminal T1 and the terminal T2 are switched to ON. The voltage of the state is called the trigger voltage. 11/29 201143088 of the above first case The voltage system is equal to the voltage at which the junction portion j5 collapses. When the junction portion j5 collapses, the pressure is set according to the impurity concentration of the P++ region 31 and the impurity of the N++ region 4]. That is, the trigger voltage of the first case is based on The impurity degree of P++ 3] and the N++ region 41 (4) impurity are set. The characteristic of the body - indicates the value of the holding current for maintaining the current value between the terminal T1 and the terminal Τ 2 - based on at least Ν Parameter setting of regional impurity f concentration. Further, in the parameter for determining the value of the holding current, the sigma includes the impurity concentration and the diffusion depth of the P region 1, the p region enthalpy and the diffusion depth, the _ shape of the Ρί1 domain 1, and the like. The k-degree of the N region 2 is one of the parameters determining the holding current value. Miscellaneous Next, in the short-circuit type inter-body fluid (10) shown in Fig. 1, it is ##Γ. In the second case of applying a bias voltage to the terminal T2, the reverse direction voltage (reverse bias) is applied to the splicing unit 3 and the splicing unit. Engagement of ^, region) with qing (third region); = (4) region 42 (6th region) and p++ region 32 (first joint. The impurity concentration of N++ region 42 is higher than nf, P++ region 32 The impurity concentration is higher than that of the P region 3=5, and the junction and the junctional breakdown voltage of the junction J6 are low. Therefore, the joint portion is dead before the junction is first:: month, the current is concentrated to the N-rope field 42 and the p++ region. The turbulence increases 'because of the lateral electrical power of the crucible region 4; = the resistance from the contact surface of the crucible region 4, through the region of the crucible from the region 12 of the electrode 12, decreases in ^^. Since this electrocution decreases, the P region is 4 When the electric power is generated, the junction portion 12/29 201143088 J4 of the he domain 4 becomes forward biased, and the bias value becomes maximum in the p++ region 31. When the bias voltage exceeds the diffusion potential of the junction portion J4, it causes The hole is injected from the p region 5 to switch the terminal T1 and T2 to the ON state. In the short-circuiting thyristor 100, the trigger voltage of the second case is equal to the voltage at which the junction J6 collapses. The junction J6 collapses. The voltage is set according to the impurity concentration of the P++ region 32 and the impurity concentration of the N++ region 42. That is, in the second case described above The voltage is set according to the impurity degree of the p++ region 32 and the impurity concentration of the N++ region 42. In addition, the holding current $h indicating the current value of the on state between the sub-T1 and the terminal D2 is at least N. The parameter setting of the impurity concentration of the region 4 is also included in the parameter determining the holding current value, and the impurity of the P region 5 < λ Γ and the diffusion depth, the impurity concentration of the p region 3 and the diffusion depth, and the map of the p region 21 The concentration of the impurity in the region 4 is determined by the number of turns of the holding current value. As described above, the short-circuiting thyristor 100 of the present embodiment is sequentially connected by ΡΝΡΝ. The door type quasi-〇 area 1, the Ν area 2, the Ρ area 3, the Ν area 4', and the short-circuited body 100 has an electrode 11 that short-circuits the Ρ area 1 and the Ν area 2. The New Zealand-type thyristor 1 ρΝρΝ sequentially joins the ρ region 5, ν 4 is short. The region 3, the N region 2, and has the polarity of the P region 5 and the N region 12. The short-circuit thyristor 100 has a higher impurity than the P region 3 = G = P++ region 31 (or 32), impurity N+ region 41 of N region 2, and N region 4 a higher concentration of impurities, so 'if a bias or ί> between the electrode 11 and the electrode 12 is applied, the junction portion J3 of the region 31 and the N++ region 41 is larger than the junction portion J2 (private 4 mountain regions 32 and 1^' The junction portion of the 1' region 42 allows the junction portion J3) to be 'first', the knife is switched to the trigger state of the ON state of the short-circuiting thyristor 100 13/29 201143088 The pressure system is based on the junction breakdown voltage of the P++ region 31 and the N++ region 41 (or The junction breakdown voltage of the P++ region 32 and the N++ region 42 is determined. This junction collapse voltage is determined by the impurity concentration of the P++ region 31 and the N++ region 41 (or the impurity concentration of the P++ region 32 and the N++ region 42). Therefore, this junction collapse voltage can be determined without depending on the impurity concentration of the N region 2 (or 4) relating to the retention characteristics. For example, the junction breakdown voltage of the P++ region 31 and the N++ region 41 (or the junction breakdown voltage of the P++ region 32 and the N++ region 42 can be lowered by increasing the impurity concentration of the N++ region (41, 42) when performing the low voltage of the trigger voltage. ). Thus, the short-circuit type thyristor 100 can reduce the voltage of the trigger voltage. Further, since the setting of the trigger voltage is easy, for example, a trigger voltage in accordance with the forward voltage of various LEDs (Light Emitting Diodes) can be set. Therefore, the short-circuit type thyristor 100 can be applied as a current bypass element when the LED is turned on. As described above, in the short-circuit type thyristor 1 of the present embodiment, the parameter for determining the trigger voltage is the impurity concentration of the P++ region 31 (or 32) and the impurity concentration of the N++ region 41 (or 42). In addition, the impurity concentration of one of the parameters determining the holding current 疋N region 2 (or 4). Therefore, the trigger voltage and the holding current can be individually controlled. In this way, the short-circuiting sluice fluid 100 can reduce the voltage of the trigger voltage without affecting the holding current characteristics. 〇 Second Embodiment Hereinafter, a short-circuiting thyristor according to a second embodiment of the present invention will be described with reference to the drawings. Fig. 2 is a view showing the wearing structure of the short-circuiting sluice fluid 100a of the second embodiment. 14/29 201143088 In Figure 2, the short-circuit type inter-flow experience has), N area (2, 4), channel cut-off ring (6~9), electrode, 5 insulation layer (21~24), P++ area (31a, Melon), and called the district, : 42a). In Fig. 2, 'the P++ region 31a having the same structure mark as that of the figure 形成 is formed on the insulating side which is in contact with the p-region 3, and is a p-type body region which is higher than the impurity concentration of the P region 3, and is yang. The region 3a is formed at a joint portion below the p region i. The two P++ regions 32a are formed over the insulating layer μ that is in contact with the p region 3, and is a p-fresh conductor region having a higher concentration than the P region 3. The P++ region 32a is formed in the junction portion b portion above the P region 5, and the N++ region 42a is formed to be in contact with the N region 2 and the p++ region 3U, and is an n-type semiconductor region having a higher impurity concentration than the N region 2. The N++ region 41a is formed in a portion above the p++ region 31a. The N++ region 41a is formed to be in contact with the n region 4 and the P++ region 32a, and is an n-type semiconductor region having a higher impurity concentration than the N region 4. In addition, the Ν++ region 42a is formed in a portion below the ρ++ region 32a. The P++ regions (31a, 32a) and the N++ regions (41a, 42a) are formed by being embedded in the inside of the semiconductor substrate by, for example, a diffusion method. Further, the P++ region 31a or the N++ region 41a Arranged in the joint surface of the joint portion J2 of the N region 2 and the P region 3 The distance from the contact surface of the electrode 11 and the N region 2. The ideal arrangement position is the position farthest from the contact surface of the electrode 11 and the N region 2 or the vicinity of the position. In addition, regarding the p++ region 31a and N++ The joint surface of the joint portion J5a' of the joint portion J5a 15/29 201143088 is parallel to the first surface F1 that is in contact with the electrode 11. In addition, the P++ region 32a or the N++ region 42a is disposed in the ]si region 4 and the P region 3 The distance between the bonding surface of the joint portion j3 and the contact surface of the electrode 12 and the N region 4. The ideal arrangement position is the position farthest from the contact surface of the electrode 12 and the N region 4 or near the position. Further, in the joint portion J6a of the P + region 32 and the N++ region 42, the joint surface of the joint portion J6a is parallel to the second surface F2 that is in contact with the electrode 12. The short-circuit type thyristor 10 is attached to the terminal T1 and the terminal T2. When a bias voltage is applied between them and the terminal voltage of the terminal T1 is higher than the terminal voltage of the terminal T2, the PNPNP thyristor operating in the ON state operates. In this case, the short-circuiting thyristor 1〇〇a is equivalent. P region 1 (first region) and N region are joined in the order of pNPN The thyristor of the domain 2 (the second region), the p region 3 (the third region), and the N region 4 (the fourth region) is equivalent. Here, the p++ region 31a is the fifth region, and the N++ region 4U is the sixth region. In addition, the short-circuit type thyristor 100a operates as a pNpNp thyristor in a 〇N state in a second case where a bias voltage is applied between the terminal T2 and the terminal T1 and the terminal of the terminal T2 is higher than the terminal voltage of the terminal T1. In the second case, the short-circuiting thyristor 1〇〇a is equivalent to the P region 5 (first region), the N region 4 (second region), the p region 3 (third region), and N in the order of pNpN. The thyristor of zone 2 (fourth zone). Here, the P++ region 32a is referred to as the fifth region, and the N++ region 42a is referred to as the sixth region. Thus, the short-circuit type thyristor 100a is a so-called bidirectional 2-terminal structure thyristor. Next, the operation of this embodiment will be described. The short-circuit type thyristor 1〇〇a shown in Fig. 2 is compared with the short-circuit type idle fluid except that the P++ region (3), 32) and the N++ region (4 〇 〇 16/29 201143088 are replaced by the P++ region (31a, 32a) Other than the *N++ region (41a, 42a), the other operations are the same. In Fig. 2, the impurity concentration of the N++ region 4la is higher than the impurity concentration of the N region 2. In addition, the impurity concentration of the P++ region 31& is higher than that of the p region 3 Therefore, the joint collapse voltage of the joint portion is lower than the joint collapse voltage of the joint portion J2. In the above-described case, the N++ region 4ι & (the ^ domain) and the P++ region 31a (the fifth region) The joint portion ... collapses before the joint portion J2. The subsequent operation is the same as the operation of the short-circuit type thyristor 1A. In addition, in the short-circuit type thyristor 1a, the trigger voltage and the joint portion 5a of the above-described second case The voltage of the collapse is equal. The voltage at which the junction 5a collapses is set according to the impurity concentration of the P++ region 31a and the impurity concentration of the N++ region 41a. That is, the trigger voltage of the above-mentioned second condition is based on the impurity concentration of the p++ region 31a and N++. The impurity concentration of the region 41 & The holding current value 'in order to maintain the current value of the 〇N state between the terminal T1 and the terminal T2' is set according to a parameter including at least the impurity concentration of the N region 2. In addition, the parameters of the holding current value of the wire include The impurity concentration and diffusion depth of the p region i, the impurity concentration and diffusion depth of the P g domain 3, the pattern shape of the P region 1, etc. The impurity concentration of the N region 2 is one of the parameters determining the holding current value. The impurity concentration of the impurity concentration region 42 of 42a is high. The impurity concentration of the P++ region 32a is higher than the impurity concentration of the p region 3. Therefore, the junction collapse voltage of the junction portion J6a is lower than the junction collapse pressure of the junction portion J3. In the second case, the joint portion J6a of the N++ region 42a (the second region) and the Ρ++ region 32a (the fifth region) collapses earlier than the joint portion J3. The subsequent operation is the same as that of the short-circuit type thyristor. /29 201143088 Further, in the short-circuit type thyristor l〇〇a, the trigger voltage in the second case is equal to the voltage at which the junction J6a collapses. The voltage at which the junction J6a collapses is based on the impurity concentration of the P++ region 32a and N++. Area The impurity concentration of the region 42a is set. That is, the trigger voltage of the second case is set according to the impurity concentration of the p++ region 32a and the impurity concentration of the N++ region 42a. In addition, it is indicated that the ON state between the terminal T2 and the terminal T1 is maintained. The holding current value of the current value is set according to a parameter including at least the impurity concentration of the N region 4. In addition, the parameter determining the holding current value includes the impurity concentration and the diffusion depth of the p region 5, and the impurity concentration of the p region 3. And the depth of diffusion, the pattern shape of the P region 5, and the like. The impurity concentration of the N region 4 is one of the parameters determining the holding current value. As described above, the short-circuit type thyristor 1a of the present embodiment has a P++ region 31a (or 32a) having a higher impurity concentration than the P region 3, and an N++ region 41a having a higher impurity concentration than the N region 2. And an N++ region 42a which is more ambiguous than the impurity concentration of the N region 4. Therefore, if a bias is applied between the electrode 11 and the electrode 12, the joint portion J5a of the P++ region 31a and the N++ region 41a occurs earlier than the joint portion J2 (or the joint portion J6a of the P++ region 32a and the N++ region 42a is larger than the joint portion J3) collapse. The trigger voltage for switching to the ON state of the short-circuit type thyristor i〇〇a is determined in accordance with the junction collapse voltage of the P++ region 31a and the N++ region 41a (or the junction breakdown voltage of the P++ region 32a and the N++ region 42a). This junction collapse voltage is determined based on the impurity concentration of the P++ region 31a and the N++ region 41a (or the impurity concentration of the P++ region 32a and the N++ region 42a). Therefore, the junction collapse voltage can be determined not depending on the impurity concentration of the N region 2 (or 4) in which the current characteristics are related. Thus, the short-circuit type thyristor l〇〇a of the present embodiment can be expected to have the same effect as the short-circuit type thyristor 100 of the first embodiment of 18/29 201143088. (THIRD EMBODIMENT) A short-circuiting thyristor according to a third embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 3 is a cross-sectional structural view showing a short-circuit type thyristor 100b according to the third embodiment. In FIG. 3, the short-circuit type thyristor i〇〇b has a P region (la, lb, 3), an N region (2a, 2b, 4), a channel cutoff ring (6 to 9), and an electrode (1 ia , 12a). Insulation layer (22a, 22b, 25), P++ region 31b, and N++ region (41b, 42b). In this figure, the same reference numerals are given to the same structures as those in Fig. 1. The P regions la and lb are p-type semiconductor regions, and are formed to be exposed on the first surface F1. The N region 2a is an n-type semiconductor region formed between the P region la and the p region 3. Further, a part of the N region 2a is in contact with the first surface F1. The N region 2b is an n-type semiconductor region formed between the P region lb and the p region 3. Further, a part of the N region 2b is in contact with the first surface F1. The N region 4 is an n-type semiconductor region and is formed to be exposed on the second surface F2. The insulating layer 22a is disposed in contact with the first surface F1 and faces the first surface F1. The insulating layer 22a is formed in such a manner as to cover a part of the N-zone 2a from a part of the channel cut ring 7. Further, the insulating layer 22b is provided in contact with the first surface F1 and faces the first surface F. The insulating layer 22b is formed so as to cover a part of the N-zone 2b from a part of the channel-cut ring 6. 19/29 201143088 meets and faces the first part to cover the P area. In addition, the insulating layer 25 s is set to be the surface of the i-th surface F1. The insulating layer 25 is formed in such a manner as to be a part of one lb of the p region la. The electrode 11a is in contact with a portion of the P region (1), (8) where the second surface π is not covered with the insulating layer μ, and a portion (2a, 2b) of the N region (2a, 2b) which is not covered with the insulating layer (22a, 22b). The material of the electrode iu is metal, for example, 1 Lu. The electrode Ua is in ohmic contact with the p region (ia, ib^N (2a, 2b) while short-circuiting the P region Ua, lb) and the N region (2a, 2b). Further, the electrode 123 is formed along the first 2 Surface F2 and N region 4 and channel ring (8, 9) are very metallic, such as aluminum. Electrode 12a is in ohmic contact with N region. = +. Region 31b (field formation and p region 3 The p-type semiconductor region under the insulating layer 疋 is higher than the P region or 3, and the 'P++ region 3lb is formed to be exposed on the surface. The N++ region 41b is in the N region 2a and Below the insulating junction of the regional training, the n-type semiconductor d-domain is higher than the impurity concentration of the N region 2a. In addition, the 'Ν++ region 41b is formed on the i-th surface F1. The N++ region 42b is formed. Below the insulating layer 25 that is in contact with the n region 2b and the P++ region 31b, is an n-type semiconductor region having a higher impurity concentration than the n region 2b. Further, the N++ region 42b is formed to be exposed on the first surface F1. The 31b and N++ regions (41b, 42b) are formed to be exposed on the first surface F1 by, for example, ion implantation or the like. Further, the N++ region 41b is disposed in the N region 2 20/29 201143088 of a and P region 3 is a distance far from the contact surface of the electrode with the n region 2a in the joint surface of the joint portion J2a. The ideal arrangement position is from the contact surface of the electrode 11a and the N region 2a. In the joint portion J7a of the P++ region 31b and the N++ region 41b, the joint surface of the joint portion J7a is perpendicular to the first surface F1 that is in contact with the electrode 11a. In addition, the 'N++ region 42b It is disposed at a distance from the contact surface of the electrode 11& and the N region 2b in the joint surface of the joint portion J2b of the n region 2b and the P region 3. The ideal arrangement position is the contact between the electrode 14 and the N region 2b. In the joint portion j7b of the p++ region 31b and the N++ region 42b, the joint surface of the joint portion j7b is perpendicular to the first surface F1 that is in contact with the electrode 11a. The fluid l〇〇b applies a bias voltage between the terminal τ1 connected to the electrode ua and the terminal T2 connected to the electrode 12a, and when the terminal voltage of the terminal T1 is higher than the terminal voltage of the terminal T2, the 〇〇N is used as the 〇N The action of the PNPNP thyristor fluid The short-circuit type thyristor l〇〇b is equivalent to the p-region la (i-th region), N-region 2a (second region), P-region 3 (third region), and N region 4 (fourth region) in the order of PNPN. ) and the thyristor of the P zone lb (first zone), the N zone 2b (second zone), the P zone 3 (third zone), and the N zone 4 (fourth zone). Here, the P++ region 31b is referred to as a fifth region, and the N++ region (4ib, 42b) is referred to as a sixth region. Further, in the second case where the short-circuit type thyristor 100b is biased between the terminal T2 and the terminal T1 and the terminal voltage of the terminal T2 is higher than the terminal voltage of the terminal τ1, it is reverse biased, so that it is not electrically conductive. Such a short-circuit type thyristor 100b is a so-called unidirectional 2-terminal structure thyristor. 21/29 201143088 Next, the operation of this embodiment will be described. The short-circuit type thyristor l〇〇b shown in Figure 3, in addition to the down
戍點以々卜， 所示的短路型閘流體100進行相同的動作。 '、 (1)短路型閘流體l〇〇b是單向性 端子結構的閘流 分別將短路型閘流體 lb)、N區域2替換為 (2)在短路型閘流體100b中， 100的P區域1替換為P區域（la、 N 區域（2a、2b)。 (3)在短路型閘流體100b巾’短路型閘流體議的 P++區域（31、32)和N++區域（41、42)被替換為 區域 31b 和 N++區域（41b、42b)。 、 在圖3中，N++區域41b的雜質濃度高區域^的 雜質濃度，Ν++區域42b的雜質濃度高區域2b的雜質 濃度。另外’P++區域31b的雜質濃度高於p區域3的雜質 濃度。因此，N++區域41b與P++區域31b的接合部J7a的 接合崩潰電壓低於N區域2a與P區域3的接合部J2a的接 合崩潰電壓。另外，N++區域42b與p++區域31b的接合部 J7b的接合崩潰電壓低於n區域2b與p區域3的接合部J2b 的接合崩潰電壓。在端子T1與端子T2之間施加偏壓的上 述第1情況下’ N++區域41b及42b (第6區域）與p++區 域31b (第5區域）的接合部J7a及J7b，比接合部J2a及 J2b先崩潰。隨後的動作與短路型閘流體1〇〇相同。 另外’在短路型閘流體100b中，上述第1情況的觸發 電壓與接合部J7a及J7b崩潰的電壓相等4妾合部j7a及J7b 崩潰的電壓係依據P++區域31b的雜質濃度和n++區域（ 41b、42b)的雜質濃度設定。即，上述第！情況的觸發電 22/29 201143088 壓係依據P++區域31b的雜質濃度和N++區域（41b、42b )的雜質濃度設定。另外，表示為了維持端子T1與端子 丁2之間的ON狀態的電流值之保持電流值，係依據至少包 含N區域（2a、2b)的雜質濃度的參數設定。另外，在決 定保持電流值的參數中，還包含p區域（la、lb)的雜質 濃度和擴散深度、p區域3的雜質濃度和擴散深度、p區域 (h、lb)的圖案形狀等。N區域（2a、2b)的雜質濃度是 決定保持電流值的參數之一。 另外’在端子T2與端子T1之間施加偏壓的第2情況 下，因短路型閘流體l〇〇b變成反向偏壓，無法導電。 如上所述，本實施形態的短路型閘流體iOOb，具有比 P區域3的雜質濃度更高的p++區域31b、比N區域2a的 雜質濃度更高的N++區域41b、以及比N區域2b的雜質濃 度更高的N++區域42b。因此，在端子T1和端子T2之間 施加偏壓的上述第1情況下，P++區域31b與N++區域41b 的接合部J7a比接合部J2a(或P++區域3lb與N++區域42b 的接合部J7b比接合部J2b)先發生崩潰。切換為短路型閘 流體100b之ON狀態的觸發電壓係依據P++區域31b與 N++區域41b的接合崩潰電壓（或P++區域31b與N++區域 42b的接合崩潰電壓）決定。 此接合崩潰電壓係依據P++區域31b與N++區域41b 的雜質濃度（或P++區域31b與N++區域42b的雜質濃度 )決定。因而，此接合崩潰電壓可以不取決與保持電流特 性相關的N區域2a及2b的雜質濃度而決定。 這樣’本實施形態的短路型閘流體100b就可期待有與 第1實施形態的短路型閘流體100同等的效果。 23/29 201143088 又，依據本發明的實施形態，短路型閘流體100係依 序接合第1導電型（P型半導體）的第1區域（P區域1) 、第2導電型（η型半導體）的第2區域（N區域）、第1 導電型的第3區域（Ρ區域3)、第2導電型的第4區域（Ν 區域4)，具有使第1區域（Ρ區域1)和第2區域（Ν區域 2)短路的電極11 ;其具有與第3區域（Ρ區域3)相接形 成、比第3區域（Ρ區域3)的雜質濃度更高的第1導電型 的第5區域（Ρ++區域31)，以及與第2區域（Ν區域2) 及第5區域（Ρ++區域31)相接形成、比第2區域（Ν區域 2)的雜質濃度更高的第2導電型的第6區域（Ν++區域41 )。另外，短路型閘流體100係依據第5區域（Ρ++區域31 )的雜質濃度和第6區域（Ν++區域41)的雜質濃度來設 定觸發電壓值，並依據至少包含第2區域（Ν區域2)的雜 質濃度的參數設定保持電流值。 這樣，短路型閘流體100就可以在不影響保持電流特 性的情況下，實現觸發電壓的低壓化。 另外，第5區域（Ρ++區域31)或第6區域（Ν++區域 41)係形成在第2區域（Ν區域2)與第3區域（Ρ區域3 )的接合面（接合部J2的接合面）内、距電極11與第2 區域（Ν區域2)的接觸面的距離最遠的位置。 因此’第2區域（Ν區域2 )的橫向電阻變大。此電阻 越大，使第1區域（Ρ區域1)與第2區域（Ν區域2)正 向偏壓的電壓下降就越大。所以，該距離越長，閘流體就 能越容易切換為ON狀態。 另外，第5區域（P++區域31或31a)和第6區域（ N++區域41或41a)至少有一方被成形為暴露在與電極11 24/29 201143088 相接的半導體基板的表面（第1表面F1或第2表面F2)。 這樣’短路型閘流體100就可以通過例如離子注入法 荨形成第5區域（P++區域31 )和第6區域（N++區域41 )°從而可簡化短路型閘流體〗〇〇的生產工程。 另外，本發明並不僅限於上述的各實施形態，只要不 脫離本發明的主旨，還可以有各種形態的變更。在上述實 施形態中，雖是以P型半導體作為第1導電型、n型半導^ 作為第2導電絲制，但亦可以η型半導體作為第】^ 電型、Ρ型半導體作為第2導電型。這時，將變成從第4區 域（Ρ型半導體區域）向第i區域（η型半導體區 二 向導電，導電方向與上述各實施形態相反。 ' h另在上述各實施形態中，帛5區域（Ρ++區域）和 =(糾+區域）的接合部（J5、仏、J6 ϋ 5 的接合面的位置，可以是形成為盥 區域）和第1旧u , 人乐z k域（Ν 區或（P區域）的接合部（J2、j2 J⑽，致的形態，也可以是形成為相互二:戈 另外，_者雖為具備通道截斷環目6互^ ，但本發明亦可、奋田从 衣⑼〜9)的形態 另外通道截斷環(6〜9)的形態。The short-circuit type thyristor 100 shown is the same as the one shown. ', (1) Short-circuit type thyristor l〇〇b is a unidirectional terminal structure thyristor respectively replace short-circuit type thyristor lb), N area 2 with (2) in short-circuit type thyristor 100b, 100 P Area 1 is replaced by P area (la, N area (2a, 2b). (3) In the short-circuit type thyristor 100b, the short-circuit type thyristor P++ area (31, 32) and the N++ area (41, 42) are Replaced by the region 31b and the N++ region (41b, 42b). In Fig. 3, the impurity concentration of the N++ region 41b is high, and the impurity concentration of the 42++ region 42b is high for the impurity concentration of the region 2b. The impurity concentration of the region 31b is higher than the impurity concentration of the p region 3. Therefore, the junction collapse voltage of the junction portion J7a of the N++ region 41b and the P++ region 31b is lower than the junction breakdown voltage of the junction portion J2a of the N region 2a and the P region 3. The junction collapse voltage of the junction portion J7b of the N++ region 42b and the p++ region 31b is lower than the junction breakdown voltage of the junction portion Jbb of the n region 2b and the p region 3. The first case where a bias voltage is applied between the terminal T1 and the terminal T2 Joint portion J7a of 'N++ region 41b and 42b (6th region) and p++ region 31b (5th region) J7b, which collapses before the joints J2a and J2b. The subsequent operation is the same as that of the short-circuit type thyristor. In addition, in the short-circuit type thyristor 100b, the trigger voltage of the first case and the voltage at which the junction portions J7a and J7b collapse The voltage at which the equal junctions j7a and J7b collapse is set according to the impurity concentration of the P++ region 31b and the impurity concentration of the n++ region (41b, 42b). That is, the triggering of the above-mentioned condition is 22/29 201143088, and the pressure is based on the P++ region. The impurity concentration of 31b and the impurity concentration of the N++ region (41b, 42b) are set. The value of the holding current for maintaining the current value between the terminal T1 and the terminal 2 is based on at least the N region (2a, 2b) Parameter setting of the impurity concentration. In addition, the parameter determining the holding current value includes the impurity concentration and diffusion depth of the p region (la, lb), the impurity concentration and diffusion depth of the p region 3, and the p region (h). The pattern shape of lb), etc. The impurity concentration of the N region (2a, 2b) is one of the parameters for determining the holding current value. In addition, in the second case where a bias voltage is applied between the terminal T2 and the terminal T1, the short-circuit type is used. Brake fluid 〇b becomes a reverse bias and cannot conduct electricity. As described above, the short-circuit type thyristor iOOb of the present embodiment has a p++ region 31b having a higher impurity concentration than the P region 3 and a higher impurity concentration than the N region 2a. The N++ region 41b and the N++ region 42b having a higher impurity concentration than the N region 2b. Therefore, in the first case where a bias voltage is applied between the terminal T1 and the terminal T2, the junction portion J7 of the P++ region 31b and the N++ region 41b The collapse occurs first than the joint portion J2a (or the joint portion J7b of the P++ region 3lb and the N++ region 42b is larger than the joint portion J2b). The trigger voltage for switching to the ON state of the short-circuit type sluice fluid 100b is determined in accordance with the junction collapse voltage of the P++ region 31b and the N++ region 41b (or the junction breakdown voltage of the P++ region 31b and the N++ region 42b). This junction collapse voltage is determined based on the impurity concentration of the P++ region 31b and the N++ region 41b (or the impurity concentration of the P++ region 31b and the N++ region 42b). Therefore, the junction collapse voltage can be determined without depending on the impurity concentration of the N regions 2a and 2b related to the retention current characteristics. Thus, the short-circuit type thyristor 100b of the present embodiment can be expected to have the same effect as the short-circuit type thyristor 100 of the first embodiment. 23/29 201143088 Further, according to the embodiment of the present invention, the short-circuit type thyristor 100 sequentially bonds the first region (P region 1) of the first conductivity type (P-type semiconductor) and the second conductivity type (n-type semiconductor). The second region (N region), the third region of the first conductivity type (Ρ region 3), and the fourth region of the second conductivity type (Ν region 4) have the first region (Ρ region 1) and the second region. The electrode 11 which is short-circuited in the region (Ν region 2); has a fifth region of the first conductivity type which is formed in contact with the third region (Ρ region 3) and has a higher impurity concentration than the third region (Ρ region 3) ( Ρ++ region 31), and second conductive layer formed in contact with the second region (Ν region 2) and the fifth region (Ρ++ region 31) and having a higher impurity concentration than the second region (Ν region 2) The sixth region of the type (Ν++ region 41). Further, the short-circuit type thyristor 100 sets the trigger voltage value according to the impurity concentration of the fifth region (Ρ++ region 31) and the impurity concentration of the sixth region (Ν++ region 41), and according to at least the second region ( The parameter of the impurity concentration of the Ν region 2) sets the holding current value. Thus, the short-circuit type thyristor 100 can achieve a low voltage of the trigger voltage without affecting the characteristics of the holding current. Further, the fifth region (Ρ++ region 31) or the sixth region (Ν++ region 41) is formed at the joint surface of the second region (Ν region 2) and the third region (Ρ region 3) (joining portion J2) In the joint surface), the distance from the contact surface of the electrode 11 and the second region (the region 2) is the farthest. Therefore, the lateral resistance of the second region (Ν region 2) becomes large. The larger the resistance, the larger the voltage drop in the forward bias of the first region (Ρ region 1) and the second region (Ν region 2). Therefore, the longer the distance, the easier it is for the thyristor to switch to the ON state. Further, at least one of the fifth region (P++ region 31 or 31a) and the sixth region (N++ region 41 or 41a) is formed to be exposed on the surface of the semiconductor substrate that is in contact with the electrode 11 24/29 201143088 (the first surface F1) Or the second surface F2). Thus, the short-circuit type thyristor 100 can form the fifth region (P++ region 31) and the sixth region (N++ region 41) by, for example, ion implantation, thereby simplifying the production process of the short-circuit type thyristor. The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention. In the above-described embodiment, the P-type semiconductor is used as the first conductivity type and the n-type semiconductor is used as the second conductive wire. However, the n-type semiconductor may be used as the second conductive type or the Ρ-type semiconductor as the second conductive material. type. At this time, the fourth region (the 半导体-type semiconductor region) is turned to the ith region (the n-type semiconductor region is electrically conductive in two directions, and the conductive direction is opposite to the above-described respective embodiments. 'h In the above respective embodiments, the 帛5 region ( Ρ++ region) and = (correction + region) joints (the positions of the joint faces of J5, 仏, J6 ϋ 5 may be formed as 盥 regions) and the first old u, the human music zk domain (Ν region or (J2, j2 J (10), the form of the junction (J2, J2, J (10), may be formed to be mutually two: Ge, _ although there is a channel cut-off ring 6 mutual ^, but the invention can also, Fenada from The form of the clothes (9) to 9) is in the form of another channel cut-off ring (6 to 9).
域(N++區域)形成弟5區域(P++區域)或第6區 乂）$成在弟2區域（N區域）知牮。广 區域）的接合面内 ）#第3區域（P 面的距離最遠的位置(N區域）的接觸 要是問流體可以進二1=’但本發明並不以此為限。只 為形成在其它位為=電：的位置，亦可 觸面起的距離越長，橫向C域(N 阻越大’使叫(。區域)和第2區域(=): 25/29 201143088 偏壓的電壓下降就越大。因此，該距離越長，閘流體就能 夠越容易切換為 ON狀態。 另外只要第5區域（P++區域）與第3區域（p區域 )相接、第6區域（N++區域）與第5區域（p++區域）及 第2區域（N區域）相接，第5區域（P++區域）與第6區 域（N++區域）的形狀及位置關係可以不限於上述各實施形 慼。例如，亦可為將第6區域配置在第5區域（p++區域） 下方的形態。 另外’在第2實施形態中雖是說明第5區域（P++區域 )與第6區域（N++區域）於縱向重疊所形成之形態，但亦 可為第5區域（p++區域）和第6區域（N++區域）的任一 方暴4在半導體基板上之形態。這時’第5區域（p++區域 )與第6區域（N++區域）的任一方，因可藉由離子注入法 等形成，故可簡化生產工程。 【圖式簡單說明】 圖1顯示第1實施形態的短路型閘流體的戴面結構圖 〇 圖2顯示第2實施形態的短路型閘流體的戴面結構圖 〇 圖3顯示第3實施形態的短路型閘流體的截面結構圖 〇 圖4顯示以往的短路型閘流體的戴面結構圖。 【主要元件符號說明】 P區域 N區域 通道截斷環 1、 3、5、】a、lb 2、 4、2a、2b 26/29 201143088 η、12、lla、12a 電極 21 ' 22 > 23 ' 24 ' 25 絕緣層 3 卜 32、31a、32a、31b、32b P++區域 4 卜 42、41a、42a、41b、42b N++區域 100、100a、100b 短路型閘流體 T1 > T2 端子 FI 第1表面 F2 第2表面 J卜 J2、J3、J4、J5、J6 接合部 J5a、J6a、J7a、J7b 接合部 27/29The domain (N++ region) forms the brother 5 region (P++ region) or the sixth region 乂)$ into the brother 2 region (N region) knowledge. In the joint area of the wide area) #3rd area (the position of the farthest distance of the P surface (N area) is the same as if the fluid can enter the second 1=', but the invention is not limited thereto. Other bits are = electric: the position, the longer the distance from the contact surface, the horizontal C domain (the larger the N resistance is, the higher the voltage is called (.) and the second region (=): 25/29 201143088 bias voltage Therefore, the longer the distance, the easier the thyristor can be switched to the ON state. In addition, the fifth region (P++ region) is connected to the third region (p region), and the sixth region (N++ region) is used. The shape and positional relationship between the fifth region (p++ region) and the sixth region (N++ region) are not limited to the above-described respective embodiments, for example, in contact with the fifth region (p++ region) and the second region (N region). For example, It is also possible to arrange the sixth region below the fifth region (p++ region). In addition, in the second embodiment, the fifth region (P++ region) and the sixth region (N++ region) are vertically overlapped. Form of formation, but can also be any of the fifth region (p++ region) and the sixth region (N++ region) The form of the storm 4 on the semiconductor substrate. At this time, either the fifth region (p++ region) and the sixth region (N++ region) can be formed by ion implantation or the like, so that the production process can be simplified. Fig. 1 shows a wearing structure of a short-circuit type thyristor according to a first embodiment. Fig. 2 shows a wearing structure of a short-circuit type thyristor according to a second embodiment. Fig. 3 shows a short-circuit type sluice of a third embodiment. Cross-sectional structure diagram Figure 4 shows the wearing structure of the conventional short-circuit type thyristor. [Key element symbol description] P-area N-area channel cut-off ring 1, 3, 5, a, lb 2, 4, 2a, 2b 26/29 201143088 η, 12, 11a, 12a electrode 21 ' 22 > 23 ' 24 ' 25 insulating layer 3 32, 31a, 32a, 31b, 32b P++ region 4 卜 42, 41a, 42a, 41b, 42b N++ region 100, 100a, 100b short-circuit type thyristor T1 > T2 terminal FI first surface F2 second surface Jb J2, J3, J4, J5, J6 joint portion J5a, J6a, J7a, J7b joint portion 27/29