TW201140811A

TW201140811A - Method of operating memory cell

Info

Publication number: TW201140811A
Application number: TW99115277A
Authority: TW
Inventors: Yu-Fong Huang; Teng-Hao Yeh; Miao-Chih Hsu; Tzung-Ting Han
Original assignee: Macronix Int Co Ltd
Priority date: 2010-05-13
Filing date: 2010-05-13
Publication date: 2011-11-16
Also published as: TWI426600B

Abstract

A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to a lower portion and an upper portion at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to an upper portion and a lower portion at the other side of the same. The second and third storage regions are regarded as a top storage region. The operating method includes programming the top storage region. A first positive voltage is applied to the word line. A second positive voltage is applied to a top bit line in a top portion of the protruding part. A bottom voltage is applied to the first and second bottom bit lines in the substrate beside the protruding part respectively.

Description

201140811. 〜w v v / 5 32286twf.doc/n 六、發明說明：【發明所屬之技術領域】本發明是有關於一種記憶胞的操作方法，且特別是有關於一種垂直記憶胞的操作方法。【先前技術】 S己憶體為設計來儲存資訊或資料之半導體元件。當電，微^理器之功能變得越來越強，軟體所進行的程式二運算也隨之增加。因此，記憶體的容量需求也就越來越高。在各式的記憶體產品中，非揮發性記憶體，例如可電抹除可程式化唯讀記憶體（Electrically Erasable programmable ^ead〇nlyMemory，EEpR〇M)允許多次的資料程式化、項取及抹除操作’且其巾儲存的資料即使在記憶體被斷電後仍可以保存。基於上述優點，可電抹除可程式化唯讀記憶體已成為個人電腦和電子設備所廣泛採用的一種記憶體。 “ 少典型的可電抹除且可程式化唯讀記憶體係以換雜的夕晶矽製作浮置閘極（Floating Gate)與控制閑極（201140811. ~w v v / 5 32286twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a method of operating a memory cell, and more particularly to a method of operating a vertical memory cell. [Prior Art] S-resonance is a semiconductor component designed to store information or data. When the power of the microprocessor becomes more and more powerful, the program 2 operation of the software increases. Therefore, the capacity requirements of the memory are getting higher and higher. Among various types of memory products, non-volatile memory, such as Electro-Erasable programmable ^ead〇nly Memory (EEpR〇M), allows multiple data programs and items to be fetched. And the erase operation' and the data stored in the towel can be saved even after the memory is powered off. Based on the above advantages, the erasable programmable read-only memory has become a memory widely used in personal computers and electronic devices. “There is a typical electrically erasable and programmable read-only memory system to make floating gates and control idle poles with complex silicon crystals.

Gate) ^ 5己憶體進行程式化（Program)時，注入浮置閘，的電子會均勻分布於整個多晶料置閘極之中。缺而，當多晶石夕浮置閘極下方的穿隨敦化層有缺陷存在時，，，就容易造成元件的漏電流，影響元件的可靠度。 ' ，此1 了職可電齡可程式化唯讀記憶體漏電流之問通’目前習知的-種方法是採用含有非導體的電荷儲 201140811 P980095 32286twf doc/n 存層之堆疊式（Staeked) _結構來極:以電荷儲存層取代多晶石夕浮置問極的匕閘在兀件程々b時’ t子僅會在接獅上= 局部性地儲存。因此，在進行程式/ +方的通道仃杈式化盼，可以分別對堆疊Gate) ^ When the program is programmed, the electrons injected into the floating gate are evenly distributed throughout the gate of the polysilicon. Insufficient, when there is a defect in the Dunhua layer under the floating gate of the polycrystalline stone, it is easy to cause leakage current of the component and affect the reliability of the component. ', This is a workable age-programmable read-only memory leakage current 'currently known - a method is to use a non-conductor charge store 201140811 P980095 32286twf doc / n storage layer stacking (Staeked ) _ Structure to the pole: replace the polycrystalline stone with a charge storage layer. The floating gate of the floating pole is only stored on the lion when it is placed on the lion. Therefore, in the program / + side of the channel, you can separately stack

式閘極-端的雜區與控制閘極絲電壓，而在接近於堆豐式閘極另-端之錄區的㈣儲存層中產生高斯分布的電子，並且也可以分別對堆叠式閘極—端躲極區與控制閘極施加電壓，而在接近於堆疊式閘極另—端之源極區的電荷儲存層巾產生高斯分布的電子。故而，藉由改變控制閘極與其兩側之源極/汲極區所施加電壓，可以在單一的電荷儲存層之中存在兩群具有高斯分布的電子、單一群具有高斯分布的電子或是不存在電子。因此，此種以電荷儲存層取代浮置閘極的快閃記憶體，可以在單一的記憶胞之中寫入四種狀態，為一種單一記憶胞二位元（2 bits/1 cell) 儲存之快閃記憶體。為了提升單一記憶胞的位元數，習知技術中有一種具有垂直11己丨$胞的έ己憶體結構，為一種.单一記憶胞四位元（4 bits/1 cell)儲存之快閃記憶體。然而’在對具有垂直記憶胞的記憶體結構的選定位元進行程式化操作時，會對其他位元產生干擾，所以造成各位元之間難以區別，而無法達到多位兀儲存的效果。【發明内容】有鑑於此’本發明的一實施例提供一種記憶胞的操作 201140811 r>〇v^5 32286twf.doc/n 方法’可達到單一記憶胞三位元儲存的效果。本發明的一實施例中提出一種記憶胞的操作方法，其 1記憶胞包括具有凸出部的基底、位於凸出部頂部中的^ 部位元線、分別位於凸出部兩側的基底中的第—底部位元線與第二底部位元線、設置於基底上方且與第一、第二^ 部，元線相交的字元線以及設置於字元線與基底之間^ 電荷儲存層。其中，記憶胞具有位於電荷儲存層中的第— 2存區n存n齡區及第四儲純存區及第二儲存區分別鄰近凸出部之第一底部位元線的卩及上部，第三儲存區及第四儲存區分卿近凸出位元線之一侧的上部及下部，而第二儲存區儲存區視為相同的上部儲存區。此操作方法包式化心隐胞的上部儲存區。首先，施加一個第一正施加—個第二正電壓至頂部位元線。然後，刀另—加一個底電壓至第-、第二底部位元線。方法的厂—實施例所述，在上述之記憶胞的操作與底電壓之間的電位差例如是3伏特至5 :第例如是0伏特。付向展電壓依照本發明的-實施例所述，在上 = == =化記憶胞的第一儲存區。奴= 严,5 ί - t存括下列步驟。首先’施加—個第三正雷 ^子兀線。接著，施加一個頂電壓施加一個第四正電壓至第-底部位元線。凡線然後， 201140811 Fysuoyi 32286twf.doc/n 依照本發明的一實施例所述，在上述之記憶胞的操作方法中，第三正電壓例如是8伏特至12伏特，第四正電壓與頂電壓之_電位差例如是3伏特至5伏特，例如是0伏特。 =本發明的—實關所述’在上叙記憶胞的操作 / #，更包括程式化記憶胞的第四儲存區。程式化記憔四儲存區包括下列步驟。首先，施加-個第五正^ 字元線。接著，施加—個頂電壓至頂部位it線。然後，也σ —個第六正電壓至第二底部位元線。方法Π本發0㈣—實施例所述，在上述之記憶胞的操作與頂電C列如是8伏特至12伏特，第六正頓例如是。簡例如是3伏特至5伏特，而頂電壓方的—實施例所述，在上述之記憶胞的操作上部儲存取記憶胞的上雜純。讀取記憶胞的字元括下列步驟。首先，施加-個第七正電壓至施加加G伏特的電壓至頂部位元線。然後，個第八正電壓至第—底部位元線。方法令，第貫施例所述’在上述之記憶胞的操作墨例如是！伏特至是2伏特至8伏特，而第八正電作方:了本-實施例所述’在上述之記憶胞的操的上部儲存區^括胞^部，存區。讀取記憶胞乂驟I先，鉍加一個第九正電壓 201140811 ry〇uw5 32286twf.d〇c/n 著’施加0伏特帽至頂部位元線。然後， %加一個第十正電壓至第二底部位元線。作方:t本所述’在上述之記憶胞的操電壓例如是i伏特伏特至8伏特，而第十正作方：本所述’在上述之記憶胞的操的上部儲存區包括部儲存區。讀取記憶胞後，施加一個:伏峨壓至頂部位元線。然施加-個第十壓至第—底部位元線。接下來， —正電壓至第二底部位元線。作方法m的又—實施例所述，在上叙記憶胞的操正電電壓例如是2伏特至8伏特，第十二伏特至2伏特。、至2伏特，而第十三正電壓例如是1 方法中，更心I貫施例所5 ’在上述之記憶胞的操作第-儲存區包括^丨^憶胞的第—儲存區。讀取記憶胞的至字元線。iir驟。首先，施加—個第切正電壓然後，施加G伏特個f十五正電驗頂部位元線。依照本發=的第一底部位元線。方法中，第h 5魏騎述’在上叙記憶胞的操作乐十四正電壓例如是2 正電壓例如是】伏特至2伏特。彳8伙特，而斜五依照本發明的一實施例所述，在上述之記憶胞的操作 201140811 P980095 322S6twf.doc/n 第四儲存區包括四儲存區。讀取記憶胞的然後’施加。伏特頂部位元線。方法广所述，在上述之記憶胞的操作正電伏特至8伏特，而第十七方法實施例所述’在上述之記憶胞的操作上部倚存胞部儲存區。抹除記憶胞的 ί:第=施加一個第十八正電壓至頂部位元= 第一底部位元線浮置。方法ί照的—f_所述，在上述之記憶胞的操作電虔例如”負電壓例如是-4伏特至-7伏特，而第十八正 &例如疋3伏特至6伏特。方法明的—實施例所述’在上述之記憶胞的操作第-儲括抹除記憶胞的第一儲存區。抹除記憶胞的字元下列步驟。首先，施加一個第二負電壓至九正雷厭Ϊί ’使頂部位元線浮置。然後，施加一個第十電埜至弟一底部位元線。方法，“\本發明的一實施例所述，在上述之記憶胞的操作泰两/ ，第二負電壓例如是-4伏特至-7伏特，而第十九正包壓例如是3伏特至6伏特。依照本發明的一實施例所述，在上述之記憶胞的操作 201140811 r^uuyi 32286twf.doc/n 方法中，更包括抹除記憶胞第四儲存區包括下列步驟。首：。抹除記憶胞的十正Ϊ壓2 線浮置。然後，施加-個第二丁止冤壓至弟二底部位元線。方法，:言發實施例所述，在上述之記憶胞的操作弟二負電壓例如是_4伏特至_7 電壓例如是3伏特至6伏特。 W-十正基於上述，在本發私記憶朗操作料卜在對記區與第三儲存區進行程式化操作時，分別 =〇伙特的電壓至第―、第二底部位元線，使得第二儲子=與第二儲存區被程式化為相同的儲存狀態，而可視為相同的士戦存區使用，因此能有效地達到單—記憶胞三位兀儲存的目的。 …為讓本發明之上述特徵和優點能更明顯易麼，下文特舉實施例，並配合所附圖式作詳細說明如下。【實施方式】圖1所繪不為本發明之一實施例的記憶體的電路簡圖。圖2所繪示為圖1中記憶胞C22的剖面圖。 "月先參照圖1，記憶體陣列包括頂部埋入式位元線 TBL1、TBL2、TBL3、底部埋入式位元線BBL1、BBL2 及字元線WL1、WL2、WL3。其中，頂部埋入式位元線 TBL1、TBL2、TBL3與底部埋入式位元線BBL1、BBL2 交替且平行配置，而字元線WL1、WL2、WL3與頂部埋入式位元線TBL1、TBL2、TBL3及底部埋入式位元線 201140811 P980095 32286twf.doc/n BBL1、BBL2相交。此外，記憶胞位於相鄰兩條底部埋入式位元線與字元線相交處。舉例來說，記憶胞C22位於相鄰兩條底部埋入式位元線BBL1、BBL2與字元線WL2相交處。首先’利用圖1及圖2說明記憶胞C22的結構。請同時參照圖1及圖2，記憶胞C22包括基底1〇〇、頂部埋入式位元線TBL2、底部埋入式位元線BBL1、BBL2、字元 φ 線WL2及電荷儲存層1〇2。基底1〇〇具有凸出部1〇4。基底100例如是矽基底。頂部埋入式位元線TBL2位於凸出部104頂部中。頂部埋入式位元線TBL2例如是埋入式摻雜區。底部埋入式位元線BBU、BBL2分別位於凸出部 1〇4兩側的基底100中。底部埋入式位元線BBL1、bbl2 例如是埋入式摻雜區。字元線WL2設置於基底1〇〇上方且與底部埋入式位元線BBL1、BBL2相交。電荷儲存層 1〇2設置於字元線WL2與基底1〇〇之間。電荷儲存層1〇曰2 例如是氮化矽層的單層結構或氧化矽層/氮化矽層/氧化矽擊層（ΟΝΟ)的多層結構。此外，§己憶胞C22具有位於電荷儲存層中的第一儲存區ΒΙΤ-1、第二儲存區ΒΙΤ_2、第三儲存區βΙτ_3及第四儲存區ΒΙΤ-4。第-儲存區及第二儲存區βιτ_2 分別鄰近凸出部104之底部埋入式位元線BBU之一側的 I部及上部’以及第三儲存區BIT_3及第四儲存區bit_4 刀別鄰近凸出部104之底部埋入式位元線BBL2之一側的上部及下部。其中，第-儲存區BIT]與第四儲存區bit 4 201140811 觸州 322S6twfdoc/n 分別可儲存—杨^ h 存區㈣’而第二錯存區肌2與第三錯位元的料，=目叫上部儲存區TBIT，而可用以儲存一、；，因此能有效地達到單一記憶胞三位元儲存的目的。以下，本貫施例的操作方法是利用對記憶胞C22的操作來進行說明。下表1為本實簡對於記憶胞C22進行择作的操作電壓彙整表。表1 〇皁位：@4#The gate-end miscellaneous region and the gate voltage are controlled, and the Gaussian distribution electrons are generated in the (four) storage layer close to the other end of the stack gate, and the stacked gates can also be respectively The terminal hiding region and the control gate apply a voltage, and the charge storage layer adjacent to the source region of the other end of the stacked gate generates Gaussian-distributed electrons. Therefore, by changing the voltage applied to the source/drain region of the control gate and its two sides, there can be two groups of electrons having a Gaussian distribution, a single group of Gaussian distribution electrons or not in a single charge storage layer. There is electrons. Therefore, such a flash memory in which a floating gate is replaced by a charge storage layer can write four states in a single memory cell, and is stored in a single memory cell (2 bits/1 cell). Flash memory. In order to increase the number of bits of a single memory cell, there is a structure in the prior art that has a vertical memory of 11 cells, which is a flash memory of a single memory cell (4 bits/1 cell). Memory. However, when the selected positioning elements of the memory structure having the vertical memory cells are programmed, interference is caused to other bits, so that it is difficult to distinguish between the elements, and the effect of the multi-bit storage cannot be achieved. SUMMARY OF THE INVENTION In view of the above, an embodiment of the present invention provides a memory cell operation 201140811 r>〇v^5 32286twf.doc/n method' to achieve the effect of a single memory cell three-bit storage. An embodiment of the present invention provides a method for operating a memory cell, wherein a memory cell includes a substrate having a protrusion, a portion of the element line located at the top of the protrusion, and a substrate respectively located on both sides of the protrusion. a first bottom bit line and a second bottom bit line, a word line disposed above the substrate and intersecting the first and second portions, the element line, and a charge storage layer disposed between the word line and the substrate. Wherein, the memory cell has a second storage area in the second storage area of the second storage area and the fourth storage area and the second storage area respectively adjacent to the first bottom bit line of the protrusion and the upper part, third The storage area and the fourth storage compartment are adjacent to the upper and lower sides of one side of the bit line, and the second storage area storage area is regarded as the same upper storage area. This method of operation encapsulates the upper reservoir of the cardiac cell. First, a first positive applied - second positive voltage is applied to the top bit line. Then, the knife adds another bottom voltage to the first and second bottom bit lines. In the factory-embodiment of the method, the potential difference between the operation of the above-mentioned memory cell and the bottom voltage is, for example, 3 volts to 5: for example, 0 volt.付展展电压 According to the embodiment of the invention, the first storage area of the memory cell is above ====. Slave = Strict, 5 ί - t includes the following steps. First, 'apply—a third positive thunder ^ sub-line. Next, a top voltage is applied to apply a fourth positive voltage to the first-bottom bit line. Then, in accordance with an embodiment of the invention, in the above method for operating a memory cell, the third positive voltage is, for example, 8 volts to 12 volts, and the fourth positive voltage and the top voltage are used. The potential difference is, for example, 3 volts to 5 volts, for example, 0 volts. = The operation of the present invention - the operation of the memory cell / #, further includes a fourth storage area of the stylized memory cell. Stylized Recording Four storage areas include the following steps. First, apply a fifth positive ^ word line. Next, apply a top voltage to the top bit it line. Then, σ is also a sixth positive voltage to the second bottom bit line. The method is described in the following section: (0) - The operation of the above-mentioned memory cell is as follows: the operation of the memory cell is 8 volts to 12 volts, and the sixth positive is, for example. The simplification is, for example, 3 volts to 5 volts, and as described in the embodiment of the top voltage, the upper impurities of the memory cells are stored in the upper portion of the operation of the above-mentioned memory cells. The characters that read the memory cell include the following steps. First, a seventh positive voltage is applied until a voltage of G volts is applied to the top bit line. Then, an eighth positive voltage to the first-bottom bit line. The method is described in the above embodiment. The operation of the memory cell described above is, for example,! The volts are from 2 volts to 8 volts, and the eighth positive electrode is the upper storage region of the above-mentioned memory cells. Read the memory cell. First, add a ninth positive voltage. 201140811 ry〇uw5 32286twf.d〇c/n. Apply a 0 volt cap to the top bit line. Then, % adds a tenth positive voltage to the second bottom bit line. The method: t described in the above memory cell operating voltage is, for example, i volt volts to 8 volts, and the tenth square: the above described in the above memory cell operation of the upper storage area including the storage Area. After reading the memory cells, apply a: volts to the top bit line. However, a tenth voltage is applied to the first-bottom bit line. Next, - a positive voltage to the second bottom bit line. In the embodiment of the method m, the operating voltage of the memory cell is, for example, 2 volts to 8 volts, twelfth volt to 2 volts. Up to 2 volts, and the thirteenth positive voltage is, for example, a method, and is more concentric. The operation of the above-mentioned memory cell includes a first storage area of the memory cell. Read the word line of the memory cell. Iir. First, a positive tangential voltage is applied. Then, a top volt line of G volts is applied. According to the first bottom bit line of the present invention. In the method, the operation of the h 5 Wei riding said in the upper memory cell is, for example, a positive voltage of 2 volts to 2 volts. In accordance with an embodiment of the present invention, the operation of the memory cell described above 201140811 P980095 322S6twf.doc/n The fourth storage area includes four storage areas. Read the memory cell and then 'apply. Volt top bit line. The method is broadly described, in which the operation of the memory cell is positively volt-voltage to 8 volts, and the seventeenth method embodiment is described above in the upper portion of the memory cell operation. Erase the memory cell ί: the first = apply an eighteenth positive voltage to the top bit = the first bottom bit line is floating. The method ί, as described in the above-mentioned, is that the operating voltage of the memory cell is, for example, "negative voltage is, for example, -4 volts to -7 volts, and the eighteenth positive & The operation of the memory cell described above - the first storage area of the memory cell is erased. The following steps are performed to erase the characters of the memory cell. First, a second negative voltage is applied to the nine positive thunder. Disgusting ί 'Let the top bit line float. Then, apply a tenth electric field to the bottom bit line. Method, "In one embodiment of the invention, the operation of the above memory cell is two / The second negative voltage is, for example, -4 volts to -7 volts, and the nineteenth positive voltage is, for example, 3 volts to 6 volts. According to an embodiment of the present invention, in the above operation of the memory cell 201140811 r^uuyi 32286 twf.doc/n, the method further comprises erasing the memory cell, the fourth storage area comprising the following steps. first:. Wipe out the memory cell's ten positive pressure 2 line floating. Then, apply a second stop to the bottom line of the second. The method, as described in the embodiment, wherein the operation of the memory cell described above is, for example, a voltage of _4 volts to _7, for example, 3 volts to 6 volts. W-Ten is based on the above, in the case of the local operation of the private memory, in the case of stylized operation of the recording area and the third storage area, respectively, the voltage of the 〇特至 to the first and second bottom bit lines, so that The second storage = is stored in the same storage state as the second storage area, and can be regarded as the same use of the gentry storage area, so that the purpose of the single-memory cell three-position storage can be effectively achieved. In order to make the above-described features and advantages of the present invention more apparent, the following detailed description of the embodiments and the accompanying drawings are set forth below. [Embodiment] A circuit diagram of a memory which is not an embodiment of the present invention is shown in Fig. 1. 2 is a cross-sectional view of the memory cell C22 of FIG. 1. Referring first to Figure 1, the memory array includes top buried bit lines TBL1, TBL2, TBL3, bottom buried bit lines BBL1, BBL2, and word lines WL1, WL2, WL3. Wherein, the top buried bit lines TBL1, TBL2, TBL3 and the bottom buried bit lines BBL1, BBL2 are alternately and arranged in parallel, and the word lines WL1, WL2, WL3 and the top buried bit lines TBL1, TBL2 , TBL3 and bottom buried bit line 201140811 P980095 32286twf.doc/n BBL1, BBL2 intersect. In addition, the memory cell is located at the intersection of the adjacent two bottom buried bit lines and the word line. For example, the memory cell C22 is located at the intersection of the adjacent two bottom buried bit lines BBL1, BBL2 and the word line WL2. First, the structure of the memory cell C22 will be described using Figs. 1 and 2 . Referring to FIG. 1 and FIG. 2 simultaneously, the memory cell C22 includes a substrate 1 顶部, a top buried bit line TBL2, a bottom buried bit line BBL1, a BBL2, a word φ line WL2, and a charge storage layer 1 〇 2 . The substrate 1 has a projection 1〇4. The substrate 100 is, for example, a crucible substrate. The top buried bit line TBL2 is located in the top of the bump 104. The top buried bit line TBL2 is, for example, a buried doped region. The bottom buried bit lines BBU, BBL2 are respectively located in the substrate 100 on both sides of the projections 1〇4. The bottom buried bit lines BBL1, bbl2 are, for example, buried doped regions. The word line WL2 is disposed above the substrate 1A and intersects the bottom buried bit lines BBL1, BBL2. The charge storage layer 1〇2 is disposed between the word line WL2 and the substrate 1〇〇. The charge storage layer 1〇曰2 is, for example, a single layer structure of a tantalum nitride layer or a multilayer structure of a hafnium oxide layer/tantalum nitride layer/cerium oxide layer. Further, the memory cell C22 has a first storage region ΒΙΤ-1, a second storage region ΒΙΤ_2, a third storage region βΙτ_3, and a fourth storage region ΒΙΤ-4 in the charge storage layer. The first storage area and the second storage area βιτ_2 are respectively adjacent to the I portion and the upper portion 'and the third storage area BIT_3 and the fourth storage area bit_4 on one side of the bottom buried bit line BBU of the protruding portion 104. The bottom of the outlet portion 104 is embedded in an upper portion and a lower portion on one side of the bit line BBL2. Wherein, the first storage area BIT] and the fourth storage area bit 4 201140811 touch state 322S6twfdoc/n respectively can store - Yang ^ h storage area (four) ' and the second wrong storage area muscle 2 and the third wrong position material, = mesh It is called the upper storage area TBIT, and can be used to store one, so that it can effectively achieve the purpose of a single memory cell three-dimensional storage. Hereinafter, the operation method of the present embodiment will be described using the operation of the memory cell C22. Table 1 below is an operational voltage summary table for the selection of memory cell C22. Table 1 〇 Soap: @4#

程式化操作請同時參照圖卜圖2及表！，本實施例的操作勺括程式化記憶胞C22的上部儲存區TBIT。程式化圮情月^ 12 201140811 P980095 32286twf.doc/n C22的上部儲存區丽包括下第一正電駐字元線WL2。接著，施力= 頂部埋入式位元線TBL2。然後二至 ^部埋人纽轉祖丨、祖2。在本糾至航5伙特’而底電壓例如是〇伏特。此外， WL3例如是被施加Q伏特的糕，而頂部埋位几線TBL1、TBL3例如是浮置。工心作方法包括程式化記憶胞⑶的第-儲存區Bim呈式化記憶胞C22的第括下列步驟。首先，施加一個第二正二ΙΊΜ包 ^ 個頂電壓至頂部埋人式位元線tbu 知加-個弟四正電墨至底部埋入式位元線bbu。例中’第三正電壓例如是8伏特至12伏二正電壓例如是3伏特至5伏特，而了f雷此外，字元線WU、WL3例1 Λ 例如是0伏特。例如疋破知加0伏特的雷屙，而底。卩埋入式位元線BBL2及 ^ TBL3例如是浮置。 .賴讀TBU、本實施例的操作方法包括程式化記憶胞⑶四 =式化記憶胞C22的第四儲存區咖包括下列步驟。百先，施加—個第五。 ί力著，力Γ個頂電壓至頂部埋人式位轉至底部埋入式位元線_。在二月的一貫施例中，弟五正雷 ^ 止包壓例如疋8伏特至12伏特，第 13 201140811. ± 32286twf.doc/n ，、正電壓例如是3伏特至5伏特，而頂該例如是此外，字元線WU、WL3.例如是被施加Q伏特寺而底部埋人式位祕BBL1及頂部埋人式位 TBL3例如是浮置。冰、讀取操作堉问Bf翏照圖包括讀取記憶胞⑵的上部儲存區“= l^IT-2及第三儲存區BIT_3被視為相同的上部儲存^ IT ’因此I獨對第二儲存區ΒΙΤ_2或第三儲存區Β 進行讀取或是㈣魏第二料區ΒΙΤ_2衫 BITj可得知上部儲存區ΤΒΙΤ的儲存狀態。子-讀取記憶胞C22的上部儲存區Tm ='，加一個第七正電壓至字元後，施式位猶购。然本發明的-實施例中，第"^電^^位元線删。在 _例如是丄:特=字元線和、讀取記憶胞=的1線^^^3例如是浮置。括下列步驟。首先，施加一^的第二種方法包，:施加。伏特的電二匕: 電塵至底部埋入式位元線祖2。2 、 ⑪，，第九正電壓例如是2伏特至8伏特， 14 201140811 P9S0095 32286twf.doc/n H 駐2鱗。此外，字元線術、㈣例如疋被施加0伏特的電麼，而底部埋入式位元缘即匕及頂雜人式料線加、_例如是忽，線括下胞7的上部儲存區TBIT的第三種方法包 =二施加一個第十-正電璧至字元線接者’施加0伏特的電壓至頂部埋入式位元飧 TBL2。然後，施加一個第+ 主八①位/〇、.泉 BBU。接下來，施加一以==:入式位元線線肌2。在本發明的—實H埋人式位兀第十三正電壓例如是伏特至2伏特，而肌3例如是被施加G伏特^°此外’字元線㈣、 TBU、TBL3例如是^特的^，而頂部埋人式位元線本實施例的操作方法包括魏存區BIT-卜讀取記憶胞 C22的弟一儲列步驟。首先，施加—個第十=:=:-1包括下著，.施加-個第十五正電^至子4 WL2 °接本發明的-實施例中二元=在 =而弟十五正鶴例如是i伏特至㈣，例如是被施加。【I:= =線觀及頂部埋入式位元線TBu: = 本實施例的操作方法包括軌記,_⑶的第四餘 15 201140811 i^y»uuy5 32286tw£doc/n 存區BIT·4。讀取記憶胞C22的第四儲存區ΒΙΤ·4包括下列步驟。首先，施加-個第十六正_至字元線wu。接者’施加-個第十七正電壓至頂部埋人式位元線 TBL2。然後’施加〇伏_雜至麵埋人纽元線bbu。在 ^發明的-實施例中，第十六正電㈣如是2伏特至8伏特’而第十七正電壓例如是i伏特至2伏特。此外，字元，WU、WL3例如是被施加〇伏特的電麗，而底部埋入 ^元線狐1及頂部埋入式位元線加、觀例如是Stylized operation Please also refer to Figure 2 and Table! The operation spoon of this embodiment includes the upper storage area TBIT of the stylized memory cell C22. Stylized lyrical month ^ 12 201140811 P980095 32286twf.doc/n The upper storage area of C22 includes the lower first positive standing word line WL2. Next, apply force = top buried bit line TBL2. Then two to the ^ part of the people to turn to the ancestors, ancestors 2. In this book, the squad is 5 volts, and the bottom voltage is, for example, volts. Further, WL3 is, for example, a cake to which Q volts are applied, and the top buried lines TBL1, TBL3 are, for example, floating. The working method includes the following steps of staging the memory cell C22 in the first storage region of the memory cell (3). First, a second positive divergence ^ top voltage is applied to the top buried bit line tbu to know the addition of the four positive electric ink to the bottom buried bit line bbu. In the example, the third positive voltage is, for example, 8 volts to 12 volts. The positive voltage is, for example, 3 volts to 5 volts, and f ray. Further, the word lines WU and WL3 are, for example, 0 volts. For example, smashing the know to add a 0 volt Thunder, and the bottom. The buried bit lines BBL2 and ^BL3 are, for example, floating. The operation method of the present embodiment includes a stylized memory cell (3). The fourth storage area of the memory cell C22 includes the following steps. Hundreds of first, apply - a fifth. ί force, force the top voltage to the top buried position to the bottom buried bit line _. In the consistent application of February, the brother of the five positive thunders, for example, 疋8 volts to 12 volts, the 13th 201140811. ± 32286twf.doc / n, the positive voltage is, for example, 3 volts to 5 volts, and the top For example, in addition, the word lines WU, WL3. For example, the Q volt temple is applied, and the bottom buried BBL1 and the top buried bit TBL3 are floated, for example. Ice, read operation Bf map includes reading the upper memory area of the memory cell (2) "= l^IT-2 and the third storage area BIT_3 are treated as the same upper storage ^ IT 'so I am the second pair The storage area ΒΙΤ_2 or the third storage area 进行 is read or (4) Wei second material area ΒΙΤ_2 shirt BITj can know the storage state of the upper storage area 。. The upper storage area of the sub-read memory cell C22 Tm = ', plus After a seventh positive voltage to a character, the application is still purchased. However, in the embodiment of the invention, the "^^^^^^^^^^^^^^^^^^^^^^^^^^ The 1 line ^^^3 of the read memory cell = for example is floating. The following steps are included. First, a second method package of ^ is applied: applying a voltage of volts: electric dust to the bottom buried position Yuan line ancestor 2.2.2, 11, the ninth positive voltage is, for example, 2 volts to 8 volts, 14 201140811 P9S0095 32286twf.doc/n H in 2 scales. In addition, word line technique, (4) for example, 疋 is applied 0 volts The third method of the upper storage area TBIT of the lower cell 7 is the same as the bottom buried type bit edge and the top miscellaneous material line plus, _ for example. = two applies a tenth-positive 璧 to word line connector' to apply a voltage of 0 volts to the top buried bit 飧TBL2. Then, apply a +th main octet/〇, .spring BBU. Down, apply a ==: into the bit line muscle 2. In the present invention, the thirteenth positive voltage is, for example, volts to 2 volts, and the muscle 3 is, for example, G volts applied. ^° In addition, the 'character line (4), TBU, TBL3 is, for example, ^, and the top buried bit line. The operation method of this embodiment includes the memory of the memory cell C22 of the BC-Bu. Step. First, apply - a tenth =: =: -1 including the next, apply - a fifteenth positive ^ to the sub 4 WL2 ° followed by the invention - in the embodiment binary = in = and ten The Wuzheng crane is, for example, i volt to (4), for example, is applied. [I: = = line view and top buried bit line TBu: = The operation method of this embodiment includes the track record, _(3) of the fourth balance 15 201140811 i^y»uuy5 32286 tw£doc/n storage area BIT·4. The fourth storage area for reading the memory cell C22 包括·4 includes the following steps. First, apply a sixteenth positive _ to the word line wu. By Applying a seventeenth positive voltage to the top buried bit line TBL2. Then 'applying the undulating _ miscellaneous to the buried nucleus line bbu. In the inventive-embodiment, the sixteenth positive (four) is 2 volts to 8 volts' and the seventeenth positive voltage is, for example, i volts to 2 volts. In addition, the characters, WU, WL3 are, for example, volts that are applied to the volts, while the bottom is buried in the ray 1 and buried at the top. Into the bit line plus, view for example is

抹除操作Erase operation

々紅請同時參照圖1、® 2及表1，本實施儀操作扣 =括抹除記憶胞C22的上部儲存區TmT。抹除記憶胞的上部儲存區TBIT包括下❹驟。首先，施加-個第」負電屋至字元線WL2。接著，施加—個第十人正 4埋入式位元線TBL2。然後，使底部埋狐1θ、狐2浮置。在本發明的—實施例中，第-負^ 列^^-4伙特至_7伏特，而第十八正電壓例如是3伏^ 6 ^特。此外，料線wu、wu例如技施特電壓，而頂部埋人式㈣線TBU、TBL^如是浮 1特的本實施_操作方法包括抹除⑽胞⑶」存區航_卜抹除記憶胞⑶的第一儲存區m = 列步驟。首先，施加-個第二負電壓至字元線wl ^下使頂部埋入式位元線TBL2浮置。然後，施加正電壓至底部埋入式位元線狐卜在本發明的4 = 16 201140811 32286twf.d〇c/n 中第一負電壓例如是·4伏特至_ ，。伏特至6伏特。此外，字元線 ==G伏特的電壓，而底部埋人式位元線服^及頂邛里入^位元線TBU、TBL3例如是浮置。、Please refer to Figure 1, ® 2 and Table 1 for the blush. The operation buckle of this implement includes erasing the upper storage area TmT of the memory cell C22. The upper storage area TBIT of the erased memory cell includes the next step. First, a negative electric house is applied to the word line WL2. Next, a tenth person positive 4 buried bit line TBL2 is applied. Then, the bottom fox 1θ and the fox 2 are floated. In the embodiment of the present invention, the first-negative voltage is _7 volts, and the eighteenth positive voltage is, for example, 3 volts. In addition, the material lines wu, wu, for example, the technical voltage, and the top buried (four) line TBU, TBL ^ such as the floating one special implementation _ operation method includes erasing (10) cells (3)" memory area _ erase memory cells (3) The first storage area m = column step. First, applying a second negative voltage to the word line wl ^ causes the top buried bit line TBL2 to float. Then, applying a positive voltage to the bottom buried bit line fox is the first negative voltage in 4 = 16 201140811 32286 twf.d 〇 c / n of the present invention, for example, 4 volts to _. Volt to 6 volts. In addition, the word line == G volts, and the bottom buried bit line device ^ and the top 邛 bit line TBU, TBL3 are, for example, floating. ,

本實施例的操作方法包括抹除記憶胞⑶的第 =BIT:4。抹除記憶胞⑶的第四儲存區抓_4包括下驟。錢，施加—個第三負電壓至字域乳2。接著，使頂部埋入式位元線TBL2浮置。然後，施加一個 :電㊁至=里入式位元線狐2。在本發明的一實施例弟二負笔壓例如是_4伏特至_7伏特，而第二十電壓疋3伏特至6伏特。此外，字元線如、肌3例如是被施加〇伏_ ，而底部埋人式位樣狐丨及埋入式位元線TBL1、TBL3例如是浮置。 —基於上述，由於在對記憶胞C22的第二儲存區bit_2 與第三儲存區BIT·3進行程式化操作時，分職加〇伏特的電壓至底部埋人式位元線BBU、BBU，使得第二儲存 f BIT_2與第三儲麵BIT_3被程式化為相同的儲存狀悲，所以第二儲存區BIT_2與第三儲存區BIT_3沒有互相干擾的問題，且可視為相同的上部儲存區TBIT使用，因此具有單一記憶胞C22三位元儲存的功效。一此外，由於在對記憶胞C22的第二儲存區BIT_2與第 ^儲存區BIT-3進行程式化操作時，分別施加〇伏特的電壓至底部埋人植元線BBU、BBU，目此底部埋入式位兀線BBL1、BBL2不會與施加於頂部埋入式位元線TBL2 17 201140811 ryeuuyi 32286twf.d〇c/n 的電壓輕合，而可避免第—儲存區BIT-1與第四儲存區 BIT-4的儲存狀態受到干擾，因此可獲得具有不互相干擾的上部儲存區TBIT、第i存區阶」與第四儲存區 BIT-4的單一記憶胞三位元儲存的記憶胞。紅^所述，上述實施例的操作方法可使得垂直記憔胞中的第二儲存區與第三儲存區視為相同的上 ^ 用’因此能有效地賴單-記憶胞三位元儲㈣化使目的The method of operation of this embodiment includes erasing the =BIT:4 of the memory cell (3). The fourth storage area of the memory cell (3) is scratched _4 including the next step. Money, apply a third negative voltage to the word domain milk 2. Next, the top buried bit line TBL2 is floated. Then, apply one: electric two to = lining bit line fox 2. In one embodiment of the invention, the second pen pressure is, for example, _4 volts to _7 volts, and the twentieth voltage is 疋3 volts to 6 volts. Further, for example, the word line, for example, the muscle 3 is applied with a stagnation _, and the bottom buried position fox and the buried bit line TBL1, TBL3 are, for example, floating. - based on the above, when the second storage area bit_2 and the third storage area BIT·3 of the memory cell C22 are programmed, the voltage of the volt-voltage is divided into the bottom buried bit line BBU, BBU, so that The second storage f BIT_2 and the third storage surface BIT_3 are programmed into the same storage sorrow, so the second storage area BIT_2 and the third storage area BIT_3 do not interfere with each other, and can be regarded as the same upper storage area TBIT. Therefore, it has the effect of a single memory cell C22 three-dimensional storage. In addition, since the voltage is applied to the second storage area BIT_2 and the second storage area BIT-3 of the memory cell C22, the voltage of the volts is applied to the BBU and BBU of the bottom buried cell line, and the bottom is buried. The input bit lines BBL1 and BBL2 do not overlap with the voltage applied to the top buried bit line TBL2 17 201140811 ryeuuyi 32286twf.d〇c/n, and the first storage area BIT-1 and the fourth storage can be avoided. The storage state of the area BIT-4 is disturbed, so that a memory cell of a single memory cell ternary storage having an upper storage area TBIT, an i-th storage stage" and a fourth storage area BIT-4 which do not interfere with each other can be obtained. According to the red method, the operation method of the above embodiment can make the second storage area and the third storage area in the vertical recording cell be regarded as the same upper-use 'so that it can effectively rely on the single-memory cell three-dimensional storage (4) Make purpose

雖然本發明已以實施例揭露如上，然其並非用本發明，任何所屬技術職t具有通f知識者本發明之精神和範_，當可作些許之更動與_，發明之保護範圍當視後附之巾請專魏_界定者為準。【圖式簡單說明】圖1所繪不為本發明之一實施例圖。。匕隐體的電路簡圖2所繪示為圖1中記憶胞C22的剖面圖。Although the present invention has been disclosed in the above embodiments by way of example, it is not intended to be the invention, and any of the technical tasks of the present invention has the spirit and scope of the present invention, and when some modifications and _ can be made, the scope of protection of the invention is regarded as Please attach the special towel to the definition of Wei. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is not an embodiment of the present invention. . FIG. 2 is a cross-sectional view of the memory cell C22 of FIG. 1.

【主要元件符號說明】 100 :基底 102 :電荷儲存層 104 :突出部 BBL1、BBL2 :底部埋入式位元線 BIT-1 :第一儲存區 BIT-2 :第二儲存區 18 201140811 1 7 0W：7J 32286twf.doc/n BIT-3 :第三儲存區 BIT-4 :第四儲存區 C22 :記憶胞 TBIT :上部儲存區 TBL1、TBL2、TBL3 :頂部埋入式位元線 WU、WL2、WL3 :字元線[Description of main component symbols] 100: Substrate 102: Charge storage layer 104: Projections BBL1, BBL2: Bottom buried bit line BIT-1: First storage area BIT-2: Second storage area 18 201140811 1 7 0W :7J 32286twf.doc/n BIT-3 : Third storage area BIT-4 : Fourth storage area C22 : Memory cell TBIT : Upper storage area TBL1 , TBL2 , TBL3 : Top buried bit line WU , WL2 , WL3 : word line

1919

Claims

32286twf.doc/n 201140811 七、申請專利範圍： 1'種&己憶胞的操作方法，其中該記憶胞包括具有一凸出部的-基底、位於該凸出部頂部中的一頂部ς元線、^位於該凸出部兩侧的該基底中的一第—底部位元，與-第二底部位元線、設置於該基底上方且輿該第—、第一底部位TL線相交的一字元線以及設置於該字元線與該 —電荷儲存層’ ^其中該記憶胞具有位於該電何儲存層中的一第一儲存區、一第二儲存區、一第 -第四儲存區，該第—儲存區及該第 ^凸，之該第—底部位㈣之—侧的下部及上部= 立第„及該第四儲存區分別鄰近該凸出部之該第二底巧兀線之-側的上部及下部，而該第：儲存區視為相同的一上部儲存區，該操作方法包括第二私式化該記憶胞的該上部儲存區，包括：施加一第一正電壓至該字元線；施加一第二正電壓至該頂部位元線；以及 2 Λ別施加—底電駐該第―、第二底部位元線。法，|料第1項所述之記憶胞的操作方法，==:1項所述之記憶胞的操作方法，利範圍第1項所述之記憶胞的操作方耘式化該記憶胞的該第一儲存區，包括·· 20 32286twf.doc/n 201140811 施加一第三正電壓至該字元線；施加一頂電壓至該頂部位元線；以及施加一第四正電壓至該第一底部位元線。 5. 如申請專利範圍第4項所述之記憶胞的操作方法，其中該第三正電壓為8伏特至12伏特，而該第四正電壓與該頂電壓之間的電位差為3伏特至5伏特。 6. 如申請專利範圍第1項所述之記憶胞的操作方法，更包括讀取該記憶胞的該上部儲存區，包括：施加一第七正電壓至該字元線；施加0伏特的電壓至該頂部位元線；以及施加一第八正電壓至該第一底部位元線。 7. 申請專利範圍第1項所述之記憶胞的操作方法，更包括讀取該記憶胞的該上部儲存區，包括：施加一第Η—正電壓至該字元線；施加0伏特的電壓至該頂部位元線；施加一第十二正電壓至該第一底部位元線；以及施加一第十三正電壓至該第二底部位元線。 8. 如申請專利範圍第1項所述之記憶胞的操作方法，更包括讀取該記憶胞的該第一儲存區，包括：施加一第十四正電壓至該字元線；施加一第十五正電壓至該頂部位元線；以及施加0伏特的電壓至該第一底部位元線。 9. 如申請專利範圍第1項所述之記憶胞的操作方法，更包括抹除該記憶胞的該上部儲存區，包括： 21 32286twf.doc/n 201140811 _______> 施加一第一負電壓至該字元線；施加一第十八正電壓至該頂部位元線；以及使該第一、第二底部位元線浮置。 10.如申請專利範圍第1項所述之記憶胞的操作方法，更包括抹除該記憶胞的該第一儲存區，包括：施加一第二負電壓至該字元線；使該頂部位元線浮置；以及施加一第十九正電壓至該第一底部位元線。32286twf.doc/n 201140811 VII. Patent application scope: 1' species & memory cell operation method, wherein the memory cell comprises a substrate having a protrusion, and a top element located in the top of the protrusion a first bottom bit in the substrate on both sides of the protruding portion, and a second bottom bit line disposed above the substrate and intersecting the first and first bottom bit TL lines a word line and the word line and the charge storage layer '^ wherein the memory cell has a first storage area, a second storage area, and a first to fourth storage located in the electrical storage layer a second bottom portion of the first storage area and the first convex portion, the lower portion and the upper portion of the first bottom portion (fourth), and the second storage area respectively adjacent to the protruding portion The upper and lower portions of the line-side, and the first: storage area is regarded as the same upper storage area, the method of operation comprising second encrypting the upper storage area of the memory cell, comprising: applying a first positive voltage To the word line; applying a second positive voltage to the top bit line; 2 Screening application—the bottom electricity is stationed in the first and second bottom bit lines. The method of operating the memory cell described in item 1 of the method, ==: the operation method of the memory cell described in item 1 The operating unit of the memory cell of the first aspect of the present invention, the first storage area of the memory cell is modified, including 20 32286 twf.doc/n 201140811, applying a third positive voltage to the word line; applying a top a voltage to the top bit line; and applying a fourth positive voltage to the first bottom bit line. 5. The method of operating a memory cell according to claim 4, wherein the third positive voltage is 8 Volt to 12 volts, and the potential difference between the fourth positive voltage and the top voltage is 3 volts to 5 volts. 6. The method of operating the memory cell according to claim 1, further comprising reading the memory The upper storage region of the cell includes: applying a seventh positive voltage to the word line; applying a voltage of 0 volts to the top bit line; and applying an eighth positive voltage to the first bottom bit line. The method of operating the memory cell described in the first application of the patent scope, Reading the upper storage area of the memory cell, comprising: applying a third 正-positive voltage to the word line; applying a voltage of 0 volts to the top bit line; applying a twelfth positive voltage to the first bottom a bit line; and applying a thirteenth positive voltage to the second bottom bit line. 8. The method of operating a memory cell according to claim 1, further comprising reading the first of the memory cell The storage area includes: applying a fourteenth positive voltage to the word line; applying a fifteenth positive voltage to the top bit line; and applying a voltage of 0 volts to the first bottom bit line. The method for operating a memory cell according to claim 1, further comprising erasing the upper storage area of the memory cell, comprising: 21 32286 twf.doc/n 201140811 _______> applying a first negative voltage to the word line Applying an eighteenth positive voltage to the top bit line; and floating the first and second bottom bit lines. 10. The method of operating a memory cell according to claim 1, further comprising erasing the first storage area of the memory cell, comprising: applying a second negative voltage to the word line; The line is floated; and a nineteenth positive voltage is applied to the first bottom bit line.

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